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authorNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>2012-11-05 22:23:43 -0500
committerSimon Horman <horms@verge.net.au>2012-11-05 23:47:09 -0500
commited9c0754cef1d9f81f70b3147189a5a1b4a307a8 (patch)
treecefee0b6ace6c72652e52d00aa80c62c36e74833
parentddffeb8c4d0331609ef2581d84de4d763607bd37 (diff)
ARM: shmobile: Remove SH7367 support
This is old CPU of shmobile, and the machine by which this CPU is used cannot be obtained. Therefore, remove SH7367 support. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Simon Horman <horms@verge.net.au>
Diffstat
-rw-r--r--arch/arm/mach-shmobile/Kconfig6
-rw-r--r--arch/arm/mach-shmobile/Makefile3
-rw-r--r--arch/arm/mach-shmobile/clock-sh7367.c355
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h9
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7367.h332
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c413
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7367.c1727
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c481
8 files changed, 0 insertions, 3326 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 8ae100cc655c..d20dab455473 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -2,12 +2,6 @@ if ARCH_SHMOBILE
2 2
3comment "SH-Mobile System Type" 3comment "SH-Mobile System Type"
4 4
5config ARCH_SH7367
6 bool "SH-Mobile G3 (SH7367)"
7 select ARCH_WANT_OPTIONAL_GPIOLIB
8 select CPU_V6
9 select SH_CLK_CPG
10
11config ARCH_SH7377 5config ARCH_SH7377
12 bool "SH-Mobile G4 (SH7377)" 6 bool "SH-Mobile G4 (SH7377)"
13 select ARCH_WANT_OPTIONAL_GPIOLIB 7 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index fe2c97c179d1..7c07a04c30fb 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,7 +6,6 @@
6obj-y := timer.o console.o clock.o 6obj-y := timer.o console.o clock.o
7 7
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o 9obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 10obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 11obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
@@ -23,7 +22,6 @@ smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
23 22
24# Pinmux setup 23# Pinmux setup
25pfc-y := 24pfc-y :=
26pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
27pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o 25pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
28pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o 26pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
29pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o 27pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
@@ -31,7 +29,6 @@ pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
31pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o 29pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
32 30
33# IRQ objects 31# IRQ objects
34obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
35obj-$(CONFIG_ARCH_SH7377) += entry-intc.o 32obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
36obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 33obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
37obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o 34obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
deleted file mode 100644
index ef0a95e592c4..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ /dev/null
@@ -1,355 +0,0 @@
1/*
2 * SH7367 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/sh_clk.h>
23#include <linux/clkdev.h>
24#include <mach/common.h>
25
26/* SH7367 registers */
27#define RTFRQCR IOMEM(0xe6150000)
28#define SYFRQCR IOMEM(0xe6150004)
29#define CMFRQCR IOMEM(0xe61500E0)
30#define VCLKCR1 IOMEM(0xe6150008)
31#define VCLKCR2 IOMEM(0xe615000C)
32#define VCLKCR3 IOMEM(0xe615001C)
33#define SCLKACR IOMEM(0xe6150010)
34#define SCLKBCR IOMEM(0xe6150014)
35#define SUBUSBCKCR IOMEM(0xe6158080)
36#define SPUCKCR IOMEM(0xe6150084)
37#define MSUCKCR IOMEM(0xe6150088)
38#define MVI3CKCR IOMEM(0xe6150090)
39#define VOUCKCR IOMEM(0xe6150094)
40#define MFCK1CR IOMEM(0xe6150098)
41#define MFCK2CR IOMEM(0xe615009C)
42#define PLLC1CR IOMEM(0xe6150028)
43#define PLLC2CR IOMEM(0xe615002C)
44#define RTMSTPCR0 IOMEM(0xe6158030)
45#define RTMSTPCR2 IOMEM(0xe6158038)
46#define SYMSTPCR0 IOMEM(0xe6158040)
47#define SYMSTPCR2 IOMEM(0xe6158048)
48#define CMMSTPCR0 IOMEM(0xe615804c)
49
50/* Fixed 32 KHz root clock from EXTALR pin */
51static struct clk r_clk = {
52 .rate = 32768,
53};
54
55/*
56 * 26MHz default rate for the EXTALB1 root input clock.
57 * If needed, reset this with clk_set_rate() from the platform code.
58 */
59struct clk sh7367_extalb1_clk = {
60 .rate = 26666666,
61};
62
63/*
64 * 48MHz default rate for the EXTAL2 root input clock.
65 * If needed, reset this with clk_set_rate() from the platform code.
66 */
67struct clk sh7367_extal2_clk = {
68 .rate = 48000000,
69};
70
71/* A fixed divide-by-2 block */
72static unsigned long div2_recalc(struct clk *clk)
73{
74 return clk->parent->rate / 2;
75}
76
77static struct sh_clk_ops div2_clk_ops = {
78 .recalc = div2_recalc,
79};
80
81/* Divide extalb1 by two */
82static struct clk extalb1_div2_clk = {
83 .ops = &div2_clk_ops,
84 .parent = &sh7367_extalb1_clk,
85};
86
87/* Divide extal2 by two */
88static struct clk extal2_div2_clk = {
89 .ops = &div2_clk_ops,
90 .parent = &sh7367_extal2_clk,
91};
92
93/* PLLC1 */
94static unsigned long pllc1_recalc(struct clk *clk)
95{
96 unsigned long mult = 1;
97
98 if (__raw_readl(PLLC1CR) & (1 << 14))
99 mult = (((__raw_readl(RTFRQCR) >> 24) & 0x3f) + 1) * 2;
100
101 return clk->parent->rate * mult;
102}
103
104static struct sh_clk_ops pllc1_clk_ops = {
105 .recalc = pllc1_recalc,
106};
107
108static struct clk pllc1_clk = {
109 .ops = &pllc1_clk_ops,
110 .flags = CLK_ENABLE_ON_INIT,
111 .parent = &extalb1_div2_clk,
112};
113
114/* Divide PLLC1 by two */
115static struct clk pllc1_div2_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &pllc1_clk,
118};
119
120/* PLLC2 */
121static unsigned long pllc2_recalc(struct clk *clk)
122{
123 unsigned long mult = 1;
124
125 if (__raw_readl(PLLC2CR) & (1 << 31))
126 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
127
128 return clk->parent->rate * mult;
129}
130
131static struct sh_clk_ops pllc2_clk_ops = {
132 .recalc = pllc2_recalc,
133};
134
135static struct clk pllc2_clk = {
136 .ops = &pllc2_clk_ops,
137 .flags = CLK_ENABLE_ON_INIT,
138 .parent = &extalb1_div2_clk,
139};
140
141static struct clk *main_clks[] = {
142 &r_clk,
143 &sh7367_extalb1_clk,
144 &sh7367_extal2_clk,
145 &extalb1_div2_clk,
146 &extal2_div2_clk,
147 &pllc1_clk,
148 &pllc1_div2_clk,
149 &pllc2_clk,
150};
151
152static void div4_kick(struct clk *clk)
153{
154 unsigned long value;
155
156 /* set KICK bit in SYFRQCR to update hardware setting */
157 value = __raw_readl(SYFRQCR);
158 value |= (1 << 31);
159 __raw_writel(value, SYFRQCR);
160}
161
162static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
163 24, 32, 36, 48, 0, 72, 0, 0 };
164
165static struct clk_div_mult_table div4_div_mult_table = {
166 .divisors = divisors,
167 .nr_divisors = ARRAY_SIZE(divisors),
168};
169
170static struct clk_div4_table div4_table = {
171 .div_mult_table = &div4_div_mult_table,
172 .kick = div4_kick,
173};
174
175enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B,
176 DIV4_ZX, DIV4_ZT, DIV4_Z, DIV4_ZD, DIV4_HP,
177 DIV4_ZS, DIV4_ZB, DIV4_ZB3, DIV4_CP, DIV4_NR };
178
179#define DIV4(_reg, _bit, _mask, _flags) \
180 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
181
182static struct clk div4_clks[DIV4_NR] = {
183 [DIV4_I] = DIV4(RTFRQCR, 20, 0x6fff, CLK_ENABLE_ON_INIT),
184 [DIV4_G] = DIV4(RTFRQCR, 16, 0x6fff, CLK_ENABLE_ON_INIT),
185 [DIV4_S] = DIV4(RTFRQCR, 12, 0x6fff, CLK_ENABLE_ON_INIT),
186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT),
187 [DIV4_ZX] = DIV4(SYFRQCR, 20, 0x6fff, 0),
188 [DIV4_ZT] = DIV4(SYFRQCR, 16, 0x6fff, 0),
189 [DIV4_Z] = DIV4(SYFRQCR, 12, 0x6fff, 0),
190 [DIV4_ZD] = DIV4(SYFRQCR, 8, 0x6fff, 0),
191 [DIV4_HP] = DIV4(SYFRQCR, 4, 0x6fff, 0),
192 [DIV4_ZS] = DIV4(CMFRQCR, 12, 0x6fff, 0),
193 [DIV4_ZB] = DIV4(CMFRQCR, 8, 0x6fff, 0),
194 [DIV4_ZB3] = DIV4(CMFRQCR, 4, 0x6fff, 0),
195 [DIV4_CP] = DIV4(CMFRQCR, 0, 0x6fff, 0),
196};
197
198enum { DIV6_SUB, DIV6_SIUA, DIV6_SIUB, DIV6_MSU, DIV6_SPU,
199 DIV6_MVI3, DIV6_MF1, DIV6_MF2,
200 DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VOU,
201 DIV6_NR };
202
203static struct clk div6_clks[DIV6_NR] = {
204 [DIV6_SUB] = SH_CLK_DIV6(&sh7367_extal2_clk, SUBUSBCKCR, 0),
205 [DIV6_SIUA] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKACR, 0),
206 [DIV6_SIUB] = SH_CLK_DIV6(&pllc1_div2_clk, SCLKBCR, 0),
207 [DIV6_MSU] = SH_CLK_DIV6(&pllc1_div2_clk, MSUCKCR, 0),
208 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
209 [DIV6_MVI3] = SH_CLK_DIV6(&pllc1_div2_clk, MVI3CKCR, 0),
210 [DIV6_MF1] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK1CR, 0),
211 [DIV6_MF2] = SH_CLK_DIV6(&pllc1_div2_clk, MFCK2CR, 0),
212 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
213 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
214 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
215 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
216};
217
218enum { RTMSTP001,
219 RTMSTP231, RTMSTP230, RTMSTP229, RTMSTP228, RTMSTP226,
220 RTMSTP216, RTMSTP206, RTMSTP205, RTMSTP201,
221 SYMSTP023, SYMSTP007, SYMSTP006, SYMSTP004,
222 SYMSTP003, SYMSTP002, SYMSTP001, SYMSTP000,
223 SYMSTP231, SYMSTP229, SYMSTP225, SYMSTP223, SYMSTP222,
224 SYMSTP215, SYMSTP214, SYMSTP213, SYMSTP211,
225 CMMSTP003,
226 MSTP_NR };
227
228#define MSTP(_parent, _reg, _bit, _flags) \
229 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
230
231static struct clk mstp_clks[MSTP_NR] = {
232 [RTMSTP001] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR0, 1, 0), /* IIC2 */
233 [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */
234 [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */
235 [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */
236 [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */
237 [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */
238 [RTMSTP216] = MSTP(&div6_clks[DIV6_SUB], RTMSTPCR2, 16, 0), /* IIC0 */
239 [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */
240 [RTMSTP205] = MSTP(&div6_clks[DIV6_VOU], RTMSTPCR2, 5, 0), /* VOU */
241 [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */
242 [SYMSTP023] = MSTP(&div6_clks[DIV6_SPU], SYMSTPCR0, 23, 0), /* SPU1 */
243 [SYMSTP007] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 7, 0), /* SCIFA5 */
244 [SYMSTP006] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 6, 0), /* SCIFB */
245 [SYMSTP004] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 4, 0), /* SCIFA0 */
246 [SYMSTP003] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 3, 0), /* SCIFA1 */
247 [SYMSTP002] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 2, 0), /* SCIFA2 */
248 [SYMSTP001] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 1, 0), /* SCIFA3 */
249 [SYMSTP000] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR0, 0, 0), /* SCIFA4 */
250 [SYMSTP231] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 31, 0), /* SIU */
251 [SYMSTP229] = MSTP(&r_clk, SYMSTPCR2, 29, 0), /* CMT10 */
252 [SYMSTP225] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 25, 0), /* IRDA */
253 [SYMSTP223] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 23, 0), /* IIC1 */
254 [SYMSTP222] = MSTP(&div6_clks[DIV6_SUB], SYMSTPCR2, 22, 0), /* USBHS */
255 [SYMSTP215] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 15, 0), /* FLCTL */
256 [SYMSTP214] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 14, 0), /* SDHI0 */
257 [SYMSTP213] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 13, 0), /* SDHI1 */
258 [SYMSTP211] = MSTP(&div4_clks[DIV4_HP], SYMSTPCR2, 11, 0), /* SDHI2 */
259 [CMMSTP003] = MSTP(&r_clk, CMMSTPCR0, 3, 0), /* KEYSC */
260};
261
262static struct clk_lookup lookups[] = {
263 /* main clocks */
264 CLKDEV_CON_ID("r_clk", &r_clk),
265 CLKDEV_CON_ID("extalb1", &sh7367_extalb1_clk),
266 CLKDEV_CON_ID("extal2", &sh7367_extal2_clk),
267 CLKDEV_CON_ID("extalb1_div2_clk", &extalb1_div2_clk),
268 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
269 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
270 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
271 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk),
272
273 /* DIV4 clocks */
274 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
275 CLKDEV_CON_ID("g_clk", &div4_clks[DIV4_G]),
276 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
277 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
278 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
279 CLKDEV_CON_ID("z_clk", &div4_clks[DIV4_Z]),
280 CLKDEV_CON_ID("zd_clk", &div4_clks[DIV4_ZD]),
281 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
282 CLKDEV_CON_ID("zs_clk", &div4_clks[DIV4_ZS]),
283 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
284 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
285 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
286
287 /* DIV6 clocks */
288 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
289 CLKDEV_CON_ID("siua_clk", &div6_clks[DIV6_SIUA]),
290 CLKDEV_CON_ID("siub_clk", &div6_clks[DIV6_SIUB]),
291 CLKDEV_CON_ID("msu_clk", &div6_clks[DIV6_MSU]),
292 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
293 CLKDEV_CON_ID("mvi3_clk", &div6_clks[DIV6_MVI3]),
294 CLKDEV_CON_ID("mf1_clk", &div6_clks[DIV6_MF1]),
295 CLKDEV_CON_ID("mf2_clk", &div6_clks[DIV6_MF2]),
296 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
297 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
298 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
299 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
300
301 /* MSTP32 clocks */
302 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[RTMSTP001]), /* IIC2 */
303 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[RTMSTP231]), /* VEU3 */
304 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[RTMSTP230]), /* VEU2 */
305 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[RTMSTP229]), /* VEU1 */
306 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[RTMSTP228]), /* VEU0 */
307 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[RTMSTP226]), /* VEU2H */
308 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[RTMSTP216]), /* IIC0 */
309 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[RTMSTP206]), /* JPU */
310 CLKDEV_DEV_ID("sh-vou", &mstp_clks[RTMSTP205]), /* VOU */
311 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[RTMSTP201]), /* VPU */
312 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[SYMSTP023]), /* SPU1 */
313 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[SYMSTP007]), /* SCIFA5 */
314 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[SYMSTP006]), /* SCIFB */
315 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[SYMSTP004]), /* SCIFA0 */
316 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[SYMSTP003]), /* SCIFA1 */
317 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[SYMSTP002]), /* SCIFA2 */
318 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
319 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
320 CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
321 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
322 CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
323 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
324 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
325 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[SYMSTP222]), /* USBHS */
326 CLKDEV_DEV_ID("sh_flctl", &mstp_clks[SYMSTP215]), /* FLCTL */
327 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[SYMSTP214]), /* SDHI0 */
328 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[SYMSTP213]), /* SDHI1 */
329 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[SYMSTP211]), /* SDHI2 */
330 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[CMMSTP003]), /* KEYSC */
331};
332
333void __init sh7367_clock_init(void)
334{
335 int k, ret = 0;
336
337 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
338 ret = clk_register(main_clks[k]);
339
340 if (!ret)
341 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
342
343 if (!ret)
344 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
345
346 if (!ret)
347 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
348
349 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
350
351 if (!ret)
352 shmobile_clk_init();
353 else
354 panic("failed to setup sh7367 clocks\n");
355}
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index d47e215aca87..f96fc29e5aec 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -18,15 +18,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
18 struct cpuidle_driver *drv, int index); 18 struct cpuidle_driver *drv, int index);
19extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 19extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
20 20
21extern void sh7367_init_irq(void);
22extern void sh7367_map_io(void);
23extern void sh7367_add_early_devices(void);
24extern void sh7367_add_standard_devices(void);
25extern void sh7367_clock_init(void);
26extern void sh7367_pinmux_init(void);
27extern struct clk sh7367_extalb1_clk;
28extern struct clk sh7367_extal2_clk;
29
30extern void sh7377_init_irq(void); 21extern void sh7377_init_irq(void);
31extern void sh7377_map_io(void); 22extern void sh7377_map_io(void);
32extern void sh7377_add_early_devices(void); 23extern void sh7377_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh7367.h b/arch/arm/mach-shmobile/include/mach/sh7367.h
deleted file mode 100644
index 52d0de686f68..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sh7367.h
+++ /dev/null
@@ -1,332 +0,0 @@
1#ifndef __ASM_SH7367_H__
2#define __ASM_SH7367_H__
3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function
6 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 /* 49-1 -> 49-6 (GPIO) */
10 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
11 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
12
13 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
14 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
15
16 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
17 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
18
19 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
20 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
21
22 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
23 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
24
25 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
26 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
27
28 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
29 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
30
31 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
32 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
33
34 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
35 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
36
37 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
38 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
39
40 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
41 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
42
43 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
44 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
45
46 GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
47 GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
48
49 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
50 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
51
52 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
53 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
54
55 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
56 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
57
58 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
59 GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
60
61 GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
62 GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
63
64 GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
65 GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
66
67 GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
68 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
69
70 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
71 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
72
73 GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
74 GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
75
76 GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
77 GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
78
79 GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
80 GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
81
82 GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
83 GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
84
85 GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
86 GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
87
88 GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
89 GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
90
91 GPIO_PORT270, GPIO_PORT271, GPIO_PORT272,
92
93 /* Special Pull-up / Pull-down Functions */
94 GPIO_FN_PORT48_KEYIN0_PU, GPIO_FN_PORT49_KEYIN1_PU,
95 GPIO_FN_PORT50_KEYIN2_PU, GPIO_FN_PORT55_KEYIN3_PU,
96 GPIO_FN_PORT56_KEYIN4_PU, GPIO_FN_PORT57_KEYIN5_PU,
97 GPIO_FN_PORT58_KEYIN6_PU,
98
99 /* 49-1 (FN) */
100 GPIO_FN_VBUS0, GPIO_FN_CPORT0, GPIO_FN_CPORT1, GPIO_FN_CPORT2,
101 GPIO_FN_CPORT3, GPIO_FN_CPORT4, GPIO_FN_CPORT5, GPIO_FN_CPORT6,
102 GPIO_FN_CPORT7, GPIO_FN_CPORT8, GPIO_FN_CPORT9, GPIO_FN_CPORT10,
103 GPIO_FN_CPORT11, GPIO_FN_SIN2, GPIO_FN_CPORT12, GPIO_FN_XCTS2,
104 GPIO_FN_CPORT13, GPIO_FN_RFSPO4, GPIO_FN_CPORT14, GPIO_FN_RFSPO5,
105 GPIO_FN_CPORT15, GPIO_FN_CPORT16, GPIO_FN_CPORT17, GPIO_FN_SOUT2,
106 GPIO_FN_CPORT18, GPIO_FN_XRTS2, GPIO_FN_CPORT19, GPIO_FN_CPORT20,
107 GPIO_FN_RFSPO6, GPIO_FN_CPORT21, GPIO_FN_STATUS0, GPIO_FN_CPORT22,
108 GPIO_FN_STATUS1, GPIO_FN_CPORT23, GPIO_FN_STATUS2, GPIO_FN_RFSPO7,
109 GPIO_FN_MPORT0, GPIO_FN_MPORT1, GPIO_FN_B_SYNLD1, GPIO_FN_B_SYNLD2,
110 GPIO_FN_XMAINPS, GPIO_FN_XDIVPS, GPIO_FN_XIDRST, GPIO_FN_IDCLK,
111 GPIO_FN_IDIO, GPIO_FN_SOUT1, GPIO_FN_SCIFA4_TXD,
112 GPIO_FN_M02_BERDAT, GPIO_FN_SIN1, GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
113 GPIO_FN_XRTS1, GPIO_FN_SCIFA4_RTS, GPIO_FN_M03_BERCLK,
114 GPIO_FN_XCTS1, GPIO_FN_SCIFA4_CTS,
115
116 /* 49-2 (FN) */
117 GPIO_FN_HSU_IQ_AGC6, GPIO_FN_MFG2_IN2, GPIO_FN_MSIOF2_MCK0,
118 GPIO_FN_HSU_IQ_AGC5, GPIO_FN_MFG2_IN1, GPIO_FN_MSIOF2_MCK1,
119 GPIO_FN_HSU_IQ_AGC4, GPIO_FN_MSIOF2_RSYNC,
120 GPIO_FN_HSU_IQ_AGC3, GPIO_FN_MFG2_OUT1, GPIO_FN_MSIOF2_RSCK,
121 GPIO_FN_HSU_IQ_AGC2, GPIO_FN_PORT42_KEYOUT0,
122 GPIO_FN_HSU_IQ_AGC1, GPIO_FN_PORT43_KEYOUT1,
123 GPIO_FN_HSU_IQ_AGC0, GPIO_FN_PORT44_KEYOUT2,
124 GPIO_FN_HSU_IQ_AGC_ST, GPIO_FN_PORT45_KEYOUT3,
125 GPIO_FN_HSU_IQ_PDO, GPIO_FN_PORT46_KEYOUT4,
126 GPIO_FN_HSU_IQ_PYO, GPIO_FN_PORT47_KEYOUT5,
127 GPIO_FN_HSU_EN_TXMUX_G3MO, GPIO_FN_PORT48_KEYIN0,
128 GPIO_FN_HSU_I_TXMUX_G3MO, GPIO_FN_PORT49_KEYIN1,
129 GPIO_FN_HSU_Q_TXMUX_G3MO, GPIO_FN_PORT50_KEYIN2,
130 GPIO_FN_HSU_SYO, GPIO_FN_PORT51_MSIOF2_TSYNC,
131 GPIO_FN_HSU_SDO, GPIO_FN_PORT52_MSIOF2_TSCK,
132 GPIO_FN_HSU_TGTTI_G3MO, GPIO_FN_PORT53_MSIOF2_TXD,
133 GPIO_FN_B_TIME_STAMP, GPIO_FN_PORT54_MSIOF2_RXD,
134 GPIO_FN_HSU_SDI, GPIO_FN_PORT55_KEYIN3,
135 GPIO_FN_HSU_SCO, GPIO_FN_PORT56_KEYIN4,
136 GPIO_FN_HSU_DREQ, GPIO_FN_PORT57_KEYIN5,
137 GPIO_FN_HSU_DACK, GPIO_FN_PORT58_KEYIN6,
138 GPIO_FN_HSU_CLK61M, GPIO_FN_PORT59_MSIOF2_SS1,
139 GPIO_FN_HSU_XRST, GPIO_FN_PORT60_MSIOF2_SS2,
140 GPIO_FN_PCMCLKO, GPIO_FN_SYNC8KO, GPIO_FN_DNPCM_A, GPIO_FN_UPPCM_A,
141 GPIO_FN_XTALB1L,
142 GPIO_FN_GPS_AGC1, GPIO_FN_SCIFA0_RTS,
143 GPIO_FN_GPS_AGC2, GPIO_FN_SCIFA0_SCK,
144 GPIO_FN_GPS_AGC3, GPIO_FN_SCIFA0_TXD,
145 GPIO_FN_GPS_AGC4, GPIO_FN_SCIFA0_RXD,
146 GPIO_FN_GPS_PWRD, GPIO_FN_SCIFA0_CTS,
147 GPIO_FN_GPS_IM, GPIO_FN_GPS_IS, GPIO_FN_GPS_QM, GPIO_FN_GPS_QS,
148 GPIO_FN_SIUBOMC, GPIO_FN_TPU2TO0,
149 GPIO_FN_SIUCKB, GPIO_FN_TPU2TO1,
150 GPIO_FN_SIUBOLR, GPIO_FN_BBIF2_TSYNC, GPIO_FN_TPU2TO2,
151 GPIO_FN_SIUBOBT, GPIO_FN_BBIF2_TSCK, GPIO_FN_TPU2TO3,
152 GPIO_FN_SIUBOSLD, GPIO_FN_BBIF2_TXD, GPIO_FN_TPU3TO0,
153 GPIO_FN_SIUBILR, GPIO_FN_TPU3TO1,
154 GPIO_FN_SIUBIBT, GPIO_FN_TPU3TO2,
155 GPIO_FN_SIUBISLD, GPIO_FN_TPU3TO3,
156 GPIO_FN_NMI, GPIO_FN_TPU4TO0,
157 GPIO_FN_DNPCM_M, GPIO_FN_TPU4TO1, GPIO_FN_TPU4TO2, GPIO_FN_TPU4TO3,
158 GPIO_FN_IRQ_TMPB,
159 GPIO_FN_PWEN, GPIO_FN_MFG1_OUT1,
160 GPIO_FN_OVCN, GPIO_FN_MFG1_IN1,
161 GPIO_FN_OVCN2, GPIO_FN_MFG1_IN2,
162
163 /* 49-3 (FN) */
164 GPIO_FN_RFSPO1, GPIO_FN_RFSPO2, GPIO_FN_RFSPO3, GPIO_FN_PORT93_VIO_CKO2,
165 GPIO_FN_USBTERM, GPIO_FN_EXTLP, GPIO_FN_IDIN,
166 GPIO_FN_SCIFA5_CTS, GPIO_FN_MFG0_IN1,
167 GPIO_FN_SCIFA5_RTS, GPIO_FN_MFG0_IN2,
168 GPIO_FN_SCIFA5_RXD,
169 GPIO_FN_SCIFA5_TXD,
170 GPIO_FN_SCIFA5_SCK, GPIO_FN_MFG0_OUT1,
171 GPIO_FN_A0_EA0, GPIO_FN_BS,
172 GPIO_FN_A14_EA14, GPIO_FN_PORT102_KEYOUT0,
173 GPIO_FN_A15_EA15, GPIO_FN_PORT103_KEYOUT1, GPIO_FN_DV_CLKOL,
174 GPIO_FN_A16_EA16, GPIO_FN_PORT104_KEYOUT2,
175 GPIO_FN_DV_VSYNCL, GPIO_FN_MSIOF0_SS1,
176 GPIO_FN_A17_EA17, GPIO_FN_PORT105_KEYOUT3,
177 GPIO_FN_DV_HSYNCL, GPIO_FN_MSIOF0_TSYNC,
178 GPIO_FN_A18_EA18, GPIO_FN_PORT106_KEYOUT4,
179 GPIO_FN_DV_DL0, GPIO_FN_MSIOF0_TSCK,
180 GPIO_FN_A19_EA19, GPIO_FN_PORT107_KEYOUT5,
181 GPIO_FN_DV_DL1, GPIO_FN_MSIOF0_TXD,
182 GPIO_FN_A20_EA20, GPIO_FN_PORT108_KEYIN0,
183 GPIO_FN_DV_DL2, GPIO_FN_MSIOF0_RSCK,
184 GPIO_FN_A21_EA21, GPIO_FN_PORT109_KEYIN1,
185 GPIO_FN_DV_DL3, GPIO_FN_MSIOF0_RSYNC,
186 GPIO_FN_A22_EA22, GPIO_FN_PORT110_KEYIN2,
187 GPIO_FN_DV_DL4, GPIO_FN_MSIOF0_MCK0,
188 GPIO_FN_A23_EA23, GPIO_FN_PORT111_KEYIN3,
189 GPIO_FN_DV_DL5, GPIO_FN_MSIOF0_MCK1,
190 GPIO_FN_A24_EA24, GPIO_FN_PORT112_KEYIN4,
191 GPIO_FN_DV_DL6, GPIO_FN_MSIOF0_RXD,
192 GPIO_FN_A25_EA25, GPIO_FN_PORT113_KEYIN5,
193 GPIO_FN_DV_DL7, GPIO_FN_MSIOF0_SS2,
194 GPIO_FN_A26, GPIO_FN_PORT113_KEYIN6, GPIO_FN_DV_CLKIL,
195 GPIO_FN_D0_ED0_NAF0, GPIO_FN_D1_ED1_NAF1, GPIO_FN_D2_ED2_NAF2,
196 GPIO_FN_D3_ED3_NAF3, GPIO_FN_D4_ED4_NAF4, GPIO_FN_D5_ED5_NAF5,
197 GPIO_FN_D6_ED6_NAF6, GPIO_FN_D7_ED7_NAF7, GPIO_FN_D8_ED8_NAF8,
198 GPIO_FN_D9_ED9_NAF9, GPIO_FN_D10_ED10_NAF10, GPIO_FN_D11_ED11_NAF11,
199 GPIO_FN_D12_ED12_NAF12, GPIO_FN_D13_ED13_NAF13,
200 GPIO_FN_D14_ED14_NAF14, GPIO_FN_D15_ED15_NAF15,
201 GPIO_FN_CS4, GPIO_FN_CS5A, GPIO_FN_CS5B, GPIO_FN_FCE1,
202 GPIO_FN_CS6B, GPIO_FN_XCS2, GPIO_FN_FCE0, GPIO_FN_CS6A,
203 GPIO_FN_DACK0, GPIO_FN_WAIT, GPIO_FN_DREQ0, GPIO_FN_RD_XRD,
204 GPIO_FN_A27, GPIO_FN_RDWR_XWE, GPIO_FN_WE0_XWR0_FWE,
205 GPIO_FN_WE1_XWR1, GPIO_FN_FRB, GPIO_FN_CKO,
206 GPIO_FN_NBRSTOUT, GPIO_FN_NBRST,
207
208 /* 49-4 (FN) */
209 GPIO_FN_RFSPO0, GPIO_FN_PORT146_VIO_CKO2, GPIO_FN_TSTMD,
210 GPIO_FN_VIO_VD, GPIO_FN_VIO_HD,
211 GPIO_FN_VIO_D0, GPIO_FN_VIO_D1, GPIO_FN_VIO_D2,
212 GPIO_FN_VIO_D3, GPIO_FN_VIO_D4, GPIO_FN_VIO_D5,
213 GPIO_FN_VIO_D6, GPIO_FN_VIO_D7, GPIO_FN_VIO_D8,
214 GPIO_FN_VIO_D9, GPIO_FN_VIO_D10, GPIO_FN_VIO_D11,
215 GPIO_FN_VIO_D12, GPIO_FN_VIO_D13, GPIO_FN_VIO_D14,
216 GPIO_FN_VIO_D15, GPIO_FN_VIO_CLK, GPIO_FN_VIO_FIELD,
217 GPIO_FN_VIO_CKO,
218 GPIO_FN_MFG3_IN1, GPIO_FN_MFG3_IN2,
219 GPIO_FN_M9_SLCD_A01, GPIO_FN_MFG3_OUT1, GPIO_FN_TPU0TO0,
220 GPIO_FN_M10_SLCD_CK1, GPIO_FN_MFG4_IN1, GPIO_FN_TPU0TO1,
221 GPIO_FN_M11_SLCD_SO1, GPIO_FN_MFG4_IN2, GPIO_FN_TPU0TO2,
222 GPIO_FN_M12_SLCD_CE1, GPIO_FN_MFG4_OUT1, GPIO_FN_TPU0TO3,
223 GPIO_FN_LCDD0, GPIO_FN_PORT175_KEYOUT0, GPIO_FN_DV_D0,
224 GPIO_FN_SIUCKA, GPIO_FN_MFG0_OUT2,
225 GPIO_FN_LCDD1, GPIO_FN_PORT176_KEYOUT1, GPIO_FN_DV_D1,
226 GPIO_FN_SIUAOLR, GPIO_FN_BBIF2_TSYNC1,
227 GPIO_FN_LCDD2, GPIO_FN_PORT177_KEYOUT2, GPIO_FN_DV_D2,
228 GPIO_FN_SIUAOBT, GPIO_FN_BBIF2_TSCK1,
229 GPIO_FN_LCDD3, GPIO_FN_PORT178_KEYOUT3, GPIO_FN_DV_D3,
230 GPIO_FN_SIUAOSLD, GPIO_FN_BBIF2_TXD1,
231 GPIO_FN_LCDD4, GPIO_FN_PORT179_KEYOUT4, GPIO_FN_DV_D4,
232 GPIO_FN_SIUAISPD, GPIO_FN_MFG1_OUT2,
233 GPIO_FN_LCDD5, GPIO_FN_PORT180_KEYOUT5, GPIO_FN_DV_D5,
234 GPIO_FN_SIUAILR, GPIO_FN_MFG2_OUT2,
235 GPIO_FN_LCDD6, GPIO_FN_DV_D6,
236 GPIO_FN_SIUAIBT, GPIO_FN_MFG3_OUT2, GPIO_FN_XWR2,
237 GPIO_FN_LCDD7, GPIO_FN_DV_D7,
238 GPIO_FN_SIUAISLD, GPIO_FN_MFG4_OUT2, GPIO_FN_XWR3,
239 GPIO_FN_LCDD8, GPIO_FN_DV_D8, GPIO_FN_D16, GPIO_FN_ED16,
240 GPIO_FN_LCDD9, GPIO_FN_DV_D9, GPIO_FN_D17, GPIO_FN_ED17,
241 GPIO_FN_LCDD10, GPIO_FN_DV_D10, GPIO_FN_D18, GPIO_FN_ED18,
242 GPIO_FN_LCDD11, GPIO_FN_DV_D11, GPIO_FN_D19, GPIO_FN_ED19,
243 GPIO_FN_LCDD12, GPIO_FN_DV_D12, GPIO_FN_D20, GPIO_FN_ED20,
244 GPIO_FN_LCDD13, GPIO_FN_DV_D13, GPIO_FN_D21, GPIO_FN_ED21,
245 GPIO_FN_LCDD14, GPIO_FN_DV_D14, GPIO_FN_D22, GPIO_FN_ED22,
246 GPIO_FN_LCDD15, GPIO_FN_DV_D15, GPIO_FN_D23, GPIO_FN_ED23,
247 GPIO_FN_LCDD16, GPIO_FN_DV_HSYNC, GPIO_FN_D24, GPIO_FN_ED24,
248 GPIO_FN_LCDD17, GPIO_FN_DV_VSYNC, GPIO_FN_D25, GPIO_FN_ED25,
249 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_MSIOF0L_TSCK,
250 GPIO_FN_D26, GPIO_FN_ED26,
251 GPIO_FN_LCDD19, GPIO_FN_MSIOF0L_TSYNC,
252 GPIO_FN_D27, GPIO_FN_ED27,
253 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0,
254 GPIO_FN_D28, GPIO_FN_ED28,
255 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1,
256 GPIO_FN_D29, GPIO_FN_ED29,
257 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_SS1,
258 GPIO_FN_D30, GPIO_FN_ED30,
259 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_SS2,
260 GPIO_FN_D31, GPIO_FN_ED31,
261 GPIO_FN_LCDDCK, GPIO_FN_LCDWR, GPIO_FN_DV_CKO, GPIO_FN_SIUAOSPD,
262 GPIO_FN_LCDRD, GPIO_FN_DACK2, GPIO_FN_MSIOF0L_RSYNC,
263
264
265 /* 49-5 (FN) */
266 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS, GPIO_FN_LCDCS2, GPIO_FN_DACK3,
267 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_RSCK,
268 GPIO_FN_LCDCSYN, GPIO_FN_LCDCSYN2, GPIO_FN_DV_CKI,
269 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_MSIOF0L_RXD,
270 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_MSIOF0L_TXD,
271 GPIO_FN_VIO_DR0, GPIO_FN_VIO_DR1, GPIO_FN_VIO_DR2, GPIO_FN_VIO_DR3,
272 GPIO_FN_VIO_DR4, GPIO_FN_VIO_DR5, GPIO_FN_VIO_DR6, GPIO_FN_VIO_DR7,
273 GPIO_FN_VIO_VDR, GPIO_FN_VIO_HDR,
274 GPIO_FN_VIO_CLKR, GPIO_FN_VIO_CKOR,
275 GPIO_FN_SCIFA1_TXD, GPIO_FN_GPS_PGFA0,
276 GPIO_FN_SCIFA1_SCK, GPIO_FN_GPS_PGFA1,
277 GPIO_FN_SCIFA1_RTS, GPIO_FN_GPS_EPPSINMON,
278 GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_CTS,
279 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA1_TXD2, GPIO_FN_GPS_TXD,
280 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA1_CTS2, GPIO_FN_I2C_SDA2,
281 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA1_SCK2,
282 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA1_RXD2, GPIO_FN_GPS_RXD,
283 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA1_RTS2,
284 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_I2C_SCL2,
285 GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
286 GPIO_FN_MSIOF1_SS1, GPIO_FN_EDBGREQ3,
287 GPIO_FN_MSIOF1_SS2,
288 GPIO_FN_PORT236_IROUT, GPIO_FN_IRDA_OUT,
289 GPIO_FN_IRDA_IN, GPIO_FN_IRDA_FIRSEL,
290 GPIO_FN_TPU1TO0, GPIO_FN_TS_SPSYNC3,
291 GPIO_FN_TPU1TO1, GPIO_FN_TS_SDAT3,
292 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT241_MSIOF2_SS1,
293 GPIO_FN_TPU1TO3, GPIO_FN_PORT242_MSIOF2_TSCK,
294 GPIO_FN_M13_BSW, GPIO_FN_PORT243_MSIOF2_TSYNC,
295 GPIO_FN_M14_GSW, GPIO_FN_PORT244_MSIOF2_TXD,
296 GPIO_FN_PORT245_IROUT, GPIO_FN_M15_RSW,
297 GPIO_FN_SOUT3, GPIO_FN_SCIFA2_TXD1,
298 GPIO_FN_SIN3, GPIO_FN_SCIFA2_RXD1,
299 GPIO_FN_XRTS3, GPIO_FN_SCIFA2_RTS1, GPIO_FN_PORT248_MSIOF2_SS2,
300 GPIO_FN_XCTS3, GPIO_FN_SCIFA2_CTS1, GPIO_FN_PORT249_MSIOF2_RXD,
301 GPIO_FN_DINT, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
302 GPIO_FN_SDHICLK0, GPIO_FN_TCK2,
303 GPIO_FN_SDHICD0,
304 GPIO_FN_SDHID0_0, GPIO_FN_TMS2,
305 GPIO_FN_SDHID0_1, GPIO_FN_TDO2,
306 GPIO_FN_SDHID0_2, GPIO_FN_TDI2,
307 GPIO_FN_SDHID0_3, GPIO_FN_RTCK2,
308
309 /* 49-6 (FN) */
310 GPIO_FN_SDHICMD0, GPIO_FN_TRST2,
311 GPIO_FN_SDHIWP0, GPIO_FN_EDBGREQ2,
312 GPIO_FN_SDHICLK1, GPIO_FN_TCK3,
313 GPIO_FN_SDHID1_0, GPIO_FN_M11_SLCD_SO2,
314 GPIO_FN_TS_SPSYNC2, GPIO_FN_TMS3,
315 GPIO_FN_SDHID1_1, GPIO_FN_M9_SLCD_AO2,
316 GPIO_FN_TS_SDAT2, GPIO_FN_TDO3,
317 GPIO_FN_SDHID1_2, GPIO_FN_M10_SLCD_CK2,
318 GPIO_FN_TS_SDEN2, GPIO_FN_TDI3,
319 GPIO_FN_SDHID1_3, GPIO_FN_M12_SLCD_CE2,
320 GPIO_FN_TS_SCK2, GPIO_FN_RTCK3,
321 GPIO_FN_SDHICMD1, GPIO_FN_TRST3,
322 GPIO_FN_SDHICLK2, GPIO_FN_SCIFB_SCK,
323 GPIO_FN_SDHID2_0, GPIO_FN_SCIFB_TXD,
324 GPIO_FN_SDHID2_1, GPIO_FN_SCIFB_CTS,
325 GPIO_FN_SDHID2_2, GPIO_FN_SCIFB_RXD,
326 GPIO_FN_SDHID2_3, GPIO_FN_SCIFB_RTS,
327 GPIO_FN_SDHICMD2,
328 GPIO_FN_RESETOUTS,
329 GPIO_FN_DIVLOCK,
330};
331
332#endif /* __ASM_SH7367_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
deleted file mode 100644
index 5bf776495b75..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ /dev/null
@@ -1,413 +0,0 @@
1/*
2 * sh7367 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <mach/intc.h>
26#include <mach/irqs.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29
30enum {
31 UNUSED_INTCA = 0,
32 ENABLED,
33 DISABLED,
34
35 /* interrupt sources INTCA */
36 DIRC,
37 CRYPT1_ERR, CRYPT2_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
39 ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMRX,
40 ETM11_ACQCMP, ETM11_FULL,
41 MFI_MFIM, MFI_MFIS,
42 BBIF1, BBIF2,
43 USBDMAC_USHDMI,
44 USBHS_USHI0, USBHS_USHI1,
45 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
46 KEYSC_KEY,
47 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
48 MSIOF2, MSIOF1,
49 SCIFA4, SCIFA5, SCIFB,
50 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
51 SDHI0,
52 SDHI1,
53 MSU_MSU, MSU_MSU2,
54 IREM,
55 SIU,
56 SPU,
57 IRDA,
58 TPU0, TPU1, TPU2, TPU3, TPU4,
59 LCRC,
60 PINT1, PINT2,
61 TTI20,
62 MISTY,
63 DDM,
64 SDHI2,
65 RWDT0, RWDT1,
66 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
67 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
68 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
69 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
70 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
71 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
72
73 /* interrupt groups INTCA */
74 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2,
75 ETM11, ARM11, USBHS, FLCTL, IIC1
76};
77
78static struct intc_vect intca_vectors[] __initdata = {
79 INTC_VECT(DIRC, 0x0560),
80 INTC_VECT(CRYPT1_ERR, 0x05e0),
81 INTC_VECT(CRYPT2_STD, 0x0700),
82 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
83 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
84 INTC_VECT(ARM11_IRQPMU, 0x0800), INTC_VECT(ARM11_COMMTX, 0x0840),
85 INTC_VECT(ARM11_COMMRX, 0x0860),
86 INTC_VECT(ETM11_ACQCMP, 0x0880), INTC_VECT(ETM11_FULL, 0x08a0),
87 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
88 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
89 INTC_VECT(USBDMAC_USHDMI, 0x0a00),
90 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
91 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
92 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
93 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
94 INTC_VECT(KEYSC_KEY, 0x0be0),
95 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
96 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
97 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
98 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
99 INTC_VECT(SCIFB, 0x0d60),
100 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
101 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
102 INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
103 INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
104 INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
105 INTC_VECT(SDHI1, 0x0ec0), INTC_VECT(SDHI1, 0x0ee0),
106 INTC_VECT(MSU_MSU, 0x0f20), INTC_VECT(MSU_MSU2, 0x0f40),
107 INTC_VECT(IREM, 0x0f60),
108 INTC_VECT(SIU, 0x0fa0),
109 INTC_VECT(SPU, 0x0fc0),
110 INTC_VECT(IRDA, 0x0480),
111 INTC_VECT(TPU0, 0x04a0), INTC_VECT(TPU1, 0x04c0),
112 INTC_VECT(TPU2, 0x04e0), INTC_VECT(TPU3, 0x0500),
113 INTC_VECT(TPU4, 0x0520),
114 INTC_VECT(LCRC, 0x0540),
115 INTC_VECT(PINT1, 0x1000), INTC_VECT(PINT2, 0x1020),
116 INTC_VECT(TTI20, 0x1100),
117 INTC_VECT(MISTY, 0x1120),
118 INTC_VECT(DDM, 0x1140),
119 INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
120 INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
121 INTC_VECT(RWDT0, 0x1280), INTC_VECT(RWDT1, 0x12a0),
122 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
123 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
124 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
125 INTC_VECT(DMAC_2_DADERR, 0x20c0),
126 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
127 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
128 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
129 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
130 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
131 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
132 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
133 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
134};
135
136static struct intc_group intca_groups[] __initdata = {
137 INTC_GROUP(DMAC_1, DMAC_1_DEI0,
138 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
139 INTC_GROUP(DMAC_2, DMAC_2_DEI4,
140 DMAC_2_DEI5, DMAC_2_DADERR),
141 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
142 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
143 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
144 DMAC2_2_DEI5, DMAC2_2_DADERR),
145 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
146 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
147 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
148 DMAC3_2_DEI5, DMAC3_2_DADERR),
149 INTC_GROUP(ETM11, ETM11_ACQCMP, ETM11_FULL),
150 INTC_GROUP(ARM11, ARM11_IRQPMU, ARM11_COMMTX, ARM11_COMMTX),
151 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
152 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
153 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
154 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
155};
156
157static struct intc_mask_reg intca_mask_registers[] __initdata = {
158 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
159 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
160 ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
161 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
162 { CRYPT1_ERR, CRYPT2_STD, DIRC, 0,
163 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
164 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
165 { PINT1, PINT2, 0, 0,
166 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
167 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
168 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
169 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
170 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
171 { DDM, 0, 0, 0,
172 0, 0, ETM11_FULL, ETM11_ACQCMP } },
173 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
174 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
175 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
176 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
177 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
178 0, 0, MSIOF2, 0 } },
179 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
180 { DISABLED, ENABLED, ENABLED, ENABLED,
181 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
182 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
183 { DISABLED, ENABLED, ENABLED, ENABLED,
184 TTI20, USBDMAC_USHDMI, SPU, SIU } },
185 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
186 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
187 CMT2, USBHS_USHI1, USBHS_USHI0, 0 } },
188 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
189 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
190 0, 0, 0, 0 } },
191 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
192 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
193 LCRC, MSU_MSU2, IREM, MSU_MSU } },
194 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
195 { 0, 0, TPU0, TPU1,
196 TPU2, TPU3, TPU4, 0 } },
197 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
198 { DISABLED, ENABLED, ENABLED, ENABLED,
199 MISTY, CMT3, RWDT1, RWDT0 } },
200};
201
202static struct intc_prio_reg intca_prio_registers[] __initdata = {
203 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
204 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
205 { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
206 CMT1_CMT11, ARM11 } },
207 { 0xe694000c, 0, 16, 4, /* IPRDA */ { PINT1, PINT2,
208 CMT1_CMT12, TPU4 } },
209 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
210 MFI_MFIM, USBHS } },
211 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
212 0, CMT1_CMT10 } },
213 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
214 SCIFA2, SCIFA3 } },
215 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBDMAC_USHDMI,
216 FLCTL, SDHI0 } },
217 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, MSU_MSU, IIC1 } },
218 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, SIU, TTI20 } },
219 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IREM, SDHI1 } },
220 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, TPU1, TPU2, TPU3 } },
221 { 0xe6940030, 0, 16, 4, /* IPRMA */ { MISTY, CMT3, RWDT1, RWDT0 } },
222 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, SPU, DDM } },
223 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
224};
225
226static struct intc_desc intca_desc __initdata = {
227 .name = "sh7367-intca",
228 .force_enable = ENABLED,
229 .force_disable = DISABLED,
230 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
231 intca_mask_registers, intca_prio_registers,
232 NULL, NULL),
233};
234
235INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
236 INTC_VECT, "sh7367-intca-irq-pins");
237
238enum {
239 UNUSED_INTCS = 0,
240
241 INTCS,
242
243 /* interrupt sources INTCS */
244 VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3,
245 VIO3_VOU,
246 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
247 VIO1_CEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2,
248 VPU,
249 SGX530,
250 _2DDMAC_2DDM0, _2DDMAC_2DDM1, _2DDMAC_2DDM2, _2DDMAC_2DDM3,
251 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
252 IPMMU_IPMMUB, IPMMU_IPMMUS,
253 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
254 MSIOF,
255 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
256 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
257 CMT,
258 TSIF,
259 IPMMUI,
260 MVI3,
261 ICB,
262 PEP,
263 ASA,
264 BEM,
265 VE2HO,
266 HQE,
267 JPEG,
268 LCDC,
269
270 /* interrupt groups INTCS */
271 _2DDMAC, RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
272};
273
274static struct intc_vect intcs_vectors[] = {
275 INTCS_VECT(VIO2_VEU0, 0x700), INTCS_VECT(VIO2_VEU1, 0x720),
276 INTCS_VECT(VIO2_VEU2, 0x740), INTCS_VECT(VIO2_VEU3, 0x760),
277 INTCS_VECT(VIO3_VOU, 0x780),
278 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
279 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
280 INTCS_VECT(VIO1_CEU, 0x880), INTCS_VECT(VIO1_BEU0, 0x8a0),
281 INTCS_VECT(VIO1_BEU1, 0x8c0), INTCS_VECT(VIO1_BEU2, 0x8e0),
282 INTCS_VECT(VPU, 0x980),
283 INTCS_VECT(SGX530, 0x9e0),
284 INTCS_VECT(_2DDMAC_2DDM0, 0xa00), INTCS_VECT(_2DDMAC_2DDM1, 0xa20),
285 INTCS_VECT(_2DDMAC_2DDM2, 0xa40), INTCS_VECT(_2DDMAC_2DDM3, 0xa60),
286 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
287 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
288 INTCS_VECT(IPMMU_IPMMUB, 0xb20), INTCS_VECT(IPMMU_IPMMUS, 0xb60),
289 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
290 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
291 INTCS_VECT(MSIOF, 0xd20),
292 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
293 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
294 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
295 INTCS_VECT(TMU_TUNI2, 0xec0),
296 INTCS_VECT(CMT, 0xf00),
297 INTCS_VECT(TSIF, 0xf20),
298 INTCS_VECT(IPMMUI, 0xf60),
299 INTCS_VECT(MVI3, 0x420),
300 INTCS_VECT(ICB, 0x480),
301 INTCS_VECT(PEP, 0x4a0),
302 INTCS_VECT(ASA, 0x4c0),
303 INTCS_VECT(BEM, 0x4e0),
304 INTCS_VECT(VE2HO, 0x520),
305 INTCS_VECT(HQE, 0x540),
306 INTCS_VECT(JPEG, 0x560),
307 INTCS_VECT(LCDC, 0x580),
308
309 INTC_VECT(INTCS, 0xf80),
310};
311
312static struct intc_group intcs_groups[] __initdata = {
313 INTC_GROUP(_2DDMAC, _2DDMAC_2DDM0, _2DDMAC_2DDM1,
314 _2DDMAC_2DDM2, _2DDMAC_2DDM3),
315 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
316 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
317 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
318 INTC_GROUP(VEU, VIO2_VEU0, VIO2_VEU1, VIO2_VEU2, VIO2_VEU3),
319 INTC_GROUP(BEU, VIO1_BEU0, VIO1_BEU1, VIO1_BEU2),
320 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
321 INTC_GROUP(IPMMU, IPMMU_IPMMUS, IPMMU_IPMMUB),
322 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
323};
324
325static struct intc_mask_reg intcs_mask_registers[] = {
326 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
327 { VIO1_BEU2, VIO1_BEU1, VIO1_BEU0, VIO1_CEU,
328 VIO2_VEU3, VIO2_VEU2, VIO2_VEU1, VIO2_VEU0 } },
329 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
330 { VIO3_VOU, 0, VE2HO, VPU,
331 0, 0, 0, 0 } },
332 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
333 { _2DDMAC_2DDM3, _2DDMAC_2DDM2, _2DDMAC_2DDM1, _2DDMAC_2DDM0,
334 BEM, ASA, PEP, ICB } },
335 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
336 { 0, 0, MVI3, 0,
337 JPEG, HQE, 0, LCDC } },
338 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
339 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
340 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
341 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
342 { 0, 0, MSIOF, 0,
343 SGX530, 0, 0, 0 } },
344 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
345 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
346 0, 0, 0, 0 } },
347 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
348 { 0, 0, 0, CMT,
349 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
350 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
351 { IPMMU_IPMMUS, 0, IPMMU_IPMMUB, 0,
352 0, 0, 0, 0 } },
353 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
354 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
355 0, 0, IPMMUI, TSIF } },
356 { 0xffd20104, 0, 16, /* INTAMASK */
357 { 0, 0, 0, 0, 0, 0, 0, 0,
358 0, 0, 0, 0, 0, 0, 0, INTCS } },
359};
360
361/* Priority is needed for INTCA to receive the INTCS interrupt */
362static struct intc_prio_reg intcs_prio_registers[] = {
363 { 0xffd20000, 0, 16, 4, /* IPRAS */ { 0, MVI3, _2DDMAC, ICB } },
364 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPEG, LCDC, 0, 0 } },
365 { 0xffd20008, 0, 16, 4, /* IPRCS */ { BBIF2, 0, 0, 0 } },
366 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, VIO1_CEU, 0, VPU } },
367 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT } },
368 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
369 TMU_TUNI2, 0 } },
370 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, VIO3_VOU, VEU, BEU } },
371 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF, IIC0 } },
372 { 0xffd20024, 0, 16, 4, /* IPRJS */ { 0, SGX530, 0, 0 } },
373 { 0xffd20028, 0, 16, 4, /* IPRKS */ { BEM, ASA, IPMMUI, PEP } },
374 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, VE2HO, HQE } },
375 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
376};
377
378static struct resource intcs_resources[] __initdata = {
379 [0] = {
380 .start = 0xffd20000,
381 .end = 0xffd2ffff,
382 .flags = IORESOURCE_MEM,
383 }
384};
385
386static struct intc_desc intcs_desc __initdata = {
387 .name = "sh7367-intcs",
388 .resource = intcs_resources,
389 .num_resources = ARRAY_SIZE(intcs_resources),
390 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
391 intcs_prio_registers, NULL, NULL),
392};
393
394static void intcs_demux(unsigned int irq, struct irq_desc *desc)
395{
396 void __iomem *reg = (void *)irq_get_handler_data(irq);
397 unsigned int evtcodeas = ioread32(reg);
398
399 generic_handle_irq(intcs_evt2irq(evtcodeas));
400}
401
402void __init sh7367_init_irq(void)
403{
404 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
405
406 register_intc_controller(&intca_desc);
407 register_intc_controller(&intca_irq_pins_desc);
408 register_intc_controller(&intcs_desc);
409
410 /* demux using INTEVTSA */
411 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
412 irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
413}
diff --git a/arch/arm/mach-shmobile/pfc-sh7367.c b/arch/arm/mach-shmobile/pfc-sh7367.c
deleted file mode 100644
index c0c137f39052..000000000000
--- a/arch/arm/mach-shmobile/pfc-sh7367.c
+++ /dev/null
@@ -1,1727 +0,0 @@
1/*
2 * sh7367 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/sh_pfc.h>
22#include <mach/sh7367.h>
23
24#define CPU_ALL_PORT(fn, pfx, sfx) \
25 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
26 PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
27 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
28 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
29 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
30 PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx), \
31 PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
32
33enum {
34 PINMUX_RESERVED = 0,
35
36 PINMUX_DATA_BEGIN,
37 PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
38 PINMUX_DATA_END,
39
40 PINMUX_INPUT_BEGIN,
41 PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
42 PINMUX_INPUT_END,
43
44 PINMUX_INPUT_PULLUP_BEGIN,
45 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
46 PINMUX_INPUT_PULLUP_END,
47
48 PINMUX_INPUT_PULLDOWN_BEGIN,
49 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
50 PINMUX_INPUT_PULLDOWN_END,
51
52 PINMUX_OUTPUT_BEGIN,
53 PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
54 PINMUX_OUTPUT_END,
55
56 PINMUX_FUNCTION_BEGIN,
57 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
58 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
59 PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
60 PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
61 PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
62 PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
63 PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
64 PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
65 PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
66 PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
67
68 MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
69 PINMUX_FUNCTION_END,
70
71 PINMUX_MARK_BEGIN,
72 /* Special Pull-up / Pull-down Functions */
73 PORT48_KEYIN0_PU_MARK, PORT49_KEYIN1_PU_MARK,
74 PORT50_KEYIN2_PU_MARK, PORT55_KEYIN3_PU_MARK,
75 PORT56_KEYIN4_PU_MARK, PORT57_KEYIN5_PU_MARK,
76 PORT58_KEYIN6_PU_MARK,
77
78 /* 49-1 */
79 VBUS0_MARK, CPORT0_MARK, CPORT1_MARK, CPORT2_MARK,
80 CPORT3_MARK, CPORT4_MARK, CPORT5_MARK, CPORT6_MARK,
81 CPORT7_MARK, CPORT8_MARK, CPORT9_MARK, CPORT10_MARK,
82 CPORT11_MARK, SIN2_MARK, CPORT12_MARK, XCTS2_MARK,
83 CPORT13_MARK, RFSPO4_MARK, CPORT14_MARK, RFSPO5_MARK,
84 CPORT15_MARK, CPORT16_MARK, CPORT17_MARK, SOUT2_MARK,
85 CPORT18_MARK, XRTS2_MARK, CPORT19_MARK, CPORT20_MARK,
86 RFSPO6_MARK, CPORT21_MARK, STATUS0_MARK, CPORT22_MARK,
87 STATUS1_MARK, CPORT23_MARK, STATUS2_MARK, RFSPO7_MARK,
88 MPORT0_MARK, MPORT1_MARK, B_SYNLD1_MARK, B_SYNLD2_MARK,
89 XMAINPS_MARK, XDIVPS_MARK, XIDRST_MARK, IDCLK_MARK,
90 IDIO_MARK, SOUT1_MARK, SCIFA4_TXD_MARK,
91 M02_BERDAT_MARK, SIN1_MARK, SCIFA4_RXD_MARK, XWUP_MARK,
92 XRTS1_MARK, SCIFA4_RTS_MARK, M03_BERCLK_MARK,
93 XCTS1_MARK, SCIFA4_CTS_MARK,
94
95 /* 49-2 */
96 HSU_IQ_AGC6_MARK, MFG2_IN2_MARK, MSIOF2_MCK0_MARK,
97 HSU_IQ_AGC5_MARK, MFG2_IN1_MARK, MSIOF2_MCK1_MARK,
98 HSU_IQ_AGC4_MARK, MSIOF2_RSYNC_MARK,
99 HSU_IQ_AGC3_MARK, MFG2_OUT1_MARK, MSIOF2_RSCK_MARK,
100 HSU_IQ_AGC2_MARK, PORT42_KEYOUT0_MARK,
101 HSU_IQ_AGC1_MARK, PORT43_KEYOUT1_MARK,
102 HSU_IQ_AGC0_MARK, PORT44_KEYOUT2_MARK,
103 HSU_IQ_AGC_ST_MARK, PORT45_KEYOUT3_MARK,
104 HSU_IQ_PDO_MARK, PORT46_KEYOUT4_MARK,
105 HSU_IQ_PYO_MARK, PORT47_KEYOUT5_MARK,
106 HSU_EN_TXMUX_G3MO_MARK, PORT48_KEYIN0_MARK,
107 HSU_I_TXMUX_G3MO_MARK, PORT49_KEYIN1_MARK,
108 HSU_Q_TXMUX_G3MO_MARK, PORT50_KEYIN2_MARK,
109 HSU_SYO_MARK, PORT51_MSIOF2_TSYNC_MARK,
110 HSU_SDO_MARK, PORT52_MSIOF2_TSCK_MARK,
111 HSU_TGTTI_G3MO_MARK, PORT53_MSIOF2_TXD_MARK,
112 B_TIME_STAMP_MARK, PORT54_MSIOF2_RXD_MARK,
113 HSU_SDI_MARK, PORT55_KEYIN3_MARK,
114 HSU_SCO_MARK, PORT56_KEYIN4_MARK,
115 HSU_DREQ_MARK, PORT57_KEYIN5_MARK,
116 HSU_DACK_MARK, PORT58_KEYIN6_MARK,
117 HSU_CLK61M_MARK, PORT59_MSIOF2_SS1_MARK,
118 HSU_XRST_MARK, PORT60_MSIOF2_SS2_MARK,
119 PCMCLKO_MARK, SYNC8KO_MARK, DNPCM_A_MARK, UPPCM_A_MARK,
120 XTALB1L_MARK,
121 GPS_AGC1_MARK, SCIFA0_RTS_MARK,
122 GPS_AGC2_MARK, SCIFA0_SCK_MARK,
123 GPS_AGC3_MARK, SCIFA0_TXD_MARK,
124 GPS_AGC4_MARK, SCIFA0_RXD_MARK,
125 GPS_PWRD_MARK, SCIFA0_CTS_MARK,
126 GPS_IM_MARK, GPS_IS_MARK, GPS_QM_MARK, GPS_QS_MARK,
127 SIUBOMC_MARK, TPU2TO0_MARK,
128 SIUCKB_MARK, TPU2TO1_MARK,
129 SIUBOLR_MARK, BBIF2_TSYNC_MARK, TPU2TO2_MARK,
130 SIUBOBT_MARK, BBIF2_TSCK_MARK, TPU2TO3_MARK,
131 SIUBOSLD_MARK, BBIF2_TXD_MARK, TPU3TO0_MARK,
132 SIUBILR_MARK, TPU3TO1_MARK,
133 SIUBIBT_MARK, TPU3TO2_MARK,
134 SIUBISLD_MARK, TPU3TO3_MARK,
135 NMI_MARK, TPU4TO0_MARK,
136 DNPCM_M_MARK, TPU4TO1_MARK, TPU4TO2_MARK, TPU4TO3_MARK,
137 IRQ_TMPB_MARK,
138 PWEN_MARK, MFG1_OUT1_MARK,
139 OVCN_MARK, MFG1_IN1_MARK,
140 OVCN2_MARK, MFG1_IN2_MARK,
141
142 /* 49-3 */
143 RFSPO1_MARK, RFSPO2_MARK, RFSPO3_MARK, PORT93_VIO_CKO2_MARK,
144 USBTERM_MARK, EXTLP_MARK, IDIN_MARK,
145 SCIFA5_CTS_MARK, MFG0_IN1_MARK,
146 SCIFA5_RTS_MARK, MFG0_IN2_MARK,
147 SCIFA5_RXD_MARK,
148 SCIFA5_TXD_MARK,
149 SCIFA5_SCK_MARK, MFG0_OUT1_MARK,
150 A0_EA0_MARK, BS_MARK,
151 A14_EA14_MARK, PORT102_KEYOUT0_MARK,
152 A15_EA15_MARK, PORT103_KEYOUT1_MARK, DV_CLKOL_MARK,
153 A16_EA16_MARK, PORT104_KEYOUT2_MARK,
154 DV_VSYNCL_MARK, MSIOF0_SS1_MARK,
155 A17_EA17_MARK, PORT105_KEYOUT3_MARK,
156 DV_HSYNCL_MARK, MSIOF0_TSYNC_MARK,
157 A18_EA18_MARK, PORT106_KEYOUT4_MARK,
158 DV_DL0_MARK, MSIOF0_TSCK_MARK,
159 A19_EA19_MARK, PORT107_KEYOUT5_MARK,
160 DV_DL1_MARK, MSIOF0_TXD_MARK,
161 A20_EA20_MARK, PORT108_KEYIN0_MARK,
162 DV_DL2_MARK, MSIOF0_RSCK_MARK,
163 A21_EA21_MARK, PORT109_KEYIN1_MARK,
164 DV_DL3_MARK, MSIOF0_RSYNC_MARK,
165 A22_EA22_MARK, PORT110_KEYIN2_MARK,
166 DV_DL4_MARK, MSIOF0_MCK0_MARK,
167 A23_EA23_MARK, PORT111_KEYIN3_MARK,
168 DV_DL5_MARK, MSIOF0_MCK1_MARK,
169 A24_EA24_MARK, PORT112_KEYIN4_MARK,
170 DV_DL6_MARK, MSIOF0_RXD_MARK,
171 A25_EA25_MARK, PORT113_KEYIN5_MARK,
172 DV_DL7_MARK, MSIOF0_SS2_MARK,
173 A26_MARK, PORT113_KEYIN6_MARK, DV_CLKIL_MARK,
174 D0_ED0_NAF0_MARK, D1_ED1_NAF1_MARK, D2_ED2_NAF2_MARK,
175 D3_ED3_NAF3_MARK, D4_ED4_NAF4_MARK, D5_ED5_NAF5_MARK,
176 D6_ED6_NAF6_MARK, D7_ED7_NAF7_MARK, D8_ED8_NAF8_MARK,
177 D9_ED9_NAF9_MARK, D10_ED10_NAF10_MARK, D11_ED11_NAF11_MARK,
178 D12_ED12_NAF12_MARK, D13_ED13_NAF13_MARK,
179 D14_ED14_NAF14_MARK, D15_ED15_NAF15_MARK,
180 CS4_MARK, CS5A_MARK, CS5B_MARK, FCE1_MARK,
181 CS6B_MARK, XCS2_MARK, FCE0_MARK, CS6A_MARK,
182 DACK0_MARK, WAIT_MARK, DREQ0_MARK, RD_XRD_MARK,
183 A27_MARK, RDWR_XWE_MARK, WE0_XWR0_FWE_MARK,
184 WE1_XWR1_MARK, FRB_MARK, CKO_MARK,
185 NBRSTOUT_MARK, NBRST_MARK,
186
187 /* 49-4 */
188 RFSPO0_MARK, PORT146_VIO_CKO2_MARK, TSTMD_MARK,
189 VIO_VD_MARK, VIO_HD_MARK,
190 VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK,
191 VIO_D3_MARK, VIO_D4_MARK, VIO_D5_MARK,
192 VIO_D6_MARK, VIO_D7_MARK, VIO_D8_MARK,
193 VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
194 VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK,
195 VIO_D15_MARK, VIO_CLK_MARK, VIO_FIELD_MARK,
196 VIO_CKO_MARK,
197 MFG3_IN1_MARK, MFG3_IN2_MARK,
198 M9_SLCD_A01_MARK, MFG3_OUT1_MARK, TPU0TO0_MARK,
199 M10_SLCD_CK1_MARK, MFG4_IN1_MARK, TPU0TO1_MARK,
200 M11_SLCD_SO1_MARK, MFG4_IN2_MARK, TPU0TO2_MARK,
201 M12_SLCD_CE1_MARK, MFG4_OUT1_MARK, TPU0TO3_MARK,
202 LCDD0_MARK, PORT175_KEYOUT0_MARK, DV_D0_MARK,
203 SIUCKA_MARK, MFG0_OUT2_MARK,
204 LCDD1_MARK, PORT176_KEYOUT1_MARK, DV_D1_MARK,
205 SIUAOLR_MARK, BBIF2_TSYNC1_MARK,
206 LCDD2_MARK, PORT177_KEYOUT2_MARK, DV_D2_MARK,
207 SIUAOBT_MARK, BBIF2_TSCK1_MARK,
208 LCDD3_MARK, PORT178_KEYOUT3_MARK, DV_D3_MARK,
209 SIUAOSLD_MARK, BBIF2_TXD1_MARK,
210 LCDD4_MARK, PORT179_KEYOUT4_MARK, DV_D4_MARK,
211 SIUAISPD_MARK, MFG1_OUT2_MARK,
212 LCDD5_MARK, PORT180_KEYOUT5_MARK, DV_D5_MARK,
213 SIUAILR_MARK, MFG2_OUT2_MARK,
214 LCDD6_MARK, DV_D6_MARK,
215 SIUAIBT_MARK, MFG3_OUT2_MARK, XWR2_MARK,
216 LCDD7_MARK, DV_D7_MARK,
217 SIUAISLD_MARK, MFG4_OUT2_MARK, XWR3_MARK,
218 LCDD8_MARK, DV_D8_MARK, D16_MARK, ED16_MARK,
219 LCDD9_MARK, DV_D9_MARK, D17_MARK, ED17_MARK,
220 LCDD10_MARK, DV_D10_MARK, D18_MARK, ED18_MARK,
221 LCDD11_MARK, DV_D11_MARK, D19_MARK, ED19_MARK,
222 LCDD12_MARK, DV_D12_MARK, D20_MARK, ED20_MARK,
223 LCDD13_MARK, DV_D13_MARK, D21_MARK, ED21_MARK,
224 LCDD14_MARK, DV_D14_MARK, D22_MARK, ED22_MARK,
225 LCDD15_MARK, DV_D15_MARK, D23_MARK, ED23_MARK,
226 LCDD16_MARK, DV_HSYNC_MARK, D24_MARK, ED24_MARK,
227 LCDD17_MARK, DV_VSYNC_MARK, D25_MARK, ED25_MARK,
228 LCDD18_MARK, DREQ2_MARK, MSIOF0L_TSCK_MARK,
229 D26_MARK, ED26_MARK,
230 LCDD19_MARK, MSIOF0L_TSYNC_MARK,
231 D27_MARK, ED27_MARK,
232 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK,
233 D28_MARK, ED28_MARK,
234 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK,
235 D29_MARK, ED29_MARK,
236 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_SS1_MARK,
237 D30_MARK, ED30_MARK,
238 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_SS2_MARK,
239 D31_MARK, ED31_MARK,
240 LCDDCK_MARK, LCDWR_MARK, DV_CKO_MARK, SIUAOSPD_MARK,
241 LCDRD_MARK, DACK2_MARK, MSIOF0L_RSYNC_MARK,
242
243 /* 49-5 */
244 LCDHSYN_MARK, LCDCS_MARK, LCDCS2_MARK, DACK3_MARK,
245 LCDDISP_MARK, LCDRS_MARK, DREQ3_MARK, MSIOF0L_RSCK_MARK,
246 LCDCSYN_MARK, LCDCSYN2_MARK, DV_CKI_MARK,
247 LCDLCLK_MARK, DREQ1_MARK, MSIOF0L_RXD_MARK,
248 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, MSIOF0L_TXD_MARK,
249 VIO_DR0_MARK, VIO_DR1_MARK, VIO_DR2_MARK, VIO_DR3_MARK,
250 VIO_DR4_MARK, VIO_DR5_MARK, VIO_DR6_MARK, VIO_DR7_MARK,
251 VIO_VDR_MARK, VIO_HDR_MARK,
252 VIO_CLKR_MARK, VIO_CKOR_MARK,
253 SCIFA1_TXD_MARK, GPS_PGFA0_MARK,
254 SCIFA1_SCK_MARK, GPS_PGFA1_MARK,
255 SCIFA1_RTS_MARK, GPS_EPPSINMON_MARK,
256 SCIFA1_RXD_MARK, SCIFA1_CTS_MARK,
257 MSIOF1_TXD_MARK, SCIFA1_TXD2_MARK, GPS_TXD_MARK,
258 MSIOF1_TSYNC_MARK, SCIFA1_CTS2_MARK, I2C_SDA2_MARK,
259 MSIOF1_TSCK_MARK, SCIFA1_SCK2_MARK,
260 MSIOF1_RXD_MARK, SCIFA1_RXD2_MARK, GPS_RXD_MARK,
261 MSIOF1_RSCK_MARK, SCIFA1_RTS2_MARK,
262 MSIOF1_RSYNC_MARK, I2C_SCL2_MARK,
263 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
264 MSIOF1_SS1_MARK, EDBGREQ3_MARK,
265 MSIOF1_SS2_MARK,
266 PORT236_IROUT_MARK, IRDA_OUT_MARK,
267 IRDA_IN_MARK, IRDA_FIRSEL_MARK,
268 TPU1TO0_MARK, TS_SPSYNC3_MARK,
269 TPU1TO1_MARK, TS_SDAT3_MARK,
270 TPU1TO2_MARK, TS_SDEN3_MARK, PORT241_MSIOF2_SS1_MARK,
271 TPU1TO3_MARK, PORT242_MSIOF2_TSCK_MARK,
272 M13_BSW_MARK, PORT243_MSIOF2_TSYNC_MARK,
273 M14_GSW_MARK, PORT244_MSIOF2_TXD_MARK,
274 PORT245_IROUT_MARK, M15_RSW_MARK,
275 SOUT3_MARK, SCIFA2_TXD1_MARK,
276 SIN3_MARK, SCIFA2_RXD1_MARK,
277 XRTS3_MARK, SCIFA2_RTS1_MARK, PORT248_MSIOF2_SS2_MARK,
278 XCTS3_MARK, SCIFA2_CTS1_MARK, PORT249_MSIOF2_RXD_MARK,
279 DINT_MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
280 SDHICLK0_MARK, TCK2_MARK,
281 SDHICD0_MARK,
282 SDHID0_0_MARK, TMS2_MARK,
283 SDHID0_1_MARK, TDO2_MARK,
284 SDHID0_2_MARK, TDI2_MARK,
285 SDHID0_3_MARK, RTCK2_MARK,
286
287 /* 49-6 */
288 SDHICMD0_MARK, TRST2_MARK,
289 SDHIWP0_MARK, EDBGREQ2_MARK,
290 SDHICLK1_MARK, TCK3_MARK,
291 SDHID1_0_MARK, M11_SLCD_SO2_MARK,
292 TS_SPSYNC2_MARK, TMS3_MARK,
293 SDHID1_1_MARK, M9_SLCD_AO2_MARK,
294 TS_SDAT2_MARK, TDO3_MARK,
295 SDHID1_2_MARK, M10_SLCD_CK2_MARK,
296 TS_SDEN2_MARK, TDI3_MARK,
297 SDHID1_3_MARK, M12_SLCD_CE2_MARK,
298 TS_SCK2_MARK, RTCK3_MARK,
299 SDHICMD1_MARK, TRST3_MARK,
300 SDHICLK2_MARK, SCIFB_SCK_MARK,
301 SDHID2_0_MARK, SCIFB_TXD_MARK,
302 SDHID2_1_MARK, SCIFB_CTS_MARK,
303 SDHID2_2_MARK, SCIFB_RXD_MARK,
304 SDHID2_3_MARK, SCIFB_RTS_MARK,
305 SDHICMD2_MARK,
306 RESETOUTS_MARK,
307 DIVLOCK_MARK,
308 PINMUX_MARK_END,
309};
310
311static pinmux_enum_t pinmux_data[] = {
312
313 /* specify valid pin states for each pin in GPIO mode */
314
315 /* 49-1 (GPIO) */
316 PORT_DATA_I_PD(0),
317 PORT_DATA_I_PU(1), PORT_DATA_I_PU(2), PORT_DATA_I_PU(3),
318 PORT_DATA_I_PU(4), PORT_DATA_I_PU(5), PORT_DATA_I_PU(6),
319 PORT_DATA_I_PU(7), PORT_DATA_I_PU(8), PORT_DATA_I_PU(9),
320 PORT_DATA_I_PU(10), PORT_DATA_I_PU(11), PORT_DATA_I_PU(12),
321 PORT_DATA_I_PU(13),
322 PORT_DATA_IO_PU_PD(14), PORT_DATA_IO_PU_PD(15),
323 PORT_DATA_O(16), PORT_DATA_O(17), PORT_DATA_O(18), PORT_DATA_O(19),
324 PORT_DATA_O(20), PORT_DATA_O(21), PORT_DATA_O(22), PORT_DATA_O(23),
325 PORT_DATA_O(24), PORT_DATA_O(25), PORT_DATA_O(26),
326 PORT_DATA_I_PD(27), PORT_DATA_I_PD(28),
327 PORT_DATA_O(29), PORT_DATA_O(30), PORT_DATA_O(31), PORT_DATA_O(32),
328 PORT_DATA_IO_PU(33),
329 PORT_DATA_O(34),
330 PORT_DATA_I_PU(35),
331 PORT_DATA_O(36),
332 PORT_DATA_I_PU_PD(37),
333
334 /* 49-2 (GPIO) */
335 PORT_DATA_IO_PU_PD(38),
336 PORT_DATA_IO_PD(39), PORT_DATA_IO_PD(40), PORT_DATA_IO_PD(41),
337 PORT_DATA_O(42), PORT_DATA_O(43), PORT_DATA_O(44), PORT_DATA_O(45),
338 PORT_DATA_O(46), PORT_DATA_O(47),
339 PORT_DATA_I_PU_PD(48), PORT_DATA_I_PU_PD(49), PORT_DATA_I_PU_PD(50),
340 PORT_DATA_IO_PD(51), PORT_DATA_IO_PD(52),
341 PORT_DATA_O(53),
342 PORT_DATA_IO_PD(54),
343 PORT_DATA_I_PU_PD(55),
344 PORT_DATA_IO_PU_PD(56),
345 PORT_DATA_I_PU_PD(57),
346 PORT_DATA_IO_PU_PD(58),
347 PORT_DATA_O(59), PORT_DATA_O(60), PORT_DATA_O(61), PORT_DATA_O(62),
348 PORT_DATA_O(63),
349 PORT_DATA_I_PU(64),
350 PORT_DATA_O(65), PORT_DATA_O(66), PORT_DATA_O(67), PORT_DATA_O(68),
351 PORT_DATA_IO_PD(69), PORT_DATA_IO_PD(70),
352 PORT_DATA_I_PD(71), PORT_DATA_I_PD(72), PORT_DATA_I_PD(73),
353 PORT_DATA_I_PD(74),
354 PORT_DATA_IO_PU_PD(75), PORT_DATA_IO_PU_PD(76),
355 PORT_DATA_IO_PD(77), PORT_DATA_IO_PD(78),
356 PORT_DATA_O(79),
357 PORT_DATA_IO_PD(80), PORT_DATA_IO_PD(81), PORT_DATA_IO_PD(82),
358 PORT_DATA_IO_PU_PD(83), PORT_DATA_IO_PU_PD(84),
359 PORT_DATA_IO_PU_PD(85), PORT_DATA_IO_PU_PD(86),
360 PORT_DATA_I_PD(87),
361 PORT_DATA_IO_PU_PD(88),
362 PORT_DATA_I_PU_PD(89), PORT_DATA_I_PU_PD(90),
363
364 /* 49-3 (GPIO) */
365 PORT_DATA_O(91), PORT_DATA_O(92), PORT_DATA_O(93), PORT_DATA_O(94),
366 PORT_DATA_I_PU_PD(95),
367 PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), PORT_DATA_IO_PU_PD(98),
368 PORT_DATA_IO_PU_PD(99), PORT_DATA_IO_PU_PD(100),
369 PORT_DATA_IO(101), PORT_DATA_IO(102), PORT_DATA_IO(103),
370 PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105), PORT_DATA_IO_PD(106),
371 PORT_DATA_IO_PD(107),
372 PORT_DATA_IO_PU_PD(108), PORT_DATA_IO_PU_PD(109),
373 PORT_DATA_IO_PU_PD(110), PORT_DATA_IO_PU_PD(111),
374 PORT_DATA_IO_PU_PD(112), PORT_DATA_IO_PU_PD(113),
375 PORT_DATA_IO_PU_PD(114),
376 PORT_DATA_IO_PU(115), PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
377 PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119), PORT_DATA_IO_PU(120),
378 PORT_DATA_IO_PU(121), PORT_DATA_IO_PU(122), PORT_DATA_IO_PU(123),
379 PORT_DATA_IO_PU(124), PORT_DATA_IO_PU(125), PORT_DATA_IO_PU(126),
380 PORT_DATA_IO_PU(127), PORT_DATA_IO_PU(128), PORT_DATA_IO_PU(129),
381 PORT_DATA_IO_PU(130),
382 PORT_DATA_O(131), PORT_DATA_O(132), PORT_DATA_O(133),
383 PORT_DATA_IO_PU(134),
384 PORT_DATA_O(135), PORT_DATA_O(136),
385 PORT_DATA_I_PU_PD(137),
386 PORT_DATA_IO(138),
387 PORT_DATA_IO_PU_PD(139),
388 PORT_DATA_IO(140), PORT_DATA_IO(141),
389 PORT_DATA_I_PU(142),
390 PORT_DATA_O(143), PORT_DATA_O(144),
391 PORT_DATA_I_PU(145),
392
393 /* 49-4 (GPIO) */
394 PORT_DATA_O(146),
395 PORT_DATA_I_PU_PD(147),
396 PORT_DATA_I_PD(148), PORT_DATA_I_PD(149),
397 PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151), PORT_DATA_IO_PD(152),
398 PORT_DATA_IO_PD(153), PORT_DATA_IO_PD(154), PORT_DATA_IO_PD(155),
399 PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157), PORT_DATA_IO_PD(158),
400 PORT_DATA_IO_PD(159), PORT_DATA_IO_PD(160), PORT_DATA_IO_PD(161),
401 PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), PORT_DATA_IO_PD(164),
402 PORT_DATA_IO_PD(165), PORT_DATA_IO_PD(166),
403 PORT_DATA_IO_PU_PD(167),
404 PORT_DATA_O(168),
405 PORT_DATA_I_PD(169), PORT_DATA_I_PD(170),
406 PORT_DATA_O(171),
407 PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
408 PORT_DATA_O(174),
409 PORT_DATA_IO_PD(175), PORT_DATA_IO_PD(176), PORT_DATA_IO_PD(177),
410 PORT_DATA_IO_PD(178), PORT_DATA_IO_PD(179), PORT_DATA_IO_PD(180),
411 PORT_DATA_IO_PD(181), PORT_DATA_IO_PD(182), PORT_DATA_IO_PD(183),
412 PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), PORT_DATA_IO_PD(186),
413 PORT_DATA_IO_PD(187), PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
414 PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), PORT_DATA_IO_PD(192),
415 PORT_DATA_IO_PD(193), PORT_DATA_IO_PD(194), PORT_DATA_IO_PD(195),
416 PORT_DATA_IO_PD(196), PORT_DATA_IO_PD(197), PORT_DATA_IO_PD(198),
417 PORT_DATA_O(199),
418 PORT_DATA_IO_PD(200),
419
420 /* 49-5 (GPIO) */
421 PORT_DATA_O(201),
422 PORT_DATA_IO_PD(202), PORT_DATA_IO_PD(203),
423 PORT_DATA_I(204),
424 PORT_DATA_O(205),
425 PORT_DATA_IO_PD(206), PORT_DATA_IO_PD(207), PORT_DATA_IO_PD(208),
426 PORT_DATA_IO_PD(209), PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
427 PORT_DATA_IO_PD(212), PORT_DATA_IO_PD(213), PORT_DATA_IO_PD(214),
428 PORT_DATA_IO_PD(215), PORT_DATA_IO_PD(216),
429 PORT_DATA_O(217),
430 PORT_DATA_I_PU_PD(218), PORT_DATA_I_PU_PD(219),
431 PORT_DATA_O(220), PORT_DATA_O(221), PORT_DATA_O(222),
432 PORT_DATA_I_PD(223),
433 PORT_DATA_I_PU_PD(224),
434 PORT_DATA_O(225),
435 PORT_DATA_IO_PD(226),
436 PORT_DATA_IO_PU_PD(227),
437 PORT_DATA_I_PD(228),
438 PORT_DATA_IO_PD(229), PORT_DATA_IO_PD(230),
439 PORT_DATA_I_PU_PD(231), PORT_DATA_I_PU_PD(232),
440 PORT_DATA_IO_PU_PD(233), PORT_DATA_IO_PU_PD(234),
441 PORT_DATA_I_PU_PD(235),
442 PORT_DATA_O(236),
443 PORT_DATA_I_PD(237),
444 PORT_DATA_IO_PU_PD(238), PORT_DATA_IO_PU_PD(239),
445 PORT_DATA_IO_PD(240), PORT_DATA_IO_PD(241),
446 PORT_DATA_IO_PD(242), PORT_DATA_IO_PD(243),
447 PORT_DATA_O(244),
448 PORT_DATA_IO_PU_PD(245),
449 PORT_DATA_O(246),
450 PORT_DATA_I_PD(247),
451 PORT_DATA_IO_PU_PD(248),
452 PORT_DATA_I_PU_PD(249),
453 PORT_DATA_IO_PD(250), PORT_DATA_IO_PD(251),
454 PORT_DATA_IO_PU_PD(252), PORT_DATA_IO_PU_PD(253),
455 PORT_DATA_IO_PU_PD(254), PORT_DATA_IO_PU_PD(255),
456 PORT_DATA_IO_PU_PD(256),
457
458 /* 49-6 (GPIO) */
459 PORT_DATA_IO_PU_PD(257), PORT_DATA_IO_PU_PD(258),
460 PORT_DATA_IO_PD(259),
461 PORT_DATA_IO_PU(260), PORT_DATA_IO_PU(261), PORT_DATA_IO_PU(262),
462 PORT_DATA_IO_PU(263), PORT_DATA_IO_PU(264),
463 PORT_DATA_O(265),
464 PORT_DATA_IO_PU(266), PORT_DATA_IO_PU(267), PORT_DATA_IO_PU(268),
465 PORT_DATA_IO_PU(269), PORT_DATA_IO_PU(270),
466 PORT_DATA_O(271),
467 PORT_DATA_I_PD(272),
468
469 /* Special Pull-up / Pull-down Functions */
470 PINMUX_DATA(PORT48_KEYIN0_PU_MARK, MSELBCR_MSEL2_1,
471 PORT48_FN2, PORT48_IN_PU),
472 PINMUX_DATA(PORT49_KEYIN1_PU_MARK, MSELBCR_MSEL2_1,
473 PORT49_FN2, PORT49_IN_PU),
474 PINMUX_DATA(PORT50_KEYIN2_PU_MARK, MSELBCR_MSEL2_1,
475 PORT50_FN2, PORT50_IN_PU),
476 PINMUX_DATA(PORT55_KEYIN3_PU_MARK, MSELBCR_MSEL2_1,
477 PORT55_FN2, PORT55_IN_PU),
478 PINMUX_DATA(PORT56_KEYIN4_PU_MARK, MSELBCR_MSEL2_1,
479 PORT56_FN2, PORT56_IN_PU),
480 PINMUX_DATA(PORT57_KEYIN5_PU_MARK, MSELBCR_MSEL2_1,
481 PORT57_FN2, PORT57_IN_PU),
482 PINMUX_DATA(PORT58_KEYIN6_PU_MARK, MSELBCR_MSEL2_1,
483 PORT58_FN2, PORT58_IN_PU),
484
485 /* 49-1 (FN) */
486 PINMUX_DATA(VBUS0_MARK, PORT0_FN1),
487 PINMUX_DATA(CPORT0_MARK, PORT1_FN1),
488 PINMUX_DATA(CPORT1_MARK, PORT2_FN1),
489 PINMUX_DATA(CPORT2_MARK, PORT3_FN1),
490 PINMUX_DATA(CPORT3_MARK, PORT4_FN1),
491 PINMUX_DATA(CPORT4_MARK, PORT5_FN1),
492 PINMUX_DATA(CPORT5_MARK, PORT6_FN1),
493 PINMUX_DATA(CPORT6_MARK, PORT7_FN1),
494 PINMUX_DATA(CPORT7_MARK, PORT8_FN1),
495 PINMUX_DATA(CPORT8_MARK, PORT9_FN1),
496 PINMUX_DATA(CPORT9_MARK, PORT10_FN1),
497 PINMUX_DATA(CPORT10_MARK, PORT11_FN1),
498 PINMUX_DATA(CPORT11_MARK, PORT12_FN1),
499 PINMUX_DATA(SIN2_MARK, PORT12_FN2),
500 PINMUX_DATA(CPORT12_MARK, PORT13_FN1),
501 PINMUX_DATA(XCTS2_MARK, PORT13_FN2),
502 PINMUX_DATA(CPORT13_MARK, PORT14_FN1),
503 PINMUX_DATA(RFSPO4_MARK, PORT14_FN2),
504 PINMUX_DATA(CPORT14_MARK, PORT15_FN1),
505 PINMUX_DATA(RFSPO5_MARK, PORT15_FN2),
506 PINMUX_DATA(CPORT15_MARK, PORT16_FN1),
507 PINMUX_DATA(CPORT16_MARK, PORT17_FN1),
508 PINMUX_DATA(CPORT17_MARK, PORT18_FN1),
509 PINMUX_DATA(SOUT2_MARK, PORT18_FN2),
510 PINMUX_DATA(CPORT18_MARK, PORT19_FN1),
511 PINMUX_DATA(XRTS2_MARK, PORT19_FN1),
512 PINMUX_DATA(CPORT19_MARK, PORT20_FN1),
513 PINMUX_DATA(CPORT20_MARK, PORT21_FN1),
514 PINMUX_DATA(RFSPO6_MARK, PORT21_FN2),
515 PINMUX_DATA(CPORT21_MARK, PORT22_FN1),
516 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
517 PINMUX_DATA(CPORT22_MARK, PORT23_FN1),
518 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
519 PINMUX_DATA(CPORT23_MARK, PORT24_FN1),
520 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
521 PINMUX_DATA(RFSPO7_MARK, PORT24_FN3),
522 PINMUX_DATA(MPORT0_MARK, PORT25_FN1),
523 PINMUX_DATA(MPORT1_MARK, PORT26_FN1),
524 PINMUX_DATA(B_SYNLD1_MARK, PORT27_FN1),
525 PINMUX_DATA(B_SYNLD2_MARK, PORT28_FN1),
526 PINMUX_DATA(XMAINPS_MARK, PORT29_FN1),
527 PINMUX_DATA(XDIVPS_MARK, PORT30_FN1),
528 PINMUX_DATA(XIDRST_MARK, PORT31_FN1),
529 PINMUX_DATA(IDCLK_MARK, PORT32_FN1),
530 PINMUX_DATA(IDIO_MARK, PORT33_FN1),
531 PINMUX_DATA(SOUT1_MARK, PORT34_FN1),
532 PINMUX_DATA(SCIFA4_TXD_MARK, PORT34_FN2),
533 PINMUX_DATA(M02_BERDAT_MARK, PORT34_FN3),
534 PINMUX_DATA(SIN1_MARK, PORT35_FN1),
535 PINMUX_DATA(SCIFA4_RXD_MARK, PORT35_FN2),
536 PINMUX_DATA(XWUP_MARK, PORT35_FN3),
537 PINMUX_DATA(XRTS1_MARK, PORT36_FN1),
538 PINMUX_DATA(SCIFA4_RTS_MARK, PORT36_FN2),
539 PINMUX_DATA(M03_BERCLK_MARK, PORT36_FN3),
540 PINMUX_DATA(XCTS1_MARK, PORT37_FN1),
541 PINMUX_DATA(SCIFA4_CTS_MARK, PORT37_FN2),
542
543 /* 49-2 (FN) */
544 PINMUX_DATA(HSU_IQ_AGC6_MARK, PORT38_FN1),
545 PINMUX_DATA(MFG2_IN2_MARK, PORT38_FN2),
546 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT38_FN3),
547 PINMUX_DATA(HSU_IQ_AGC5_MARK, PORT39_FN1),
548 PINMUX_DATA(MFG2_IN1_MARK, PORT39_FN2),
549 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT39_FN3),
550 PINMUX_DATA(HSU_IQ_AGC4_MARK, PORT40_FN1),
551 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT40_FN3),
552 PINMUX_DATA(HSU_IQ_AGC3_MARK, PORT41_FN1),
553 PINMUX_DATA(MFG2_OUT1_MARK, PORT41_FN2),
554 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT41_FN3),
555 PINMUX_DATA(HSU_IQ_AGC2_MARK, PORT42_FN1),
556 PINMUX_DATA(PORT42_KEYOUT0_MARK, MSELBCR_MSEL2_1, PORT42_FN2),
557 PINMUX_DATA(HSU_IQ_AGC1_MARK, PORT43_FN1),
558 PINMUX_DATA(PORT43_KEYOUT1_MARK, MSELBCR_MSEL2_1, PORT43_FN2),
559 PINMUX_DATA(HSU_IQ_AGC0_MARK, PORT44_FN1),
560 PINMUX_DATA(PORT44_KEYOUT2_MARK, MSELBCR_MSEL2_1, PORT44_FN2),
561 PINMUX_DATA(HSU_IQ_AGC_ST_MARK, PORT45_FN1),
562 PINMUX_DATA(PORT45_KEYOUT3_MARK, MSELBCR_MSEL2_1, PORT45_FN2),
563 PINMUX_DATA(HSU_IQ_PDO_MARK, PORT46_FN1),
564 PINMUX_DATA(PORT46_KEYOUT4_MARK, MSELBCR_MSEL2_1, PORT46_FN2),
565 PINMUX_DATA(HSU_IQ_PYO_MARK, PORT47_FN1),
566 PINMUX_DATA(PORT47_KEYOUT5_MARK, MSELBCR_MSEL2_1, PORT47_FN2),
567 PINMUX_DATA(HSU_EN_TXMUX_G3MO_MARK, PORT48_FN1),
568 PINMUX_DATA(PORT48_KEYIN0_MARK, MSELBCR_MSEL2_1, PORT48_FN2),
569 PINMUX_DATA(HSU_I_TXMUX_G3MO_MARK, PORT49_FN1),
570 PINMUX_DATA(PORT49_KEYIN1_MARK, MSELBCR_MSEL2_1, PORT49_FN2),
571 PINMUX_DATA(HSU_Q_TXMUX_G3MO_MARK, PORT50_FN1),
572 PINMUX_DATA(PORT50_KEYIN2_MARK, MSELBCR_MSEL2_1, PORT50_FN2),
573 PINMUX_DATA(HSU_SYO_MARK, PORT51_FN1),
574 PINMUX_DATA(PORT51_MSIOF2_TSYNC_MARK, PORT51_FN2),
575 PINMUX_DATA(HSU_SDO_MARK, PORT52_FN1),
576 PINMUX_DATA(PORT52_MSIOF2_TSCK_MARK, PORT52_FN2),
577 PINMUX_DATA(HSU_TGTTI_G3MO_MARK, PORT53_FN1),
578 PINMUX_DATA(PORT53_MSIOF2_TXD_MARK, PORT53_FN2),
579 PINMUX_DATA(B_TIME_STAMP_MARK, PORT54_FN1),
580 PINMUX_DATA(PORT54_MSIOF2_RXD_MARK, PORT54_FN2),
581 PINMUX_DATA(HSU_SDI_MARK, PORT55_FN1),
582 PINMUX_DATA(PORT55_KEYIN3_MARK, MSELBCR_MSEL2_1, PORT55_FN2),
583 PINMUX_DATA(HSU_SCO_MARK, PORT56_FN1),
584 PINMUX_DATA(PORT56_KEYIN4_MARK, MSELBCR_MSEL2_1, PORT56_FN2),
585 PINMUX_DATA(HSU_DREQ_MARK, PORT57_FN1),
586 PINMUX_DATA(PORT57_KEYIN5_MARK, MSELBCR_MSEL2_1, PORT57_FN2),
587 PINMUX_DATA(HSU_DACK_MARK, PORT58_FN1),
588 PINMUX_DATA(PORT58_KEYIN6_MARK, MSELBCR_MSEL2_1, PORT58_FN2),
589 PINMUX_DATA(HSU_CLK61M_MARK, PORT59_FN1),
590 PINMUX_DATA(PORT59_MSIOF2_SS1_MARK, PORT59_FN2),
591 PINMUX_DATA(HSU_XRST_MARK, PORT60_FN1),
592 PINMUX_DATA(PORT60_MSIOF2_SS2_MARK, PORT60_FN2),
593 PINMUX_DATA(PCMCLKO_MARK, PORT61_FN1),
594 PINMUX_DATA(SYNC8KO_MARK, PORT62_FN1),
595 PINMUX_DATA(DNPCM_A_MARK, PORT63_FN1),
596 PINMUX_DATA(UPPCM_A_MARK, PORT64_FN1),
597 PINMUX_DATA(XTALB1L_MARK, PORT65_FN1),
598 PINMUX_DATA(GPS_AGC1_MARK, PORT66_FN1),
599 PINMUX_DATA(SCIFA0_RTS_MARK, PORT66_FN2),
600 PINMUX_DATA(GPS_AGC2_MARK, PORT67_FN1),
601 PINMUX_DATA(SCIFA0_SCK_MARK, PORT67_FN2),
602 PINMUX_DATA(GPS_AGC3_MARK, PORT68_FN1),
603 PINMUX_DATA(SCIFA0_TXD_MARK, PORT68_FN2),
604 PINMUX_DATA(GPS_AGC4_MARK, PORT69_FN1),
605 PINMUX_DATA(SCIFA0_RXD_MARK, PORT69_FN2),
606 PINMUX_DATA(GPS_PWRD_MARK, PORT70_FN1),
607 PINMUX_DATA(SCIFA0_CTS_MARK, PORT70_FN2),
608 PINMUX_DATA(GPS_IM_MARK, PORT71_FN1),
609 PINMUX_DATA(GPS_IS_MARK, PORT72_FN1),
610 PINMUX_DATA(GPS_QM_MARK, PORT73_FN1),
611 PINMUX_DATA(GPS_QS_MARK, PORT74_FN1),
612 PINMUX_DATA(SIUBOMC_MARK, PORT75_FN1),
613 PINMUX_DATA(TPU2TO0_MARK, PORT75_FN3),
614 PINMUX_DATA(SIUCKB_MARK, PORT76_FN1),
615 PINMUX_DATA(TPU2TO1_MARK, PORT76_FN3),
616 PINMUX_DATA(SIUBOLR_MARK, PORT77_FN1),
617 PINMUX_DATA(BBIF2_TSYNC_MARK, PORT77_FN2),
618 PINMUX_DATA(TPU2TO2_MARK, PORT77_FN3),
619 PINMUX_DATA(SIUBOBT_MARK, PORT78_FN1),
620 PINMUX_DATA(BBIF2_TSCK_MARK, PORT78_FN2),
621 PINMUX_DATA(TPU2TO3_MARK, PORT78_FN3),
622 PINMUX_DATA(SIUBOSLD_MARK, PORT79_FN1),
623 PINMUX_DATA(BBIF2_TXD_MARK, PORT79_FN2),
624 PINMUX_DATA(TPU3TO0_MARK, PORT79_FN3),
625 PINMUX_DATA(SIUBILR_MARK, PORT80_FN1),
626 PINMUX_DATA(TPU3TO1_MARK, PORT80_FN3),
627 PINMUX_DATA(SIUBIBT_MARK, PORT81_FN1),
628 PINMUX_DATA(TPU3TO2_MARK, PORT81_FN3),
629 PINMUX_DATA(SIUBISLD_MARK, PORT82_FN1),
630 PINMUX_DATA(TPU3TO3_MARK, PORT82_FN3),
631 PINMUX_DATA(NMI_MARK, PORT83_FN1),
632 PINMUX_DATA(TPU4TO0_MARK, PORT83_FN3),
633 PINMUX_DATA(DNPCM_M_MARK, PORT84_FN1),
634 PINMUX_DATA(TPU4TO1_MARK, PORT84_FN3),
635 PINMUX_DATA(TPU4TO2_MARK, PORT85_FN3),
636 PINMUX_DATA(TPU4TO3_MARK, PORT86_FN3),
637 PINMUX_DATA(IRQ_TMPB_MARK, PORT87_FN1),
638 PINMUX_DATA(PWEN_MARK, PORT88_FN1),
639 PINMUX_DATA(MFG1_OUT1_MARK, PORT88_FN2),
640 PINMUX_DATA(OVCN_MARK, PORT89_FN1),
641 PINMUX_DATA(MFG1_IN1_MARK, PORT89_FN2),
642 PINMUX_DATA(OVCN2_MARK, PORT90_FN1),
643 PINMUX_DATA(MFG1_IN2_MARK, PORT90_FN2),
644
645 /* 49-3 (FN) */
646 PINMUX_DATA(RFSPO1_MARK, PORT91_FN1),
647 PINMUX_DATA(RFSPO2_MARK, PORT92_FN1),
648 PINMUX_DATA(RFSPO3_MARK, PORT93_FN1),
649 PINMUX_DATA(PORT93_VIO_CKO2_MARK, PORT93_FN2),
650 PINMUX_DATA(USBTERM_MARK, PORT94_FN1),
651 PINMUX_DATA(EXTLP_MARK, PORT94_FN2),
652 PINMUX_DATA(IDIN_MARK, PORT95_FN1),
653 PINMUX_DATA(SCIFA5_CTS_MARK, PORT96_FN1),
654 PINMUX_DATA(MFG0_IN1_MARK, PORT96_FN2),
655 PINMUX_DATA(SCIFA5_RTS_MARK, PORT97_FN1),
656 PINMUX_DATA(MFG0_IN2_MARK, PORT97_FN2),
657 PINMUX_DATA(SCIFA5_RXD_MARK, PORT98_FN1),
658 PINMUX_DATA(SCIFA5_TXD_MARK, PORT99_FN1),
659 PINMUX_DATA(SCIFA5_SCK_MARK, PORT100_FN1),
660 PINMUX_DATA(MFG0_OUT1_MARK, PORT100_FN2),
661 PINMUX_DATA(A0_EA0_MARK, PORT101_FN1),
662 PINMUX_DATA(BS_MARK, PORT101_FN2),
663 PINMUX_DATA(A14_EA14_MARK, PORT102_FN1),
664 PINMUX_DATA(PORT102_KEYOUT0_MARK, MSELBCR_MSEL2_0, PORT102_FN2),
665 PINMUX_DATA(A15_EA15_MARK, PORT103_FN1),
666 PINMUX_DATA(PORT103_KEYOUT1_MARK, MSELBCR_MSEL2_0, PORT103_FN2),
667 PINMUX_DATA(DV_CLKOL_MARK, PORT103_FN3),
668 PINMUX_DATA(A16_EA16_MARK, PORT104_FN1),
669 PINMUX_DATA(PORT104_KEYOUT2_MARK, MSELBCR_MSEL2_0, PORT104_FN2),
670 PINMUX_DATA(DV_VSYNCL_MARK, PORT104_FN3),
671 PINMUX_DATA(MSIOF0_SS1_MARK, PORT104_FN4),
672 PINMUX_DATA(A17_EA17_MARK, PORT105_FN1),
673 PINMUX_DATA(PORT105_KEYOUT3_MARK, MSELBCR_MSEL2_0, PORT105_FN2),
674 PINMUX_DATA(DV_HSYNCL_MARK, PORT105_FN3),
675 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT105_FN4),
676 PINMUX_DATA(A18_EA18_MARK, PORT106_FN1),
677 PINMUX_DATA(PORT106_KEYOUT4_MARK, MSELBCR_MSEL2_0, PORT106_FN2),
678 PINMUX_DATA(DV_DL0_MARK, PORT106_FN3),
679 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT106_FN4),
680 PINMUX_DATA(A19_EA19_MARK, PORT107_FN1),
681 PINMUX_DATA(PORT107_KEYOUT5_MARK, MSELBCR_MSEL2_0, PORT107_FN2),
682 PINMUX_DATA(DV_DL1_MARK, PORT107_FN3),
683 PINMUX_DATA(MSIOF0_TXD_MARK, PORT107_FN4),
684 PINMUX_DATA(A20_EA20_MARK, PORT108_FN1),
685 PINMUX_DATA(PORT108_KEYIN0_MARK, MSELBCR_MSEL2_0, PORT108_FN2),
686 PINMUX_DATA(DV_DL2_MARK, PORT108_FN3),
687 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT108_FN4),
688 PINMUX_DATA(A21_EA21_MARK, PORT109_FN1),
689 PINMUX_DATA(PORT109_KEYIN1_MARK, MSELBCR_MSEL2_0, PORT109_FN2),
690 PINMUX_DATA(DV_DL3_MARK, PORT109_FN3),
691 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT109_FN4),
692 PINMUX_DATA(A22_EA22_MARK, PORT110_FN1),
693 PINMUX_DATA(PORT110_KEYIN2_MARK, MSELBCR_MSEL2_0, PORT110_FN2),
694 PINMUX_DATA(DV_DL4_MARK, PORT110_FN3),
695 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT110_FN4),
696 PINMUX_DATA(A23_EA23_MARK, PORT111_FN1),
697 PINMUX_DATA(PORT111_KEYIN3_MARK, MSELBCR_MSEL2_0, PORT111_FN2),
698 PINMUX_DATA(DV_DL5_MARK, PORT111_FN3),
699 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT111_FN4),
700 PINMUX_DATA(A24_EA24_MARK, PORT112_FN1),
701 PINMUX_DATA(PORT112_KEYIN4_MARK, MSELBCR_MSEL2_0, PORT112_FN2),
702 PINMUX_DATA(DV_DL6_MARK, PORT112_FN3),
703 PINMUX_DATA(MSIOF0_RXD_MARK, PORT112_FN4),
704 PINMUX_DATA(A25_EA25_MARK, PORT113_FN1),
705 PINMUX_DATA(PORT113_KEYIN5_MARK, MSELBCR_MSEL2_0, PORT113_FN2),
706 PINMUX_DATA(DV_DL7_MARK, PORT113_FN3),
707 PINMUX_DATA(MSIOF0_SS2_MARK, PORT113_FN4),
708 PINMUX_DATA(A26_MARK, PORT114_FN1),
709 PINMUX_DATA(PORT113_KEYIN6_MARK, MSELBCR_MSEL2_0, PORT114_FN2),
710 PINMUX_DATA(DV_CLKIL_MARK, PORT114_FN3),
711 PINMUX_DATA(D0_ED0_NAF0_MARK, PORT115_FN1),
712 PINMUX_DATA(D1_ED1_NAF1_MARK, PORT116_FN1),
713 PINMUX_DATA(D2_ED2_NAF2_MARK, PORT117_FN1),
714 PINMUX_DATA(D3_ED3_NAF3_MARK, PORT118_FN1),
715 PINMUX_DATA(D4_ED4_NAF4_MARK, PORT119_FN1),
716 PINMUX_DATA(D5_ED5_NAF5_MARK, PORT120_FN1),
717 PINMUX_DATA(D6_ED6_NAF6_MARK, PORT121_FN1),
718 PINMUX_DATA(D7_ED7_NAF7_MARK, PORT122_FN1),
719 PINMUX_DATA(D8_ED8_NAF8_MARK, PORT123_FN1),
720 PINMUX_DATA(D9_ED9_NAF9_MARK, PORT124_FN1),
721 PINMUX_DATA(D10_ED10_NAF10_MARK, PORT125_FN1),
722 PINMUX_DATA(D11_ED11_NAF11_MARK, PORT126_FN1),
723 PINMUX_DATA(D12_ED12_NAF12_MARK, PORT127_FN1),
724 PINMUX_DATA(D13_ED13_NAF13_MARK, PORT128_FN1),
725 PINMUX_DATA(D14_ED14_NAF14_MARK, PORT129_FN1),
726 PINMUX_DATA(D15_ED15_NAF15_MARK, PORT130_FN1),
727 PINMUX_DATA(CS4_MARK, PORT131_FN1),
728 PINMUX_DATA(CS5A_MARK, PORT132_FN1),
729 PINMUX_DATA(CS5B_MARK, PORT133_FN1),
730 PINMUX_DATA(FCE1_MARK, PORT133_FN2),
731 PINMUX_DATA(CS6B_MARK, PORT134_FN1),
732 PINMUX_DATA(XCS2_MARK, PORT134_FN2),
733 PINMUX_DATA(FCE0_MARK, PORT135_FN1),
734 PINMUX_DATA(CS6A_MARK, PORT136_FN1),
735 PINMUX_DATA(DACK0_MARK, PORT136_FN2),
736 PINMUX_DATA(WAIT_MARK, PORT137_FN1),
737 PINMUX_DATA(DREQ0_MARK, PORT137_FN2),
738 PINMUX_DATA(RD_XRD_MARK, PORT138_FN1),
739 PINMUX_DATA(A27_MARK, PORT139_FN1),
740 PINMUX_DATA(RDWR_XWE_MARK, PORT139_FN2),
741 PINMUX_DATA(WE0_XWR0_FWE_MARK, PORT140_FN1),
742 PINMUX_DATA(WE1_XWR1_MARK, PORT141_FN1),
743 PINMUX_DATA(FRB_MARK, PORT142_FN1),
744 PINMUX_DATA(CKO_MARK, PORT143_FN1),
745 PINMUX_DATA(NBRSTOUT_MARK, PORT144_FN1),
746 PINMUX_DATA(NBRST_MARK, PORT145_FN1),
747
748 /* 49-4 (FN) */
749 PINMUX_DATA(RFSPO0_MARK, PORT146_FN1),
750 PINMUX_DATA(PORT146_VIO_CKO2_MARK, PORT146_FN2),
751 PINMUX_DATA(TSTMD_MARK, PORT147_FN1),
752 PINMUX_DATA(VIO_VD_MARK, PORT148_FN1),
753 PINMUX_DATA(VIO_HD_MARK, PORT149_FN1),
754 PINMUX_DATA(VIO_D0_MARK, PORT150_FN1),
755 PINMUX_DATA(VIO_D1_MARK, PORT151_FN1),
756 PINMUX_DATA(VIO_D2_MARK, PORT152_FN1),
757 PINMUX_DATA(VIO_D3_MARK, PORT153_FN1),
758 PINMUX_DATA(VIO_D4_MARK, PORT154_FN1),
759 PINMUX_DATA(VIO_D5_MARK, PORT155_FN1),
760 PINMUX_DATA(VIO_D6_MARK, PORT156_FN1),
761 PINMUX_DATA(VIO_D7_MARK, PORT157_FN1),
762 PINMUX_DATA(VIO_D8_MARK, PORT158_FN1),
763 PINMUX_DATA(VIO_D9_MARK, PORT159_FN1),
764 PINMUX_DATA(VIO_D10_MARK, PORT160_FN1),
765 PINMUX_DATA(VIO_D11_MARK, PORT161_FN1),
766 PINMUX_DATA(VIO_D12_MARK, PORT162_FN1),
767 PINMUX_DATA(VIO_D13_MARK, PORT163_FN1),
768 PINMUX_DATA(VIO_D14_MARK, PORT164_FN1),
769 PINMUX_DATA(VIO_D15_MARK, PORT165_FN1),
770 PINMUX_DATA(VIO_CLK_MARK, PORT166_FN1),
771 PINMUX_DATA(VIO_FIELD_MARK, PORT167_FN1),
772 PINMUX_DATA(VIO_CKO_MARK, PORT168_FN1),
773 PINMUX_DATA(MFG3_IN1_MARK, PORT169_FN2),
774 PINMUX_DATA(MFG3_IN2_MARK, PORT170_FN2),
775 PINMUX_DATA(M9_SLCD_A01_MARK, PORT171_FN1),
776 PINMUX_DATA(MFG3_OUT1_MARK, PORT171_FN2),
777 PINMUX_DATA(TPU0TO0_MARK, PORT171_FN3),
778 PINMUX_DATA(M10_SLCD_CK1_MARK, PORT172_FN1),
779 PINMUX_DATA(MFG4_IN1_MARK, PORT172_FN2),
780 PINMUX_DATA(TPU0TO1_MARK, PORT172_FN3),
781 PINMUX_DATA(M11_SLCD_SO1_MARK, PORT173_FN1),
782 PINMUX_DATA(MFG4_IN2_MARK, PORT173_FN2),
783 PINMUX_DATA(TPU0TO2_MARK, PORT173_FN3),
784 PINMUX_DATA(M12_SLCD_CE1_MARK, PORT174_FN1),
785 PINMUX_DATA(MFG4_OUT1_MARK, PORT174_FN2),
786 PINMUX_DATA(TPU0TO3_MARK, PORT174_FN3),
787 PINMUX_DATA(LCDD0_MARK, PORT175_FN1),
788 PINMUX_DATA(PORT175_KEYOUT0_MARK, PORT175_FN2),
789 PINMUX_DATA(DV_D0_MARK, PORT175_FN3),
790 PINMUX_DATA(SIUCKA_MARK, PORT175_FN4),
791 PINMUX_DATA(MFG0_OUT2_MARK, PORT175_FN5),
792 PINMUX_DATA(LCDD1_MARK, PORT176_FN1),
793 PINMUX_DATA(PORT176_KEYOUT1_MARK, PORT176_FN2),
794 PINMUX_DATA(DV_D1_MARK, PORT176_FN3),
795 PINMUX_DATA(SIUAOLR_MARK, PORT176_FN4),
796 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT176_FN5),
797 PINMUX_DATA(LCDD2_MARK, PORT177_FN1),
798 PINMUX_DATA(PORT177_KEYOUT2_MARK, PORT177_FN2),
799 PINMUX_DATA(DV_D2_MARK, PORT177_FN3),
800 PINMUX_DATA(SIUAOBT_MARK, PORT177_FN4),
801 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT177_FN5),
802 PINMUX_DATA(LCDD3_MARK, PORT178_FN1),
803 PINMUX_DATA(PORT178_KEYOUT3_MARK, PORT178_FN2),
804 PINMUX_DATA(DV_D3_MARK, PORT178_FN3),
805 PINMUX_DATA(SIUAOSLD_MARK, PORT178_FN4),
806 PINMUX_DATA(BBIF2_TXD1_MARK, PORT178_FN5),
807 PINMUX_DATA(LCDD4_MARK, PORT179_FN1),
808 PINMUX_DATA(PORT179_KEYOUT4_MARK, PORT179_FN2),
809 PINMUX_DATA(DV_D4_MARK, PORT179_FN3),
810 PINMUX_DATA(SIUAISPD_MARK, PORT179_FN4),
811 PINMUX_DATA(MFG1_OUT2_MARK, PORT179_FN5),
812 PINMUX_DATA(LCDD5_MARK, PORT180_FN1),
813 PINMUX_DATA(PORT180_KEYOUT5_MARK, PORT180_FN2),
814 PINMUX_DATA(DV_D5_MARK, PORT180_FN3),
815 PINMUX_DATA(SIUAILR_MARK, PORT180_FN4),
816 PINMUX_DATA(MFG2_OUT2_MARK, PORT180_FN5),
817 PINMUX_DATA(LCDD6_MARK, PORT181_FN1),
818 PINMUX_DATA(DV_D6_MARK, PORT181_FN3),
819 PINMUX_DATA(SIUAIBT_MARK, PORT181_FN4),
820 PINMUX_DATA(MFG3_OUT2_MARK, PORT181_FN5),
821 PINMUX_DATA(XWR2_MARK, PORT181_FN7),
822 PINMUX_DATA(LCDD7_MARK, PORT182_FN1),
823 PINMUX_DATA(DV_D7_MARK, PORT182_FN3),
824 PINMUX_DATA(SIUAISLD_MARK, PORT182_FN4),
825 PINMUX_DATA(MFG4_OUT2_MARK, PORT182_FN5),
826 PINMUX_DATA(XWR3_MARK, PORT182_FN7),
827 PINMUX_DATA(LCDD8_MARK, PORT183_FN1),
828 PINMUX_DATA(DV_D8_MARK, PORT183_FN3),
829 PINMUX_DATA(D16_MARK, PORT183_FN6),
830 PINMUX_DATA(ED16_MARK, PORT183_FN7),
831 PINMUX_DATA(LCDD9_MARK, PORT184_FN1),
832 PINMUX_DATA(DV_D9_MARK, PORT184_FN3),
833 PINMUX_DATA(D17_MARK, PORT184_FN6),
834 PINMUX_DATA(ED17_MARK, PORT184_FN7),
835 PINMUX_DATA(LCDD10_MARK, PORT185_FN1),
836 PINMUX_DATA(DV_D10_MARK, PORT185_FN3),
837 PINMUX_DATA(D18_MARK, PORT185_FN6),
838 PINMUX_DATA(ED18_MARK, PORT185_FN7),
839 PINMUX_DATA(LCDD11_MARK, PORT186_FN1),
840 PINMUX_DATA(DV_D11_MARK, PORT186_FN3),
841 PINMUX_DATA(D19_MARK, PORT186_FN6),
842 PINMUX_DATA(ED19_MARK, PORT186_FN7),
843 PINMUX_DATA(LCDD12_MARK, PORT187_FN1),
844 PINMUX_DATA(DV_D12_MARK, PORT187_FN3),
845 PINMUX_DATA(D20_MARK, PORT187_FN6),
846 PINMUX_DATA(ED20_MARK, PORT187_FN7),
847 PINMUX_DATA(LCDD13_MARK, PORT188_FN1),
848 PINMUX_DATA(DV_D13_MARK, PORT188_FN3),
849 PINMUX_DATA(D21_MARK, PORT188_FN6),
850 PINMUX_DATA(ED21_MARK, PORT188_FN7),
851 PINMUX_DATA(LCDD14_MARK, PORT189_FN1),
852 PINMUX_DATA(DV_D14_MARK, PORT189_FN3),
853 PINMUX_DATA(D22_MARK, PORT189_FN6),
854 PINMUX_DATA(ED22_MARK, PORT189_FN7),
855 PINMUX_DATA(LCDD15_MARK, PORT190_FN1),
856 PINMUX_DATA(DV_D15_MARK, PORT190_FN3),
857 PINMUX_DATA(D23_MARK, PORT190_FN6),
858 PINMUX_DATA(ED23_MARK, PORT190_FN7),
859 PINMUX_DATA(LCDD16_MARK, PORT191_FN1),
860 PINMUX_DATA(DV_HSYNC_MARK, PORT191_FN3),
861 PINMUX_DATA(D24_MARK, PORT191_FN6),
862 PINMUX_DATA(ED24_MARK, PORT191_FN7),
863 PINMUX_DATA(LCDD17_MARK, PORT192_FN1),
864 PINMUX_DATA(DV_VSYNC_MARK, PORT192_FN3),
865 PINMUX_DATA(D25_MARK, PORT192_FN6),
866 PINMUX_DATA(ED25_MARK, PORT192_FN7),
867 PINMUX_DATA(LCDD18_MARK, PORT193_FN1),
868 PINMUX_DATA(DREQ2_MARK, PORT193_FN2),
869 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT193_FN5),
870 PINMUX_DATA(D26_MARK, PORT193_FN6),
871 PINMUX_DATA(ED26_MARK, PORT193_FN7),
872 PINMUX_DATA(LCDD19_MARK, PORT194_FN1),
873 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT194_FN5),
874 PINMUX_DATA(D27_MARK, PORT194_FN6),
875 PINMUX_DATA(ED27_MARK, PORT194_FN7),
876 PINMUX_DATA(LCDD20_MARK, PORT195_FN1),
877 PINMUX_DATA(TS_SPSYNC1_MARK, PORT195_FN2),
878 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT195_FN5),
879 PINMUX_DATA(D28_MARK, PORT195_FN6),
880 PINMUX_DATA(ED28_MARK, PORT195_FN7),
881 PINMUX_DATA(LCDD21_MARK, PORT196_FN1),
882 PINMUX_DATA(TS_SDAT1_MARK, PORT196_FN2),
883 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT196_FN5),
884 PINMUX_DATA(D29_MARK, PORT196_FN6),
885 PINMUX_DATA(ED29_MARK, PORT196_FN7),
886 PINMUX_DATA(LCDD22_MARK, PORT197_FN1),
887 PINMUX_DATA(TS_SDEN1_MARK, PORT197_FN2),
888 PINMUX_DATA(MSIOF0L_SS1_MARK, PORT197_FN5),
889 PINMUX_DATA(D30_MARK, PORT197_FN6),
890 PINMUX_DATA(ED30_MARK, PORT197_FN7),
891 PINMUX_DATA(LCDD23_MARK, PORT198_FN1),
892 PINMUX_DATA(TS_SCK1_MARK, PORT198_FN2),
893 PINMUX_DATA(MSIOF0L_SS2_MARK, PORT198_FN5),
894 PINMUX_DATA(D31_MARK, PORT198_FN6),
895 PINMUX_DATA(ED31_MARK, PORT198_FN7),
896 PINMUX_DATA(LCDDCK_MARK, PORT199_FN1),
897 PINMUX_DATA(LCDWR_MARK, PORT199_FN2),
898 PINMUX_DATA(DV_CKO_MARK, PORT199_FN3),
899 PINMUX_DATA(SIUAOSPD_MARK, PORT199_FN4),
900 PINMUX_DATA(LCDRD_MARK, PORT200_FN1),
901 PINMUX_DATA(DACK2_MARK, PORT200_FN2),
902 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT200_FN5),
903
904 /* 49-5 (FN) */
905 PINMUX_DATA(LCDHSYN_MARK, PORT201_FN1),
906 PINMUX_DATA(LCDCS_MARK, PORT201_FN2),
907 PINMUX_DATA(LCDCS2_MARK, PORT201_FN3),
908 PINMUX_DATA(DACK3_MARK, PORT201_FN4),
909 PINMUX_DATA(LCDDISP_MARK, PORT202_FN1),
910 PINMUX_DATA(LCDRS_MARK, PORT202_FN2),
911 PINMUX_DATA(DREQ3_MARK, PORT202_FN4),
912 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT202_FN5),
913 PINMUX_DATA(LCDCSYN_MARK, PORT203_FN1),
914 PINMUX_DATA(LCDCSYN2_MARK, PORT203_FN2),
915 PINMUX_DATA(DV_CKI_MARK, PORT203_FN3),
916 PINMUX_DATA(LCDLCLK_MARK, PORT204_FN1),
917 PINMUX_DATA(DREQ1_MARK, PORT204_FN3),
918 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT204_FN5),
919 PINMUX_DATA(LCDDON_MARK, PORT205_FN1),
920 PINMUX_DATA(LCDDON2_MARK, PORT205_FN2),
921 PINMUX_DATA(DACK1_MARK, PORT205_FN3),
922 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT205_FN5),
923 PINMUX_DATA(VIO_DR0_MARK, PORT206_FN1),
924 PINMUX_DATA(VIO_DR1_MARK, PORT207_FN1),
925 PINMUX_DATA(VIO_DR2_MARK, PORT208_FN1),
926 PINMUX_DATA(VIO_DR3_MARK, PORT209_FN1),
927 PINMUX_DATA(VIO_DR4_MARK, PORT210_FN1),
928 PINMUX_DATA(VIO_DR5_MARK, PORT211_FN1),
929 PINMUX_DATA(VIO_DR6_MARK, PORT212_FN1),
930 PINMUX_DATA(VIO_DR7_MARK, PORT213_FN1),
931 PINMUX_DATA(VIO_VDR_MARK, PORT214_FN1),
932 PINMUX_DATA(VIO_HDR_MARK, PORT215_FN1),
933 PINMUX_DATA(VIO_CLKR_MARK, PORT216_FN1),
934 PINMUX_DATA(VIO_CKOR_MARK, PORT217_FN1),
935 PINMUX_DATA(SCIFA1_TXD_MARK, PORT220_FN2),
936 PINMUX_DATA(GPS_PGFA0_MARK, PORT220_FN3),
937 PINMUX_DATA(SCIFA1_SCK_MARK, PORT221_FN2),
938 PINMUX_DATA(GPS_PGFA1_MARK, PORT221_FN3),
939 PINMUX_DATA(SCIFA1_RTS_MARK, PORT222_FN2),
940 PINMUX_DATA(GPS_EPPSINMON_MARK, PORT222_FN3),
941 PINMUX_DATA(SCIFA1_RXD_MARK, PORT223_FN2),
942 PINMUX_DATA(SCIFA1_CTS_MARK, PORT224_FN2),
943 PINMUX_DATA(MSIOF1_TXD_MARK, PORT225_FN1),
944 PINMUX_DATA(SCIFA1_TXD2_MARK, PORT225_FN2),
945 PINMUX_DATA(GPS_TXD_MARK, PORT225_FN3),
946 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT226_FN1),
947 PINMUX_DATA(SCIFA1_CTS2_MARK, PORT226_FN2),
948 PINMUX_DATA(I2C_SDA2_MARK, PORT226_FN3),
949 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT227_FN1),
950 PINMUX_DATA(SCIFA1_SCK2_MARK, PORT227_FN2),
951 PINMUX_DATA(MSIOF1_RXD_MARK, PORT228_FN1),
952 PINMUX_DATA(SCIFA1_RXD2_MARK, PORT228_FN2),
953 PINMUX_DATA(GPS_RXD_MARK, PORT228_FN3),
954 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT229_FN1),
955 PINMUX_DATA(SCIFA1_RTS2_MARK, PORT229_FN2),
956 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT230_FN1),
957 PINMUX_DATA(I2C_SCL2_MARK, PORT230_FN3),
958 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT231_FN1),
959 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT232_FN1),
960 PINMUX_DATA(MSIOF1_SS1_MARK, PORT233_FN1),
961 PINMUX_DATA(EDBGREQ3_MARK, PORT233_FN2),
962 PINMUX_DATA(MSIOF1_SS2_MARK, PORT234_FN1),
963 PINMUX_DATA(PORT236_IROUT_MARK, PORT236_FN1),
964 PINMUX_DATA(IRDA_OUT_MARK, PORT236_FN2),
965 PINMUX_DATA(IRDA_IN_MARK, PORT237_FN2),
966 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT238_FN1),
967 PINMUX_DATA(TPU1TO0_MARK, PORT239_FN3),
968 PINMUX_DATA(TS_SPSYNC3_MARK, PORT239_FN4),
969 PINMUX_DATA(TPU1TO1_MARK, PORT240_FN3),
970 PINMUX_DATA(TS_SDAT3_MARK, PORT240_FN4),
971 PINMUX_DATA(TPU1TO2_MARK, PORT241_FN3),
972 PINMUX_DATA(TS_SDEN3_MARK, PORT241_FN4),
973 PINMUX_DATA(PORT241_MSIOF2_SS1_MARK, PORT241_FN5),
974 PINMUX_DATA(TPU1TO3_MARK, PORT242_FN3),
975 PINMUX_DATA(PORT242_MSIOF2_TSCK_MARK, PORT242_FN5),
976 PINMUX_DATA(M13_BSW_MARK, PORT243_FN2),
977 PINMUX_DATA(PORT243_MSIOF2_TSYNC_MARK, PORT243_FN5),
978 PINMUX_DATA(M14_GSW_MARK, PORT244_FN2),
979 PINMUX_DATA(PORT244_MSIOF2_TXD_MARK, PORT244_FN5),
980 PINMUX_DATA(PORT245_IROUT_MARK, PORT245_FN1),
981 PINMUX_DATA(M15_RSW_MARK, PORT245_FN2),
982 PINMUX_DATA(SOUT3_MARK, PORT246_FN1),
983 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT246_FN2),
984 PINMUX_DATA(SIN3_MARK, PORT247_FN1),
985 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT247_FN2),
986 PINMUX_DATA(XRTS3_MARK, PORT248_FN1),
987 PINMUX_DATA(SCIFA2_RTS1_MARK, PORT248_FN2),
988 PINMUX_DATA(PORT248_MSIOF2_SS2_MARK, PORT248_FN5),
989 PINMUX_DATA(XCTS3_MARK, PORT249_FN1),
990 PINMUX_DATA(SCIFA2_CTS1_MARK, PORT249_FN2),
991 PINMUX_DATA(PORT249_MSIOF2_RXD_MARK, PORT249_FN5),
992 PINMUX_DATA(DINT_MARK, PORT250_FN1),
993 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT250_FN2),
994 PINMUX_DATA(TS_SCK3_MARK, PORT250_FN4),
995 PINMUX_DATA(SDHICLK0_MARK, PORT251_FN1),
996 PINMUX_DATA(TCK2_MARK, PORT251_FN2),
997 PINMUX_DATA(SDHICD0_MARK, PORT252_FN1),
998 PINMUX_DATA(SDHID0_0_MARK, PORT253_FN1),
999 PINMUX_DATA(TMS2_MARK, PORT253_FN2),
1000 PINMUX_DATA(SDHID0_1_MARK, PORT254_FN1),
1001 PINMUX_DATA(TDO2_MARK, PORT254_FN2),
1002 PINMUX_DATA(SDHID0_2_MARK, PORT255_FN1),
1003 PINMUX_DATA(TDI2_MARK, PORT255_FN2),
1004 PINMUX_DATA(SDHID0_3_MARK, PORT256_FN1),
1005 PINMUX_DATA(RTCK2_MARK, PORT256_FN2),
1006
1007 /* 49-6 (FN) */
1008 PINMUX_DATA(SDHICMD0_MARK, PORT257_FN1),
1009 PINMUX_DATA(TRST2_MARK, PORT257_FN2),
1010 PINMUX_DATA(SDHIWP0_MARK, PORT258_FN1),
1011 PINMUX_DATA(EDBGREQ2_MARK, PORT258_FN2),
1012 PINMUX_DATA(SDHICLK1_MARK, PORT259_FN1),
1013 PINMUX_DATA(TCK3_MARK, PORT259_FN4),
1014 PINMUX_DATA(SDHID1_0_MARK, PORT260_FN1),
1015 PINMUX_DATA(M11_SLCD_SO2_MARK, PORT260_FN2),
1016 PINMUX_DATA(TS_SPSYNC2_MARK, PORT260_FN3),
1017 PINMUX_DATA(TMS3_MARK, PORT260_FN4),
1018 PINMUX_DATA(SDHID1_1_MARK, PORT261_FN1),
1019 PINMUX_DATA(M9_SLCD_AO2_MARK, PORT261_FN2),
1020 PINMUX_DATA(TS_SDAT2_MARK, PORT261_FN3),
1021 PINMUX_DATA(TDO3_MARK, PORT261_FN4),
1022 PINMUX_DATA(SDHID1_2_MARK, PORT262_FN1),
1023 PINMUX_DATA(M10_SLCD_CK2_MARK, PORT262_FN2),
1024 PINMUX_DATA(TS_SDEN2_MARK, PORT262_FN3),
1025 PINMUX_DATA(TDI3_MARK, PORT262_FN4),
1026 PINMUX_DATA(SDHID1_3_MARK, PORT263_FN1),
1027 PINMUX_DATA(M12_SLCD_CE2_MARK, PORT263_FN2),
1028 PINMUX_DATA(TS_SCK2_MARK, PORT263_FN3),
1029 PINMUX_DATA(RTCK3_MARK, PORT263_FN4),
1030 PINMUX_DATA(SDHICMD1_MARK, PORT264_FN1),
1031 PINMUX_DATA(TRST3_MARK, PORT264_FN4),
1032 PINMUX_DATA(SDHICLK2_MARK, PORT265_FN1),
1033 PINMUX_DATA(SCIFB_SCK_MARK, PORT265_FN2),
1034 PINMUX_DATA(SDHID2_0_MARK, PORT266_FN1),
1035 PINMUX_DATA(SCIFB_TXD_MARK, PORT266_FN2),
1036 PINMUX_DATA(SDHID2_1_MARK, PORT267_FN1),
1037 PINMUX_DATA(SCIFB_CTS_MARK, PORT267_FN2),
1038 PINMUX_DATA(SDHID2_2_MARK, PORT268_FN1),
1039 PINMUX_DATA(SCIFB_RXD_MARK, PORT268_FN2),
1040 PINMUX_DATA(SDHID2_3_MARK, PORT269_FN1),
1041 PINMUX_DATA(SCIFB_RTS_MARK, PORT269_FN2),
1042 PINMUX_DATA(SDHICMD2_MARK, PORT270_FN1),
1043 PINMUX_DATA(RESETOUTS_MARK, PORT271_FN1),
1044 PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
1045};
1046
1047static struct pinmux_gpio pinmux_gpios[] = {
1048 /* 49-1 -> 49-6 (GPIO) */
1049 GPIO_PORT_ALL(),
1050
1051 /* Special Pull-up / Pull-down Functions */
1052 GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
1053 GPIO_FN(PORT50_KEYIN2_PU), GPIO_FN(PORT55_KEYIN3_PU),
1054 GPIO_FN(PORT56_KEYIN4_PU), GPIO_FN(PORT57_KEYIN5_PU),
1055 GPIO_FN(PORT58_KEYIN6_PU),
1056
1057 /* 49-1 (FN) */
1058 GPIO_FN(VBUS0), GPIO_FN(CPORT0), GPIO_FN(CPORT1), GPIO_FN(CPORT2),
1059 GPIO_FN(CPORT3), GPIO_FN(CPORT4), GPIO_FN(CPORT5), GPIO_FN(CPORT6),
1060 GPIO_FN(CPORT7), GPIO_FN(CPORT8), GPIO_FN(CPORT9), GPIO_FN(CPORT10),
1061 GPIO_FN(CPORT11), GPIO_FN(SIN2), GPIO_FN(CPORT12), GPIO_FN(XCTS2),
1062 GPIO_FN(CPORT13), GPIO_FN(RFSPO4), GPIO_FN(CPORT14), GPIO_FN(RFSPO5),
1063 GPIO_FN(CPORT15), GPIO_FN(CPORT16), GPIO_FN(CPORT17), GPIO_FN(SOUT2),
1064 GPIO_FN(CPORT18), GPIO_FN(XRTS2), GPIO_FN(CPORT19), GPIO_FN(CPORT20),
1065 GPIO_FN(RFSPO6), GPIO_FN(CPORT21), GPIO_FN(STATUS0), GPIO_FN(CPORT22),
1066 GPIO_FN(STATUS1), GPIO_FN(CPORT23), GPIO_FN(STATUS2), GPIO_FN(RFSPO7),
1067 GPIO_FN(MPORT0), GPIO_FN(MPORT1), GPIO_FN(B_SYNLD1), GPIO_FN(B_SYNLD2),
1068 GPIO_FN(XMAINPS), GPIO_FN(XDIVPS), GPIO_FN(XIDRST), GPIO_FN(IDCLK),
1069 GPIO_FN(IDIO), GPIO_FN(SOUT1), GPIO_FN(SCIFA4_TXD),
1070 GPIO_FN(M02_BERDAT), GPIO_FN(SIN1), GPIO_FN(SCIFA4_RXD), GPIO_FN(XWUP),
1071 GPIO_FN(XRTS1), GPIO_FN(SCIFA4_RTS), GPIO_FN(M03_BERCLK),
1072 GPIO_FN(XCTS1), GPIO_FN(SCIFA4_CTS),
1073
1074 /* 49-2 (FN) */
1075 GPIO_FN(HSU_IQ_AGC6), GPIO_FN(MFG2_IN2), GPIO_FN(MSIOF2_MCK0),
1076 GPIO_FN(HSU_IQ_AGC5), GPIO_FN(MFG2_IN1), GPIO_FN(MSIOF2_MCK1),
1077 GPIO_FN(HSU_IQ_AGC4), GPIO_FN(MSIOF2_RSYNC),
1078 GPIO_FN(HSU_IQ_AGC3), GPIO_FN(MFG2_OUT1), GPIO_FN(MSIOF2_RSCK),
1079 GPIO_FN(HSU_IQ_AGC2), GPIO_FN(PORT42_KEYOUT0),
1080 GPIO_FN(HSU_IQ_AGC1), GPIO_FN(PORT43_KEYOUT1),
1081 GPIO_FN(HSU_IQ_AGC0), GPIO_FN(PORT44_KEYOUT2),
1082 GPIO_FN(HSU_IQ_AGC_ST), GPIO_FN(PORT45_KEYOUT3),
1083 GPIO_FN(HSU_IQ_PDO), GPIO_FN(PORT46_KEYOUT4),
1084 GPIO_FN(HSU_IQ_PYO), GPIO_FN(PORT47_KEYOUT5),
1085 GPIO_FN(HSU_EN_TXMUX_G3MO), GPIO_FN(PORT48_KEYIN0),
1086 GPIO_FN(HSU_I_TXMUX_G3MO), GPIO_FN(PORT49_KEYIN1),
1087 GPIO_FN(HSU_Q_TXMUX_G3MO), GPIO_FN(PORT50_KEYIN2),
1088 GPIO_FN(HSU_SYO), GPIO_FN(PORT51_MSIOF2_TSYNC),
1089 GPIO_FN(HSU_SDO), GPIO_FN(PORT52_MSIOF2_TSCK),
1090 GPIO_FN(HSU_TGTTI_G3MO), GPIO_FN(PORT53_MSIOF2_TXD),
1091 GPIO_FN(B_TIME_STAMP), GPIO_FN(PORT54_MSIOF2_RXD),
1092 GPIO_FN(HSU_SDI), GPIO_FN(PORT55_KEYIN3),
1093 GPIO_FN(HSU_SCO), GPIO_FN(PORT56_KEYIN4),
1094 GPIO_FN(HSU_DREQ), GPIO_FN(PORT57_KEYIN5),
1095 GPIO_FN(HSU_DACK), GPIO_FN(PORT58_KEYIN6),
1096 GPIO_FN(HSU_CLK61M), GPIO_FN(PORT59_MSIOF2_SS1),
1097 GPIO_FN(HSU_XRST), GPIO_FN(PORT60_MSIOF2_SS2),
1098 GPIO_FN(PCMCLKO), GPIO_FN(SYNC8KO), GPIO_FN(DNPCM_A), GPIO_FN(UPPCM_A),
1099 GPIO_FN(XTALB1L),
1100 GPIO_FN(GPS_AGC1), GPIO_FN(SCIFA0_RTS),
1101 GPIO_FN(GPS_AGC2), GPIO_FN(SCIFA0_SCK),
1102 GPIO_FN(GPS_AGC3), GPIO_FN(SCIFA0_TXD),
1103 GPIO_FN(GPS_AGC4), GPIO_FN(SCIFA0_RXD),
1104 GPIO_FN(GPS_PWRD), GPIO_FN(SCIFA0_CTS),
1105 GPIO_FN(GPS_IM), GPIO_FN(GPS_IS), GPIO_FN(GPS_QM), GPIO_FN(GPS_QS),
1106 GPIO_FN(SIUBOMC), GPIO_FN(TPU2TO0),
1107 GPIO_FN(SIUCKB), GPIO_FN(TPU2TO1),
1108 GPIO_FN(SIUBOLR), GPIO_FN(BBIF2_TSYNC), GPIO_FN(TPU2TO2),
1109 GPIO_FN(SIUBOBT), GPIO_FN(BBIF2_TSCK), GPIO_FN(TPU2TO3),
1110 GPIO_FN(SIUBOSLD), GPIO_FN(BBIF2_TXD), GPIO_FN(TPU3TO0),
1111 GPIO_FN(SIUBILR), GPIO_FN(TPU3TO1),
1112 GPIO_FN(SIUBIBT), GPIO_FN(TPU3TO2),
1113 GPIO_FN(SIUBISLD), GPIO_FN(TPU3TO3),
1114 GPIO_FN(NMI), GPIO_FN(TPU4TO0),
1115 GPIO_FN(DNPCM_M), GPIO_FN(TPU4TO1), GPIO_FN(TPU4TO2), GPIO_FN(TPU4TO3),
1116 GPIO_FN(IRQ_TMPB),
1117 GPIO_FN(PWEN), GPIO_FN(MFG1_OUT1),
1118 GPIO_FN(OVCN), GPIO_FN(MFG1_IN1),
1119 GPIO_FN(OVCN2), GPIO_FN(MFG1_IN2),
1120
1121 /* 49-3 (FN) */
1122 GPIO_FN(RFSPO1), GPIO_FN(RFSPO2), GPIO_FN(RFSPO3),
1123 GPIO_FN(PORT93_VIO_CKO2),
1124 GPIO_FN(USBTERM), GPIO_FN(EXTLP), GPIO_FN(IDIN),
1125 GPIO_FN(SCIFA5_CTS), GPIO_FN(MFG0_IN1),
1126 GPIO_FN(SCIFA5_RTS), GPIO_FN(MFG0_IN2),
1127 GPIO_FN(SCIFA5_RXD),
1128 GPIO_FN(SCIFA5_TXD),
1129 GPIO_FN(SCIFA5_SCK), GPIO_FN(MFG0_OUT1),
1130 GPIO_FN(A0_EA0), GPIO_FN(BS),
1131 GPIO_FN(A14_EA14), GPIO_FN(PORT102_KEYOUT0),
1132 GPIO_FN(A15_EA15), GPIO_FN(PORT103_KEYOUT1), GPIO_FN(DV_CLKOL),
1133 GPIO_FN(A16_EA16), GPIO_FN(PORT104_KEYOUT2),
1134 GPIO_FN(DV_VSYNCL), GPIO_FN(MSIOF0_SS1),
1135 GPIO_FN(A17_EA17), GPIO_FN(PORT105_KEYOUT3),
1136 GPIO_FN(DV_HSYNCL), GPIO_FN(MSIOF0_TSYNC),
1137 GPIO_FN(A18_EA18), GPIO_FN(PORT106_KEYOUT4),
1138 GPIO_FN(DV_DL0), GPIO_FN(MSIOF0_TSCK),
1139 GPIO_FN(A19_EA19), GPIO_FN(PORT107_KEYOUT5),
1140 GPIO_FN(DV_DL1), GPIO_FN(MSIOF0_TXD),
1141 GPIO_FN(A20_EA20), GPIO_FN(PORT108_KEYIN0),
1142 GPIO_FN(DV_DL2), GPIO_FN(MSIOF0_RSCK),
1143 GPIO_FN(A21_EA21), GPIO_FN(PORT109_KEYIN1),
1144 GPIO_FN(DV_DL3), GPIO_FN(MSIOF0_RSYNC),
1145 GPIO_FN(A22_EA22), GPIO_FN(PORT110_KEYIN2),
1146 GPIO_FN(DV_DL4), GPIO_FN(MSIOF0_MCK0),
1147 GPIO_FN(A23_EA23), GPIO_FN(PORT111_KEYIN3),
1148 GPIO_FN(DV_DL5), GPIO_FN(MSIOF0_MCK1),
1149 GPIO_FN(A24_EA24), GPIO_FN(PORT112_KEYIN4),
1150 GPIO_FN(DV_DL6), GPIO_FN(MSIOF0_RXD),
1151 GPIO_FN(A25_EA25), GPIO_FN(PORT113_KEYIN5),
1152 GPIO_FN(DV_DL7), GPIO_FN(MSIOF0_SS2),
1153 GPIO_FN(A26), GPIO_FN(PORT113_KEYIN6), GPIO_FN(DV_CLKIL),
1154 GPIO_FN(D0_ED0_NAF0), GPIO_FN(D1_ED1_NAF1), GPIO_FN(D2_ED2_NAF2),
1155 GPIO_FN(D3_ED3_NAF3), GPIO_FN(D4_ED4_NAF4), GPIO_FN(D5_ED5_NAF5),
1156 GPIO_FN(D6_ED6_NAF6), GPIO_FN(D7_ED7_NAF7), GPIO_FN(D8_ED8_NAF8),
1157 GPIO_FN(D9_ED9_NAF9), GPIO_FN(D10_ED10_NAF10), GPIO_FN(D11_ED11_NAF11),
1158 GPIO_FN(D12_ED12_NAF12), GPIO_FN(D13_ED13_NAF13),
1159 GPIO_FN(D14_ED14_NAF14), GPIO_FN(D15_ED15_NAF15),
1160 GPIO_FN(CS4), GPIO_FN(CS5A), GPIO_FN(CS5B), GPIO_FN(FCE1),
1161 GPIO_FN(CS6B), GPIO_FN(XCS2), GPIO_FN(FCE0), GPIO_FN(CS6A),
1162 GPIO_FN(DACK0), GPIO_FN(WAIT), GPIO_FN(DREQ0), GPIO_FN(RD_XRD),
1163 GPIO_FN(A27), GPIO_FN(RDWR_XWE), GPIO_FN(WE0_XWR0_FWE),
1164 GPIO_FN(WE1_XWR1), GPIO_FN(FRB), GPIO_FN(CKO),
1165 GPIO_FN(NBRSTOUT), GPIO_FN(NBRST),
1166
1167 /* 49-4 (FN) */
1168 GPIO_FN(RFSPO0), GPIO_FN(PORT146_VIO_CKO2), GPIO_FN(TSTMD),
1169 GPIO_FN(VIO_VD), GPIO_FN(VIO_HD),
1170 GPIO_FN(VIO_D0), GPIO_FN(VIO_D1), GPIO_FN(VIO_D2),
1171 GPIO_FN(VIO_D3), GPIO_FN(VIO_D4), GPIO_FN(VIO_D5),
1172 GPIO_FN(VIO_D6), GPIO_FN(VIO_D7), GPIO_FN(VIO_D8),
1173 GPIO_FN(VIO_D9), GPIO_FN(VIO_D10), GPIO_FN(VIO_D11),
1174 GPIO_FN(VIO_D12), GPIO_FN(VIO_D13), GPIO_FN(VIO_D14),
1175 GPIO_FN(VIO_D15), GPIO_FN(VIO_CLK), GPIO_FN(VIO_FIELD),
1176 GPIO_FN(VIO_CKO),
1177 GPIO_FN(MFG3_IN1), GPIO_FN(MFG3_IN2),
1178 GPIO_FN(M9_SLCD_A01), GPIO_FN(MFG3_OUT1), GPIO_FN(TPU0TO0),
1179 GPIO_FN(M10_SLCD_CK1), GPIO_FN(MFG4_IN1), GPIO_FN(TPU0TO1),
1180 GPIO_FN(M11_SLCD_SO1), GPIO_FN(MFG4_IN2), GPIO_FN(TPU0TO2),
1181 GPIO_FN(M12_SLCD_CE1), GPIO_FN(MFG4_OUT1), GPIO_FN(TPU0TO3),
1182 GPIO_FN(LCDD0), GPIO_FN(PORT175_KEYOUT0), GPIO_FN(DV_D0),
1183 GPIO_FN(SIUCKA), GPIO_FN(MFG0_OUT2),
1184 GPIO_FN(LCDD1), GPIO_FN(PORT176_KEYOUT1), GPIO_FN(DV_D1),
1185 GPIO_FN(SIUAOLR), GPIO_FN(BBIF2_TSYNC1),
1186 GPIO_FN(LCDD2), GPIO_FN(PORT177_KEYOUT2), GPIO_FN(DV_D2),
1187 GPIO_FN(SIUAOBT), GPIO_FN(BBIF2_TSCK1),
1188 GPIO_FN(LCDD3), GPIO_FN(PORT178_KEYOUT3), GPIO_FN(DV_D3),
1189 GPIO_FN(SIUAOSLD), GPIO_FN(BBIF2_TXD1),
1190 GPIO_FN(LCDD4), GPIO_FN(PORT179_KEYOUT4), GPIO_FN(DV_D4),
1191 GPIO_FN(SIUAISPD), GPIO_FN(MFG1_OUT2),
1192 GPIO_FN(LCDD5), GPIO_FN(PORT180_KEYOUT5), GPIO_FN(DV_D5),
1193 GPIO_FN(SIUAILR), GPIO_FN(MFG2_OUT2),
1194 GPIO_FN(LCDD6), GPIO_FN(DV_D6),
1195 GPIO_FN(SIUAIBT), GPIO_FN(MFG3_OUT2), GPIO_FN(XWR2),
1196 GPIO_FN(LCDD7), GPIO_FN(DV_D7),
1197 GPIO_FN(SIUAISLD), GPIO_FN(MFG4_OUT2), GPIO_FN(XWR3),
1198 GPIO_FN(LCDD8), GPIO_FN(DV_D8), GPIO_FN(D16), GPIO_FN(ED16),
1199 GPIO_FN(LCDD9), GPIO_FN(DV_D9), GPIO_FN(D17), GPIO_FN(ED17),
1200 GPIO_FN(LCDD10), GPIO_FN(DV_D10), GPIO_FN(D18), GPIO_FN(ED18),
1201 GPIO_FN(LCDD11), GPIO_FN(DV_D11), GPIO_FN(D19), GPIO_FN(ED19),
1202 GPIO_FN(LCDD12), GPIO_FN(DV_D12), GPIO_FN(D20), GPIO_FN(ED20),
1203 GPIO_FN(LCDD13), GPIO_FN(DV_D13), GPIO_FN(D21), GPIO_FN(ED21),
1204 GPIO_FN(LCDD14), GPIO_FN(DV_D14), GPIO_FN(D22), GPIO_FN(ED22),
1205 GPIO_FN(LCDD15), GPIO_FN(DV_D15), GPIO_FN(D23), GPIO_FN(ED23),
1206 GPIO_FN(LCDD16), GPIO_FN(DV_HSYNC), GPIO_FN(D24), GPIO_FN(ED24),
1207 GPIO_FN(LCDD17), GPIO_FN(DV_VSYNC), GPIO_FN(D25), GPIO_FN(ED25),
1208 GPIO_FN(LCDD18), GPIO_FN(DREQ2), GPIO_FN(MSIOF0L_TSCK),
1209 GPIO_FN(D26), GPIO_FN(ED26),
1210 GPIO_FN(LCDD19), GPIO_FN(MSIOF0L_TSYNC),
1211 GPIO_FN(D27), GPIO_FN(ED27),
1212 GPIO_FN(LCDD20), GPIO_FN(TS_SPSYNC1), GPIO_FN(MSIOF0L_MCK0),
1213 GPIO_FN(D28), GPIO_FN(ED28),
1214 GPIO_FN(LCDD21), GPIO_FN(TS_SDAT1), GPIO_FN(MSIOF0L_MCK1),
1215 GPIO_FN(D29), GPIO_FN(ED29),
1216 GPIO_FN(LCDD22), GPIO_FN(TS_SDEN1), GPIO_FN(MSIOF0L_SS1),
1217 GPIO_FN(D30), GPIO_FN(ED30),
1218 GPIO_FN(LCDD23), GPIO_FN(TS_SCK1), GPIO_FN(MSIOF0L_SS2),
1219 GPIO_FN(D31), GPIO_FN(ED31),
1220 GPIO_FN(LCDDCK), GPIO_FN(LCDWR), GPIO_FN(DV_CKO), GPIO_FN(SIUAOSPD),
1221 GPIO_FN(LCDRD), GPIO_FN(DACK2), GPIO_FN(MSIOF0L_RSYNC),
1222
1223 /* 49-5 (FN) */
1224 GPIO_FN(LCDHSYN), GPIO_FN(LCDCS), GPIO_FN(LCDCS2), GPIO_FN(DACK3),
1225 GPIO_FN(LCDDISP), GPIO_FN(LCDRS), GPIO_FN(DREQ3), GPIO_FN(MSIOF0L_RSCK),
1226 GPIO_FN(LCDCSYN), GPIO_FN(LCDCSYN2), GPIO_FN(DV_CKI),
1227 GPIO_FN(LCDLCLK), GPIO_FN(DREQ1), GPIO_FN(MSIOF0L_RXD),
1228 GPIO_FN(LCDDON), GPIO_FN(LCDDON2), GPIO_FN(DACK1), GPIO_FN(MSIOF0L_TXD),
1229 GPIO_FN(VIO_DR0), GPIO_FN(VIO_DR1), GPIO_FN(VIO_DR2), GPIO_FN(VIO_DR3),
1230 GPIO_FN(VIO_DR4), GPIO_FN(VIO_DR5), GPIO_FN(VIO_DR6), GPIO_FN(VIO_DR7),
1231 GPIO_FN(VIO_VDR), GPIO_FN(VIO_HDR),
1232 GPIO_FN(VIO_CLKR), GPIO_FN(VIO_CKOR),
1233 GPIO_FN(SCIFA1_TXD), GPIO_FN(GPS_PGFA0),
1234 GPIO_FN(SCIFA1_SCK), GPIO_FN(GPS_PGFA1),
1235 GPIO_FN(SCIFA1_RTS), GPIO_FN(GPS_EPPSINMON),
1236 GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_CTS),
1237 GPIO_FN(MSIOF1_TXD), GPIO_FN(SCIFA1_TXD2), GPIO_FN(GPS_TXD),
1238 GPIO_FN(MSIOF1_TSYNC), GPIO_FN(SCIFA1_CTS2), GPIO_FN(I2C_SDA2),
1239 GPIO_FN(MSIOF1_TSCK), GPIO_FN(SCIFA1_SCK2),
1240 GPIO_FN(MSIOF1_RXD), GPIO_FN(SCIFA1_RXD2), GPIO_FN(GPS_RXD),
1241 GPIO_FN(MSIOF1_RSCK), GPIO_FN(SCIFA1_RTS2),
1242 GPIO_FN(MSIOF1_RSYNC), GPIO_FN(I2C_SCL2),
1243 GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
1244 GPIO_FN(MSIOF1_SS1), GPIO_FN(EDBGREQ3),
1245 GPIO_FN(MSIOF1_SS2),
1246 GPIO_FN(PORT236_IROUT), GPIO_FN(IRDA_OUT),
1247 GPIO_FN(IRDA_IN), GPIO_FN(IRDA_FIRSEL),
1248 GPIO_FN(TPU1TO0), GPIO_FN(TS_SPSYNC3),
1249 GPIO_FN(TPU1TO1), GPIO_FN(TS_SDAT3),
1250 GPIO_FN(TPU1TO2), GPIO_FN(TS_SDEN3), GPIO_FN(PORT241_MSIOF2_SS1),
1251 GPIO_FN(TPU1TO3), GPIO_FN(PORT242_MSIOF2_TSCK),
1252 GPIO_FN(M13_BSW), GPIO_FN(PORT243_MSIOF2_TSYNC),
1253 GPIO_FN(M14_GSW), GPIO_FN(PORT244_MSIOF2_TXD),
1254 GPIO_FN(PORT245_IROUT), GPIO_FN(M15_RSW),
1255 GPIO_FN(SOUT3), GPIO_FN(SCIFA2_TXD1),
1256 GPIO_FN(SIN3), GPIO_FN(SCIFA2_RXD1),
1257 GPIO_FN(XRTS3), GPIO_FN(SCIFA2_RTS1), GPIO_FN(PORT248_MSIOF2_SS2),
1258 GPIO_FN(XCTS3), GPIO_FN(SCIFA2_CTS1), GPIO_FN(PORT249_MSIOF2_RXD),
1259 GPIO_FN(DINT), GPIO_FN(SCIFA2_SCK1), GPIO_FN(TS_SCK3),
1260 GPIO_FN(SDHICLK0), GPIO_FN(TCK2),
1261 GPIO_FN(SDHICD0),
1262 GPIO_FN(SDHID0_0), GPIO_FN(TMS2),
1263 GPIO_FN(SDHID0_1), GPIO_FN(TDO2),
1264 GPIO_FN(SDHID0_2), GPIO_FN(TDI2),
1265 GPIO_FN(SDHID0_3), GPIO_FN(RTCK2),
1266
1267 /* 49-6 (FN) */
1268 GPIO_FN(SDHICMD0), GPIO_FN(TRST2),
1269 GPIO_FN(SDHIWP0), GPIO_FN(EDBGREQ2),
1270 GPIO_FN(SDHICLK1), GPIO_FN(TCK3),
1271 GPIO_FN(SDHID1_0), GPIO_FN(M11_SLCD_SO2),
1272 GPIO_FN(TS_SPSYNC2), GPIO_FN(TMS3),
1273 GPIO_FN(SDHID1_1), GPIO_FN(M9_SLCD_AO2),
1274 GPIO_FN(TS_SDAT2), GPIO_FN(TDO3),
1275 GPIO_FN(SDHID1_2), GPIO_FN(M10_SLCD_CK2),
1276 GPIO_FN(TS_SDEN2), GPIO_FN(TDI3),
1277 GPIO_FN(SDHID1_3), GPIO_FN(M12_SLCD_CE2),
1278 GPIO_FN(TS_SCK2), GPIO_FN(RTCK3),
1279 GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
1280 GPIO_FN(SDHICLK2), GPIO_FN(SCIFB_SCK),
1281 GPIO_FN(SDHID2_0), GPIO_FN(SCIFB_TXD),
1282 GPIO_FN(SDHID2_1), GPIO_FN(SCIFB_CTS),
1283 GPIO_FN(SDHID2_2), GPIO_FN(SCIFB_RXD),
1284 GPIO_FN(SDHID2_3), GPIO_FN(SCIFB_RTS),
1285 GPIO_FN(SDHICMD2),
1286 GPIO_FN(RESETOUTS),
1287 GPIO_FN(DIVLOCK),
1288};
1289
1290static struct pinmux_cfg_reg pinmux_config_regs[] = {
1291 PORTCR(0, 0xe6050000), /* PORT0CR */
1292 PORTCR(1, 0xe6050001), /* PORT1CR */
1293 PORTCR(2, 0xe6050002), /* PORT2CR */
1294 PORTCR(3, 0xe6050003), /* PORT3CR */
1295 PORTCR(4, 0xe6050004), /* PORT4CR */
1296 PORTCR(5, 0xe6050005), /* PORT5CR */
1297 PORTCR(6, 0xe6050006), /* PORT6CR */
1298 PORTCR(7, 0xe6050007), /* PORT7CR */
1299 PORTCR(8, 0xe6050008), /* PORT8CR */
1300 PORTCR(9, 0xe6050009), /* PORT9CR */
1301
1302 PORTCR(10, 0xe605000a), /* PORT10CR */
1303 PORTCR(11, 0xe605000b), /* PORT11CR */
1304 PORTCR(12, 0xe605000c), /* PORT12CR */
1305 PORTCR(13, 0xe605000d), /* PORT13CR */
1306 PORTCR(14, 0xe605000e), /* PORT14CR */
1307 PORTCR(15, 0xe605000f), /* PORT15CR */
1308 PORTCR(16, 0xe6050010), /* PORT16CR */
1309 PORTCR(17, 0xe6050011), /* PORT17CR */
1310 PORTCR(18, 0xe6050012), /* PORT18CR */
1311 PORTCR(19, 0xe6050013), /* PORT19CR */
1312
1313 PORTCR(20, 0xe6050014), /* PORT20CR */
1314 PORTCR(21, 0xe6050015), /* PORT21CR */
1315 PORTCR(22, 0xe6050016), /* PORT22CR */
1316 PORTCR(23, 0xe6050017), /* PORT23CR */
1317 PORTCR(24, 0xe6050018), /* PORT24CR */
1318 PORTCR(25, 0xe6050019), /* PORT25CR */
1319 PORTCR(26, 0xe605001a), /* PORT26CR */
1320 PORTCR(27, 0xe605001b), /* PORT27CR */
1321 PORTCR(28, 0xe605001c), /* PORT28CR */
1322 PORTCR(29, 0xe605001d), /* PORT29CR */
1323
1324 PORTCR(30, 0xe605001e), /* PORT30CR */
1325 PORTCR(31, 0xe605001f), /* PORT31CR */
1326 PORTCR(32, 0xe6050020), /* PORT32CR */
1327 PORTCR(33, 0xe6050021), /* PORT33CR */
1328 PORTCR(34, 0xe6050022), /* PORT34CR */
1329 PORTCR(35, 0xe6050023), /* PORT35CR */
1330 PORTCR(36, 0xe6050024), /* PORT36CR */
1331 PORTCR(37, 0xe6050025), /* PORT37CR */
1332 PORTCR(38, 0xe6050026), /* PORT38CR */
1333 PORTCR(39, 0xe6050027), /* PORT39CR */
1334
1335 PORTCR(40, 0xe6050028), /* PORT40CR */
1336 PORTCR(41, 0xe6050029), /* PORT41CR */
1337 PORTCR(42, 0xe605002a), /* PORT42CR */
1338 PORTCR(43, 0xe605002b), /* PORT43CR */
1339 PORTCR(44, 0xe605002c), /* PORT44CR */
1340 PORTCR(45, 0xe605002d), /* PORT45CR */
1341 PORTCR(46, 0xe605002e), /* PORT46CR */
1342 PORTCR(47, 0xe605002f), /* PORT47CR */
1343 PORTCR(48, 0xe6050030), /* PORT48CR */
1344 PORTCR(49, 0xe6050031), /* PORT49CR */
1345
1346 PORTCR(50, 0xe6050032), /* PORT50CR */
1347 PORTCR(51, 0xe6050033), /* PORT51CR */
1348 PORTCR(52, 0xe6050034), /* PORT52CR */
1349 PORTCR(53, 0xe6050035), /* PORT53CR */
1350 PORTCR(54, 0xe6050036), /* PORT54CR */
1351 PORTCR(55, 0xe6050037), /* PORT55CR */
1352 PORTCR(56, 0xe6050038), /* PORT56CR */
1353 PORTCR(57, 0xe6050039), /* PORT57CR */
1354 PORTCR(58, 0xe605003a), /* PORT58CR */
1355 PORTCR(59, 0xe605003b), /* PORT59CR */
1356
1357 PORTCR(60, 0xe605003c), /* PORT60CR */
1358 PORTCR(61, 0xe605003d), /* PORT61CR */
1359 PORTCR(62, 0xe605003e), /* PORT62CR */
1360 PORTCR(63, 0xe605003f), /* PORT63CR */
1361 PORTCR(64, 0xe6050040), /* PORT64CR */
1362 PORTCR(65, 0xe6050041), /* PORT65CR */
1363 PORTCR(66, 0xe6050042), /* PORT66CR */
1364 PORTCR(67, 0xe6050043), /* PORT67CR */
1365 PORTCR(68, 0xe6050044), /* PORT68CR */
1366 PORTCR(69, 0xe6050045), /* PORT69CR */
1367
1368 PORTCR(70, 0xe6050046), /* PORT70CR */
1369 PORTCR(71, 0xe6050047), /* PORT71CR */
1370 PORTCR(72, 0xe6050048), /* PORT72CR */
1371 PORTCR(73, 0xe6050049), /* PORT73CR */
1372 PORTCR(74, 0xe605004a), /* PORT74CR */
1373 PORTCR(75, 0xe605004b), /* PORT75CR */
1374 PORTCR(76, 0xe605004c), /* PORT76CR */
1375 PORTCR(77, 0xe605004d), /* PORT77CR */
1376 PORTCR(78, 0xe605004e), /* PORT78CR */
1377 PORTCR(79, 0xe605004f), /* PORT79CR */
1378
1379 PORTCR(80, 0xe6050050), /* PORT80CR */
1380 PORTCR(81, 0xe6050051), /* PORT81CR */
1381 PORTCR(82, 0xe6050052), /* PORT82CR */
1382 PORTCR(83, 0xe6050053), /* PORT83CR */
1383 PORTCR(84, 0xe6050054), /* PORT84CR */
1384 PORTCR(85, 0xe6050055), /* PORT85CR */
1385 PORTCR(86, 0xe6050056), /* PORT86CR */
1386 PORTCR(87, 0xe6050057), /* PORT87CR */
1387 PORTCR(88, 0xe6051058), /* PORT88CR */
1388 PORTCR(89, 0xe6051059), /* PORT89CR */
1389
1390 PORTCR(90, 0xe605105a), /* PORT90CR */
1391 PORTCR(91, 0xe605105b), /* PORT91CR */
1392 PORTCR(92, 0xe605105c), /* PORT92CR */
1393 PORTCR(93, 0xe605105d), /* PORT93CR */
1394 PORTCR(94, 0xe605105e), /* PORT94CR */
1395 PORTCR(95, 0xe605105f), /* PORT95CR */
1396 PORTCR(96, 0xe6051060), /* PORT96CR */
1397 PORTCR(97, 0xe6051061), /* PORT97CR */
1398 PORTCR(98, 0xe6051062), /* PORT98CR */
1399 PORTCR(99, 0xe6051063), /* PORT99CR */
1400
1401 PORTCR(100, 0xe6051064), /* PORT100CR */
1402 PORTCR(101, 0xe6051065), /* PORT101CR */
1403 PORTCR(102, 0xe6051066), /* PORT102CR */
1404 PORTCR(103, 0xe6051067), /* PORT103CR */
1405 PORTCR(104, 0xe6051068), /* PORT104CR */
1406 PORTCR(105, 0xe6051069), /* PORT105CR */
1407 PORTCR(106, 0xe605106a), /* PORT106CR */
1408 PORTCR(107, 0xe605106b), /* PORT107CR */
1409 PORTCR(108, 0xe605106c), /* PORT108CR */
1410 PORTCR(109, 0xe605106d), /* PORT109CR */
1411
1412 PORTCR(110, 0xe605106e), /* PORT110CR */
1413 PORTCR(111, 0xe605106f), /* PORT111CR */
1414 PORTCR(112, 0xe6051070), /* PORT112CR */
1415 PORTCR(113, 0xe6051071), /* PORT113CR */
1416 PORTCR(114, 0xe6051072), /* PORT114CR */
1417 PORTCR(115, 0xe6051073), /* PORT115CR */
1418 PORTCR(116, 0xe6051074), /* PORT116CR */
1419 PORTCR(117, 0xe6051075), /* PORT117CR */
1420 PORTCR(118, 0xe6051076), /* PORT118CR */
1421 PORTCR(119, 0xe6051077), /* PORT119CR */
1422
1423 PORTCR(120, 0xe6051078), /* PORT120CR */
1424 PORTCR(121, 0xe6051079), /* PORT121CR */
1425 PORTCR(122, 0xe605107a), /* PORT122CR */
1426 PORTCR(123, 0xe605107b), /* PORT123CR */
1427 PORTCR(124, 0xe605107c), /* PORT124CR */
1428 PORTCR(125, 0xe605107d), /* PORT125CR */
1429 PORTCR(126, 0xe605107e), /* PORT126CR */
1430 PORTCR(127, 0xe605107f), /* PORT127CR */
1431 PORTCR(128, 0xe6051080), /* PORT128CR */
1432 PORTCR(129, 0xe6051081), /* PORT129CR */
1433
1434 PORTCR(130, 0xe6051082), /* PORT130CR */
1435 PORTCR(131, 0xe6051083), /* PORT131CR */
1436 PORTCR(132, 0xe6051084), /* PORT132CR */
1437 PORTCR(133, 0xe6051085), /* PORT133CR */
1438 PORTCR(134, 0xe6051086), /* PORT134CR */
1439 PORTCR(135, 0xe6051087), /* PORT135CR */
1440 PORTCR(136, 0xe6051088), /* PORT136CR */
1441 PORTCR(137, 0xe6051089), /* PORT137CR */
1442 PORTCR(138, 0xe605108a), /* PORT138CR */
1443 PORTCR(139, 0xe605108b), /* PORT139CR */
1444
1445 PORTCR(140, 0xe605108c), /* PORT140CR */
1446 PORTCR(141, 0xe605108d), /* PORT141CR */
1447 PORTCR(142, 0xe605108e), /* PORT142CR */
1448 PORTCR(143, 0xe605108f), /* PORT143CR */
1449 PORTCR(144, 0xe6051090), /* PORT144CR */
1450 PORTCR(145, 0xe6051091), /* PORT145CR */
1451 PORTCR(146, 0xe6051092), /* PORT146CR */
1452 PORTCR(147, 0xe6051093), /* PORT147CR */
1453 PORTCR(148, 0xe6051094), /* PORT148CR */
1454 PORTCR(149, 0xe6051095), /* PORT149CR */
1455
1456 PORTCR(150, 0xe6051096), /* PORT150CR */
1457 PORTCR(151, 0xe6051097), /* PORT151CR */
1458 PORTCR(152, 0xe6051098), /* PORT152CR */
1459 PORTCR(153, 0xe6051099), /* PORT153CR */
1460 PORTCR(154, 0xe605109a), /* PORT154CR */
1461 PORTCR(155, 0xe605109b), /* PORT155CR */
1462 PORTCR(156, 0xe605109c), /* PORT156CR */
1463 PORTCR(157, 0xe605109d), /* PORT157CR */
1464 PORTCR(158, 0xe605109e), /* PORT158CR */
1465 PORTCR(159, 0xe605109f), /* PORT159CR */
1466
1467 PORTCR(160, 0xe60510a0), /* PORT160CR */
1468 PORTCR(161, 0xe60510a1), /* PORT161CR */
1469 PORTCR(162, 0xe60510a2), /* PORT162CR */
1470 PORTCR(163, 0xe60510a3), /* PORT163CR */
1471 PORTCR(164, 0xe60510a4), /* PORT164CR */
1472 PORTCR(165, 0xe60510a5), /* PORT165CR */
1473 PORTCR(166, 0xe60510a6), /* PORT166CR */
1474 PORTCR(167, 0xe60510a7), /* PORT167CR */
1475 PORTCR(168, 0xe60510a8), /* PORT168CR */
1476 PORTCR(169, 0xe60510a9), /* PORT169CR */
1477
1478 PORTCR(170, 0xe60510aa), /* PORT170CR */
1479 PORTCR(171, 0xe60510ab), /* PORT171CR */
1480 PORTCR(172, 0xe60510ac), /* PORT172CR */
1481 PORTCR(173, 0xe60510ad), /* PORT173CR */
1482 PORTCR(174, 0xe60510ae), /* PORT174CR */
1483 PORTCR(175, 0xe60520af), /* PORT175CR */
1484 PORTCR(176, 0xe60520b0), /* PORT176CR */
1485 PORTCR(177, 0xe60520b1), /* PORT177CR */
1486 PORTCR(178, 0xe60520b2), /* PORT178CR */
1487 PORTCR(179, 0xe60520b3), /* PORT179CR */
1488
1489 PORTCR(180, 0xe60520b4), /* PORT180CR */
1490 PORTCR(181, 0xe60520b5), /* PORT181CR */
1491 PORTCR(182, 0xe60520b6), /* PORT182CR */
1492 PORTCR(183, 0xe60520b7), /* PORT183CR */
1493 PORTCR(184, 0xe60520b8), /* PORT184CR */
1494 PORTCR(185, 0xe60520b9), /* PORT185CR */
1495 PORTCR(186, 0xe60520ba), /* PORT186CR */
1496 PORTCR(187, 0xe60520bb), /* PORT187CR */
1497 PORTCR(188, 0xe60520bc), /* PORT188CR */
1498 PORTCR(189, 0xe60520bd), /* PORT189CR */
1499
1500 PORTCR(190, 0xe60520be), /* PORT190CR */
1501 PORTCR(191, 0xe60520bf), /* PORT191CR */
1502 PORTCR(192, 0xe60520c0), /* PORT192CR */
1503 PORTCR(193, 0xe60520c1), /* PORT193CR */
1504 PORTCR(194, 0xe60520c2), /* PORT194CR */
1505 PORTCR(195, 0xe60520c3), /* PORT195CR */
1506 PORTCR(196, 0xe60520c4), /* PORT196CR */
1507 PORTCR(197, 0xe60520c5), /* PORT197CR */
1508 PORTCR(198, 0xe60520c6), /* PORT198CR */
1509 PORTCR(199, 0xe60520c7), /* PORT199CR */
1510
1511 PORTCR(200, 0xe60520c8), /* PORT200CR */
1512 PORTCR(201, 0xe60520c9), /* PORT201CR */
1513 PORTCR(202, 0xe60520ca), /* PORT202CR */
1514 PORTCR(203, 0xe60520cb), /* PORT203CR */
1515 PORTCR(204, 0xe60520cc), /* PORT204CR */
1516 PORTCR(205, 0xe60520cd), /* PORT205CR */
1517 PORTCR(206, 0xe60520ce), /* PORT206CR */
1518 PORTCR(207, 0xe60520cf), /* PORT207CR */
1519 PORTCR(208, 0xe60520d0), /* PORT208CR */
1520 PORTCR(209, 0xe60520d1), /* PORT209CR */
1521
1522 PORTCR(210, 0xe60520d2), /* PORT210CR */
1523 PORTCR(211, 0xe60520d3), /* PORT211CR */
1524 PORTCR(212, 0xe60520d4), /* PORT212CR */
1525 PORTCR(213, 0xe60520d5), /* PORT213CR */
1526 PORTCR(214, 0xe60520d6), /* PORT214CR */
1527 PORTCR(215, 0xe60520d7), /* PORT215CR */
1528 PORTCR(216, 0xe60520d8), /* PORT216CR */
1529 PORTCR(217, 0xe60520d9), /* PORT217CR */
1530 PORTCR(218, 0xe60520da), /* PORT218CR */
1531 PORTCR(219, 0xe60520db), /* PORT219CR */
1532
1533 PORTCR(220, 0xe60520dc), /* PORT220CR */
1534 PORTCR(221, 0xe60520dd), /* PORT221CR */
1535 PORTCR(222, 0xe60520de), /* PORT222CR */
1536 PORTCR(223, 0xe60520df), /* PORT223CR */
1537 PORTCR(224, 0xe60520e0), /* PORT224CR */
1538 PORTCR(225, 0xe60520e1), /* PORT225CR */
1539 PORTCR(226, 0xe60520e2), /* PORT226CR */
1540 PORTCR(227, 0xe60520e3), /* PORT227CR */
1541 PORTCR(228, 0xe60520e4), /* PORT228CR */
1542 PORTCR(229, 0xe60520e5), /* PORT229CR */
1543
1544 PORTCR(230, 0xe60520e6), /* PORT230CR */
1545 PORTCR(231, 0xe60520e7), /* PORT231CR */
1546 PORTCR(232, 0xe60520e8), /* PORT232CR */
1547 PORTCR(233, 0xe60520e9), /* PORT233CR */
1548 PORTCR(234, 0xe60520ea), /* PORT234CR */
1549 PORTCR(235, 0xe60520eb), /* PORT235CR */
1550 PORTCR(236, 0xe60530ec), /* PORT236CR */
1551 PORTCR(237, 0xe60530ed), /* PORT237CR */
1552 PORTCR(238, 0xe60530ee), /* PORT238CR */
1553 PORTCR(239, 0xe60530ef), /* PORT239CR */
1554
1555 PORTCR(240, 0xe60530f0), /* PORT240CR */
1556 PORTCR(241, 0xe60530f1), /* PORT241CR */
1557 PORTCR(242, 0xe60530f2), /* PORT242CR */
1558 PORTCR(243, 0xe60530f3), /* PORT243CR */
1559 PORTCR(244, 0xe60530f4), /* PORT244CR */
1560 PORTCR(245, 0xe60530f5), /* PORT245CR */
1561 PORTCR(246, 0xe60530f6), /* PORT246CR */
1562 PORTCR(247, 0xe60530f7), /* PORT247CR */
1563 PORTCR(248, 0xe60530f8), /* PORT248CR */
1564 PORTCR(249, 0xe60530f9), /* PORT249CR */
1565
1566 PORTCR(250, 0xe60530fa), /* PORT250CR */
1567 PORTCR(251, 0xe60530fb), /* PORT251CR */
1568 PORTCR(252, 0xe60530fc), /* PORT252CR */
1569 PORTCR(253, 0xe60530fd), /* PORT253CR */
1570 PORTCR(254, 0xe60530fe), /* PORT254CR */
1571 PORTCR(255, 0xe60530ff), /* PORT255CR */
1572 PORTCR(256, 0xe6053100), /* PORT256CR */
1573 PORTCR(257, 0xe6053101), /* PORT257CR */
1574 PORTCR(258, 0xe6053102), /* PORT258CR */
1575 PORTCR(259, 0xe6053103), /* PORT259CR */
1576
1577 PORTCR(260, 0xe6053104), /* PORT260CR */
1578 PORTCR(261, 0xe6053105), /* PORT261CR */
1579 PORTCR(262, 0xe6053106), /* PORT262CR */
1580 PORTCR(263, 0xe6053107), /* PORT263CR */
1581 PORTCR(264, 0xe6053108), /* PORT264CR */
1582 PORTCR(265, 0xe6053109), /* PORT265CR */
1583 PORTCR(266, 0xe605310a), /* PORT266CR */
1584 PORTCR(267, 0xe605310b), /* PORT267CR */
1585 PORTCR(268, 0xe605310c), /* PORT268CR */
1586 PORTCR(269, 0xe605310d), /* PORT269CR */
1587
1588 PORTCR(270, 0xe605310e), /* PORT270CR */
1589 PORTCR(271, 0xe605310f), /* PORT271CR */
1590 PORTCR(272, 0xe6053110), /* PORT272CR */
1591
1592 { PINMUX_CFG_REG("MSELBCR", 0xe6058024, 32, 1) {
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1596 0, 0,
1597 0, 0,
1598 0, 0,
1599 0, 0,
1600 0, 0,
1601 MSELBCR_MSEL2_0, MSELBCR_MSEL2_1,
1602 0, 0,
1603 0, 0 }
1604 },
1605 { },
1606};
1607
1608static struct pinmux_data_reg pinmux_data_regs[] = {
1609 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
1610 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
1611 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
1612 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
1613 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
1614 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
1615 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
1616 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
1617 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
1618 },
1619 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054004, 32) {
1620 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
1621 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
1622 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
1623 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
1624 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
1625 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
1626 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
1627 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
1628 },
1629 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054008, 32) {
1630 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
1631 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
1632 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
1633 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
1634 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
1635 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
1636 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
1637 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
1638 },
1639 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
1640 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
1641 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
1642 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
1643 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
1644 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
1645 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
1646 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
1647 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
1648 },
1649 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
1650 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
1651 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
1652 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
1653 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
1654 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
1655 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
1656 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
1657 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
1658 },
1659 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
1660 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
1661 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
1662 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
1663 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
1664 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
1665 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
1666 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
1667 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
1668 },
1669 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
1670 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
1671 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
1672 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
1673 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
1674 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
1675 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
1676 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
1677 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
1678 },
1679 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
1680 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
1681 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
1682 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
1683 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
1684 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
1685 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
1686 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
1687 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
1688 },
1689 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
1690 0, 0, 0, 0,
1691 0, 0, 0, 0,
1692 0, 0, 0, 0,
1693 0, 0, 0, PORT272_DATA,
1694 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
1695 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
1696 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
1697 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
1698 },
1699 { },
1700};
1701
1702static struct pinmux_info sh7367_pinmux_info = {
1703 .name = "sh7367_pfc",
1704 .reserved_id = PINMUX_RESERVED,
1705 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1706 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1707 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1708 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1709 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1710 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1711 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1712
1713 .first_gpio = GPIO_PORT0,
1714 .last_gpio = GPIO_FN_DIVLOCK,
1715
1716 .gpios = pinmux_gpios,
1717 .cfg_regs = pinmux_config_regs,
1718 .data_regs = pinmux_data_regs,
1719
1720 .gpio_data = pinmux_data,
1721 .gpio_data_size = ARRAY_SIZE(pinmux_data),
1722};
1723
1724void sh7367_pinmux_init(void)
1725{
1726 register_pinmux(&sh7367_pinmux_info);
1727}
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
deleted file mode 100644
index e647f5410879..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ /dev/null
@@ -1,481 +0,0 @@
1/*
2 * sh7367 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/uio_driver.h>
26#include <linux/delay.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/serial_sci.h>
30#include <linux/sh_timer.h>
31#include <mach/hardware.h>
32#include <mach/common.h>
33#include <mach/irqs.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach/time.h>
38
39static struct map_desc sh7367_io_desc[] __initdata = {
40 /* create a 1:1 entity map for 0xe6xxxxxx
41 * used by CPGA, INTC and PFC.
42 */
43 {
44 .virtual = 0xe6000000,
45 .pfn = __phys_to_pfn(0xe6000000),
46 .length = 256 << 20,
47 .type = MT_DEVICE_NONSHARED
48 },
49};
50
51void __init sh7367_map_io(void)
52{
53 iotable_init(sh7367_io_desc, ARRAY_SIZE(sh7367_io_desc));
54}
55
56/* SCIFA0 */
57static struct plat_sci_port scif0_platform_data = {
58 .mapbase = 0xe6c40000,
59 .flags = UPF_BOOT_AUTOCONF,
60 .scscr = SCSCR_RE | SCSCR_TE,
61 .scbrr_algo_id = SCBRR_ALGO_4,
62 .type = PORT_SCIFA,
63 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
64 evt2irq(0xc00), evt2irq(0xc00) },
65};
66
67static struct platform_device scif0_device = {
68 .name = "sh-sci",
69 .id = 0,
70 .dev = {
71 .platform_data = &scif0_platform_data,
72 },
73};
74
75/* SCIFA1 */
76static struct plat_sci_port scif1_platform_data = {
77 .mapbase = 0xe6c50000,
78 .flags = UPF_BOOT_AUTOCONF,
79 .scscr = SCSCR_RE | SCSCR_TE,
80 .scbrr_algo_id = SCBRR_ALGO_4,
81 .type = PORT_SCIFA,
82 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
83 evt2irq(0xc20), evt2irq(0xc20) },
84};
85
86static struct platform_device scif1_device = {
87 .name = "sh-sci",
88 .id = 1,
89 .dev = {
90 .platform_data = &scif1_platform_data,
91 },
92};
93
94/* SCIFA2 */
95static struct plat_sci_port scif2_platform_data = {
96 .mapbase = 0xe6c60000,
97 .flags = UPF_BOOT_AUTOCONF,
98 .scscr = SCSCR_RE | SCSCR_TE,
99 .scbrr_algo_id = SCBRR_ALGO_4,
100 .type = PORT_SCIFA,
101 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
102 evt2irq(0xc40), evt2irq(0xc40) },
103};
104
105static struct platform_device scif2_device = {
106 .name = "sh-sci",
107 .id = 2,
108 .dev = {
109 .platform_data = &scif2_platform_data,
110 },
111};
112
113/* SCIFA3 */
114static struct plat_sci_port scif3_platform_data = {
115 .mapbase = 0xe6c70000,
116 .flags = UPF_BOOT_AUTOCONF,
117 .scscr = SCSCR_RE | SCSCR_TE,
118 .scbrr_algo_id = SCBRR_ALGO_4,
119 .type = PORT_SCIFA,
120 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
121 evt2irq(0xc60), evt2irq(0xc60) },
122};
123
124static struct platform_device scif3_device = {
125 .name = "sh-sci",
126 .id = 3,
127 .dev = {
128 .platform_data = &scif3_platform_data,
129 },
130};
131
132/* SCIFA4 */
133static struct plat_sci_port scif4_platform_data = {
134 .mapbase = 0xe6c80000,
135 .flags = UPF_BOOT_AUTOCONF,
136 .scscr = SCSCR_RE | SCSCR_TE,
137 .scbrr_algo_id = SCBRR_ALGO_4,
138 .type = PORT_SCIFA,
139 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
140 evt2irq(0xd20), evt2irq(0xd20) },
141};
142
143static struct platform_device scif4_device = {
144 .name = "sh-sci",
145 .id = 4,
146 .dev = {
147 .platform_data = &scif4_platform_data,
148 },
149};
150
151/* SCIFA5 */
152static struct plat_sci_port scif5_platform_data = {
153 .mapbase = 0xe6cb0000,
154 .flags = UPF_BOOT_AUTOCONF,
155 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA,
158 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
159 evt2irq(0xd40), evt2irq(0xd40) },
160};
161
162static struct platform_device scif5_device = {
163 .name = "sh-sci",
164 .id = 5,
165 .dev = {
166 .platform_data = &scif5_platform_data,
167 },
168};
169
170/* SCIFB */
171static struct plat_sci_port scif6_platform_data = {
172 .mapbase = 0xe6c30000,
173 .flags = UPF_BOOT_AUTOCONF,
174 .scscr = SCSCR_RE | SCSCR_TE,
175 .scbrr_algo_id = SCBRR_ALGO_4,
176 .type = PORT_SCIFB,
177 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
178 evt2irq(0xd60), evt2irq(0xd60) },
179};
180
181static struct platform_device scif6_device = {
182 .name = "sh-sci",
183 .id = 6,
184 .dev = {
185 .platform_data = &scif6_platform_data,
186 },
187};
188
189static struct sh_timer_config cmt10_platform_data = {
190 .name = "CMT10",
191 .channel_offset = 0x10,
192 .timer_bit = 0,
193 .clockevent_rating = 125,
194 .clocksource_rating = 125,
195};
196
197static struct resource cmt10_resources[] = {
198 [0] = {
199 .name = "CMT10",
200 .start = 0xe6138010,
201 .end = 0xe613801b,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 .start = evt2irq(0xb00), /* CMT1_CMT10 */
206 .flags = IORESOURCE_IRQ,
207 },
208};
209
210static struct platform_device cmt10_device = {
211 .name = "sh_cmt",
212 .id = 10,
213 .dev = {
214 .platform_data = &cmt10_platform_data,
215 },
216 .resource = cmt10_resources,
217 .num_resources = ARRAY_SIZE(cmt10_resources),
218};
219
220/* VPU */
221static struct uio_info vpu_platform_data = {
222 .name = "VPU5",
223 .version = "0",
224 .irq = intcs_evt2irq(0x980),
225};
226
227static struct resource vpu_resources[] = {
228 [0] = {
229 .name = "VPU",
230 .start = 0xfe900000,
231 .end = 0xfe902807,
232 .flags = IORESOURCE_MEM,
233 },
234};
235
236static struct platform_device vpu_device = {
237 .name = "uio_pdrv_genirq",
238 .id = 0,
239 .dev = {
240 .platform_data = &vpu_platform_data,
241 },
242 .resource = vpu_resources,
243 .num_resources = ARRAY_SIZE(vpu_resources),
244};
245
246/* VEU0 */
247static struct uio_info veu0_platform_data = {
248 .name = "VEU0",
249 .version = "0",
250 .irq = intcs_evt2irq(0x700),
251};
252
253static struct resource veu0_resources[] = {
254 [0] = {
255 .name = "VEU0",
256 .start = 0xfe920000,
257 .end = 0xfe9200b7,
258 .flags = IORESOURCE_MEM,
259 },
260};
261
262static struct platform_device veu0_device = {
263 .name = "uio_pdrv_genirq",
264 .id = 1,
265 .dev = {
266 .platform_data = &veu0_platform_data,
267 },
268 .resource = veu0_resources,
269 .num_resources = ARRAY_SIZE(veu0_resources),
270};
271
272/* VEU1 */
273static struct uio_info veu1_platform_data = {
274 .name = "VEU1",
275 .version = "0",
276 .irq = intcs_evt2irq(0x720),
277};
278
279static struct resource veu1_resources[] = {
280 [0] = {
281 .name = "VEU1",
282 .start = 0xfe924000,
283 .end = 0xfe9240b7,
284 .flags = IORESOURCE_MEM,
285 },
286};
287
288static struct platform_device veu1_device = {
289 .name = "uio_pdrv_genirq",
290 .id = 2,
291 .dev = {
292 .platform_data = &veu1_platform_data,
293 },
294 .resource = veu1_resources,
295 .num_resources = ARRAY_SIZE(veu1_resources),
296};
297
298/* VEU2 */
299static struct uio_info veu2_platform_data = {
300 .name = "VEU2",
301 .version = "0",
302 .irq = intcs_evt2irq(0x740),
303};
304
305static struct resource veu2_resources[] = {
306 [0] = {
307 .name = "VEU2",
308 .start = 0xfe928000,
309 .end = 0xfe9280b7,
310 .flags = IORESOURCE_MEM,
311 },
312};
313
314static struct platform_device veu2_device = {
315 .name = "uio_pdrv_genirq",
316 .id = 3,
317 .dev = {
318 .platform_data = &veu2_platform_data,
319 },
320 .resource = veu2_resources,
321 .num_resources = ARRAY_SIZE(veu2_resources),
322};
323
324/* VEU3 */
325static struct uio_info veu3_platform_data = {
326 .name = "VEU3",
327 .version = "0",
328 .irq = intcs_evt2irq(0x760),
329};
330
331static struct resource veu3_resources[] = {
332 [0] = {
333 .name = "VEU3",
334 .start = 0xfe92c000,
335 .end = 0xfe92c0b7,
336 .flags = IORESOURCE_MEM,
337 },
338};
339
340static struct platform_device veu3_device = {
341 .name = "uio_pdrv_genirq",
342 .id = 4,
343 .dev = {
344 .platform_data = &veu3_platform_data,
345 },
346 .resource = veu3_resources,
347 .num_resources = ARRAY_SIZE(veu3_resources),
348};
349
350/* VEU2H */
351static struct uio_info veu2h_platform_data = {
352 .name = "VEU2H",
353 .version = "0",
354 .irq = intcs_evt2irq(0x520),
355};
356
357static struct resource veu2h_resources[] = {
358 [0] = {
359 .name = "VEU2H",
360 .start = 0xfe93c000,
361 .end = 0xfe93c27b,
362 .flags = IORESOURCE_MEM,
363 },
364};
365
366static struct platform_device veu2h_device = {
367 .name = "uio_pdrv_genirq",
368 .id = 5,
369 .dev = {
370 .platform_data = &veu2h_platform_data,
371 },
372 .resource = veu2h_resources,
373 .num_resources = ARRAY_SIZE(veu2h_resources),
374};
375
376/* JPU */
377static struct uio_info jpu_platform_data = {
378 .name = "JPU",
379 .version = "0",
380 .irq = intcs_evt2irq(0x560),
381};
382
383static struct resource jpu_resources[] = {
384 [0] = {
385 .name = "JPU",
386 .start = 0xfe980000,
387 .end = 0xfe9902d3,
388 .flags = IORESOURCE_MEM,
389 },
390};
391
392static struct platform_device jpu_device = {
393 .name = "uio_pdrv_genirq",
394 .id = 6,
395 .dev = {
396 .platform_data = &jpu_platform_data,
397 },
398 .resource = jpu_resources,
399 .num_resources = ARRAY_SIZE(jpu_resources),
400};
401
402/* SPU1 */
403static struct uio_info spu1_platform_data = {
404 .name = "SPU1",
405 .version = "0",
406 .irq = evt2irq(0xfc0),
407};
408
409static struct resource spu1_resources[] = {
410 [0] = {
411 .name = "SPU1",
412 .start = 0xfe300000,
413 .end = 0xfe3fffff,
414 .flags = IORESOURCE_MEM,
415 },
416};
417
418static struct platform_device spu1_device = {
419 .name = "uio_pdrv_genirq",
420 .id = 7,
421 .dev = {
422 .platform_data = &spu1_platform_data,
423 },
424 .resource = spu1_resources,
425 .num_resources = ARRAY_SIZE(spu1_resources),
426};
427
428static struct platform_device *sh7367_early_devices[] __initdata = {
429 &scif0_device,
430 &scif1_device,
431 &scif2_device,
432 &scif3_device,
433 &scif4_device,
434 &scif5_device,
435 &scif6_device,
436 &cmt10_device,
437};
438
439static struct platform_device *sh7367_devices[] __initdata = {
440 &vpu_device,
441 &veu0_device,
442 &veu1_device,
443 &veu2_device,
444 &veu3_device,
445 &veu2h_device,
446 &jpu_device,
447 &spu1_device,
448};
449
450void __init sh7367_add_standard_devices(void)
451{
452 platform_add_devices(sh7367_early_devices,
453 ARRAY_SIZE(sh7367_early_devices));
454
455 platform_add_devices(sh7367_devices,
456 ARRAY_SIZE(sh7367_devices));
457}
458
459static void __init sh7367_earlytimer_init(void)
460{
461 sh7367_clock_init();
462 shmobile_earlytimer_init();
463}
464
465#define SYMSTPCR2 IOMEM(0xe6158048)
466#define SYMSTPCR2_CMT1 (1 << 29)
467
468void __init sh7367_add_early_devices(void)
469{
470 /* enable clock to CMT1 */
471 __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
472
473 early_platform_add_devices(sh7367_early_devices,
474 ARRAY_SIZE(sh7367_early_devices));
475
476 /* setup early console here as well */
477 shmobile_setup_console();
478
479 /* override timer setup with soc-specific code */
480 shmobile_timer.init = sh7367_earlytimer_init;
481}
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