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authorLinus Torvalds <torvalds@linux-foundation.org>2014-12-09 20:17:47 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2014-12-09 20:17:47 -0500
commited8efd2de75479a175bd21df073d9e97df65a820 (patch)
treeced8d7eaac311de88c88b5536edeecd4db6b7ae2
parent151cd97630f87451cab412e40750d0e5f7581c98 (diff)
parent70bcc9ba15690f1e616fd5f60831f4602dd39670 (diff)
Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM64 SoC changes from Arnd Bergmann: "This adds support for two new ARM64 platforms: - ARM Juno - AMD Seattle We had submissions for a number of additional platforms from Samsung, Freescale and Spreadtrum but are still working out the best process for getting these merged" * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: amd-seattle: Fix PCI bus range due to SMMU limitation arm64: ARM: Fix the Generic Timers interrupt active level description arm64: amd-seattle: Adding device tree for AMD Seattle platform arm64: Add Juno board device tree. arm64: Create link to include/dt-bindings to enable C preprocessor use.
Diffstat
-rw-r--r--arch/arm64/Kconfig5
-rw-r--r--arch/arm64/boot/dts/Makefile1
-rw-r--r--arch/arm64/boot/dts/amd/Makefile5
-rw-r--r--arch/arm64/boot/dts/amd/amd-overdrive.dts66
-rw-r--r--arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi54
-rw-r--r--arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi172
-rw-r--r--arch/arm64/boot/dts/arm/Makefile1
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dts8
-rw-r--r--arch/arm64/boot/dts/arm/juno-clocks.dtsi44
-rw-r--r--arch/arm64/boot/dts/arm/juno-motherboard.dtsi129
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts218
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts8
l---------arch/arm64/boot/dts/include/dt-bindings1
13 files changed, 704 insertions, 8 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 6caad5428178..f385273f4b24 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -145,6 +145,11 @@ source "kernel/Kconfig.freezer"
145 145
146menu "Platform selection" 146menu "Platform selection"
147 147
148config ARCH_SEATTLE
149 bool "AMD Seattle SoC Family"
150 help
151 This enables support for AMD Seattle SOC Family
152
148config ARCH_THUNDER 153config ARCH_THUNDER
149 bool "Cavium Inc. Thunder SoC Family" 154 bool "Cavium Inc. Thunder SoC Family"
150 help 155 help
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e8efc8ff3d58..3b8d427c3985 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,3 +1,4 @@
1dts-dirs += amd
1dts-dirs += apm 2dts-dirs += apm
2dts-dirs += arm 3dts-dirs += arm
3dts-dirs += cavium 4dts-dirs += cavium
diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
new file mode 100644
index 000000000000..cfdf701e05df
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/Makefile
@@ -0,0 +1,5 @@
1dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb
2
3always := $(dtb-y)
4subdir-y := $(dts-dirs)
5clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/amd/amd-overdrive.dts b/arch/arm64/boot/dts/amd/amd-overdrive.dts
new file mode 100644
index 000000000000..564a3f7df71d
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-overdrive.dts
@@ -0,0 +1,66 @@
1/*
2 * DTS file for AMD Seattle Overdrive Development Board
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 */
6
7/dts-v1/;
8
9/include/ "amd-seattle-soc.dtsi"
10
11/ {
12 model = "AMD Seattle Development Board (Overdrive)";
13 compatible = "amd,seattle-overdrive", "amd,seattle";
14
15 chosen {
16 stdout-path = &serial0;
17 linux,pci-probe-only;
18 };
19};
20
21&ccp0 {
22 status = "ok";
23};
24
25&gpio0 {
26 status = "ok";
27};
28
29&gpio1 {
30 status = "ok";
31};
32
33&i2c0 {
34 status = "ok";
35};
36
37&pcie0 {
38 status = "ok";
39};
40
41&spi0 {
42 status = "ok";
43};
44
45&spi1 {
46 status = "ok";
47 sdcard0: sdcard@0 {
48 compatible = "mmc-spi-slot";
49 reg = <0>;
50 spi-max-frequency = <20000000>;
51 voltage-ranges = <3200 3400>;
52 gpios = <&gpio0 7 0>;
53 interrupt-parent = <&gpio0>;
54 interrupts = <7 3>;
55 pl022,hierarchy = <0>;
56 pl022,interface = <0>;
57 pl022,com-mode = <0x0>;
58 pl022,rx-level-trig = <0>;
59 pl022,tx-level-trig = <0>;
60 };
61};
62
63&v2m0 {
64 arm,msi-base-spi = <64>;
65 arm,msi-num-spis = <256>;
66};
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
new file mode 100644
index 000000000000..f623c46525a6
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-seattle-clks.dtsi
@@ -0,0 +1,54 @@
1/*
2 * DTS file for AMD Seattle Clocks
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 */
6
7 adl3clk_100mhz: clk100mhz_0 {
8 compatible = "fixed-clock";
9 #clock-cells = <0>;
10 clock-frequency = <100000000>;
11 clock-output-names = "adl3clk_100mhz";
12 };
13
14 ccpclk_375mhz: clk375mhz {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <375000000>;
18 clock-output-names = "ccpclk_375mhz";
19 };
20
21 sataclk_333mhz: clk333mhz {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <333000000>;
25 clock-output-names = "sataclk_333mhz";
26 };
27
28 pcieclk_500mhz: clk500mhz_0 {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <500000000>;
32 clock-output-names = "pcieclk_500mhz";
33 };
34
35 dmaclk_500mhz: clk500mhz_1 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <500000000>;
39 clock-output-names = "dmaclk_500mhz";
40 };
41
42 miscclk_250mhz: clk250mhz_4 {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <250000000>;
46 clock-output-names = "miscclk_250mhz";
47 };
48
49 uartspiclk_100mhz: clk100mhz_1 {
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <100000000>;
53 clock-output-names = "uartspiclk_100mhz";
54 };
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
new file mode 100644
index 000000000000..2874d92881fd
--- /dev/null
+++ b/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
@@ -0,0 +1,172 @@
1/*
2 * DTS file for AMD Seattle SoC
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 */
6
7/ {
8 compatible = "amd,seattle";
9 interrupt-parent = <&gic0>;
10 #address-cells = <2>;
11 #size-cells = <2>;
12
13 gic0: interrupt-controller@e1101000 {
14 compatible = "arm,gic-400", "arm,cortex-a15-gic";
15 interrupt-controller;
16 #interrupt-cells = <3>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19 reg = <0x0 0xe1110000 0 0x1000>,
20 <0x0 0xe112f000 0 0x2000>,
21 <0x0 0xe1140000 0 0x10000>,
22 <0x0 0xe1160000 0 0x10000>;
23 interrupts = <1 9 0xf04>;
24 ranges = <0 0 0 0xe1100000 0 0x100000>;
25 v2m0: v2m@e0080000 {
26 compatible = "arm,gic-v2m-frame";
27 msi-controller;
28 reg = <0x0 0x00080000 0 0x1000>;
29 };
30 };
31
32 timer {
33 compatible = "arm,armv8-timer";
34 interrupts = <1 13 0xff04>,
35 <1 14 0xff04>,
36 <1 11 0xff04>,
37 <1 10 0xff04>;
38 };
39
40 pmu {
41 compatible = "arm,armv8-pmuv3";
42 interrupts = <0 7 4>,
43 <0 8 4>,
44 <0 9 4>,
45 <0 10 4>,
46 <0 11 4>,
47 <0 12 4>,
48 <0 13 4>,
49 <0 14 4>;
50 };
51
52 smb0: smb {
53 compatible = "simple-bus";
54 #address-cells = <2>;
55 #size-cells = <2>;
56 ranges;
57
58 /* DDR range is 40-bit addressing */
59 dma-ranges = <0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
60
61 /include/ "amd-seattle-clks.dtsi"
62
63 sata0: sata@e0300000 {
64 compatible = "snps,dwc-ahci";
65 reg = <0 0xe0300000 0 0x800>;
66 interrupts = <0 355 4>;
67 clocks = <&sataclk_333mhz>;
68 dma-coherent;
69 };
70
71 i2c0: i2c@e1000000 {
72 status = "disabled";
73 compatible = "snps,designware-i2c";
74 reg = <0 0xe1000000 0 0x1000>;
75 interrupts = <0 357 4>;
76 clocks = <&uartspiclk_100mhz>;
77 };
78
79 serial0: serial@e1010000 {
80 compatible = "arm,pl011", "arm,primecell";
81 reg = <0 0xe1010000 0 0x1000>;
82 interrupts = <0 328 4>;
83 clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>;
84 clock-names = "uartclk", "apb_pclk";
85 };
86
87 spi0: ssp@e1020000 {
88 status = "disabled";
89 compatible = "arm,pl022", "arm,primecell";
90 #gpio-cells = <2>;
91 reg = <0 0xe1020000 0 0x1000>;
92 spi-controller;
93 interrupts = <0 330 4>;
94 clocks = <&uartspiclk_100mhz>;
95 clock-names = "apb_pclk";
96 };
97
98 spi1: ssp@e1030000 {
99 status = "disabled";
100 compatible = "arm,pl022", "arm,primecell";
101 #gpio-cells = <2>;
102 reg = <0 0xe1030000 0 0x1000>;
103 spi-controller;
104 interrupts = <0 329 4>;
105 clocks = <&uartspiclk_100mhz>;
106 clock-names = "apb_pclk";
107 num-cs = <1>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 };
111
112 gpio0: gpio@e1040000 {
113 status = "disabled";
114 compatible = "arm,pl061", "arm,primecell";
115 #gpio-cells = <2>;
116 reg = <0 0xe1040000 0 0x1000>;
117 gpio-controller;
118 interrupts = <0 359 4>;
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 clocks = <&uartspiclk_100mhz>;
122 clock-names = "apb_pclk";
123 };
124
125 gpio1: gpio@e1050000 {
126 status = "disabled";
127 compatible = "arm,pl061", "arm,primecell";
128 #gpio-cells = <2>;
129 reg = <0 0xe1050000 0 0x1000>;
130 gpio-controller;
131 interrupts = <0 358 4>;
132 clocks = <&uartspiclk_100mhz>;
133 clock-names = "apb_pclk";
134 };
135
136 ccp0: ccp@e0100000 {
137 status = "disabled";
138 compatible = "amd,ccp-seattle-v1a";
139 reg = <0 0xe0100000 0 0x10000>;
140 interrupts = <0 3 4>;
141 dma-coherent;
142 };
143
144 pcie0: pcie@f0000000 {
145 compatible = "pci-host-ecam-generic";
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 device_type = "pci";
150 bus-range = <0 0x7f>;
151 msi-parent = <&v2m0>;
152 reg = <0 0xf0000000 0 0x10000000>;
153
154 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
155 interrupt-map =
156 <0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
157 <0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
158 <0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
159 <0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
160
161 dma-coherent;
162 dma-ranges = <0x43000000 0x80 0x0 0x80 0x0 0x7f 0xffffffff>;
163 ranges =
164 /* I/O Memory (size=64K) */
165 <0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
166 /* 32-bit MMIO (size=2G) */
167 <0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
168 /* 64-bit MMIO (size= 124G) */
169 <0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
170 };
171 };
172};
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index 43d1404bb3c1..301a0dada1fe 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -1,4 +1,5 @@
1dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb 1dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
2dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb
2dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb 3dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
3 4
4always := $(dtb-y) 5always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 4a060906809d..27f32962e55c 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -78,10 +78,10 @@
78 78
79 timer { 79 timer {
80 compatible = "arm,armv8-timer"; 80 compatible = "arm,armv8-timer";
81 interrupts = <1 13 0xff01>, 81 interrupts = <1 13 0xf08>,
82 <1 14 0xff01>, 82 <1 14 0xf08>,
83 <1 11 0xff01>, 83 <1 11 0xf08>,
84 <1 10 0xff01>; 84 <1 10 0xf08>;
85 clock-frequency = <100000000>; 85 clock-frequency = <100000000>;
86 }; 86 };
87 87
diff --git a/arch/arm64/boot/dts/arm/juno-clocks.dtsi b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
new file mode 100644
index 000000000000..ea2b5666a16f
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno-clocks.dtsi
@@ -0,0 +1,44 @@
1/*
2 * ARM Juno Platform clocks
3 *
4 * Copyright (c) 2013-2014 ARM Ltd
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 *
8 */
9
10 /* SoC fixed clocks */
11 soc_uartclk: refclk72738khz {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <7273800>;
15 clock-output-names = "juno:uartclk";
16 };
17
18 soc_usb48mhz: clk48mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <48000000>;
22 clock-output-names = "clk48mhz";
23 };
24
25 soc_smc50mhz: clk50mhz {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <50000000>;
29 clock-output-names = "smc_clk";
30 };
31
32 soc_refclk100mhz: refclk100mhz {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <100000000>;
36 clock-output-names = "apb_pclk";
37 };
38
39 soc_faxiclk: refclk533mhz {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <533000000>;
43 clock-output-names = "faxi_clk";
44 };
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
new file mode 100644
index 000000000000..c138b95a8356
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi
@@ -0,0 +1,129 @@
1/*
2 * ARM Juno Platform motherboard peripherals
3 *
4 * Copyright (c) 2013-2014 ARM Ltd
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 *
8 */
9
10 mb_clk24mhz: clk24mhz {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <24000000>;
14 clock-output-names = "juno_mb:clk24mhz";
15 };
16
17 mb_clk25mhz: clk25mhz {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <25000000>;
21 clock-output-names = "juno_mb:clk25mhz";
22 };
23
24 motherboard {
25 compatible = "arm,vexpress,v2p-p1", "simple-bus";
26 #address-cells = <2>; /* SMB chipselect number and offset */
27 #size-cells = <1>;
28 #interrupt-cells = <1>;
29 ranges;
30 model = "V2M-Juno";
31 arm,hbi = <0x252>;
32 arm,vexpress,site = <0>;
33 arm,v2m-memory-map = "rs1";
34
35 mb_fixed_3v3: fixedregulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "MCC_SB_3V3";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 regulator-always-on;
41 };
42
43 ethernet@2,00000000 {
44 compatible = "smsc,lan9118", "smsc,lan9115";
45 reg = <2 0x00000000 0x10000>;
46 interrupts = <3>;
47 phy-mode = "mii";
48 reg-io-width = <4>;
49 smsc,irq-active-high;
50 smsc,irq-push-pull;
51 clocks = <&mb_clk25mhz>;
52 vdd33a-supply = <&mb_fixed_3v3>;
53 vddvario-supply = <&mb_fixed_3v3>;
54 };
55
56 usb@5,00000000 {
57 compatible = "nxp,usb-isp1763";
58 reg = <5 0x00000000 0x20000>;
59 bus-width = <16>;
60 interrupts = <4>;
61 };
62
63 iofpga@3,00000000 {
64 compatible = "arm,amba-bus", "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges = <0 3 0 0x200000>;
68
69 mmci@050000 {
70 compatible = "arm,pl180", "arm,primecell";
71 reg = <0x050000 0x1000>;
72 interrupts = <5>;
73 /* cd-gpios = <&v2m_mmc_gpios 0 0>;
74 wp-gpios = <&v2m_mmc_gpios 1 0>; */
75 max-frequency = <12000000>;
76 vmmc-supply = <&mb_fixed_3v3>;
77 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
78 clock-names = "mclk", "apb_pclk";
79 };
80
81 kmi@060000 {
82 compatible = "arm,pl050", "arm,primecell";
83 reg = <0x060000 0x1000>;
84 interrupts = <8>;
85 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
86 clock-names = "KMIREFCLK", "apb_pclk";
87 };
88
89 kmi@070000 {
90 compatible = "arm,pl050", "arm,primecell";
91 reg = <0x070000 0x1000>;
92 interrupts = <8>;
93 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
94 clock-names = "KMIREFCLK", "apb_pclk";
95 };
96
97 wdt@0f0000 {
98 compatible = "arm,sp805", "arm,primecell";
99 reg = <0x0f0000 0x10000>;
100 interrupts = <7>;
101 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
102 clock-names = "wdogclk", "apb_pclk";
103 };
104
105 v2m_timer01: timer@110000 {
106 compatible = "arm,sp804", "arm,primecell";
107 reg = <0x110000 0x10000>;
108 interrupts = <9>;
109 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
110 clock-names = "timclken1", "apb_pclk";
111 };
112
113 v2m_timer23: timer@120000 {
114 compatible = "arm,sp804", "arm,primecell";
115 reg = <0x120000 0x10000>;
116 interrupts = <9>;
117 clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
118 clock-names = "timclken1", "apb_pclk";
119 };
120
121 rtc@170000 {
122 compatible = "arm,pl031", "arm,primecell";
123 reg = <0x170000 0x10000>;
124 interrupts = <0>;
125 clocks = <&soc_smc50mhz>;
126 clock-names = "apb_pclk";
127 };
128 };
129 };
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
new file mode 100644
index 000000000000..cb3073e4e7a8
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -0,0 +1,218 @@
1/*
2 * ARM Ltd. Juno Platform
3 *
4 * Copyright (c) 2013-2014 ARM Ltd.
5 *
6 * This file is licensed under a dual GPLv2 or BSD license.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14 model = "ARM Juno development board (r0)";
15 compatible = "arm,juno", "arm,vexpress";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 serial0 = &soc_uart0;
22 };
23
24 chosen {
25 stdout-path = &soc_uart0;
26 };
27
28 psci {
29 compatible = "arm,psci-0.2";
30 method = "smc";
31 };
32
33 cpus {
34 #address-cells = <2>;
35 #size-cells = <0>;
36
37 A57_0: cpu@0 {
38 compatible = "arm,cortex-a57","arm,armv8";
39 reg = <0x0 0x0>;
40 device_type = "cpu";
41 enable-method = "psci";
42 };
43
44 A57_1: cpu@1 {
45 compatible = "arm,cortex-a57","arm,armv8";
46 reg = <0x0 0x1>;
47 device_type = "cpu";
48 enable-method = "psci";
49 };
50
51 A53_0: cpu@100 {
52 compatible = "arm,cortex-a53","arm,armv8";
53 reg = <0x0 0x100>;
54 device_type = "cpu";
55 enable-method = "psci";
56 };
57
58 A53_1: cpu@101 {
59 compatible = "arm,cortex-a53","arm,armv8";
60 reg = <0x0 0x101>;
61 device_type = "cpu";
62 enable-method = "psci";
63 };
64
65 A53_2: cpu@102 {
66 compatible = "arm,cortex-a53","arm,armv8";
67 reg = <0x0 0x102>;
68 device_type = "cpu";
69 enable-method = "psci";
70 };
71
72 A53_3: cpu@103 {
73 compatible = "arm,cortex-a53","arm,armv8";
74 reg = <0x0 0x103>;
75 device_type = "cpu";
76 enable-method = "psci";
77 };
78 };
79
80 memory@80000000 {
81 device_type = "memory";
82 /* last 16MB of the first memory area is reserved for secure world use by firmware */
83 reg = <0x00000000 0x80000000 0x0 0x7f000000>,
84 <0x00000008 0x80000000 0x1 0x80000000>;
85 };
86
87 gic: interrupt-controller@2c001000 {
88 compatible = "arm,gic-400", "arm,cortex-a15-gic";
89 reg = <0x0 0x2c010000 0 0x1000>,
90 <0x0 0x2c02f000 0 0x2000>,
91 <0x0 0x2c04f000 0 0x2000>,
92 <0x0 0x2c06f000 0 0x2000>;
93 #address-cells = <0>;
94 #interrupt-cells = <3>;
95 interrupt-controller;
96 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
97 };
98
99 timer {
100 compatible = "arm,armv8-timer";
101 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
105 };
106
107 pmu {
108 compatible = "arm,armv8-pmuv3";
109 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
115 };
116
117 /include/ "juno-clocks.dtsi"
118
119 dma@7ff00000 {
120 compatible = "arm,pl330", "arm,primecell";
121 reg = <0x0 0x7ff00000 0 0x1000>;
122 #dma-cells = <1>;
123 #dma-channels = <8>;
124 #dma-requests = <32>;
125 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&soc_faxiclk>;
134 clock-names = "apb_pclk";
135 };
136
137 soc_uart0: uart@7ff80000 {
138 compatible = "arm,pl011", "arm,primecell";
139 reg = <0x0 0x7ff80000 0x0 0x1000>;
140 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
142 clock-names = "uartclk", "apb_pclk";
143 };
144
145 i2c@7ffa0000 {
146 compatible = "snps,designware-i2c";
147 reg = <0x0 0x7ffa0000 0x0 0x1000>;
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
151 clock-frequency = <400000>;
152 i2c-sda-hold-time-ns = <500>;
153 clocks = <&soc_smc50mhz>;
154
155 dvi0: dvi-transmitter@70 {
156 compatible = "nxp,tda998x";
157 reg = <0x70>;
158 };
159
160 dvi1: dvi-transmitter@71 {
161 compatible = "nxp,tda998x";
162 reg = <0x71>;
163 };
164 };
165
166 ohci@7ffb0000 {
167 compatible = "generic-ohci";
168 reg = <0x0 0x7ffb0000 0x0 0x10000>;
169 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&soc_usb48mhz>;
171 };
172
173 ehci@7ffc0000 {
174 compatible = "generic-ehci";
175 reg = <0x0 0x7ffc0000 0x0 0x10000>;
176 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&soc_usb48mhz>;
178 };
179
180 memory-controller@7ffd0000 {
181 compatible = "arm,pl354", "arm,primecell";
182 reg = <0 0x7ffd0000 0 0x1000>;
183 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&soc_smc50mhz>;
186 clock-names = "apb_pclk";
187 };
188
189 smb {
190 compatible = "simple-bus";
191 #address-cells = <2>;
192 #size-cells = <1>;
193 ranges = <0 0 0 0x08000000 0x04000000>,
194 <1 0 0 0x14000000 0x04000000>,
195 <2 0 0 0x18000000 0x04000000>,
196 <3 0 0 0x1c000000 0x04000000>,
197 <4 0 0 0x0c000000 0x04000000>,
198 <5 0 0 0x10000000 0x04000000>;
199
200 #interrupt-cells = <1>;
201 interrupt-map-mask = <0 0 15>;
202 interrupt-map = <0 0 0 &gic 0 68 IRQ_TYPE_LEVEL_HIGH>,
203 <0 0 1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
204 <0 0 2 &gic 0 70 IRQ_TYPE_LEVEL_HIGH>,
205 <0 0 3 &gic 0 160 IRQ_TYPE_LEVEL_HIGH>,
206 <0 0 4 &gic 0 161 IRQ_TYPE_LEVEL_HIGH>,
207 <0 0 5 &gic 0 162 IRQ_TYPE_LEVEL_HIGH>,
208 <0 0 6 &gic 0 163 IRQ_TYPE_LEVEL_HIGH>,
209 <0 0 7 &gic 0 164 IRQ_TYPE_LEVEL_HIGH>,
210 <0 0 8 &gic 0 165 IRQ_TYPE_LEVEL_HIGH>,
211 <0 0 9 &gic 0 166 IRQ_TYPE_LEVEL_HIGH>,
212 <0 0 10 &gic 0 167 IRQ_TYPE_LEVEL_HIGH>,
213 <0 0 11 &gic 0 168 IRQ_TYPE_LEVEL_HIGH>,
214 <0 0 12 &gic 0 169 IRQ_TYPE_LEVEL_HIGH>;
215
216 /include/ "juno-motherboard.dtsi"
217 };
218};
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index 572005ea2217..efc59b3baf63 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -81,10 +81,10 @@
81 81
82 timer { 82 timer {
83 compatible = "arm,armv8-timer"; 83 compatible = "arm,armv8-timer";
84 interrupts = <1 13 0xff01>, 84 interrupts = <1 13 0xf08>,
85 <1 14 0xff01>, 85 <1 14 0xf08>,
86 <1 11 0xff01>, 86 <1 11 0xf08>,
87 <1 10 0xff01>; 87 <1 10 0xf08>;
88 clock-frequency = <100000000>; 88 clock-frequency = <100000000>;
89 }; 89 };
90 90
diff --git a/arch/arm64/boot/dts/include/dt-bindings b/arch/arm64/boot/dts/include/dt-bindings
new file mode 120000
index 000000000000..08c00e4972fa
--- /dev/null
+++ b/arch/arm64/boot/dts/include/dt-bindings
@@ -0,0 +1 @@
../../../../../include/dt-bindings \ No newline at end of file
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 11:09:56 -0500