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authorJiang Liu <jiang.liu@linux.intel.com>2014-06-09 04:20:01 -0400
committerThomas Gleixner <tglx@linutronix.de>2014-06-21 17:05:43 -0400
commitecc527d560cd87c74cc0bc7aff36eb72f7e18615 (patch)
treecb09c8ae51fbc58c41efd235813a372093329d25
parent9506063992cc0785246fd314a4a40b6314685aa8 (diff)
x86, irq, SFI: Use common irqdomain map interface to program IOAPIC pins
Refine SFI to use common irqdomain map interface to program IOAPIC pins, so we can unify the callsite to progam IOAPIC pins. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: H. Peter Anvin <hpa@linux.intel.com> Cc: sfi-devel@simplefirmware.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Yinghai Lu <yinghai@kernel.org> Cc: Len Brown <lenb@kernel.org> Cc: David Cohen <david.a.cohen@linux.intel.com> Cc: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Link: http://lkml.kernel.org/r/1402302011-23642-33-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
-rw-r--r--arch/x86/pci/intel_mid_pci.c19
-rw-r--r--arch/x86/platform/intel-mid/sfi.c58
-rw-r--r--arch/x86/platform/sfi/sfi.c4
3 files changed, 35 insertions, 46 deletions
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index fcbdc5fac2c6..337d165c64f1 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -208,27 +208,22 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
208 208
209static int intel_mid_pci_irq_enable(struct pci_dev *dev) 209static int intel_mid_pci_irq_enable(struct pci_dev *dev)
210{ 210{
211 u8 pin; 211 int polarity;
212 struct io_apic_irq_attr irq_attr;
213 212
214 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 213 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
214 polarity = 0; /* active high */
215 else
216 polarity = 1; /* active low */
215 217
216 /* 218 /*
217 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to 219 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
218 * IOAPIC RTE entries, so we just enable RTE for the device. 220 * IOAPIC RTE entries, so we just enable RTE for the device.
219 */ 221 */
222 if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
223 return -EBUSY;
220 if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0) 224 if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
221 return -EBUSY; 225 return -EBUSY;
222 226
223 irq_attr.ioapic = mp_find_ioapic(dev->irq);
224 irq_attr.ioapic_pin = dev->irq;
225 irq_attr.trigger = 1; /* level */
226 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
227 irq_attr.polarity = 0; /* active high */
228 else
229 irq_attr.polarity = 1; /* active low */
230 io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
231
232 return 0; 227 return 0;
233} 228}
234 229
diff --git a/arch/x86/platform/intel-mid/sfi.c b/arch/x86/platform/intel-mid/sfi.c
index 7161395e7de7..3c53a90fdb18 100644
--- a/arch/x86/platform/intel-mid/sfi.c
+++ b/arch/x86/platform/intel-mid/sfi.c
@@ -432,9 +432,8 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
432 struct sfi_table_simple *sb; 432 struct sfi_table_simple *sb;
433 struct sfi_device_table_entry *pentry; 433 struct sfi_device_table_entry *pentry;
434 struct devs_id *dev = NULL; 434 struct devs_id *dev = NULL;
435 int num, i; 435 int num, i, ret;
436 int ioapic; 436 int polarity;
437 struct io_apic_irq_attr irq_attr;
438 437
439 sb = (struct sfi_table_simple *)table; 438 sb = (struct sfi_table_simple *)table;
440 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry); 439 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
@@ -448,37 +447,30 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
448 * devices, but they have separate RTE entry in IOAPIC 447 * devices, but they have separate RTE entry in IOAPIC
449 * so we have to enable them one by one here 448 * so we have to enable them one by one here
450 */ 449 */
451 ioapic = mp_find_ioapic(irq); 450 if (intel_mid_identify_cpu() ==
452 if (ioapic >= 0) { 451 INTEL_MID_CPU_CHIP_TANGIER) {
453 irq_attr.ioapic = ioapic; 452 if (!strncmp(pentry->name, "r69001-ts-i2c", 13))
454 irq_attr.ioapic_pin = irq; 453 /* active low */
455 irq_attr.trigger = 1; 454 polarity = 1;
456 if (intel_mid_identify_cpu() == 455 else if (!strncmp(pentry->name,
457 INTEL_MID_CPU_CHIP_TANGIER) { 456 "synaptics_3202", 14))
458 if (!strncmp(pentry->name, 457 /* active low */
459 "r69001-ts-i2c", 13)) 458 polarity = 1;
460 /* active low */ 459 else if (irq == 41)
461 irq_attr.polarity = 1; 460 /* fast_int_1 */
462 else if (!strncmp(pentry->name, 461 polarity = 1;
463 "synaptics_3202", 14)) 462 else
464 /* active low */ 463 /* active high */
465 irq_attr.polarity = 1; 464 polarity = 0;
466 else if (irq == 41) 465 } else {
467 /* fast_int_1 */ 466 /* PNW and CLV go with active low */
468 irq_attr.polarity = 1; 467 polarity = 1;
469 else
470 /* active high */
471 irq_attr.polarity = 0;
472 } else {
473 /* PNW and CLV go with active low */
474 irq_attr.polarity = 1;
475 }
476 WARN_ON(mp_map_gsi_to_irq(irq,
477 IOAPIC_MAP_ALLOC) < 0);
478 io_apic_set_pci_routing(NULL, irq, &irq_attr);
479 } 468 }
480 } else { 469
481 irq = 0; /* No irq */ 470 ret = mp_set_gsi_attr(irq, 1, polarity, NUMA_NO_NODE);
471 if (ret == 0)
472 ret = mp_map_gsi_to_irq(irq, IOAPIC_MAP_ALLOC);
473 WARN_ON(ret < 0);
482 } 474 }
483 475
484 dev = get_device_id(pentry->type, pentry->name); 476 dev = get_device_id(pentry->type, pentry->name);
diff --git a/arch/x86/platform/sfi/sfi.c b/arch/x86/platform/sfi/sfi.c
index 1fdaa57f41a5..2a8a74f3bd76 100644
--- a/arch/x86/platform/sfi/sfi.c
+++ b/arch/x86/platform/sfi/sfi.c
@@ -71,7 +71,9 @@ static int __init sfi_parse_cpus(struct sfi_table_header *table)
71#endif /* CONFIG_X86_LOCAL_APIC */ 71#endif /* CONFIG_X86_LOCAL_APIC */
72 72
73#ifdef CONFIG_X86_IO_APIC 73#ifdef CONFIG_X86_IO_APIC
74static struct irq_domain_ops sfi_ioapic_irqdomain_ops; 74static struct irq_domain_ops sfi_ioapic_irqdomain_ops = {
75 .map = mp_irqdomain_map,
76};
75 77
76static int __init sfi_parse_ioapic(struct sfi_table_header *table) 78static int __init sfi_parse_ioapic(struct sfi_table_header *table)
77{ 79{