Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc updates from Benjamin Herrenschmidt:
 "Kumar sent me a handful of Freescale related fixes and I added another
  regression fix to the pile.

  PS.  I -will- eventually learn about that signed tag business :-)"

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc/kvm/book3s_32: Fix MTMSR_EERI macro
  powerpc/85xx: p1022ds: fix DIU/LBC switching with NAND enabled
  powerpc/85xx: p1022ds: disable the NAND flash node if video is enabled
  powerpc/85xx: Fix sram_offset parameter type
  powerpc/85xx: P3041DS - change espi input-clock from 40MHz to 35MHz
  powerpc/85xx: Fix pci base address error for p2020rdb-pc in dts

7 files changed, 121 insertions, 55 deletions

diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
index 852e5b27485d..57573bd52caa 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -56,7 +56,7 @@
                 ranges = <0x0 0x0 0xffe00000 0x100000>;
         };
 
-        pci0: pcie@ffe08000 {
+        pci2: pcie@ffe08000 {
                 reg = <0 0xffe08000 0 0x1000>;
                 status = "disabled";
         };
@@ -76,7 +76,7 @@
                 };
         };
 
-        pci2: pcie@ffe0a000 {
+        pci0: pcie@ffe0a000 {
                 reg = <0 0xffe0a000 0 0x1000>;
                 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
index b5a56ca51cf7..470247ea68b4 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -56,7 +56,7 @@
                 ranges = <0x0 0xf 0xffe00000 0x100000>;
         };
 
-        pci0: pcie@fffe08000 {
+        pci2: pcie@fffe08000 {
                 reg = <0xf 0xffe08000 0 0x1000>;
                 status = "disabled";
         };
@@ -76,7 +76,7 @@
                 };
         };
 
-        pci2: pcie@fffe0a000 {
+        pci0: pcie@fffe0a000 {
                 reg = <0xf 0xffe0a000 0 0x1000>;
                 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                           0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index 22a215e94162..6cdcadc80c30 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -58,7 +58,7 @@
                                 #size-cells = <1>;
                                 compatible = "spansion,s25sl12801";
                                 reg = <0>;
-                                spi-max-frequency = <40000000>; /* input clock */
+                                spi-max-frequency = <35000000>; /* input clock */
                                 partition@u-boot {
                                         label = "u-boot";
                                         reg = <0x00000000 0x00100000>;
diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S b/arch/powerpc/kvm/book3s_rmhandlers.S
index ab523f3c1731..9ecf6e35cd8d 100644
--- a/arch/powerpc/kvm/book3s_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_rmhandlers.S
@@ -67,7 +67,6 @@ kvmppc_skip_Hinterrupt:
 #elif defined(CONFIG_PPC_BOOK3S_32)
 
 #define FUNC(name)              name
-#define MTMSR_EERI(reg)         mtmsr   (reg)
 
 .macro INTERRUPT_TRAMPOLINE intno
 
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 89ee02c54561..3c732acf331d 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -208,6 +208,7 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
         u8 __iomem *lbc_lcs0_ba = NULL;
         u8 __iomem *lbc_lcs1_ba = NULL;
         phys_addr_t cs0_addr, cs1_addr;
+        u32 br0, or0, br1, or1;
         const __be32 *iprop;
         unsigned int num_laws;
         u8 b;
@@ -256,11 +257,70 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
         }
         num_laws = be32_to_cpup(iprop);
 
-        cs0_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[0].br));
-        cs1_addr = lbc_br_to_phys(ecm, num_laws, in_be32(&lbc->bank[1].br));
+        /*
+         * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
+         * otherwise writes to these addresses won't actually appear on the
+         * local bus, and so the PIXIS won't see them.
+         *
+         * In FCM mode, writes go to the NAND controller, which does not pass
+         * them to the localbus directly.  So we force BR0 and BR1 into GPCM
+         * mode, since we don't care about what's behind the localbus any
+         * more.
+         */
+        br0 = in_be32(&lbc->bank[0].br);
+        br1 = in_be32(&lbc->bank[1].br);
+        or0 = in_be32(&lbc->bank[0].or);
+        or1 = in_be32(&lbc->bank[1].or);
+
+        /* Make sure CS0 and CS1 are programmed */
+        if (!(br0 & BR_V) || !(br1 & BR_V)) {
+                pr_err("p1022ds: CS0 and/or CS1 is not programmed\n");
+                goto exit;
+        }
+
+        /*
+         * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
+         * force the values to simple 32KB GPCM windows with the most
+         * conservative timing.
+         */
+        if ((br0 & BR_MSEL) != BR_MS_GPCM) {
+                br0 = (br0 & BR_BA) | BR_V;
+                or0 = 0xFFFF8000 | 0xFF7;
+                out_be32(&lbc->bank[0].br, br0);
+                out_be32(&lbc->bank[0].or, or0);
+        }
+        if ((br1 & BR_MSEL) != BR_MS_GPCM) {
+                br1 = (br1 & BR_BA) | BR_V;
+                or1 = 0xFFFF8000 | 0xFF7;
+                out_be32(&lbc->bank[1].br, br1);
+                out_be32(&lbc->bank[1].or, or1);
+        }
+
+        cs0_addr = lbc_br_to_phys(ecm, num_laws, br0);
+        if (!cs0_addr) {
+                pr_err("p1022ds: could not determine physical address for CS0"
+                       " (BR0=%08x)\n", br0);
+                goto exit;
+        }
+        cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
+        if (!cs0_addr) {
+                pr_err("p1022ds: could not determine physical address for CS1"
+                       " (BR1=%08x)\n", br1);
+                goto exit;
+        }
 
         lbc_lcs0_ba = ioremap(cs0_addr, 1);
+        if (!lbc_lcs0_ba) {
+                pr_err("p1022ds: could not ioremap CS0 address %llx\n",
+                       (unsigned long long)cs0_addr);
+                goto exit;
+        }
         lbc_lcs1_ba = ioremap(cs1_addr, 1);
+        if (!lbc_lcs1_ba) {
+                pr_err("p1022ds: could not ioremap CS1 address %llx\n",
+                       (unsigned long long)cs1_addr);
+                goto exit;
+        }
 
         /* Make sure we're in indirect mode first. */
         if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
@@ -419,18 +479,6 @@ void __init p1022_ds_pic_init(void)
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)