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authorMaxime Bizon <mbizon@freebox.fr>2011-11-04 14:09:29 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:03:03 -0500
commitec68c5206ab32f67583c1297f7883ceb91b043eb (patch)
treeee7b52c7a0e14f95c583e623963fc201ed48dd9f
parentd64ed7ada2f689d2c62af1892ca55e47d3653e36 (diff)
MIPS: BCM63XX: Cleanup cpu registers.
Use preprocessor when possible to avoid duplicated and error-prone code. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2897/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/bcm63xx/cpu.c180
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h311
2 files changed, 125 insertions, 366 deletions
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 7c7e4d4486ce..8bd5133eafd1 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,166 +29,38 @@ static u16 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq; 29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size; 30static unsigned int bcm63xx_memory_size;
31 31
32/* 32static const unsigned long bcm6338_regs_base[] = {
33 * 6338 register sets and irqs 33 __GEN_CPU_REGS_TABLE(6338)
34 */
35static const unsigned long bcm96338_regs_base[] = {
36 [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE,
37 [RSET_PERF] = BCM_6338_PERF_BASE,
38 [RSET_TIMER] = BCM_6338_TIMER_BASE,
39 [RSET_WDT] = BCM_6338_WDT_BASE,
40 [RSET_UART0] = BCM_6338_UART0_BASE,
41 [RSET_UART1] = BCM_6338_UART1_BASE,
42 [RSET_GPIO] = BCM_6338_GPIO_BASE,
43 [RSET_SPI] = BCM_6338_SPI_BASE,
44 [RSET_OHCI0] = BCM_6338_OHCI0_BASE,
45 [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE,
46 [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE,
47 [RSET_UDC0] = BCM_6338_UDC0_BASE,
48 [RSET_MPI] = BCM_6338_MPI_BASE,
49 [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE,
50 [RSET_SDRAM] = BCM_6338_SDRAM_BASE,
51 [RSET_DSL] = BCM_6338_DSL_BASE,
52 [RSET_ENET0] = BCM_6338_ENET0_BASE,
53 [RSET_ENET1] = BCM_6338_ENET1_BASE,
54 [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE,
55 [RSET_MEMC] = BCM_6338_MEMC_BASE,
56 [RSET_DDR] = BCM_6338_DDR_BASE,
57}; 34};
58 35
59static const int bcm96338_irqs[] = { 36static const int bcm6338_irqs[] = {
60 [IRQ_TIMER] = BCM_6338_TIMER_IRQ, 37 __GEN_CPU_IRQ_TABLE(6338)
61 [IRQ_UART0] = BCM_6338_UART0_IRQ,
62 [IRQ_DSL] = BCM_6338_DSL_IRQ,
63 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
64 [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ,
65 [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ,
66 [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ,
67}; 38};
68 39
69/* 40static const unsigned long bcm6345_regs_base[] = {
70 * 6345 register sets and irqs 41 __GEN_CPU_REGS_TABLE(6345)
71 */
72static const unsigned long bcm96345_regs_base[] = {
73 [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE,
74 [RSET_PERF] = BCM_6345_PERF_BASE,
75 [RSET_TIMER] = BCM_6345_TIMER_BASE,
76 [RSET_WDT] = BCM_6345_WDT_BASE,
77 [RSET_UART0] = BCM_6345_UART0_BASE,
78 [RSET_UART1] = BCM_6345_UART1_BASE,
79 [RSET_GPIO] = BCM_6345_GPIO_BASE,
80 [RSET_SPI] = BCM_6345_SPI_BASE,
81 [RSET_UDC0] = BCM_6345_UDC0_BASE,
82 [RSET_OHCI0] = BCM_6345_OHCI0_BASE,
83 [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE,
84 [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE,
85 [RSET_MPI] = BCM_6345_MPI_BASE,
86 [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE,
87 [RSET_DSL] = BCM_6345_DSL_BASE,
88 [RSET_ENET0] = BCM_6345_ENET0_BASE,
89 [RSET_ENET1] = BCM_6345_ENET1_BASE,
90 [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE,
91 [RSET_EHCI0] = BCM_6345_EHCI0_BASE,
92 [RSET_SDRAM] = BCM_6345_SDRAM_BASE,
93 [RSET_MEMC] = BCM_6345_MEMC_BASE,
94 [RSET_DDR] = BCM_6345_DDR_BASE,
95}; 42};
96 43
97static const int bcm96345_irqs[] = { 44static const int bcm6345_irqs[] = {
98 [IRQ_TIMER] = BCM_6345_TIMER_IRQ, 45 __GEN_CPU_IRQ_TABLE(6345)
99 [IRQ_UART0] = BCM_6345_UART0_IRQ,
100 [IRQ_DSL] = BCM_6345_DSL_IRQ,
101 [IRQ_ENET0] = BCM_6345_ENET0_IRQ,
102 [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ,
103 [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ,
104 [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ,
105}; 46};
106 47
107/* 48static const unsigned long bcm6348_regs_base[] = {
108 * 6348 register sets and irqs 49 __GEN_CPU_REGS_TABLE(6348)
109 */
110static const unsigned long bcm96348_regs_base[] = {
111 [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE,
112 [RSET_PERF] = BCM_6348_PERF_BASE,
113 [RSET_TIMER] = BCM_6348_TIMER_BASE,
114 [RSET_WDT] = BCM_6348_WDT_BASE,
115 [RSET_UART0] = BCM_6348_UART0_BASE,
116 [RSET_UART1] = BCM_6348_UART1_BASE,
117 [RSET_GPIO] = BCM_6348_GPIO_BASE,
118 [RSET_SPI] = BCM_6348_SPI_BASE,
119 [RSET_OHCI0] = BCM_6348_OHCI0_BASE,
120 [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE,
121 [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE,
122 [RSET_MPI] = BCM_6348_MPI_BASE,
123 [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE,
124 [RSET_SDRAM] = BCM_6348_SDRAM_BASE,
125 [RSET_DSL] = BCM_6348_DSL_BASE,
126 [RSET_ENET0] = BCM_6348_ENET0_BASE,
127 [RSET_ENET1] = BCM_6348_ENET1_BASE,
128 [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE,
129 [RSET_MEMC] = BCM_6348_MEMC_BASE,
130 [RSET_DDR] = BCM_6348_DDR_BASE,
131}; 50};
132 51
133static const int bcm96348_irqs[] = { 52static const int bcm6348_irqs[] = {
134 [IRQ_TIMER] = BCM_6348_TIMER_IRQ, 53 __GEN_CPU_IRQ_TABLE(6348)
135 [IRQ_UART0] = BCM_6348_UART0_IRQ, 54
136 [IRQ_DSL] = BCM_6348_DSL_IRQ,
137 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
138 [IRQ_ENET1] = BCM_6348_ENET1_IRQ,
139 [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ,
140 [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ,
141 [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ,
142 [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ,
143 [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ,
144 [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ,
145 [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ,
146 [IRQ_PCI] = BCM_6348_PCI_IRQ,
147}; 55};
148 56
149/* 57static const unsigned long bcm6358_regs_base[] = {
150 * 6358 register sets and irqs 58 __GEN_CPU_REGS_TABLE(6358)
151 */
152static const unsigned long bcm96358_regs_base[] = {
153 [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE,
154 [RSET_PERF] = BCM_6358_PERF_BASE,
155 [RSET_TIMER] = BCM_6358_TIMER_BASE,
156 [RSET_WDT] = BCM_6358_WDT_BASE,
157 [RSET_UART0] = BCM_6358_UART0_BASE,
158 [RSET_UART1] = BCM_6358_UART1_BASE,
159 [RSET_GPIO] = BCM_6358_GPIO_BASE,
160 [RSET_SPI] = BCM_6358_SPI_BASE,
161 [RSET_OHCI0] = BCM_6358_OHCI0_BASE,
162 [RSET_EHCI0] = BCM_6358_EHCI0_BASE,
163 [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE,
164 [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE,
165 [RSET_MPI] = BCM_6358_MPI_BASE,
166 [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE,
167 [RSET_SDRAM] = BCM_6358_SDRAM_BASE,
168 [RSET_DSL] = BCM_6358_DSL_BASE,
169 [RSET_ENET0] = BCM_6358_ENET0_BASE,
170 [RSET_ENET1] = BCM_6358_ENET1_BASE,
171 [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE,
172 [RSET_MEMC] = BCM_6358_MEMC_BASE,
173 [RSET_DDR] = BCM_6358_DDR_BASE,
174}; 59};
175 60
176static const int bcm96358_irqs[] = { 61static const int bcm6358_irqs[] = {
177 [IRQ_TIMER] = BCM_6358_TIMER_IRQ, 62 __GEN_CPU_IRQ_TABLE(6358)
178 [IRQ_UART0] = BCM_6358_UART0_IRQ, 63
179 [IRQ_UART1] = BCM_6358_UART1_IRQ,
180 [IRQ_DSL] = BCM_6358_DSL_IRQ,
181 [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
182 [IRQ_ENET1] = BCM_6358_ENET1_IRQ,
183 [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ,
184 [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ,
185 [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ,
186 [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ,
187 [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ,
188 [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ,
189 [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ,
190 [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ,
191 [IRQ_PCI] = BCM_6358_PCI_IRQ,
192}; 64};
193 65
194u16 __bcm63xx_get_cpu_id(void) 66u16 __bcm63xx_get_cpu_id(void)
@@ -301,24 +173,24 @@ void __init bcm63xx_cpu_init(void)
301 case CPU_BMIPS3300: 173 case CPU_BMIPS3300:
302 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) { 174 if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
303 expected_cpu_id = BCM6348_CPU_ID; 175 expected_cpu_id = BCM6348_CPU_ID;
304 bcm63xx_regs_base = bcm96348_regs_base; 176 bcm63xx_regs_base = bcm6348_regs_base;
305 bcm63xx_irqs = bcm96348_irqs; 177 bcm63xx_irqs = bcm6348_irqs;
306 } else { 178 } else {
307 __cpu_name[cpu] = "Broadcom BCM6338"; 179 __cpu_name[cpu] = "Broadcom BCM6338";
308 expected_cpu_id = BCM6338_CPU_ID; 180 expected_cpu_id = BCM6338_CPU_ID;
309 bcm63xx_regs_base = bcm96338_regs_base; 181 bcm63xx_regs_base = bcm6338_regs_base;
310 bcm63xx_irqs = bcm96338_irqs; 182 bcm63xx_irqs = bcm6338_irqs;
311 } 183 }
312 break; 184 break;
313 case CPU_BMIPS32: 185 case CPU_BMIPS32:
314 expected_cpu_id = BCM6345_CPU_ID; 186 expected_cpu_id = BCM6345_CPU_ID;
315 bcm63xx_regs_base = bcm96345_regs_base; 187 bcm63xx_regs_base = bcm6345_regs_base;
316 bcm63xx_irqs = bcm96345_irqs; 188 bcm63xx_irqs = bcm6345_irqs;
317 break; 189 break;
318 case CPU_BMIPS4350: 190 case CPU_BMIPS4350:
319 expected_cpu_id = BCM6358_CPU_ID; 191 expected_cpu_id = BCM6358_CPU_ID;
320 bcm63xx_regs_base = bcm96358_regs_base; 192 bcm63xx_regs_base = bcm6358_regs_base;
321 bcm63xx_irqs = bcm96358_irqs; 193 bcm63xx_irqs = bcm6358_irqs;
322 break; 194 break;
323 } 195 }
324 196
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 96a2391ad85b..464f948e6504 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -234,202 +234,77 @@ enum bcm63xx_regs_set {
234 234
235extern const unsigned long *bcm63xx_regs_base; 235extern const unsigned long *bcm63xx_regs_base;
236 236
237#define __GEN_RSET_BASE(__cpu, __rset) \
238 case RSET_## __rset : \
239 return BCM_## __cpu ##_## __rset ##_BASE;
240
241#define __GEN_RSET(__cpu) \
242 switch (set) { \
243 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
244 __GEN_RSET_BASE(__cpu, PERF) \
245 __GEN_RSET_BASE(__cpu, TIMER) \
246 __GEN_RSET_BASE(__cpu, WDT) \
247 __GEN_RSET_BASE(__cpu, UART0) \
248 __GEN_RSET_BASE(__cpu, UART1) \
249 __GEN_RSET_BASE(__cpu, GPIO) \
250 __GEN_RSET_BASE(__cpu, SPI) \
251 __GEN_RSET_BASE(__cpu, UDC0) \
252 __GEN_RSET_BASE(__cpu, OHCI0) \
253 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
254 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
255 __GEN_RSET_BASE(__cpu, MPI) \
256 __GEN_RSET_BASE(__cpu, PCMCIA) \
257 __GEN_RSET_BASE(__cpu, DSL) \
258 __GEN_RSET_BASE(__cpu, ENET0) \
259 __GEN_RSET_BASE(__cpu, ENET1) \
260 __GEN_RSET_BASE(__cpu, ENETDMA) \
261 __GEN_RSET_BASE(__cpu, EHCI0) \
262 __GEN_RSET_BASE(__cpu, SDRAM) \
263 __GEN_RSET_BASE(__cpu, MEMC) \
264 __GEN_RSET_BASE(__cpu, DDR) \
265 }
266
267#define __GEN_CPU_REGS_TABLE(__cpu) \
268 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
269 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
270 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
271 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
272 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
273 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
274 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
275 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
276 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
277 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
278 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
279 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
280 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
281 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
282 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
283 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
284 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
285 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
286 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
287 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
288 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
289 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
290
291
237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 292static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
238{ 293{
239#ifdef BCMCPU_RUNTIME_DETECT 294#ifdef BCMCPU_RUNTIME_DETECT
240 return bcm63xx_regs_base[set]; 295 return bcm63xx_regs_base[set];
241#else 296#else
242#ifdef CONFIG_BCM63XX_CPU_6338 297#ifdef CONFIG_BCM63XX_CPU_6338
243 switch (set) { 298 __GEN_RSET(6338)
244 case RSET_DSL_LMEM:
245 return BCM_6338_DSL_LMEM_BASE;
246 case RSET_PERF:
247 return BCM_6338_PERF_BASE;
248 case RSET_TIMER:
249 return BCM_6338_TIMER_BASE;
250 case RSET_WDT:
251 return BCM_6338_WDT_BASE;
252 case RSET_UART0:
253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
256 case RSET_GPIO:
257 return BCM_6338_GPIO_BASE;
258 case RSET_SPI:
259 return BCM_6338_SPI_BASE;
260 case RSET_UDC0:
261 return BCM_6338_UDC0_BASE;
262 case RSET_OHCI0:
263 return BCM_6338_OHCI0_BASE;
264 case RSET_OHCI_PRIV:
265 return BCM_6338_OHCI_PRIV_BASE;
266 case RSET_USBH_PRIV:
267 return BCM_6338_USBH_PRIV_BASE;
268 case RSET_MPI:
269 return BCM_6338_MPI_BASE;
270 case RSET_PCMCIA:
271 return BCM_6338_PCMCIA_BASE;
272 case RSET_DSL:
273 return BCM_6338_DSL_BASE;
274 case RSET_ENET0:
275 return BCM_6338_ENET0_BASE;
276 case RSET_ENET1:
277 return BCM_6338_ENET1_BASE;
278 case RSET_ENETDMA:
279 return BCM_6338_ENETDMA_BASE;
280 case RSET_EHCI0:
281 return BCM_6338_EHCI0_BASE;
282 case RSET_SDRAM:
283 return BCM_6338_SDRAM_BASE;
284 case RSET_MEMC:
285 return BCM_6338_MEMC_BASE;
286 case RSET_DDR:
287 return BCM_6338_DDR_BASE;
288 }
289#endif 299#endif
290#ifdef CONFIG_BCM63XX_CPU_6345 300#ifdef CONFIG_BCM63XX_CPU_6345
291 switch (set) { 301 __GEN_RSET(6345)
292 case RSET_DSL_LMEM:
293 return BCM_6345_DSL_LMEM_BASE;
294 case RSET_PERF:
295 return BCM_6345_PERF_BASE;
296 case RSET_TIMER:
297 return BCM_6345_TIMER_BASE;
298 case RSET_WDT:
299 return BCM_6345_WDT_BASE;
300 case RSET_UART0:
301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
304 case RSET_GPIO:
305 return BCM_6345_GPIO_BASE;
306 case RSET_SPI:
307 return BCM_6345_SPI_BASE;
308 case RSET_UDC0:
309 return BCM_6345_UDC0_BASE;
310 case RSET_OHCI0:
311 return BCM_6345_OHCI0_BASE;
312 case RSET_OHCI_PRIV:
313 return BCM_6345_OHCI_PRIV_BASE;
314 case RSET_USBH_PRIV:
315 return BCM_6345_USBH_PRIV_BASE;
316 case RSET_MPI:
317 return BCM_6345_MPI_BASE;
318 case RSET_PCMCIA:
319 return BCM_6345_PCMCIA_BASE;
320 case RSET_DSL:
321 return BCM_6345_DSL_BASE;
322 case RSET_ENET0:
323 return BCM_6345_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6345_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6345_ENETDMA_BASE;
328 case RSET_EHCI0:
329 return BCM_6345_EHCI0_BASE;
330 case RSET_SDRAM:
331 return BCM_6345_SDRAM_BASE;
332 case RSET_MEMC:
333 return BCM_6345_MEMC_BASE;
334 case RSET_DDR:
335 return BCM_6345_DDR_BASE;
336 }
337#endif 302#endif
338#ifdef CONFIG_BCM63XX_CPU_6348 303#ifdef CONFIG_BCM63XX_CPU_6348
339 switch (set) { 304 __GEN_RSET(6348)
340 case RSET_DSL_LMEM:
341 return BCM_6348_DSL_LMEM_BASE;
342 case RSET_PERF:
343 return BCM_6348_PERF_BASE;
344 case RSET_TIMER:
345 return BCM_6348_TIMER_BASE;
346 case RSET_WDT:
347 return BCM_6348_WDT_BASE;
348 case RSET_UART0:
349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
352 case RSET_GPIO:
353 return BCM_6348_GPIO_BASE;
354 case RSET_SPI:
355 return BCM_6348_SPI_BASE;
356 case RSET_UDC0:
357 return BCM_6348_UDC0_BASE;
358 case RSET_OHCI0:
359 return BCM_6348_OHCI0_BASE;
360 case RSET_OHCI_PRIV:
361 return BCM_6348_OHCI_PRIV_BASE;
362 case RSET_USBH_PRIV:
363 return BCM_6348_USBH_PRIV_BASE;
364 case RSET_MPI:
365 return BCM_6348_MPI_BASE;
366 case RSET_PCMCIA:
367 return BCM_6348_PCMCIA_BASE;
368 case RSET_DSL:
369 return BCM_6348_DSL_BASE;
370 case RSET_ENET0:
371 return BCM_6348_ENET0_BASE;
372 case RSET_ENET1:
373 return BCM_6348_ENET1_BASE;
374 case RSET_ENETDMA:
375 return BCM_6348_ENETDMA_BASE;
376 case RSET_EHCI0:
377 return BCM_6348_EHCI0_BASE;
378 case RSET_SDRAM:
379 return BCM_6348_SDRAM_BASE;
380 case RSET_MEMC:
381 return BCM_6348_MEMC_BASE;
382 case RSET_DDR:
383 return BCM_6348_DDR_BASE;
384 }
385#endif 305#endif
386#ifdef CONFIG_BCM63XX_CPU_6358 306#ifdef CONFIG_BCM63XX_CPU_6358
387 switch (set) { 307 __GEN_RSET(6358)
388 case RSET_DSL_LMEM:
389 return BCM_6358_DSL_LMEM_BASE;
390 case RSET_PERF:
391 return BCM_6358_PERF_BASE;
392 case RSET_TIMER:
393 return BCM_6358_TIMER_BASE;
394 case RSET_WDT:
395 return BCM_6358_WDT_BASE;
396 case RSET_UART0:
397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
400 case RSET_GPIO:
401 return BCM_6358_GPIO_BASE;
402 case RSET_SPI:
403 return BCM_6358_SPI_BASE;
404 case RSET_UDC0:
405 return BCM_6358_UDC0_BASE;
406 case RSET_OHCI0:
407 return BCM_6358_OHCI0_BASE;
408 case RSET_OHCI_PRIV:
409 return BCM_6358_OHCI_PRIV_BASE;
410 case RSET_USBH_PRIV:
411 return BCM_6358_USBH_PRIV_BASE;
412 case RSET_MPI:
413 return BCM_6358_MPI_BASE;
414 case RSET_PCMCIA:
415 return BCM_6358_PCMCIA_BASE;
416 case RSET_ENET0:
417 return BCM_6358_ENET0_BASE;
418 case RSET_ENET1:
419 return BCM_6358_ENET1_BASE;
420 case RSET_ENETDMA:
421 return BCM_6358_ENETDMA_BASE;
422 case RSET_DSL:
423 return BCM_6358_DSL_BASE;
424 case RSET_EHCI0:
425 return BCM_6358_EHCI0_BASE;
426 case RSET_SDRAM:
427 return BCM_6358_SDRAM_BASE;
428 case RSET_MEMC:
429 return BCM_6358_MEMC_BASE;
430 case RSET_DDR:
431 return BCM_6358_DDR_BASE;
432 }
433#endif 308#endif
434#endif 309#endif
435 /* unreached */ 310 /* unreached */
@@ -449,7 +324,6 @@ enum bcm63xx_irq {
449 IRQ_ENET_PHY, 324 IRQ_ENET_PHY,
450 IRQ_OHCI0, 325 IRQ_OHCI0,
451 IRQ_EHCI0, 326 IRQ_EHCI0,
452 IRQ_PCMCIA0,
453 IRQ_ENET0_RXDMA, 327 IRQ_ENET0_RXDMA,
454 IRQ_ENET0_TXDMA, 328 IRQ_ENET0_TXDMA,
455 IRQ_ENET1_RXDMA, 329 IRQ_ENET1_RXDMA,
@@ -462,62 +336,58 @@ enum bcm63xx_irq {
462 * 6338 irqs 336 * 6338 irqs
463 */ 337 */
464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 338#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 339#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) 340#define BCM_6338_UART1_IRQ 0
468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 341#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 342#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
343#define BCM_6338_ENET1_IRQ 0
472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 344#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) 345#define BCM_6338_OHCI0_IRQ 0
474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) 346#define BCM_6338_EHCI0_IRQ 0
475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 347#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 348#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) 349#define BCM_6338_ENET1_RXDMA_IRQ 0
350#define BCM_6338_ENET1_TXDMA_IRQ 0
351#define BCM_6338_PCI_IRQ 0
352#define BCM_6338_PCMCIA_IRQ 0
481 353
482/* 354/*
483 * 6345 irqs 355 * 6345 irqs
484 */ 356 */
485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 357#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 358#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
359#define BCM_6345_UART1_IRQ 0
487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 360#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 361#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
362#define BCM_6345_ENET1_IRQ 0
491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 363#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
364#define BCM_6345_OHCI0_IRQ 0
365#define BCM_6345_EHCI0_IRQ 0
492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 366#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 367#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) 368#define BCM_6345_ENET1_RXDMA_IRQ 0
495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) 369#define BCM_6345_ENET1_TXDMA_IRQ 0
496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) 370#define BCM_6345_PCI_IRQ 0
497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) 371#define BCM_6345_PCMCIA_IRQ 0
498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
504 372
505/* 373/*
506 * 6348 irqs 374 * 6348 irqs
507 */ 375 */
508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 376#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 377#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
378#define BCM_6348_UART1_IRQ 0
510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 379#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 380#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
381#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 382#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 383#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
384#define BCM_6348_EHCI0_IRQ 0
515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 385#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 386#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 387#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 388#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) 389#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
390#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
521 391
522/* 392/*
523 * 6358 irqs 393 * 6358 irqs
@@ -525,21 +395,38 @@ enum bcm63xx_irq {
525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 395#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 396#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 397#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) 398#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 399#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
400#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 401#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
402#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 403#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 404#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 405#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 406#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 407#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 408#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 409#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
540 410
541extern const int *bcm63xx_irqs; 411extern const int *bcm63xx_irqs;
542 412
413#define __GEN_CPU_IRQ_TABLE(__cpu) \
414 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
415 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
416 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
417 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
418 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
419 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
420 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
421 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
422 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
423 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
424 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
425 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
426 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
427 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
428 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
429
543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 430static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
544{ 431{
545 return bcm63xx_irqs[irq]; 432 return bcm63xx_irqs[irq];
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 12:47:58 -0400