diff options
author | Chris Metcalf <cmetcalf@tilera.com> | 2011-11-02 23:02:17 -0400 |
---|---|---|
committer | Chris Metcalf <cmetcalf@tilera.com> | 2011-11-03 16:58:54 -0400 |
commit | eb7c792da5afa3b9ec3e802c30952f82d2e9722b (patch) | |
tree | db796193297d4cc14bdb4d2b8001750a1f515f17 | |
parent | aeddea5d37d86d38c7a347110d8a052e9f45d955 (diff) |
arch/tile: factor out <arch/opcode.h> header
The kernel code was using some <asm> headers that included a mix
of hardware-specific information (typically found in Tilera <arch>
headers) and structures, enums, and function declarations supporting
the disassembly function of the tile-desc.c sources.
This change refactors that code so that a hardware-specific, but
OS- and application-agnostic header, is created: <arch/opcode.h>.
This header is then exported to userspace along with the other
<arch> headers and can be used to build userspace code; in particular,
it is used by glibc as part of implementing the backtrace() function.
The new header, together with a header that specifically describes
the disassembly code (<asm/tile-desc.h> with _32 and _64 variants),
replaces the old <asm/opcode-tile*.h> and <asm/opcode_constants*.h>
headers.
As part of this change, we are also renaming the 32-bit constants
from TILE_xxx to TILEPRO_xxx to better reflect the fact that they
are specific to the TILEPro architecture, and not to TILE-Gx
and any successor "tile" architecture chips.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
-rw-r--r-- | arch/tile/include/arch/opcode.h (renamed from arch/tile/include/asm/opcode_constants.h) | 17 | ||||
-rw-r--r-- | arch/tile/include/arch/opcode_tilegx.h (renamed from arch/tile/include/asm/opcode_constants_64.h) | 806 | ||||
-rw-r--r-- | arch/tile/include/arch/opcode_tilepro.h | 1471 | ||||
-rw-r--r-- | arch/tile/include/asm/opcode-tile_32.h | 1513 | ||||
-rw-r--r-- | arch/tile/include/asm/opcode-tile_64.h | 1248 | ||||
-rw-r--r-- | arch/tile/include/asm/opcode_constants_32.h | 480 | ||||
-rw-r--r-- | arch/tile/include/asm/tile-desc.h (renamed from arch/tile/include/asm/opcode-tile.h) | 19 | ||||
-rw-r--r-- | arch/tile/include/asm/tile-desc_32.h | 553 | ||||
-rw-r--r-- | arch/tile/include/asm/tile-desc_64.h | 483 | ||||
-rw-r--r-- | arch/tile/kernel/backtrace.c | 19 | ||||
-rw-r--r-- | arch/tile/kernel/module.c | 2 | ||||
-rw-r--r-- | arch/tile/kernel/single_step.c | 9 | ||||
-rw-r--r-- | arch/tile/kernel/tile-desc_32.c | 2242 | ||||
-rw-r--r-- | arch/tile/kernel/tile-desc_64.c | 28 | ||||
-rw-r--r-- | arch/tile/kernel/traps.c | 5 |
15 files changed, 4536 insertions, 4359 deletions
diff --git a/arch/tile/include/asm/opcode_constants.h b/arch/tile/include/arch/opcode.h index 37a9f2958cb1..92d15229ecec 100644 --- a/arch/tile/include/asm/opcode_constants.h +++ b/arch/tile/include/arch/opcode.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | 2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or | 4 | * This program is free software; you can redistribute it and/or |
5 | * modify it under the terms of the GNU General Public License | 5 | * modify it under the terms of the GNU General Public License |
@@ -12,15 +12,10 @@ | |||
12 | * more details. | 12 | * more details. |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #ifndef _ASM_TILE_OPCODE_CONSTANTS_H | 15 | #if defined(__tilepro__) |
16 | #define _ASM_TILE_OPCODE_CONSTANTS_H | 16 | #include <arch/opcode_tilepro.h> |
17 | 17 | #elif defined(__tilegx__) | |
18 | #include <arch/chip.h> | 18 | #include <arch/opcode_tilegx.h> |
19 | |||
20 | #if CHIP_WORD_SIZE() == 64 | ||
21 | #include <asm/opcode_constants_64.h> | ||
22 | #else | 19 | #else |
23 | #include <asm/opcode_constants_32.h> | 20 | #error Unexpected Tilera chip type |
24 | #endif | 21 | #endif |
25 | |||
26 | #endif /* _ASM_TILE_OPCODE_CONSTANTS_H */ | ||
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/arch/opcode_tilegx.h index 710192869476..c14d02c81600 100644 --- a/arch/tile/include/asm/opcode_constants_64.h +++ b/arch/tile/include/arch/opcode_tilegx.h | |||
@@ -1,4 +1,5 @@ | |||
1 | /* | 1 | /* TILE-Gx opcode information. |
2 | * | ||
2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | 3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
3 | * | 4 | * |
4 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
@@ -10,13 +11,805 @@ | |||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | 11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
11 | * NON INFRINGEMENT. See the GNU General Public License for | 12 | * NON INFRINGEMENT. See the GNU General Public License for |
12 | * more details. | 13 | * more details. |
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
13 | */ | 19 | */ |
14 | 20 | ||
15 | /* This file is machine-generated; DO NOT EDIT! */ | 21 | #ifndef __ARCH_OPCODE_H__ |
22 | #define __ARCH_OPCODE_H__ | ||
23 | |||
24 | #ifndef __ASSEMBLER__ | ||
25 | |||
26 | typedef unsigned long long tilegx_bundle_bits; | ||
27 | |||
28 | /* These are the bits that determine if a bundle is in the X encoding. */ | ||
29 | #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62) | ||
30 | |||
31 | enum | ||
32 | { | ||
33 | /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ | ||
34 | TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3, | ||
35 | |||
36 | /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ | ||
37 | TILEGX_NUM_PIPELINE_ENCODINGS = 5, | ||
38 | |||
39 | /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */ | ||
40 | TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3, | ||
41 | |||
42 | /* Instructions take this many bytes. */ | ||
43 | TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES, | ||
44 | |||
45 | /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */ | ||
46 | TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, | ||
47 | |||
48 | /* Bundles should be aligned modulo this number of bytes. */ | ||
49 | TILEGX_BUNDLE_ALIGNMENT_IN_BYTES = | ||
50 | (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), | ||
51 | |||
52 | /* Number of registers (some are magic, such as network I/O). */ | ||
53 | TILEGX_NUM_REGISTERS = 64, | ||
54 | }; | ||
55 | |||
56 | /* Make a few "tile_" variables to simplify common code between | ||
57 | architectures. */ | ||
58 | |||
59 | typedef tilegx_bundle_bits tile_bundle_bits; | ||
60 | #define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES | ||
61 | #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES | ||
62 | #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ | ||
63 | TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES | ||
64 | |||
65 | /* 64-bit pattern for a { bpt ; nop } bundle. */ | ||
66 | #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL | ||
67 | |||
68 | static __inline unsigned int | ||
69 | get_BFEnd_X0(tilegx_bundle_bits num) | ||
70 | { | ||
71 | const unsigned int n = (unsigned int)num; | ||
72 | return (((n >> 12)) & 0x3f); | ||
73 | } | ||
74 | |||
75 | static __inline unsigned int | ||
76 | get_BFOpcodeExtension_X0(tilegx_bundle_bits num) | ||
77 | { | ||
78 | const unsigned int n = (unsigned int)num; | ||
79 | return (((n >> 24)) & 0xf); | ||
80 | } | ||
81 | |||
82 | static __inline unsigned int | ||
83 | get_BFStart_X0(tilegx_bundle_bits num) | ||
84 | { | ||
85 | const unsigned int n = (unsigned int)num; | ||
86 | return (((n >> 18)) & 0x3f); | ||
87 | } | ||
88 | |||
89 | static __inline unsigned int | ||
90 | get_BrOff_X1(tilegx_bundle_bits n) | ||
91 | { | ||
92 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
93 | (((unsigned int)(n >> 37)) & 0x0001ffc0); | ||
94 | } | ||
95 | |||
96 | static __inline unsigned int | ||
97 | get_BrType_X1(tilegx_bundle_bits n) | ||
98 | { | ||
99 | return (((unsigned int)(n >> 54)) & 0x1f); | ||
100 | } | ||
101 | |||
102 | static __inline unsigned int | ||
103 | get_Dest_Imm8_X1(tilegx_bundle_bits n) | ||
104 | { | ||
105 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
106 | (((unsigned int)(n >> 43)) & 0x000000c0); | ||
107 | } | ||
108 | |||
109 | static __inline unsigned int | ||
110 | get_Dest_X0(tilegx_bundle_bits num) | ||
111 | { | ||
112 | const unsigned int n = (unsigned int)num; | ||
113 | return (((n >> 0)) & 0x3f); | ||
114 | } | ||
115 | |||
116 | static __inline unsigned int | ||
117 | get_Dest_X1(tilegx_bundle_bits n) | ||
118 | { | ||
119 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
120 | } | ||
121 | |||
122 | static __inline unsigned int | ||
123 | get_Dest_Y0(tilegx_bundle_bits num) | ||
124 | { | ||
125 | const unsigned int n = (unsigned int)num; | ||
126 | return (((n >> 0)) & 0x3f); | ||
127 | } | ||
128 | |||
129 | static __inline unsigned int | ||
130 | get_Dest_Y1(tilegx_bundle_bits n) | ||
131 | { | ||
132 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
133 | } | ||
134 | |||
135 | static __inline unsigned int | ||
136 | get_Imm16_X0(tilegx_bundle_bits num) | ||
137 | { | ||
138 | const unsigned int n = (unsigned int)num; | ||
139 | return (((n >> 12)) & 0xffff); | ||
140 | } | ||
141 | |||
142 | static __inline unsigned int | ||
143 | get_Imm16_X1(tilegx_bundle_bits n) | ||
144 | { | ||
145 | return (((unsigned int)(n >> 43)) & 0xffff); | ||
146 | } | ||
147 | |||
148 | static __inline unsigned int | ||
149 | get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num) | ||
150 | { | ||
151 | const unsigned int n = (unsigned int)num; | ||
152 | return (((n >> 20)) & 0xff); | ||
153 | } | ||
154 | |||
155 | static __inline unsigned int | ||
156 | get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n) | ||
157 | { | ||
158 | return (((unsigned int)(n >> 51)) & 0xff); | ||
159 | } | ||
160 | |||
161 | static __inline unsigned int | ||
162 | get_Imm8_X0(tilegx_bundle_bits num) | ||
163 | { | ||
164 | const unsigned int n = (unsigned int)num; | ||
165 | return (((n >> 12)) & 0xff); | ||
166 | } | ||
167 | |||
168 | static __inline unsigned int | ||
169 | get_Imm8_X1(tilegx_bundle_bits n) | ||
170 | { | ||
171 | return (((unsigned int)(n >> 43)) & 0xff); | ||
172 | } | ||
173 | |||
174 | static __inline unsigned int | ||
175 | get_Imm8_Y0(tilegx_bundle_bits num) | ||
176 | { | ||
177 | const unsigned int n = (unsigned int)num; | ||
178 | return (((n >> 12)) & 0xff); | ||
179 | } | ||
180 | |||
181 | static __inline unsigned int | ||
182 | get_Imm8_Y1(tilegx_bundle_bits n) | ||
183 | { | ||
184 | return (((unsigned int)(n >> 43)) & 0xff); | ||
185 | } | ||
186 | |||
187 | static __inline unsigned int | ||
188 | get_JumpOff_X1(tilegx_bundle_bits n) | ||
189 | { | ||
190 | return (((unsigned int)(n >> 31)) & 0x7ffffff); | ||
191 | } | ||
192 | |||
193 | static __inline unsigned int | ||
194 | get_JumpOpcodeExtension_X1(tilegx_bundle_bits n) | ||
195 | { | ||
196 | return (((unsigned int)(n >> 58)) & 0x1); | ||
197 | } | ||
198 | |||
199 | static __inline unsigned int | ||
200 | get_MF_Imm14_X1(tilegx_bundle_bits n) | ||
201 | { | ||
202 | return (((unsigned int)(n >> 37)) & 0x3fff); | ||
203 | } | ||
204 | |||
205 | static __inline unsigned int | ||
206 | get_MT_Imm14_X1(tilegx_bundle_bits n) | ||
207 | { | ||
208 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
209 | (((unsigned int)(n >> 37)) & 0x00003fc0); | ||
210 | } | ||
211 | |||
212 | static __inline unsigned int | ||
213 | get_Mode(tilegx_bundle_bits n) | ||
214 | { | ||
215 | return (((unsigned int)(n >> 62)) & 0x3); | ||
216 | } | ||
217 | |||
218 | static __inline unsigned int | ||
219 | get_Opcode_X0(tilegx_bundle_bits num) | ||
220 | { | ||
221 | const unsigned int n = (unsigned int)num; | ||
222 | return (((n >> 28)) & 0x7); | ||
223 | } | ||
224 | |||
225 | static __inline unsigned int | ||
226 | get_Opcode_X1(tilegx_bundle_bits n) | ||
227 | { | ||
228 | return (((unsigned int)(n >> 59)) & 0x7); | ||
229 | } | ||
230 | |||
231 | static __inline unsigned int | ||
232 | get_Opcode_Y0(tilegx_bundle_bits num) | ||
233 | { | ||
234 | const unsigned int n = (unsigned int)num; | ||
235 | return (((n >> 27)) & 0xf); | ||
236 | } | ||
237 | |||
238 | static __inline unsigned int | ||
239 | get_Opcode_Y1(tilegx_bundle_bits n) | ||
240 | { | ||
241 | return (((unsigned int)(n >> 58)) & 0xf); | ||
242 | } | ||
243 | |||
244 | static __inline unsigned int | ||
245 | get_Opcode_Y2(tilegx_bundle_bits n) | ||
246 | { | ||
247 | return (((n >> 26)) & 0x00000001) | | ||
248 | (((unsigned int)(n >> 56)) & 0x00000002); | ||
249 | } | ||
250 | |||
251 | static __inline unsigned int | ||
252 | get_RRROpcodeExtension_X0(tilegx_bundle_bits num) | ||
253 | { | ||
254 | const unsigned int n = (unsigned int)num; | ||
255 | return (((n >> 18)) & 0x3ff); | ||
256 | } | ||
257 | |||
258 | static __inline unsigned int | ||
259 | get_RRROpcodeExtension_X1(tilegx_bundle_bits n) | ||
260 | { | ||
261 | return (((unsigned int)(n >> 49)) & 0x3ff); | ||
262 | } | ||
263 | |||
264 | static __inline unsigned int | ||
265 | get_RRROpcodeExtension_Y0(tilegx_bundle_bits num) | ||
266 | { | ||
267 | const unsigned int n = (unsigned int)num; | ||
268 | return (((n >> 18)) & 0x3); | ||
269 | } | ||
270 | |||
271 | static __inline unsigned int | ||
272 | get_RRROpcodeExtension_Y1(tilegx_bundle_bits n) | ||
273 | { | ||
274 | return (((unsigned int)(n >> 49)) & 0x3); | ||
275 | } | ||
276 | |||
277 | static __inline unsigned int | ||
278 | get_ShAmt_X0(tilegx_bundle_bits num) | ||
279 | { | ||
280 | const unsigned int n = (unsigned int)num; | ||
281 | return (((n >> 12)) & 0x3f); | ||
282 | } | ||
283 | |||
284 | static __inline unsigned int | ||
285 | get_ShAmt_X1(tilegx_bundle_bits n) | ||
286 | { | ||
287 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
288 | } | ||
289 | |||
290 | static __inline unsigned int | ||
291 | get_ShAmt_Y0(tilegx_bundle_bits num) | ||
292 | { | ||
293 | const unsigned int n = (unsigned int)num; | ||
294 | return (((n >> 12)) & 0x3f); | ||
295 | } | ||
296 | |||
297 | static __inline unsigned int | ||
298 | get_ShAmt_Y1(tilegx_bundle_bits n) | ||
299 | { | ||
300 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
301 | } | ||
302 | |||
303 | static __inline unsigned int | ||
304 | get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num) | ||
305 | { | ||
306 | const unsigned int n = (unsigned int)num; | ||
307 | return (((n >> 18)) & 0x3ff); | ||
308 | } | ||
309 | |||
310 | static __inline unsigned int | ||
311 | get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n) | ||
312 | { | ||
313 | return (((unsigned int)(n >> 49)) & 0x3ff); | ||
314 | } | ||
315 | |||
316 | static __inline unsigned int | ||
317 | get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num) | ||
318 | { | ||
319 | const unsigned int n = (unsigned int)num; | ||
320 | return (((n >> 18)) & 0x3); | ||
321 | } | ||
322 | |||
323 | static __inline unsigned int | ||
324 | get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n) | ||
325 | { | ||
326 | return (((unsigned int)(n >> 49)) & 0x3); | ||
327 | } | ||
328 | |||
329 | static __inline unsigned int | ||
330 | get_SrcA_X0(tilegx_bundle_bits num) | ||
331 | { | ||
332 | const unsigned int n = (unsigned int)num; | ||
333 | return (((n >> 6)) & 0x3f); | ||
334 | } | ||
335 | |||
336 | static __inline unsigned int | ||
337 | get_SrcA_X1(tilegx_bundle_bits n) | ||
338 | { | ||
339 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
340 | } | ||
341 | |||
342 | static __inline unsigned int | ||
343 | get_SrcA_Y0(tilegx_bundle_bits num) | ||
344 | { | ||
345 | const unsigned int n = (unsigned int)num; | ||
346 | return (((n >> 6)) & 0x3f); | ||
347 | } | ||
348 | |||
349 | static __inline unsigned int | ||
350 | get_SrcA_Y1(tilegx_bundle_bits n) | ||
351 | { | ||
352 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
353 | } | ||
354 | |||
355 | static __inline unsigned int | ||
356 | get_SrcA_Y2(tilegx_bundle_bits num) | ||
357 | { | ||
358 | const unsigned int n = (unsigned int)num; | ||
359 | return (((n >> 20)) & 0x3f); | ||
360 | } | ||
361 | |||
362 | static __inline unsigned int | ||
363 | get_SrcBDest_Y2(tilegx_bundle_bits n) | ||
364 | { | ||
365 | return (((unsigned int)(n >> 51)) & 0x3f); | ||
366 | } | ||
367 | |||
368 | static __inline unsigned int | ||
369 | get_SrcB_X0(tilegx_bundle_bits num) | ||
370 | { | ||
371 | const unsigned int n = (unsigned int)num; | ||
372 | return (((n >> 12)) & 0x3f); | ||
373 | } | ||
374 | |||
375 | static __inline unsigned int | ||
376 | get_SrcB_X1(tilegx_bundle_bits n) | ||
377 | { | ||
378 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
379 | } | ||
380 | |||
381 | static __inline unsigned int | ||
382 | get_SrcB_Y0(tilegx_bundle_bits num) | ||
383 | { | ||
384 | const unsigned int n = (unsigned int)num; | ||
385 | return (((n >> 12)) & 0x3f); | ||
386 | } | ||
387 | |||
388 | static __inline unsigned int | ||
389 | get_SrcB_Y1(tilegx_bundle_bits n) | ||
390 | { | ||
391 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
392 | } | ||
393 | |||
394 | static __inline unsigned int | ||
395 | get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num) | ||
396 | { | ||
397 | const unsigned int n = (unsigned int)num; | ||
398 | return (((n >> 12)) & 0x3f); | ||
399 | } | ||
400 | |||
401 | static __inline unsigned int | ||
402 | get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n) | ||
403 | { | ||
404 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
405 | } | ||
406 | |||
407 | static __inline unsigned int | ||
408 | get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num) | ||
409 | { | ||
410 | const unsigned int n = (unsigned int)num; | ||
411 | return (((n >> 12)) & 0x3f); | ||
412 | } | ||
413 | |||
414 | static __inline unsigned int | ||
415 | get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n) | ||
416 | { | ||
417 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
418 | } | ||
419 | |||
420 | |||
421 | static __inline int | ||
422 | sign_extend(int n, int num_bits) | ||
423 | { | ||
424 | int shift = (int)(sizeof(int) * 8 - num_bits); | ||
425 | return (n << shift) >> shift; | ||
426 | } | ||
427 | |||
428 | |||
429 | |||
430 | static __inline tilegx_bundle_bits | ||
431 | create_BFEnd_X0(int num) | ||
432 | { | ||
433 | const unsigned int n = (unsigned int)num; | ||
434 | return ((n & 0x3f) << 12); | ||
435 | } | ||
436 | |||
437 | static __inline tilegx_bundle_bits | ||
438 | create_BFOpcodeExtension_X0(int num) | ||
439 | { | ||
440 | const unsigned int n = (unsigned int)num; | ||
441 | return ((n & 0xf) << 24); | ||
442 | } | ||
443 | |||
444 | static __inline tilegx_bundle_bits | ||
445 | create_BFStart_X0(int num) | ||
446 | { | ||
447 | const unsigned int n = (unsigned int)num; | ||
448 | return ((n & 0x3f) << 18); | ||
449 | } | ||
450 | |||
451 | static __inline tilegx_bundle_bits | ||
452 | create_BrOff_X1(int num) | ||
453 | { | ||
454 | const unsigned int n = (unsigned int)num; | ||
455 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
456 | (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37); | ||
457 | } | ||
458 | |||
459 | static __inline tilegx_bundle_bits | ||
460 | create_BrType_X1(int num) | ||
461 | { | ||
462 | const unsigned int n = (unsigned int)num; | ||
463 | return (((tilegx_bundle_bits)(n & 0x1f)) << 54); | ||
464 | } | ||
465 | |||
466 | static __inline tilegx_bundle_bits | ||
467 | create_Dest_Imm8_X1(int num) | ||
468 | { | ||
469 | const unsigned int n = (unsigned int)num; | ||
470 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
471 | (((tilegx_bundle_bits)(n & 0x000000c0)) << 43); | ||
472 | } | ||
473 | |||
474 | static __inline tilegx_bundle_bits | ||
475 | create_Dest_X0(int num) | ||
476 | { | ||
477 | const unsigned int n = (unsigned int)num; | ||
478 | return ((n & 0x3f) << 0); | ||
479 | } | ||
480 | |||
481 | static __inline tilegx_bundle_bits | ||
482 | create_Dest_X1(int num) | ||
483 | { | ||
484 | const unsigned int n = (unsigned int)num; | ||
485 | return (((tilegx_bundle_bits)(n & 0x3f)) << 31); | ||
486 | } | ||
487 | |||
488 | static __inline tilegx_bundle_bits | ||
489 | create_Dest_Y0(int num) | ||
490 | { | ||
491 | const unsigned int n = (unsigned int)num; | ||
492 | return ((n & 0x3f) << 0); | ||
493 | } | ||
494 | |||
495 | static __inline tilegx_bundle_bits | ||
496 | create_Dest_Y1(int num) | ||
497 | { | ||
498 | const unsigned int n = (unsigned int)num; | ||
499 | return (((tilegx_bundle_bits)(n & 0x3f)) << 31); | ||
500 | } | ||
501 | |||
502 | static __inline tilegx_bundle_bits | ||
503 | create_Imm16_X0(int num) | ||
504 | { | ||
505 | const unsigned int n = (unsigned int)num; | ||
506 | return ((n & 0xffff) << 12); | ||
507 | } | ||
508 | |||
509 | static __inline tilegx_bundle_bits | ||
510 | create_Imm16_X1(int num) | ||
511 | { | ||
512 | const unsigned int n = (unsigned int)num; | ||
513 | return (((tilegx_bundle_bits)(n & 0xffff)) << 43); | ||
514 | } | ||
515 | |||
516 | static __inline tilegx_bundle_bits | ||
517 | create_Imm8OpcodeExtension_X0(int num) | ||
518 | { | ||
519 | const unsigned int n = (unsigned int)num; | ||
520 | return ((n & 0xff) << 20); | ||
521 | } | ||
522 | |||
523 | static __inline tilegx_bundle_bits | ||
524 | create_Imm8OpcodeExtension_X1(int num) | ||
525 | { | ||
526 | const unsigned int n = (unsigned int)num; | ||
527 | return (((tilegx_bundle_bits)(n & 0xff)) << 51); | ||
528 | } | ||
529 | |||
530 | static __inline tilegx_bundle_bits | ||
531 | create_Imm8_X0(int num) | ||
532 | { | ||
533 | const unsigned int n = (unsigned int)num; | ||
534 | return ((n & 0xff) << 12); | ||
535 | } | ||
536 | |||
537 | static __inline tilegx_bundle_bits | ||
538 | create_Imm8_X1(int num) | ||
539 | { | ||
540 | const unsigned int n = (unsigned int)num; | ||
541 | return (((tilegx_bundle_bits)(n & 0xff)) << 43); | ||
542 | } | ||
543 | |||
544 | static __inline tilegx_bundle_bits | ||
545 | create_Imm8_Y0(int num) | ||
546 | { | ||
547 | const unsigned int n = (unsigned int)num; | ||
548 | return ((n & 0xff) << 12); | ||
549 | } | ||
550 | |||
551 | static __inline tilegx_bundle_bits | ||
552 | create_Imm8_Y1(int num) | ||
553 | { | ||
554 | const unsigned int n = (unsigned int)num; | ||
555 | return (((tilegx_bundle_bits)(n & 0xff)) << 43); | ||
556 | } | ||
557 | |||
558 | static __inline tilegx_bundle_bits | ||
559 | create_JumpOff_X1(int num) | ||
560 | { | ||
561 | const unsigned int n = (unsigned int)num; | ||
562 | return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31); | ||
563 | } | ||
564 | |||
565 | static __inline tilegx_bundle_bits | ||
566 | create_JumpOpcodeExtension_X1(int num) | ||
567 | { | ||
568 | const unsigned int n = (unsigned int)num; | ||
569 | return (((tilegx_bundle_bits)(n & 0x1)) << 58); | ||
570 | } | ||
571 | |||
572 | static __inline tilegx_bundle_bits | ||
573 | create_MF_Imm14_X1(int num) | ||
574 | { | ||
575 | const unsigned int n = (unsigned int)num; | ||
576 | return (((tilegx_bundle_bits)(n & 0x3fff)) << 37); | ||
577 | } | ||
578 | |||
579 | static __inline tilegx_bundle_bits | ||
580 | create_MT_Imm14_X1(int num) | ||
581 | { | ||
582 | const unsigned int n = (unsigned int)num; | ||
583 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
584 | (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37); | ||
585 | } | ||
586 | |||
587 | static __inline tilegx_bundle_bits | ||
588 | create_Mode(int num) | ||
589 | { | ||
590 | const unsigned int n = (unsigned int)num; | ||
591 | return (((tilegx_bundle_bits)(n & 0x3)) << 62); | ||
592 | } | ||
593 | |||
594 | static __inline tilegx_bundle_bits | ||
595 | create_Opcode_X0(int num) | ||
596 | { | ||
597 | const unsigned int n = (unsigned int)num; | ||
598 | return ((n & 0x7) << 28); | ||
599 | } | ||
600 | |||
601 | static __inline tilegx_bundle_bits | ||
602 | create_Opcode_X1(int num) | ||
603 | { | ||
604 | const unsigned int n = (unsigned int)num; | ||
605 | return (((tilegx_bundle_bits)(n & 0x7)) << 59); | ||
606 | } | ||
607 | |||
608 | static __inline tilegx_bundle_bits | ||
609 | create_Opcode_Y0(int num) | ||
610 | { | ||
611 | const unsigned int n = (unsigned int)num; | ||
612 | return ((n & 0xf) << 27); | ||
613 | } | ||
614 | |||
615 | static __inline tilegx_bundle_bits | ||
616 | create_Opcode_Y1(int num) | ||
617 | { | ||
618 | const unsigned int n = (unsigned int)num; | ||
619 | return (((tilegx_bundle_bits)(n & 0xf)) << 58); | ||
620 | } | ||
621 | |||
622 | static __inline tilegx_bundle_bits | ||
623 | create_Opcode_Y2(int num) | ||
624 | { | ||
625 | const unsigned int n = (unsigned int)num; | ||
626 | return ((n & 0x00000001) << 26) | | ||
627 | (((tilegx_bundle_bits)(n & 0x00000002)) << 56); | ||
628 | } | ||
629 | |||
630 | static __inline tilegx_bundle_bits | ||
631 | create_RRROpcodeExtension_X0(int num) | ||
632 | { | ||
633 | const unsigned int n = (unsigned int)num; | ||
634 | return ((n & 0x3ff) << 18); | ||
635 | } | ||
636 | |||
637 | static __inline tilegx_bundle_bits | ||
638 | create_RRROpcodeExtension_X1(int num) | ||
639 | { | ||
640 | const unsigned int n = (unsigned int)num; | ||
641 | return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); | ||
642 | } | ||
643 | |||
644 | static __inline tilegx_bundle_bits | ||
645 | create_RRROpcodeExtension_Y0(int num) | ||
646 | { | ||
647 | const unsigned int n = (unsigned int)num; | ||
648 | return ((n & 0x3) << 18); | ||
649 | } | ||
650 | |||
651 | static __inline tilegx_bundle_bits | ||
652 | create_RRROpcodeExtension_Y1(int num) | ||
653 | { | ||
654 | const unsigned int n = (unsigned int)num; | ||
655 | return (((tilegx_bundle_bits)(n & 0x3)) << 49); | ||
656 | } | ||
657 | |||
658 | static __inline tilegx_bundle_bits | ||
659 | create_ShAmt_X0(int num) | ||
660 | { | ||
661 | const unsigned int n = (unsigned int)num; | ||
662 | return ((n & 0x3f) << 12); | ||
663 | } | ||
664 | |||
665 | static __inline tilegx_bundle_bits | ||
666 | create_ShAmt_X1(int num) | ||
667 | { | ||
668 | const unsigned int n = (unsigned int)num; | ||
669 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
670 | } | ||
671 | |||
672 | static __inline tilegx_bundle_bits | ||
673 | create_ShAmt_Y0(int num) | ||
674 | { | ||
675 | const unsigned int n = (unsigned int)num; | ||
676 | return ((n & 0x3f) << 12); | ||
677 | } | ||
678 | |||
679 | static __inline tilegx_bundle_bits | ||
680 | create_ShAmt_Y1(int num) | ||
681 | { | ||
682 | const unsigned int n = (unsigned int)num; | ||
683 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
684 | } | ||
685 | |||
686 | static __inline tilegx_bundle_bits | ||
687 | create_ShiftOpcodeExtension_X0(int num) | ||
688 | { | ||
689 | const unsigned int n = (unsigned int)num; | ||
690 | return ((n & 0x3ff) << 18); | ||
691 | } | ||
692 | |||
693 | static __inline tilegx_bundle_bits | ||
694 | create_ShiftOpcodeExtension_X1(int num) | ||
695 | { | ||
696 | const unsigned int n = (unsigned int)num; | ||
697 | return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); | ||
698 | } | ||
699 | |||
700 | static __inline tilegx_bundle_bits | ||
701 | create_ShiftOpcodeExtension_Y0(int num) | ||
702 | { | ||
703 | const unsigned int n = (unsigned int)num; | ||
704 | return ((n & 0x3) << 18); | ||
705 | } | ||
706 | |||
707 | static __inline tilegx_bundle_bits | ||
708 | create_ShiftOpcodeExtension_Y1(int num) | ||
709 | { | ||
710 | const unsigned int n = (unsigned int)num; | ||
711 | return (((tilegx_bundle_bits)(n & 0x3)) << 49); | ||
712 | } | ||
713 | |||
714 | static __inline tilegx_bundle_bits | ||
715 | create_SrcA_X0(int num) | ||
716 | { | ||
717 | const unsigned int n = (unsigned int)num; | ||
718 | return ((n & 0x3f) << 6); | ||
719 | } | ||
720 | |||
721 | static __inline tilegx_bundle_bits | ||
722 | create_SrcA_X1(int num) | ||
723 | { | ||
724 | const unsigned int n = (unsigned int)num; | ||
725 | return (((tilegx_bundle_bits)(n & 0x3f)) << 37); | ||
726 | } | ||
727 | |||
728 | static __inline tilegx_bundle_bits | ||
729 | create_SrcA_Y0(int num) | ||
730 | { | ||
731 | const unsigned int n = (unsigned int)num; | ||
732 | return ((n & 0x3f) << 6); | ||
733 | } | ||
734 | |||
735 | static __inline tilegx_bundle_bits | ||
736 | create_SrcA_Y1(int num) | ||
737 | { | ||
738 | const unsigned int n = (unsigned int)num; | ||
739 | return (((tilegx_bundle_bits)(n & 0x3f)) << 37); | ||
740 | } | ||
741 | |||
742 | static __inline tilegx_bundle_bits | ||
743 | create_SrcA_Y2(int num) | ||
744 | { | ||
745 | const unsigned int n = (unsigned int)num; | ||
746 | return ((n & 0x3f) << 20); | ||
747 | } | ||
748 | |||
749 | static __inline tilegx_bundle_bits | ||
750 | create_SrcBDest_Y2(int num) | ||
751 | { | ||
752 | const unsigned int n = (unsigned int)num; | ||
753 | return (((tilegx_bundle_bits)(n & 0x3f)) << 51); | ||
754 | } | ||
755 | |||
756 | static __inline tilegx_bundle_bits | ||
757 | create_SrcB_X0(int num) | ||
758 | { | ||
759 | const unsigned int n = (unsigned int)num; | ||
760 | return ((n & 0x3f) << 12); | ||
761 | } | ||
762 | |||
763 | static __inline tilegx_bundle_bits | ||
764 | create_SrcB_X1(int num) | ||
765 | { | ||
766 | const unsigned int n = (unsigned int)num; | ||
767 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
768 | } | ||
769 | |||
770 | static __inline tilegx_bundle_bits | ||
771 | create_SrcB_Y0(int num) | ||
772 | { | ||
773 | const unsigned int n = (unsigned int)num; | ||
774 | return ((n & 0x3f) << 12); | ||
775 | } | ||
776 | |||
777 | static __inline tilegx_bundle_bits | ||
778 | create_SrcB_Y1(int num) | ||
779 | { | ||
780 | const unsigned int n = (unsigned int)num; | ||
781 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
782 | } | ||
783 | |||
784 | static __inline tilegx_bundle_bits | ||
785 | create_UnaryOpcodeExtension_X0(int num) | ||
786 | { | ||
787 | const unsigned int n = (unsigned int)num; | ||
788 | return ((n & 0x3f) << 12); | ||
789 | } | ||
790 | |||
791 | static __inline tilegx_bundle_bits | ||
792 | create_UnaryOpcodeExtension_X1(int num) | ||
793 | { | ||
794 | const unsigned int n = (unsigned int)num; | ||
795 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
796 | } | ||
797 | |||
798 | static __inline tilegx_bundle_bits | ||
799 | create_UnaryOpcodeExtension_Y0(int num) | ||
800 | { | ||
801 | const unsigned int n = (unsigned int)num; | ||
802 | return ((n & 0x3f) << 12); | ||
803 | } | ||
804 | |||
805 | static __inline tilegx_bundle_bits | ||
806 | create_UnaryOpcodeExtension_Y1(int num) | ||
807 | { | ||
808 | const unsigned int n = (unsigned int)num; | ||
809 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
810 | } | ||
16 | 811 | ||
17 | 812 | ||
18 | #ifndef _TILE_OPCODE_CONSTANTS_H | ||
19 | #define _TILE_OPCODE_CONSTANTS_H | ||
20 | enum | 813 | enum |
21 | { | 814 | { |
22 | ADDI_IMM8_OPCODE_X0 = 1, | 815 | ADDI_IMM8_OPCODE_X0 = 1, |
@@ -606,4 +1399,7 @@ enum | |||
606 | XOR_RRR_5_OPCODE_Y1 = 3 | 1399 | XOR_RRR_5_OPCODE_Y1 = 3 |
607 | }; | 1400 | }; |
608 | 1401 | ||
609 | #endif /* !_TILE_OPCODE_CONSTANTS_H */ | 1402 | |
1403 | #endif /* __ASSEMBLER__ */ | ||
1404 | |||
1405 | #endif /* __ARCH_OPCODE_H__ */ | ||
diff --git a/arch/tile/include/arch/opcode_tilepro.h b/arch/tile/include/arch/opcode_tilepro.h new file mode 100644 index 000000000000..71b763b8ce83 --- /dev/null +++ b/arch/tile/include/arch/opcode_tilepro.h | |||
@@ -0,0 +1,1471 @@ | |||
1 | /* TILEPro opcode information. | ||
2 | * | ||
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation, version 2. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
12 | * NON INFRINGEMENT. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #ifndef __ARCH_OPCODE_H__ | ||
22 | #define __ARCH_OPCODE_H__ | ||
23 | |||
24 | #ifndef __ASSEMBLER__ | ||
25 | |||
26 | typedef unsigned long long tilepro_bundle_bits; | ||
27 | |||
28 | /* This is the bit that determines if a bundle is in the Y encoding. */ | ||
29 | #define TILEPRO_BUNDLE_Y_ENCODING_MASK ((tilepro_bundle_bits)1 << 63) | ||
30 | |||
31 | enum | ||
32 | { | ||
33 | /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ | ||
34 | TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE = 3, | ||
35 | |||
36 | /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ | ||
37 | TILEPRO_NUM_PIPELINE_ENCODINGS = 5, | ||
38 | |||
39 | /* Log base 2 of TILEPRO_BUNDLE_SIZE_IN_BYTES. */ | ||
40 | TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES = 3, | ||
41 | |||
42 | /* Instructions take this many bytes. */ | ||
43 | TILEPRO_BUNDLE_SIZE_IN_BYTES = 1 << TILEPRO_LOG2_BUNDLE_SIZE_IN_BYTES, | ||
44 | |||
45 | /* Log base 2 of TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES. */ | ||
46 | TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, | ||
47 | |||
48 | /* Bundles should be aligned modulo this number of bytes. */ | ||
49 | TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES = | ||
50 | (1 << TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), | ||
51 | |||
52 | /* Log base 2 of TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES. */ | ||
53 | TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1, | ||
54 | |||
55 | /* Static network instructions take this many bytes. */ | ||
56 | TILEPRO_SN_INSTRUCTION_SIZE_IN_BYTES = | ||
57 | (1 << TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES), | ||
58 | |||
59 | /* Number of registers (some are magic, such as network I/O). */ | ||
60 | TILEPRO_NUM_REGISTERS = 64, | ||
61 | |||
62 | /* Number of static network registers. */ | ||
63 | TILEPRO_NUM_SN_REGISTERS = 4 | ||
64 | }; | ||
65 | |||
66 | /* Make a few "tile_" variables to simplify common code between | ||
67 | architectures. */ | ||
68 | |||
69 | typedef tilepro_bundle_bits tile_bundle_bits; | ||
70 | #define TILE_BUNDLE_SIZE_IN_BYTES TILEPRO_BUNDLE_SIZE_IN_BYTES | ||
71 | #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEPRO_BUNDLE_ALIGNMENT_IN_BYTES | ||
72 | #define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \ | ||
73 | TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES | ||
74 | |||
75 | /* 64-bit pattern for a { bpt ; nop } bundle. */ | ||
76 | #define TILEPRO_BPT_BUNDLE 0x400b3cae70166000ULL | ||
77 | |||
78 | static __inline unsigned int | ||
79 | get_BrOff_SN(tilepro_bundle_bits num) | ||
80 | { | ||
81 | const unsigned int n = (unsigned int)num; | ||
82 | return (((n >> 0)) & 0x3ff); | ||
83 | } | ||
84 | |||
85 | static __inline unsigned int | ||
86 | get_BrOff_X1(tilepro_bundle_bits n) | ||
87 | { | ||
88 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
89 | (((unsigned int)(n >> 20)) & 0x00018000); | ||
90 | } | ||
91 | |||
92 | static __inline unsigned int | ||
93 | get_BrType_X1(tilepro_bundle_bits n) | ||
94 | { | ||
95 | return (((unsigned int)(n >> 31)) & 0xf); | ||
96 | } | ||
97 | |||
98 | static __inline unsigned int | ||
99 | get_Dest_Imm8_X1(tilepro_bundle_bits n) | ||
100 | { | ||
101 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
102 | (((unsigned int)(n >> 43)) & 0x000000c0); | ||
103 | } | ||
104 | |||
105 | static __inline unsigned int | ||
106 | get_Dest_SN(tilepro_bundle_bits num) | ||
107 | { | ||
108 | const unsigned int n = (unsigned int)num; | ||
109 | return (((n >> 2)) & 0x3); | ||
110 | } | ||
111 | |||
112 | static __inline unsigned int | ||
113 | get_Dest_X0(tilepro_bundle_bits num) | ||
114 | { | ||
115 | const unsigned int n = (unsigned int)num; | ||
116 | return (((n >> 0)) & 0x3f); | ||
117 | } | ||
118 | |||
119 | static __inline unsigned int | ||
120 | get_Dest_X1(tilepro_bundle_bits n) | ||
121 | { | ||
122 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
123 | } | ||
124 | |||
125 | static __inline unsigned int | ||
126 | get_Dest_Y0(tilepro_bundle_bits num) | ||
127 | { | ||
128 | const unsigned int n = (unsigned int)num; | ||
129 | return (((n >> 0)) & 0x3f); | ||
130 | } | ||
131 | |||
132 | static __inline unsigned int | ||
133 | get_Dest_Y1(tilepro_bundle_bits n) | ||
134 | { | ||
135 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
136 | } | ||
137 | |||
138 | static __inline unsigned int | ||
139 | get_Imm16_X0(tilepro_bundle_bits num) | ||
140 | { | ||
141 | const unsigned int n = (unsigned int)num; | ||
142 | return (((n >> 12)) & 0xffff); | ||
143 | } | ||
144 | |||
145 | static __inline unsigned int | ||
146 | get_Imm16_X1(tilepro_bundle_bits n) | ||
147 | { | ||
148 | return (((unsigned int)(n >> 43)) & 0xffff); | ||
149 | } | ||
150 | |||
151 | static __inline unsigned int | ||
152 | get_Imm8_SN(tilepro_bundle_bits num) | ||
153 | { | ||
154 | const unsigned int n = (unsigned int)num; | ||
155 | return (((n >> 0)) & 0xff); | ||
156 | } | ||
157 | |||
158 | static __inline unsigned int | ||
159 | get_Imm8_X0(tilepro_bundle_bits num) | ||
160 | { | ||
161 | const unsigned int n = (unsigned int)num; | ||
162 | return (((n >> 12)) & 0xff); | ||
163 | } | ||
164 | |||
165 | static __inline unsigned int | ||
166 | get_Imm8_X1(tilepro_bundle_bits n) | ||
167 | { | ||
168 | return (((unsigned int)(n >> 43)) & 0xff); | ||
169 | } | ||
170 | |||
171 | static __inline unsigned int | ||
172 | get_Imm8_Y0(tilepro_bundle_bits num) | ||
173 | { | ||
174 | const unsigned int n = (unsigned int)num; | ||
175 | return (((n >> 12)) & 0xff); | ||
176 | } | ||
177 | |||
178 | static __inline unsigned int | ||
179 | get_Imm8_Y1(tilepro_bundle_bits n) | ||
180 | { | ||
181 | return (((unsigned int)(n >> 43)) & 0xff); | ||
182 | } | ||
183 | |||
184 | static __inline unsigned int | ||
185 | get_ImmOpcodeExtension_X0(tilepro_bundle_bits num) | ||
186 | { | ||
187 | const unsigned int n = (unsigned int)num; | ||
188 | return (((n >> 20)) & 0x7f); | ||
189 | } | ||
190 | |||
191 | static __inline unsigned int | ||
192 | get_ImmOpcodeExtension_X1(tilepro_bundle_bits n) | ||
193 | { | ||
194 | return (((unsigned int)(n >> 51)) & 0x7f); | ||
195 | } | ||
196 | |||
197 | static __inline unsigned int | ||
198 | get_ImmRROpcodeExtension_SN(tilepro_bundle_bits num) | ||
199 | { | ||
200 | const unsigned int n = (unsigned int)num; | ||
201 | return (((n >> 8)) & 0x3); | ||
202 | } | ||
203 | |||
204 | static __inline unsigned int | ||
205 | get_JOffLong_X1(tilepro_bundle_bits n) | ||
206 | { | ||
207 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
208 | (((unsigned int)(n >> 20)) & 0x00018000) | | ||
209 | (((unsigned int)(n >> 14)) & 0x001e0000) | | ||
210 | (((unsigned int)(n >> 16)) & 0x07e00000) | | ||
211 | (((unsigned int)(n >> 31)) & 0x18000000); | ||
212 | } | ||
213 | |||
214 | static __inline unsigned int | ||
215 | get_JOff_X1(tilepro_bundle_bits n) | ||
216 | { | ||
217 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
218 | (((unsigned int)(n >> 20)) & 0x00018000) | | ||
219 | (((unsigned int)(n >> 14)) & 0x001e0000) | | ||
220 | (((unsigned int)(n >> 16)) & 0x07e00000) | | ||
221 | (((unsigned int)(n >> 31)) & 0x08000000); | ||
222 | } | ||
223 | |||
224 | static __inline unsigned int | ||
225 | get_MF_Imm15_X1(tilepro_bundle_bits n) | ||
226 | { | ||
227 | return (((unsigned int)(n >> 37)) & 0x00003fff) | | ||
228 | (((unsigned int)(n >> 44)) & 0x00004000); | ||
229 | } | ||
230 | |||
231 | static __inline unsigned int | ||
232 | get_MMEnd_X0(tilepro_bundle_bits num) | ||
233 | { | ||
234 | const unsigned int n = (unsigned int)num; | ||
235 | return (((n >> 18)) & 0x1f); | ||
236 | } | ||
237 | |||
238 | static __inline unsigned int | ||
239 | get_MMEnd_X1(tilepro_bundle_bits n) | ||
240 | { | ||
241 | return (((unsigned int)(n >> 49)) & 0x1f); | ||
242 | } | ||
243 | |||
244 | static __inline unsigned int | ||
245 | get_MMStart_X0(tilepro_bundle_bits num) | ||
246 | { | ||
247 | const unsigned int n = (unsigned int)num; | ||
248 | return (((n >> 23)) & 0x1f); | ||
249 | } | ||
250 | |||
251 | static __inline unsigned int | ||
252 | get_MMStart_X1(tilepro_bundle_bits n) | ||
253 | { | ||
254 | return (((unsigned int)(n >> 54)) & 0x1f); | ||
255 | } | ||
256 | |||
257 | static __inline unsigned int | ||
258 | get_MT_Imm15_X1(tilepro_bundle_bits n) | ||
259 | { | ||
260 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
261 | (((unsigned int)(n >> 37)) & 0x00003fc0) | | ||
262 | (((unsigned int)(n >> 44)) & 0x00004000); | ||
263 | } | ||
264 | |||
265 | static __inline unsigned int | ||
266 | get_Mode(tilepro_bundle_bits n) | ||
267 | { | ||
268 | return (((unsigned int)(n >> 63)) & 0x1); | ||
269 | } | ||
270 | |||
271 | static __inline unsigned int | ||
272 | get_NoRegOpcodeExtension_SN(tilepro_bundle_bits num) | ||
273 | { | ||
274 | const unsigned int n = (unsigned int)num; | ||
275 | return (((n >> 0)) & 0xf); | ||
276 | } | ||
277 | |||
278 | static __inline unsigned int | ||
279 | get_Opcode_SN(tilepro_bundle_bits num) | ||
280 | { | ||
281 | const unsigned int n = (unsigned int)num; | ||
282 | return (((n >> 10)) & 0x3f); | ||
283 | } | ||
284 | |||
285 | static __inline unsigned int | ||
286 | get_Opcode_X0(tilepro_bundle_bits num) | ||
287 | { | ||
288 | const unsigned int n = (unsigned int)num; | ||
289 | return (((n >> 28)) & 0x7); | ||
290 | } | ||
291 | |||
292 | static __inline unsigned int | ||
293 | get_Opcode_X1(tilepro_bundle_bits n) | ||
294 | { | ||
295 | return (((unsigned int)(n >> 59)) & 0xf); | ||
296 | } | ||
297 | |||
298 | static __inline unsigned int | ||
299 | get_Opcode_Y0(tilepro_bundle_bits num) | ||
300 | { | ||
301 | const unsigned int n = (unsigned int)num; | ||
302 | return (((n >> 27)) & 0xf); | ||
303 | } | ||
304 | |||
305 | static __inline unsigned int | ||
306 | get_Opcode_Y1(tilepro_bundle_bits n) | ||
307 | { | ||
308 | return (((unsigned int)(n >> 59)) & 0xf); | ||
309 | } | ||
310 | |||
311 | static __inline unsigned int | ||
312 | get_Opcode_Y2(tilepro_bundle_bits n) | ||
313 | { | ||
314 | return (((unsigned int)(n >> 56)) & 0x7); | ||
315 | } | ||
316 | |||
317 | static __inline unsigned int | ||
318 | get_RROpcodeExtension_SN(tilepro_bundle_bits num) | ||
319 | { | ||
320 | const unsigned int n = (unsigned int)num; | ||
321 | return (((n >> 4)) & 0xf); | ||
322 | } | ||
323 | |||
324 | static __inline unsigned int | ||
325 | get_RRROpcodeExtension_X0(tilepro_bundle_bits num) | ||
326 | { | ||
327 | const unsigned int n = (unsigned int)num; | ||
328 | return (((n >> 18)) & 0x1ff); | ||
329 | } | ||
330 | |||
331 | static __inline unsigned int | ||
332 | get_RRROpcodeExtension_X1(tilepro_bundle_bits n) | ||
333 | { | ||
334 | return (((unsigned int)(n >> 49)) & 0x1ff); | ||
335 | } | ||
336 | |||
337 | static __inline unsigned int | ||
338 | get_RRROpcodeExtension_Y0(tilepro_bundle_bits num) | ||
339 | { | ||
340 | const unsigned int n = (unsigned int)num; | ||
341 | return (((n >> 18)) & 0x3); | ||
342 | } | ||
343 | |||
344 | static __inline unsigned int | ||
345 | get_RRROpcodeExtension_Y1(tilepro_bundle_bits n) | ||
346 | { | ||
347 | return (((unsigned int)(n >> 49)) & 0x3); | ||
348 | } | ||
349 | |||
350 | static __inline unsigned int | ||
351 | get_RouteOpcodeExtension_SN(tilepro_bundle_bits num) | ||
352 | { | ||
353 | const unsigned int n = (unsigned int)num; | ||
354 | return (((n >> 0)) & 0x3ff); | ||
355 | } | ||
356 | |||
357 | static __inline unsigned int | ||
358 | get_S_X0(tilepro_bundle_bits num) | ||
359 | { | ||
360 | const unsigned int n = (unsigned int)num; | ||
361 | return (((n >> 27)) & 0x1); | ||
362 | } | ||
363 | |||
364 | static __inline unsigned int | ||
365 | get_S_X1(tilepro_bundle_bits n) | ||
366 | { | ||
367 | return (((unsigned int)(n >> 58)) & 0x1); | ||
368 | } | ||
369 | |||
370 | static __inline unsigned int | ||
371 | get_ShAmt_X0(tilepro_bundle_bits num) | ||
372 | { | ||
373 | const unsigned int n = (unsigned int)num; | ||
374 | return (((n >> 12)) & 0x1f); | ||
375 | } | ||
376 | |||
377 | static __inline unsigned int | ||
378 | get_ShAmt_X1(tilepro_bundle_bits n) | ||
379 | { | ||
380 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
381 | } | ||
382 | |||
383 | static __inline unsigned int | ||
384 | get_ShAmt_Y0(tilepro_bundle_bits num) | ||
385 | { | ||
386 | const unsigned int n = (unsigned int)num; | ||
387 | return (((n >> 12)) & 0x1f); | ||
388 | } | ||
389 | |||
390 | static __inline unsigned int | ||
391 | get_ShAmt_Y1(tilepro_bundle_bits n) | ||
392 | { | ||
393 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
394 | } | ||
395 | |||
396 | static __inline unsigned int | ||
397 | get_SrcA_X0(tilepro_bundle_bits num) | ||
398 | { | ||
399 | const unsigned int n = (unsigned int)num; | ||
400 | return (((n >> 6)) & 0x3f); | ||
401 | } | ||
402 | |||
403 | static __inline unsigned int | ||
404 | get_SrcA_X1(tilepro_bundle_bits n) | ||
405 | { | ||
406 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
407 | } | ||
408 | |||
409 | static __inline unsigned int | ||
410 | get_SrcA_Y0(tilepro_bundle_bits num) | ||
411 | { | ||
412 | const unsigned int n = (unsigned int)num; | ||
413 | return (((n >> 6)) & 0x3f); | ||
414 | } | ||
415 | |||
416 | static __inline unsigned int | ||
417 | get_SrcA_Y1(tilepro_bundle_bits n) | ||
418 | { | ||
419 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
420 | } | ||
421 | |||
422 | static __inline unsigned int | ||
423 | get_SrcA_Y2(tilepro_bundle_bits n) | ||
424 | { | ||
425 | return (((n >> 26)) & 0x00000001) | | ||
426 | (((unsigned int)(n >> 50)) & 0x0000003e); | ||
427 | } | ||
428 | |||
429 | static __inline unsigned int | ||
430 | get_SrcBDest_Y2(tilepro_bundle_bits num) | ||
431 | { | ||
432 | const unsigned int n = (unsigned int)num; | ||
433 | return (((n >> 20)) & 0x3f); | ||
434 | } | ||
435 | |||
436 | static __inline unsigned int | ||
437 | get_SrcB_X0(tilepro_bundle_bits num) | ||
438 | { | ||
439 | const unsigned int n = (unsigned int)num; | ||
440 | return (((n >> 12)) & 0x3f); | ||
441 | } | ||
442 | |||
443 | static __inline unsigned int | ||
444 | get_SrcB_X1(tilepro_bundle_bits n) | ||
445 | { | ||
446 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
447 | } | ||
448 | |||
449 | static __inline unsigned int | ||
450 | get_SrcB_Y0(tilepro_bundle_bits num) | ||
451 | { | ||
452 | const unsigned int n = (unsigned int)num; | ||
453 | return (((n >> 12)) & 0x3f); | ||
454 | } | ||
455 | |||
456 | static __inline unsigned int | ||
457 | get_SrcB_Y1(tilepro_bundle_bits n) | ||
458 | { | ||
459 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
460 | } | ||
461 | |||
462 | static __inline unsigned int | ||
463 | get_Src_SN(tilepro_bundle_bits num) | ||
464 | { | ||
465 | const unsigned int n = (unsigned int)num; | ||
466 | return (((n >> 0)) & 0x3); | ||
467 | } | ||
468 | |||
469 | static __inline unsigned int | ||
470 | get_UnOpcodeExtension_X0(tilepro_bundle_bits num) | ||
471 | { | ||
472 | const unsigned int n = (unsigned int)num; | ||
473 | return (((n >> 12)) & 0x1f); | ||
474 | } | ||
475 | |||
476 | static __inline unsigned int | ||
477 | get_UnOpcodeExtension_X1(tilepro_bundle_bits n) | ||
478 | { | ||
479 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
480 | } | ||
481 | |||
482 | static __inline unsigned int | ||
483 | get_UnOpcodeExtension_Y0(tilepro_bundle_bits num) | ||
484 | { | ||
485 | const unsigned int n = (unsigned int)num; | ||
486 | return (((n >> 12)) & 0x1f); | ||
487 | } | ||
488 | |||
489 | static __inline unsigned int | ||
490 | get_UnOpcodeExtension_Y1(tilepro_bundle_bits n) | ||
491 | { | ||
492 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
493 | } | ||
494 | |||
495 | static __inline unsigned int | ||
496 | get_UnShOpcodeExtension_X0(tilepro_bundle_bits num) | ||
497 | { | ||
498 | const unsigned int n = (unsigned int)num; | ||
499 | return (((n >> 17)) & 0x3ff); | ||
500 | } | ||
501 | |||
502 | static __inline unsigned int | ||
503 | get_UnShOpcodeExtension_X1(tilepro_bundle_bits n) | ||
504 | { | ||
505 | return (((unsigned int)(n >> 48)) & 0x3ff); | ||
506 | } | ||
507 | |||
508 | static __inline unsigned int | ||
509 | get_UnShOpcodeExtension_Y0(tilepro_bundle_bits num) | ||
510 | { | ||
511 | const unsigned int n = (unsigned int)num; | ||
512 | return (((n >> 17)) & 0x7); | ||
513 | } | ||
514 | |||
515 | static __inline unsigned int | ||
516 | get_UnShOpcodeExtension_Y1(tilepro_bundle_bits n) | ||
517 | { | ||
518 | return (((unsigned int)(n >> 48)) & 0x7); | ||
519 | } | ||
520 | |||
521 | |||
522 | static __inline int | ||
523 | sign_extend(int n, int num_bits) | ||
524 | { | ||
525 | int shift = (int)(sizeof(int) * 8 - num_bits); | ||
526 | return (n << shift) >> shift; | ||
527 | } | ||
528 | |||
529 | |||
530 | |||
531 | static __inline tilepro_bundle_bits | ||
532 | create_BrOff_SN(int num) | ||
533 | { | ||
534 | const unsigned int n = (unsigned int)num; | ||
535 | return ((n & 0x3ff) << 0); | ||
536 | } | ||
537 | |||
538 | static __inline tilepro_bundle_bits | ||
539 | create_BrOff_X1(int num) | ||
540 | { | ||
541 | const unsigned int n = (unsigned int)num; | ||
542 | return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | | ||
543 | (((tilepro_bundle_bits)(n & 0x00018000)) << 20); | ||
544 | } | ||
545 | |||
546 | static __inline tilepro_bundle_bits | ||
547 | create_BrType_X1(int num) | ||
548 | { | ||
549 | const unsigned int n = (unsigned int)num; | ||
550 | return (((tilepro_bundle_bits)(n & 0xf)) << 31); | ||
551 | } | ||
552 | |||
553 | static __inline tilepro_bundle_bits | ||
554 | create_Dest_Imm8_X1(int num) | ||
555 | { | ||
556 | const unsigned int n = (unsigned int)num; | ||
557 | return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | | ||
558 | (((tilepro_bundle_bits)(n & 0x000000c0)) << 43); | ||
559 | } | ||
560 | |||
561 | static __inline tilepro_bundle_bits | ||
562 | create_Dest_SN(int num) | ||
563 | { | ||
564 | const unsigned int n = (unsigned int)num; | ||
565 | return ((n & 0x3) << 2); | ||
566 | } | ||
567 | |||
568 | static __inline tilepro_bundle_bits | ||
569 | create_Dest_X0(int num) | ||
570 | { | ||
571 | const unsigned int n = (unsigned int)num; | ||
572 | return ((n & 0x3f) << 0); | ||
573 | } | ||
574 | |||
575 | static __inline tilepro_bundle_bits | ||
576 | create_Dest_X1(int num) | ||
577 | { | ||
578 | const unsigned int n = (unsigned int)num; | ||
579 | return (((tilepro_bundle_bits)(n & 0x3f)) << 31); | ||
580 | } | ||
581 | |||
582 | static __inline tilepro_bundle_bits | ||
583 | create_Dest_Y0(int num) | ||
584 | { | ||
585 | const unsigned int n = (unsigned int)num; | ||
586 | return ((n & 0x3f) << 0); | ||
587 | } | ||
588 | |||
589 | static __inline tilepro_bundle_bits | ||
590 | create_Dest_Y1(int num) | ||
591 | { | ||
592 | const unsigned int n = (unsigned int)num; | ||
593 | return (((tilepro_bundle_bits)(n & 0x3f)) << 31); | ||
594 | } | ||
595 | |||
596 | static __inline tilepro_bundle_bits | ||
597 | create_Imm16_X0(int num) | ||
598 | { | ||
599 | const unsigned int n = (unsigned int)num; | ||
600 | return ((n & 0xffff) << 12); | ||
601 | } | ||
602 | |||
603 | static __inline tilepro_bundle_bits | ||
604 | create_Imm16_X1(int num) | ||
605 | { | ||
606 | const unsigned int n = (unsigned int)num; | ||
607 | return (((tilepro_bundle_bits)(n & 0xffff)) << 43); | ||
608 | } | ||
609 | |||
610 | static __inline tilepro_bundle_bits | ||
611 | create_Imm8_SN(int num) | ||
612 | { | ||
613 | const unsigned int n = (unsigned int)num; | ||
614 | return ((n & 0xff) << 0); | ||
615 | } | ||
616 | |||
617 | static __inline tilepro_bundle_bits | ||
618 | create_Imm8_X0(int num) | ||
619 | { | ||
620 | const unsigned int n = (unsigned int)num; | ||
621 | return ((n & 0xff) << 12); | ||
622 | } | ||
623 | |||
624 | static __inline tilepro_bundle_bits | ||
625 | create_Imm8_X1(int num) | ||
626 | { | ||
627 | const unsigned int n = (unsigned int)num; | ||
628 | return (((tilepro_bundle_bits)(n & 0xff)) << 43); | ||
629 | } | ||
630 | |||
631 | static __inline tilepro_bundle_bits | ||
632 | create_Imm8_Y0(int num) | ||
633 | { | ||
634 | const unsigned int n = (unsigned int)num; | ||
635 | return ((n & 0xff) << 12); | ||
636 | } | ||
637 | |||
638 | static __inline tilepro_bundle_bits | ||
639 | create_Imm8_Y1(int num) | ||
640 | { | ||
641 | const unsigned int n = (unsigned int)num; | ||
642 | return (((tilepro_bundle_bits)(n & 0xff)) << 43); | ||
643 | } | ||
644 | |||
645 | static __inline tilepro_bundle_bits | ||
646 | create_ImmOpcodeExtension_X0(int num) | ||
647 | { | ||
648 | const unsigned int n = (unsigned int)num; | ||
649 | return ((n & 0x7f) << 20); | ||
650 | } | ||
651 | |||
652 | static __inline tilepro_bundle_bits | ||
653 | create_ImmOpcodeExtension_X1(int num) | ||
654 | { | ||
655 | const unsigned int n = (unsigned int)num; | ||
656 | return (((tilepro_bundle_bits)(n & 0x7f)) << 51); | ||
657 | } | ||
658 | |||
659 | static __inline tilepro_bundle_bits | ||
660 | create_ImmRROpcodeExtension_SN(int num) | ||
661 | { | ||
662 | const unsigned int n = (unsigned int)num; | ||
663 | return ((n & 0x3) << 8); | ||
664 | } | ||
665 | |||
666 | static __inline tilepro_bundle_bits | ||
667 | create_JOffLong_X1(int num) | ||
668 | { | ||
669 | const unsigned int n = (unsigned int)num; | ||
670 | return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | | ||
671 | (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | | ||
672 | (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | | ||
673 | (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | | ||
674 | (((tilepro_bundle_bits)(n & 0x18000000)) << 31); | ||
675 | } | ||
676 | |||
677 | static __inline tilepro_bundle_bits | ||
678 | create_JOff_X1(int num) | ||
679 | { | ||
680 | const unsigned int n = (unsigned int)num; | ||
681 | return (((tilepro_bundle_bits)(n & 0x00007fff)) << 43) | | ||
682 | (((tilepro_bundle_bits)(n & 0x00018000)) << 20) | | ||
683 | (((tilepro_bundle_bits)(n & 0x001e0000)) << 14) | | ||
684 | (((tilepro_bundle_bits)(n & 0x07e00000)) << 16) | | ||
685 | (((tilepro_bundle_bits)(n & 0x08000000)) << 31); | ||
686 | } | ||
687 | |||
688 | static __inline tilepro_bundle_bits | ||
689 | create_MF_Imm15_X1(int num) | ||
690 | { | ||
691 | const unsigned int n = (unsigned int)num; | ||
692 | return (((tilepro_bundle_bits)(n & 0x00003fff)) << 37) | | ||
693 | (((tilepro_bundle_bits)(n & 0x00004000)) << 44); | ||
694 | } | ||
695 | |||
696 | static __inline tilepro_bundle_bits | ||
697 | create_MMEnd_X0(int num) | ||
698 | { | ||
699 | const unsigned int n = (unsigned int)num; | ||
700 | return ((n & 0x1f) << 18); | ||
701 | } | ||
702 | |||
703 | static __inline tilepro_bundle_bits | ||
704 | create_MMEnd_X1(int num) | ||
705 | { | ||
706 | const unsigned int n = (unsigned int)num; | ||
707 | return (((tilepro_bundle_bits)(n & 0x1f)) << 49); | ||
708 | } | ||
709 | |||
710 | static __inline tilepro_bundle_bits | ||
711 | create_MMStart_X0(int num) | ||
712 | { | ||
713 | const unsigned int n = (unsigned int)num; | ||
714 | return ((n & 0x1f) << 23); | ||
715 | } | ||
716 | |||
717 | static __inline tilepro_bundle_bits | ||
718 | create_MMStart_X1(int num) | ||
719 | { | ||
720 | const unsigned int n = (unsigned int)num; | ||
721 | return (((tilepro_bundle_bits)(n & 0x1f)) << 54); | ||
722 | } | ||
723 | |||
724 | static __inline tilepro_bundle_bits | ||
725 | create_MT_Imm15_X1(int num) | ||
726 | { | ||
727 | const unsigned int n = (unsigned int)num; | ||
728 | return (((tilepro_bundle_bits)(n & 0x0000003f)) << 31) | | ||
729 | (((tilepro_bundle_bits)(n & 0x00003fc0)) << 37) | | ||
730 | (((tilepro_bundle_bits)(n & 0x00004000)) << 44); | ||
731 | } | ||
732 | |||
733 | static __inline tilepro_bundle_bits | ||
734 | create_Mode(int num) | ||
735 | { | ||
736 | const unsigned int n = (unsigned int)num; | ||
737 | return (((tilepro_bundle_bits)(n & 0x1)) << 63); | ||
738 | } | ||
739 | |||
740 | static __inline tilepro_bundle_bits | ||
741 | create_NoRegOpcodeExtension_SN(int num) | ||
742 | { | ||
743 | const unsigned int n = (unsigned int)num; | ||
744 | return ((n & 0xf) << 0); | ||
745 | } | ||
746 | |||
747 | static __inline tilepro_bundle_bits | ||
748 | create_Opcode_SN(int num) | ||
749 | { | ||
750 | const unsigned int n = (unsigned int)num; | ||
751 | return ((n & 0x3f) << 10); | ||
752 | } | ||
753 | |||
754 | static __inline tilepro_bundle_bits | ||
755 | create_Opcode_X0(int num) | ||
756 | { | ||
757 | const unsigned int n = (unsigned int)num; | ||
758 | return ((n & 0x7) << 28); | ||
759 | } | ||
760 | |||
761 | static __inline tilepro_bundle_bits | ||
762 | create_Opcode_X1(int num) | ||
763 | { | ||
764 | const unsigned int n = (unsigned int)num; | ||
765 | return (((tilepro_bundle_bits)(n & 0xf)) << 59); | ||
766 | } | ||
767 | |||
768 | static __inline tilepro_bundle_bits | ||
769 | create_Opcode_Y0(int num) | ||
770 | { | ||
771 | const unsigned int n = (unsigned int)num; | ||
772 | return ((n & 0xf) << 27); | ||
773 | } | ||
774 | |||
775 | static __inline tilepro_bundle_bits | ||
776 | create_Opcode_Y1(int num) | ||
777 | { | ||
778 | const unsigned int n = (unsigned int)num; | ||
779 | return (((tilepro_bundle_bits)(n & 0xf)) << 59); | ||
780 | } | ||
781 | |||
782 | static __inline tilepro_bundle_bits | ||
783 | create_Opcode_Y2(int num) | ||
784 | { | ||
785 | const unsigned int n = (unsigned int)num; | ||
786 | return (((tilepro_bundle_bits)(n & 0x7)) << 56); | ||
787 | } | ||
788 | |||
789 | static __inline tilepro_bundle_bits | ||
790 | create_RROpcodeExtension_SN(int num) | ||
791 | { | ||
792 | const unsigned int n = (unsigned int)num; | ||
793 | return ((n & 0xf) << 4); | ||
794 | } | ||
795 | |||
796 | static __inline tilepro_bundle_bits | ||
797 | create_RRROpcodeExtension_X0(int num) | ||
798 | { | ||
799 | const unsigned int n = (unsigned int)num; | ||
800 | return ((n & 0x1ff) << 18); | ||
801 | } | ||
802 | |||
803 | static __inline tilepro_bundle_bits | ||
804 | create_RRROpcodeExtension_X1(int num) | ||
805 | { | ||
806 | const unsigned int n = (unsigned int)num; | ||
807 | return (((tilepro_bundle_bits)(n & 0x1ff)) << 49); | ||
808 | } | ||
809 | |||
810 | static __inline tilepro_bundle_bits | ||
811 | create_RRROpcodeExtension_Y0(int num) | ||
812 | { | ||
813 | const unsigned int n = (unsigned int)num; | ||
814 | return ((n & 0x3) << 18); | ||
815 | } | ||
816 | |||
817 | static __inline tilepro_bundle_bits | ||
818 | create_RRROpcodeExtension_Y1(int num) | ||
819 | { | ||
820 | const unsigned int n = (unsigned int)num; | ||
821 | return (((tilepro_bundle_bits)(n & 0x3)) << 49); | ||
822 | } | ||
823 | |||
824 | static __inline tilepro_bundle_bits | ||
825 | create_RouteOpcodeExtension_SN(int num) | ||
826 | { | ||
827 | const unsigned int n = (unsigned int)num; | ||
828 | return ((n & 0x3ff) << 0); | ||
829 | } | ||
830 | |||
831 | static __inline tilepro_bundle_bits | ||
832 | create_S_X0(int num) | ||
833 | { | ||
834 | const unsigned int n = (unsigned int)num; | ||
835 | return ((n & 0x1) << 27); | ||
836 | } | ||
837 | |||
838 | static __inline tilepro_bundle_bits | ||
839 | create_S_X1(int num) | ||
840 | { | ||
841 | const unsigned int n = (unsigned int)num; | ||
842 | return (((tilepro_bundle_bits)(n & 0x1)) << 58); | ||
843 | } | ||
844 | |||
845 | static __inline tilepro_bundle_bits | ||
846 | create_ShAmt_X0(int num) | ||
847 | { | ||
848 | const unsigned int n = (unsigned int)num; | ||
849 | return ((n & 0x1f) << 12); | ||
850 | } | ||
851 | |||
852 | static __inline tilepro_bundle_bits | ||
853 | create_ShAmt_X1(int num) | ||
854 | { | ||
855 | const unsigned int n = (unsigned int)num; | ||
856 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
857 | } | ||
858 | |||
859 | static __inline tilepro_bundle_bits | ||
860 | create_ShAmt_Y0(int num) | ||
861 | { | ||
862 | const unsigned int n = (unsigned int)num; | ||
863 | return ((n & 0x1f) << 12); | ||
864 | } | ||
865 | |||
866 | static __inline tilepro_bundle_bits | ||
867 | create_ShAmt_Y1(int num) | ||
868 | { | ||
869 | const unsigned int n = (unsigned int)num; | ||
870 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
871 | } | ||
872 | |||
873 | static __inline tilepro_bundle_bits | ||
874 | create_SrcA_X0(int num) | ||
875 | { | ||
876 | const unsigned int n = (unsigned int)num; | ||
877 | return ((n & 0x3f) << 6); | ||
878 | } | ||
879 | |||
880 | static __inline tilepro_bundle_bits | ||
881 | create_SrcA_X1(int num) | ||
882 | { | ||
883 | const unsigned int n = (unsigned int)num; | ||
884 | return (((tilepro_bundle_bits)(n & 0x3f)) << 37); | ||
885 | } | ||
886 | |||
887 | static __inline tilepro_bundle_bits | ||
888 | create_SrcA_Y0(int num) | ||
889 | { | ||
890 | const unsigned int n = (unsigned int)num; | ||
891 | return ((n & 0x3f) << 6); | ||
892 | } | ||
893 | |||
894 | static __inline tilepro_bundle_bits | ||
895 | create_SrcA_Y1(int num) | ||
896 | { | ||
897 | const unsigned int n = (unsigned int)num; | ||
898 | return (((tilepro_bundle_bits)(n & 0x3f)) << 37); | ||
899 | } | ||
900 | |||
901 | static __inline tilepro_bundle_bits | ||
902 | create_SrcA_Y2(int num) | ||
903 | { | ||
904 | const unsigned int n = (unsigned int)num; | ||
905 | return ((n & 0x00000001) << 26) | | ||
906 | (((tilepro_bundle_bits)(n & 0x0000003e)) << 50); | ||
907 | } | ||
908 | |||
909 | static __inline tilepro_bundle_bits | ||
910 | create_SrcBDest_Y2(int num) | ||
911 | { | ||
912 | const unsigned int n = (unsigned int)num; | ||
913 | return ((n & 0x3f) << 20); | ||
914 | } | ||
915 | |||
916 | static __inline tilepro_bundle_bits | ||
917 | create_SrcB_X0(int num) | ||
918 | { | ||
919 | const unsigned int n = (unsigned int)num; | ||
920 | return ((n & 0x3f) << 12); | ||
921 | } | ||
922 | |||
923 | static __inline tilepro_bundle_bits | ||
924 | create_SrcB_X1(int num) | ||
925 | { | ||
926 | const unsigned int n = (unsigned int)num; | ||
927 | return (((tilepro_bundle_bits)(n & 0x3f)) << 43); | ||
928 | } | ||
929 | |||
930 | static __inline tilepro_bundle_bits | ||
931 | create_SrcB_Y0(int num) | ||
932 | { | ||
933 | const unsigned int n = (unsigned int)num; | ||
934 | return ((n & 0x3f) << 12); | ||
935 | } | ||
936 | |||
937 | static __inline tilepro_bundle_bits | ||
938 | create_SrcB_Y1(int num) | ||
939 | { | ||
940 | const unsigned int n = (unsigned int)num; | ||
941 | return (((tilepro_bundle_bits)(n & 0x3f)) << 43); | ||
942 | } | ||
943 | |||
944 | static __inline tilepro_bundle_bits | ||
945 | create_Src_SN(int num) | ||
946 | { | ||
947 | const unsigned int n = (unsigned int)num; | ||
948 | return ((n & 0x3) << 0); | ||
949 | } | ||
950 | |||
951 | static __inline tilepro_bundle_bits | ||
952 | create_UnOpcodeExtension_X0(int num) | ||
953 | { | ||
954 | const unsigned int n = (unsigned int)num; | ||
955 | return ((n & 0x1f) << 12); | ||
956 | } | ||
957 | |||
958 | static __inline tilepro_bundle_bits | ||
959 | create_UnOpcodeExtension_X1(int num) | ||
960 | { | ||
961 | const unsigned int n = (unsigned int)num; | ||
962 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
963 | } | ||
964 | |||
965 | static __inline tilepro_bundle_bits | ||
966 | create_UnOpcodeExtension_Y0(int num) | ||
967 | { | ||
968 | const unsigned int n = (unsigned int)num; | ||
969 | return ((n & 0x1f) << 12); | ||
970 | } | ||
971 | |||
972 | static __inline tilepro_bundle_bits | ||
973 | create_UnOpcodeExtension_Y1(int num) | ||
974 | { | ||
975 | const unsigned int n = (unsigned int)num; | ||
976 | return (((tilepro_bundle_bits)(n & 0x1f)) << 43); | ||
977 | } | ||
978 | |||
979 | static __inline tilepro_bundle_bits | ||
980 | create_UnShOpcodeExtension_X0(int num) | ||
981 | { | ||
982 | const unsigned int n = (unsigned int)num; | ||
983 | return ((n & 0x3ff) << 17); | ||
984 | } | ||
985 | |||
986 | static __inline tilepro_bundle_bits | ||
987 | create_UnShOpcodeExtension_X1(int num) | ||
988 | { | ||
989 | const unsigned int n = (unsigned int)num; | ||
990 | return (((tilepro_bundle_bits)(n & 0x3ff)) << 48); | ||
991 | } | ||
992 | |||
993 | static __inline tilepro_bundle_bits | ||
994 | create_UnShOpcodeExtension_Y0(int num) | ||
995 | { | ||
996 | const unsigned int n = (unsigned int)num; | ||
997 | return ((n & 0x7) << 17); | ||
998 | } | ||
999 | |||
1000 | static __inline tilepro_bundle_bits | ||
1001 | create_UnShOpcodeExtension_Y1(int num) | ||
1002 | { | ||
1003 | const unsigned int n = (unsigned int)num; | ||
1004 | return (((tilepro_bundle_bits)(n & 0x7)) << 48); | ||
1005 | } | ||
1006 | |||
1007 | |||
1008 | enum | ||
1009 | { | ||
1010 | ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, | ||
1011 | ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, | ||
1012 | ADDB_SPECIAL_0_OPCODE_X0 = 1, | ||
1013 | ADDB_SPECIAL_0_OPCODE_X1 = 1, | ||
1014 | ADDHS_SPECIAL_0_OPCODE_X0 = 99, | ||
1015 | ADDHS_SPECIAL_0_OPCODE_X1 = 69, | ||
1016 | ADDH_SPECIAL_0_OPCODE_X0 = 2, | ||
1017 | ADDH_SPECIAL_0_OPCODE_X1 = 2, | ||
1018 | ADDIB_IMM_0_OPCODE_X0 = 1, | ||
1019 | ADDIB_IMM_0_OPCODE_X1 = 1, | ||
1020 | ADDIH_IMM_0_OPCODE_X0 = 2, | ||
1021 | ADDIH_IMM_0_OPCODE_X1 = 2, | ||
1022 | ADDI_IMM_0_OPCODE_X0 = 3, | ||
1023 | ADDI_IMM_0_OPCODE_X1 = 3, | ||
1024 | ADDI_IMM_1_OPCODE_SN = 1, | ||
1025 | ADDI_OPCODE_Y0 = 9, | ||
1026 | ADDI_OPCODE_Y1 = 7, | ||
1027 | ADDLIS_OPCODE_X0 = 1, | ||
1028 | ADDLIS_OPCODE_X1 = 2, | ||
1029 | ADDLI_OPCODE_X0 = 2, | ||
1030 | ADDLI_OPCODE_X1 = 3, | ||
1031 | ADDS_SPECIAL_0_OPCODE_X0 = 96, | ||
1032 | ADDS_SPECIAL_0_OPCODE_X1 = 66, | ||
1033 | ADD_SPECIAL_0_OPCODE_X0 = 3, | ||
1034 | ADD_SPECIAL_0_OPCODE_X1 = 3, | ||
1035 | ADD_SPECIAL_0_OPCODE_Y0 = 0, | ||
1036 | ADD_SPECIAL_0_OPCODE_Y1 = 0, | ||
1037 | ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, | ||
1038 | ADIFFH_SPECIAL_0_OPCODE_X0 = 5, | ||
1039 | ANDI_IMM_0_OPCODE_X0 = 1, | ||
1040 | ANDI_IMM_0_OPCODE_X1 = 4, | ||
1041 | ANDI_OPCODE_Y0 = 10, | ||
1042 | ANDI_OPCODE_Y1 = 8, | ||
1043 | AND_SPECIAL_0_OPCODE_X0 = 6, | ||
1044 | AND_SPECIAL_0_OPCODE_X1 = 4, | ||
1045 | AND_SPECIAL_2_OPCODE_Y0 = 0, | ||
1046 | AND_SPECIAL_2_OPCODE_Y1 = 0, | ||
1047 | AULI_OPCODE_X0 = 3, | ||
1048 | AULI_OPCODE_X1 = 4, | ||
1049 | AVGB_U_SPECIAL_0_OPCODE_X0 = 7, | ||
1050 | AVGH_SPECIAL_0_OPCODE_X0 = 8, | ||
1051 | BBNST_BRANCH_OPCODE_X1 = 15, | ||
1052 | BBNS_BRANCH_OPCODE_X1 = 14, | ||
1053 | BBNS_OPCODE_SN = 63, | ||
1054 | BBST_BRANCH_OPCODE_X1 = 13, | ||
1055 | BBS_BRANCH_OPCODE_X1 = 12, | ||
1056 | BBS_OPCODE_SN = 62, | ||
1057 | BGEZT_BRANCH_OPCODE_X1 = 7, | ||
1058 | BGEZ_BRANCH_OPCODE_X1 = 6, | ||
1059 | BGEZ_OPCODE_SN = 61, | ||
1060 | BGZT_BRANCH_OPCODE_X1 = 5, | ||
1061 | BGZ_BRANCH_OPCODE_X1 = 4, | ||
1062 | BGZ_OPCODE_SN = 58, | ||
1063 | BITX_UN_0_SHUN_0_OPCODE_X0 = 1, | ||
1064 | BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, | ||
1065 | BLEZT_BRANCH_OPCODE_X1 = 11, | ||
1066 | BLEZ_BRANCH_OPCODE_X1 = 10, | ||
1067 | BLEZ_OPCODE_SN = 59, | ||
1068 | BLZT_BRANCH_OPCODE_X1 = 9, | ||
1069 | BLZ_BRANCH_OPCODE_X1 = 8, | ||
1070 | BLZ_OPCODE_SN = 60, | ||
1071 | BNZT_BRANCH_OPCODE_X1 = 3, | ||
1072 | BNZ_BRANCH_OPCODE_X1 = 2, | ||
1073 | BNZ_OPCODE_SN = 57, | ||
1074 | BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, | ||
1075 | BRANCH_OPCODE_X1 = 5, | ||
1076 | BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, | ||
1077 | BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, | ||
1078 | BZT_BRANCH_OPCODE_X1 = 1, | ||
1079 | BZ_BRANCH_OPCODE_X1 = 0, | ||
1080 | BZ_OPCODE_SN = 56, | ||
1081 | CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, | ||
1082 | CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, | ||
1083 | CRC32_32_SPECIAL_0_OPCODE_X0 = 9, | ||
1084 | CRC32_8_SPECIAL_0_OPCODE_X0 = 10, | ||
1085 | CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, | ||
1086 | CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, | ||
1087 | DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, | ||
1088 | DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, | ||
1089 | DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, | ||
1090 | FINV_UN_0_SHUN_0_OPCODE_X1 = 3, | ||
1091 | FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, | ||
1092 | FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, | ||
1093 | FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, | ||
1094 | FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, | ||
1095 | FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, | ||
1096 | FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, | ||
1097 | HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, | ||
1098 | ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, | ||
1099 | ILL_UN_0_SHUN_0_OPCODE_X1 = 7, | ||
1100 | ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, | ||
1101 | IMM_0_OPCODE_SN = 0, | ||
1102 | IMM_0_OPCODE_X0 = 4, | ||
1103 | IMM_0_OPCODE_X1 = 6, | ||
1104 | IMM_1_OPCODE_SN = 1, | ||
1105 | IMM_OPCODE_0_X0 = 5, | ||
1106 | INTHB_SPECIAL_0_OPCODE_X0 = 11, | ||
1107 | INTHB_SPECIAL_0_OPCODE_X1 = 5, | ||
1108 | INTHH_SPECIAL_0_OPCODE_X0 = 12, | ||
1109 | INTHH_SPECIAL_0_OPCODE_X1 = 6, | ||
1110 | INTLB_SPECIAL_0_OPCODE_X0 = 13, | ||
1111 | INTLB_SPECIAL_0_OPCODE_X1 = 7, | ||
1112 | INTLH_SPECIAL_0_OPCODE_X0 = 14, | ||
1113 | INTLH_SPECIAL_0_OPCODE_X1 = 8, | ||
1114 | INV_UN_0_SHUN_0_OPCODE_X1 = 8, | ||
1115 | IRET_UN_0_SHUN_0_OPCODE_X1 = 9, | ||
1116 | JALB_OPCODE_X1 = 13, | ||
1117 | JALF_OPCODE_X1 = 12, | ||
1118 | JALRP_SPECIAL_0_OPCODE_X1 = 9, | ||
1119 | JALRR_IMM_1_OPCODE_SN = 3, | ||
1120 | JALR_RR_IMM_0_OPCODE_SN = 5, | ||
1121 | JALR_SPECIAL_0_OPCODE_X1 = 10, | ||
1122 | JB_OPCODE_X1 = 11, | ||
1123 | JF_OPCODE_X1 = 10, | ||
1124 | JRP_SPECIAL_0_OPCODE_X1 = 11, | ||
1125 | JRR_IMM_1_OPCODE_SN = 2, | ||
1126 | JR_RR_IMM_0_OPCODE_SN = 4, | ||
1127 | JR_SPECIAL_0_OPCODE_X1 = 12, | ||
1128 | LBADD_IMM_0_OPCODE_X1 = 22, | ||
1129 | LBADD_U_IMM_0_OPCODE_X1 = 23, | ||
1130 | LB_OPCODE_Y2 = 0, | ||
1131 | LB_UN_0_SHUN_0_OPCODE_X1 = 10, | ||
1132 | LB_U_OPCODE_Y2 = 1, | ||
1133 | LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, | ||
1134 | LHADD_IMM_0_OPCODE_X1 = 24, | ||
1135 | LHADD_U_IMM_0_OPCODE_X1 = 25, | ||
1136 | LH_OPCODE_Y2 = 2, | ||
1137 | LH_UN_0_SHUN_0_OPCODE_X1 = 12, | ||
1138 | LH_U_OPCODE_Y2 = 3, | ||
1139 | LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, | ||
1140 | LNK_SPECIAL_0_OPCODE_X1 = 13, | ||
1141 | LWADD_IMM_0_OPCODE_X1 = 26, | ||
1142 | LWADD_NA_IMM_0_OPCODE_X1 = 27, | ||
1143 | LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, | ||
1144 | LW_OPCODE_Y2 = 4, | ||
1145 | LW_UN_0_SHUN_0_OPCODE_X1 = 14, | ||
1146 | MAXB_U_SPECIAL_0_OPCODE_X0 = 15, | ||
1147 | MAXB_U_SPECIAL_0_OPCODE_X1 = 14, | ||
1148 | MAXH_SPECIAL_0_OPCODE_X0 = 16, | ||
1149 | MAXH_SPECIAL_0_OPCODE_X1 = 15, | ||
1150 | MAXIB_U_IMM_0_OPCODE_X0 = 4, | ||
1151 | MAXIB_U_IMM_0_OPCODE_X1 = 5, | ||
1152 | MAXIH_IMM_0_OPCODE_X0 = 5, | ||
1153 | MAXIH_IMM_0_OPCODE_X1 = 6, | ||
1154 | MFSPR_IMM_0_OPCODE_X1 = 7, | ||
1155 | MF_UN_0_SHUN_0_OPCODE_X1 = 15, | ||
1156 | MINB_U_SPECIAL_0_OPCODE_X0 = 17, | ||
1157 | MINB_U_SPECIAL_0_OPCODE_X1 = 16, | ||
1158 | MINH_SPECIAL_0_OPCODE_X0 = 18, | ||
1159 | MINH_SPECIAL_0_OPCODE_X1 = 17, | ||
1160 | MINIB_U_IMM_0_OPCODE_X0 = 6, | ||
1161 | MINIB_U_IMM_0_OPCODE_X1 = 8, | ||
1162 | MINIH_IMM_0_OPCODE_X0 = 7, | ||
1163 | MINIH_IMM_0_OPCODE_X1 = 9, | ||
1164 | MM_OPCODE_X0 = 6, | ||
1165 | MM_OPCODE_X1 = 7, | ||
1166 | MNZB_SPECIAL_0_OPCODE_X0 = 19, | ||
1167 | MNZB_SPECIAL_0_OPCODE_X1 = 18, | ||
1168 | MNZH_SPECIAL_0_OPCODE_X0 = 20, | ||
1169 | MNZH_SPECIAL_0_OPCODE_X1 = 19, | ||
1170 | MNZ_SPECIAL_0_OPCODE_X0 = 21, | ||
1171 | MNZ_SPECIAL_0_OPCODE_X1 = 20, | ||
1172 | MNZ_SPECIAL_1_OPCODE_Y0 = 0, | ||
1173 | MNZ_SPECIAL_1_OPCODE_Y1 = 1, | ||
1174 | MOVEI_IMM_1_OPCODE_SN = 0, | ||
1175 | MOVE_RR_IMM_0_OPCODE_SN = 8, | ||
1176 | MTSPR_IMM_0_OPCODE_X1 = 10, | ||
1177 | MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, | ||
1178 | MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, | ||
1179 | MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, | ||
1180 | MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, | ||
1181 | MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, | ||
1182 | MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, | ||
1183 | MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, | ||
1184 | MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, | ||
1185 | MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, | ||
1186 | MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, | ||
1187 | MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, | ||
1188 | MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, | ||
1189 | MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, | ||
1190 | MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, | ||
1191 | MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, | ||
1192 | MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, | ||
1193 | MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, | ||
1194 | MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, | ||
1195 | MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, | ||
1196 | MULHL_US_SPECIAL_0_OPCODE_X0 = 36, | ||
1197 | MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, | ||
1198 | MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, | ||
1199 | MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, | ||
1200 | MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, | ||
1201 | MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, | ||
1202 | MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, | ||
1203 | MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, | ||
1204 | MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, | ||
1205 | MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, | ||
1206 | MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, | ||
1207 | MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, | ||
1208 | MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, | ||
1209 | MVNZ_SPECIAL_0_OPCODE_X0 = 45, | ||
1210 | MVNZ_SPECIAL_1_OPCODE_Y0 = 1, | ||
1211 | MVZ_SPECIAL_0_OPCODE_X0 = 46, | ||
1212 | MVZ_SPECIAL_1_OPCODE_Y0 = 2, | ||
1213 | MZB_SPECIAL_0_OPCODE_X0 = 47, | ||
1214 | MZB_SPECIAL_0_OPCODE_X1 = 21, | ||
1215 | MZH_SPECIAL_0_OPCODE_X0 = 48, | ||
1216 | MZH_SPECIAL_0_OPCODE_X1 = 22, | ||
1217 | MZ_SPECIAL_0_OPCODE_X0 = 49, | ||
1218 | MZ_SPECIAL_0_OPCODE_X1 = 23, | ||
1219 | MZ_SPECIAL_1_OPCODE_Y0 = 3, | ||
1220 | MZ_SPECIAL_1_OPCODE_Y1 = 2, | ||
1221 | NAP_UN_0_SHUN_0_OPCODE_X1 = 16, | ||
1222 | NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, | ||
1223 | NOP_UN_0_SHUN_0_OPCODE_X0 = 6, | ||
1224 | NOP_UN_0_SHUN_0_OPCODE_X1 = 17, | ||
1225 | NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, | ||
1226 | NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, | ||
1227 | NOREG_RR_IMM_0_OPCODE_SN = 0, | ||
1228 | NOR_SPECIAL_0_OPCODE_X0 = 50, | ||
1229 | NOR_SPECIAL_0_OPCODE_X1 = 24, | ||
1230 | NOR_SPECIAL_2_OPCODE_Y0 = 1, | ||
1231 | NOR_SPECIAL_2_OPCODE_Y1 = 1, | ||
1232 | ORI_IMM_0_OPCODE_X0 = 8, | ||
1233 | ORI_IMM_0_OPCODE_X1 = 11, | ||
1234 | ORI_OPCODE_Y0 = 11, | ||
1235 | ORI_OPCODE_Y1 = 9, | ||
1236 | OR_SPECIAL_0_OPCODE_X0 = 51, | ||
1237 | OR_SPECIAL_0_OPCODE_X1 = 25, | ||
1238 | OR_SPECIAL_2_OPCODE_Y0 = 2, | ||
1239 | OR_SPECIAL_2_OPCODE_Y1 = 2, | ||
1240 | PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, | ||
1241 | PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, | ||
1242 | PACKHB_SPECIAL_0_OPCODE_X0 = 52, | ||
1243 | PACKHB_SPECIAL_0_OPCODE_X1 = 26, | ||
1244 | PACKHS_SPECIAL_0_OPCODE_X0 = 102, | ||
1245 | PACKHS_SPECIAL_0_OPCODE_X1 = 72, | ||
1246 | PACKLB_SPECIAL_0_OPCODE_X0 = 53, | ||
1247 | PACKLB_SPECIAL_0_OPCODE_X1 = 27, | ||
1248 | PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, | ||
1249 | PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, | ||
1250 | RLI_SHUN_0_OPCODE_X0 = 1, | ||
1251 | RLI_SHUN_0_OPCODE_X1 = 1, | ||
1252 | RLI_SHUN_0_OPCODE_Y0 = 1, | ||
1253 | RLI_SHUN_0_OPCODE_Y1 = 1, | ||
1254 | RL_SPECIAL_0_OPCODE_X0 = 54, | ||
1255 | RL_SPECIAL_0_OPCODE_X1 = 28, | ||
1256 | RL_SPECIAL_3_OPCODE_Y0 = 0, | ||
1257 | RL_SPECIAL_3_OPCODE_Y1 = 0, | ||
1258 | RR_IMM_0_OPCODE_SN = 0, | ||
1259 | S1A_SPECIAL_0_OPCODE_X0 = 55, | ||
1260 | S1A_SPECIAL_0_OPCODE_X1 = 29, | ||
1261 | S1A_SPECIAL_0_OPCODE_Y0 = 1, | ||
1262 | S1A_SPECIAL_0_OPCODE_Y1 = 1, | ||
1263 | S2A_SPECIAL_0_OPCODE_X0 = 56, | ||
1264 | S2A_SPECIAL_0_OPCODE_X1 = 30, | ||
1265 | S2A_SPECIAL_0_OPCODE_Y0 = 2, | ||
1266 | S2A_SPECIAL_0_OPCODE_Y1 = 2, | ||
1267 | S3A_SPECIAL_0_OPCODE_X0 = 57, | ||
1268 | S3A_SPECIAL_0_OPCODE_X1 = 31, | ||
1269 | S3A_SPECIAL_5_OPCODE_Y0 = 1, | ||
1270 | S3A_SPECIAL_5_OPCODE_Y1 = 1, | ||
1271 | SADAB_U_SPECIAL_0_OPCODE_X0 = 58, | ||
1272 | SADAH_SPECIAL_0_OPCODE_X0 = 59, | ||
1273 | SADAH_U_SPECIAL_0_OPCODE_X0 = 60, | ||
1274 | SADB_U_SPECIAL_0_OPCODE_X0 = 61, | ||
1275 | SADH_SPECIAL_0_OPCODE_X0 = 62, | ||
1276 | SADH_U_SPECIAL_0_OPCODE_X0 = 63, | ||
1277 | SBADD_IMM_0_OPCODE_X1 = 28, | ||
1278 | SB_OPCODE_Y2 = 5, | ||
1279 | SB_SPECIAL_0_OPCODE_X1 = 32, | ||
1280 | SEQB_SPECIAL_0_OPCODE_X0 = 64, | ||
1281 | SEQB_SPECIAL_0_OPCODE_X1 = 33, | ||
1282 | SEQH_SPECIAL_0_OPCODE_X0 = 65, | ||
1283 | SEQH_SPECIAL_0_OPCODE_X1 = 34, | ||
1284 | SEQIB_IMM_0_OPCODE_X0 = 9, | ||
1285 | SEQIB_IMM_0_OPCODE_X1 = 12, | ||
1286 | SEQIH_IMM_0_OPCODE_X0 = 10, | ||
1287 | SEQIH_IMM_0_OPCODE_X1 = 13, | ||
1288 | SEQI_IMM_0_OPCODE_X0 = 11, | ||
1289 | SEQI_IMM_0_OPCODE_X1 = 14, | ||
1290 | SEQI_OPCODE_Y0 = 12, | ||
1291 | SEQI_OPCODE_Y1 = 10, | ||
1292 | SEQ_SPECIAL_0_OPCODE_X0 = 66, | ||
1293 | SEQ_SPECIAL_0_OPCODE_X1 = 35, | ||
1294 | SEQ_SPECIAL_5_OPCODE_Y0 = 2, | ||
1295 | SEQ_SPECIAL_5_OPCODE_Y1 = 2, | ||
1296 | SHADD_IMM_0_OPCODE_X1 = 29, | ||
1297 | SHL8II_IMM_0_OPCODE_SN = 3, | ||
1298 | SHLB_SPECIAL_0_OPCODE_X0 = 67, | ||
1299 | SHLB_SPECIAL_0_OPCODE_X1 = 36, | ||
1300 | SHLH_SPECIAL_0_OPCODE_X0 = 68, | ||
1301 | SHLH_SPECIAL_0_OPCODE_X1 = 37, | ||
1302 | SHLIB_SHUN_0_OPCODE_X0 = 2, | ||
1303 | SHLIB_SHUN_0_OPCODE_X1 = 2, | ||
1304 | SHLIH_SHUN_0_OPCODE_X0 = 3, | ||
1305 | SHLIH_SHUN_0_OPCODE_X1 = 3, | ||
1306 | SHLI_SHUN_0_OPCODE_X0 = 4, | ||
1307 | SHLI_SHUN_0_OPCODE_X1 = 4, | ||
1308 | SHLI_SHUN_0_OPCODE_Y0 = 2, | ||
1309 | SHLI_SHUN_0_OPCODE_Y1 = 2, | ||
1310 | SHL_SPECIAL_0_OPCODE_X0 = 69, | ||
1311 | SHL_SPECIAL_0_OPCODE_X1 = 38, | ||
1312 | SHL_SPECIAL_3_OPCODE_Y0 = 1, | ||
1313 | SHL_SPECIAL_3_OPCODE_Y1 = 1, | ||
1314 | SHR1_RR_IMM_0_OPCODE_SN = 9, | ||
1315 | SHRB_SPECIAL_0_OPCODE_X0 = 70, | ||
1316 | SHRB_SPECIAL_0_OPCODE_X1 = 39, | ||
1317 | SHRH_SPECIAL_0_OPCODE_X0 = 71, | ||
1318 | SHRH_SPECIAL_0_OPCODE_X1 = 40, | ||
1319 | SHRIB_SHUN_0_OPCODE_X0 = 5, | ||
1320 | SHRIB_SHUN_0_OPCODE_X1 = 5, | ||
1321 | SHRIH_SHUN_0_OPCODE_X0 = 6, | ||
1322 | SHRIH_SHUN_0_OPCODE_X1 = 6, | ||
1323 | SHRI_SHUN_0_OPCODE_X0 = 7, | ||
1324 | SHRI_SHUN_0_OPCODE_X1 = 7, | ||
1325 | SHRI_SHUN_0_OPCODE_Y0 = 3, | ||
1326 | SHRI_SHUN_0_OPCODE_Y1 = 3, | ||
1327 | SHR_SPECIAL_0_OPCODE_X0 = 72, | ||
1328 | SHR_SPECIAL_0_OPCODE_X1 = 41, | ||
1329 | SHR_SPECIAL_3_OPCODE_Y0 = 2, | ||
1330 | SHR_SPECIAL_3_OPCODE_Y1 = 2, | ||
1331 | SHUN_0_OPCODE_X0 = 7, | ||
1332 | SHUN_0_OPCODE_X1 = 8, | ||
1333 | SHUN_0_OPCODE_Y0 = 13, | ||
1334 | SHUN_0_OPCODE_Y1 = 11, | ||
1335 | SH_OPCODE_Y2 = 6, | ||
1336 | SH_SPECIAL_0_OPCODE_X1 = 42, | ||
1337 | SLTB_SPECIAL_0_OPCODE_X0 = 73, | ||
1338 | SLTB_SPECIAL_0_OPCODE_X1 = 43, | ||
1339 | SLTB_U_SPECIAL_0_OPCODE_X0 = 74, | ||
1340 | SLTB_U_SPECIAL_0_OPCODE_X1 = 44, | ||
1341 | SLTEB_SPECIAL_0_OPCODE_X0 = 75, | ||
1342 | SLTEB_SPECIAL_0_OPCODE_X1 = 45, | ||
1343 | SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, | ||
1344 | SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, | ||
1345 | SLTEH_SPECIAL_0_OPCODE_X0 = 77, | ||
1346 | SLTEH_SPECIAL_0_OPCODE_X1 = 47, | ||
1347 | SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, | ||
1348 | SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, | ||
1349 | SLTE_SPECIAL_0_OPCODE_X0 = 79, | ||
1350 | SLTE_SPECIAL_0_OPCODE_X1 = 49, | ||
1351 | SLTE_SPECIAL_4_OPCODE_Y0 = 0, | ||
1352 | SLTE_SPECIAL_4_OPCODE_Y1 = 0, | ||
1353 | SLTE_U_SPECIAL_0_OPCODE_X0 = 80, | ||
1354 | SLTE_U_SPECIAL_0_OPCODE_X1 = 50, | ||
1355 | SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, | ||
1356 | SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, | ||
1357 | SLTH_SPECIAL_0_OPCODE_X0 = 81, | ||
1358 | SLTH_SPECIAL_0_OPCODE_X1 = 51, | ||
1359 | SLTH_U_SPECIAL_0_OPCODE_X0 = 82, | ||
1360 | SLTH_U_SPECIAL_0_OPCODE_X1 = 52, | ||
1361 | SLTIB_IMM_0_OPCODE_X0 = 12, | ||
1362 | SLTIB_IMM_0_OPCODE_X1 = 15, | ||
1363 | SLTIB_U_IMM_0_OPCODE_X0 = 13, | ||
1364 | SLTIB_U_IMM_0_OPCODE_X1 = 16, | ||
1365 | SLTIH_IMM_0_OPCODE_X0 = 14, | ||
1366 | SLTIH_IMM_0_OPCODE_X1 = 17, | ||
1367 | SLTIH_U_IMM_0_OPCODE_X0 = 15, | ||
1368 | SLTIH_U_IMM_0_OPCODE_X1 = 18, | ||
1369 | SLTI_IMM_0_OPCODE_X0 = 16, | ||
1370 | SLTI_IMM_0_OPCODE_X1 = 19, | ||
1371 | SLTI_OPCODE_Y0 = 14, | ||
1372 | SLTI_OPCODE_Y1 = 12, | ||
1373 | SLTI_U_IMM_0_OPCODE_X0 = 17, | ||
1374 | SLTI_U_IMM_0_OPCODE_X1 = 20, | ||
1375 | SLTI_U_OPCODE_Y0 = 15, | ||
1376 | SLTI_U_OPCODE_Y1 = 13, | ||
1377 | SLT_SPECIAL_0_OPCODE_X0 = 83, | ||
1378 | SLT_SPECIAL_0_OPCODE_X1 = 53, | ||
1379 | SLT_SPECIAL_4_OPCODE_Y0 = 2, | ||
1380 | SLT_SPECIAL_4_OPCODE_Y1 = 2, | ||
1381 | SLT_U_SPECIAL_0_OPCODE_X0 = 84, | ||
1382 | SLT_U_SPECIAL_0_OPCODE_X1 = 54, | ||
1383 | SLT_U_SPECIAL_4_OPCODE_Y0 = 3, | ||
1384 | SLT_U_SPECIAL_4_OPCODE_Y1 = 3, | ||
1385 | SNEB_SPECIAL_0_OPCODE_X0 = 85, | ||
1386 | SNEB_SPECIAL_0_OPCODE_X1 = 55, | ||
1387 | SNEH_SPECIAL_0_OPCODE_X0 = 86, | ||
1388 | SNEH_SPECIAL_0_OPCODE_X1 = 56, | ||
1389 | SNE_SPECIAL_0_OPCODE_X0 = 87, | ||
1390 | SNE_SPECIAL_0_OPCODE_X1 = 57, | ||
1391 | SNE_SPECIAL_5_OPCODE_Y0 = 3, | ||
1392 | SNE_SPECIAL_5_OPCODE_Y1 = 3, | ||
1393 | SPECIAL_0_OPCODE_X0 = 0, | ||
1394 | SPECIAL_0_OPCODE_X1 = 1, | ||
1395 | SPECIAL_0_OPCODE_Y0 = 1, | ||
1396 | SPECIAL_0_OPCODE_Y1 = 1, | ||
1397 | SPECIAL_1_OPCODE_Y0 = 2, | ||
1398 | SPECIAL_1_OPCODE_Y1 = 2, | ||
1399 | SPECIAL_2_OPCODE_Y0 = 3, | ||
1400 | SPECIAL_2_OPCODE_Y1 = 3, | ||
1401 | SPECIAL_3_OPCODE_Y0 = 4, | ||
1402 | SPECIAL_3_OPCODE_Y1 = 4, | ||
1403 | SPECIAL_4_OPCODE_Y0 = 5, | ||
1404 | SPECIAL_4_OPCODE_Y1 = 5, | ||
1405 | SPECIAL_5_OPCODE_Y0 = 6, | ||
1406 | SPECIAL_5_OPCODE_Y1 = 6, | ||
1407 | SPECIAL_6_OPCODE_Y0 = 7, | ||
1408 | SPECIAL_7_OPCODE_Y0 = 8, | ||
1409 | SRAB_SPECIAL_0_OPCODE_X0 = 88, | ||
1410 | SRAB_SPECIAL_0_OPCODE_X1 = 58, | ||
1411 | SRAH_SPECIAL_0_OPCODE_X0 = 89, | ||
1412 | SRAH_SPECIAL_0_OPCODE_X1 = 59, | ||
1413 | SRAIB_SHUN_0_OPCODE_X0 = 8, | ||
1414 | SRAIB_SHUN_0_OPCODE_X1 = 8, | ||
1415 | SRAIH_SHUN_0_OPCODE_X0 = 9, | ||
1416 | SRAIH_SHUN_0_OPCODE_X1 = 9, | ||
1417 | SRAI_SHUN_0_OPCODE_X0 = 10, | ||
1418 | SRAI_SHUN_0_OPCODE_X1 = 10, | ||
1419 | SRAI_SHUN_0_OPCODE_Y0 = 4, | ||
1420 | SRAI_SHUN_0_OPCODE_Y1 = 4, | ||
1421 | SRA_SPECIAL_0_OPCODE_X0 = 90, | ||
1422 | SRA_SPECIAL_0_OPCODE_X1 = 60, | ||
1423 | SRA_SPECIAL_3_OPCODE_Y0 = 3, | ||
1424 | SRA_SPECIAL_3_OPCODE_Y1 = 3, | ||
1425 | SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, | ||
1426 | SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, | ||
1427 | SUBB_SPECIAL_0_OPCODE_X0 = 91, | ||
1428 | SUBB_SPECIAL_0_OPCODE_X1 = 61, | ||
1429 | SUBHS_SPECIAL_0_OPCODE_X0 = 101, | ||
1430 | SUBHS_SPECIAL_0_OPCODE_X1 = 71, | ||
1431 | SUBH_SPECIAL_0_OPCODE_X0 = 92, | ||
1432 | SUBH_SPECIAL_0_OPCODE_X1 = 62, | ||
1433 | SUBS_SPECIAL_0_OPCODE_X0 = 97, | ||
1434 | SUBS_SPECIAL_0_OPCODE_X1 = 67, | ||
1435 | SUB_SPECIAL_0_OPCODE_X0 = 93, | ||
1436 | SUB_SPECIAL_0_OPCODE_X1 = 63, | ||
1437 | SUB_SPECIAL_0_OPCODE_Y0 = 3, | ||
1438 | SUB_SPECIAL_0_OPCODE_Y1 = 3, | ||
1439 | SWADD_IMM_0_OPCODE_X1 = 30, | ||
1440 | SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, | ||
1441 | SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, | ||
1442 | SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, | ||
1443 | SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, | ||
1444 | SW_OPCODE_Y2 = 7, | ||
1445 | SW_SPECIAL_0_OPCODE_X1 = 64, | ||
1446 | TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, | ||
1447 | TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, | ||
1448 | TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, | ||
1449 | TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, | ||
1450 | TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, | ||
1451 | TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, | ||
1452 | TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, | ||
1453 | TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, | ||
1454 | TNS_UN_0_SHUN_0_OPCODE_X1 = 22, | ||
1455 | UN_0_SHUN_0_OPCODE_X0 = 11, | ||
1456 | UN_0_SHUN_0_OPCODE_X1 = 11, | ||
1457 | UN_0_SHUN_0_OPCODE_Y0 = 5, | ||
1458 | UN_0_SHUN_0_OPCODE_Y1 = 5, | ||
1459 | WH64_UN_0_SHUN_0_OPCODE_X1 = 23, | ||
1460 | XORI_IMM_0_OPCODE_X0 = 2, | ||
1461 | XORI_IMM_0_OPCODE_X1 = 21, | ||
1462 | XOR_SPECIAL_0_OPCODE_X0 = 94, | ||
1463 | XOR_SPECIAL_0_OPCODE_X1 = 65, | ||
1464 | XOR_SPECIAL_2_OPCODE_Y0 = 3, | ||
1465 | XOR_SPECIAL_2_OPCODE_Y1 = 3 | ||
1466 | }; | ||
1467 | |||
1468 | |||
1469 | #endif /* __ASSEMBLER__ */ | ||
1470 | |||
1471 | #endif /* __ARCH_OPCODE_H__ */ | ||
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h deleted file mode 100644 index 03df7b1e77bf..000000000000 --- a/arch/tile/include/asm/opcode-tile_32.h +++ /dev/null | |||
@@ -1,1513 +0,0 @@ | |||
1 | /* tile.h -- Header file for TILE opcode table | ||
2 | Copyright (C) 2005 Free Software Foundation, Inc. | ||
3 | Contributed by Tilera Corp. */ | ||
4 | |||
5 | #ifndef opcode_tile_h | ||
6 | #define opcode_tile_h | ||
7 | |||
8 | typedef unsigned long long tile_bundle_bits; | ||
9 | |||
10 | |||
11 | enum | ||
12 | { | ||
13 | TILE_MAX_OPERANDS = 5 /* mm */ | ||
14 | }; | ||
15 | |||
16 | typedef enum | ||
17 | { | ||
18 | TILE_OPC_BPT, | ||
19 | TILE_OPC_INFO, | ||
20 | TILE_OPC_INFOL, | ||
21 | TILE_OPC_J, | ||
22 | TILE_OPC_JAL, | ||
23 | TILE_OPC_MOVE, | ||
24 | TILE_OPC_MOVE_SN, | ||
25 | TILE_OPC_MOVEI, | ||
26 | TILE_OPC_MOVEI_SN, | ||
27 | TILE_OPC_MOVELI, | ||
28 | TILE_OPC_MOVELI_SN, | ||
29 | TILE_OPC_MOVELIS, | ||
30 | TILE_OPC_PREFETCH, | ||
31 | TILE_OPC_RAISE, | ||
32 | TILE_OPC_ADD, | ||
33 | TILE_OPC_ADD_SN, | ||
34 | TILE_OPC_ADDB, | ||
35 | TILE_OPC_ADDB_SN, | ||
36 | TILE_OPC_ADDBS_U, | ||
37 | TILE_OPC_ADDBS_U_SN, | ||
38 | TILE_OPC_ADDH, | ||
39 | TILE_OPC_ADDH_SN, | ||
40 | TILE_OPC_ADDHS, | ||
41 | TILE_OPC_ADDHS_SN, | ||
42 | TILE_OPC_ADDI, | ||
43 | TILE_OPC_ADDI_SN, | ||
44 | TILE_OPC_ADDIB, | ||
45 | TILE_OPC_ADDIB_SN, | ||
46 | TILE_OPC_ADDIH, | ||
47 | TILE_OPC_ADDIH_SN, | ||
48 | TILE_OPC_ADDLI, | ||
49 | TILE_OPC_ADDLI_SN, | ||
50 | TILE_OPC_ADDLIS, | ||
51 | TILE_OPC_ADDS, | ||
52 | TILE_OPC_ADDS_SN, | ||
53 | TILE_OPC_ADIFFB_U, | ||
54 | TILE_OPC_ADIFFB_U_SN, | ||
55 | TILE_OPC_ADIFFH, | ||
56 | TILE_OPC_ADIFFH_SN, | ||
57 | TILE_OPC_AND, | ||
58 | TILE_OPC_AND_SN, | ||
59 | TILE_OPC_ANDI, | ||
60 | TILE_OPC_ANDI_SN, | ||
61 | TILE_OPC_AULI, | ||
62 | TILE_OPC_AVGB_U, | ||
63 | TILE_OPC_AVGB_U_SN, | ||
64 | TILE_OPC_AVGH, | ||
65 | TILE_OPC_AVGH_SN, | ||
66 | TILE_OPC_BBNS, | ||
67 | TILE_OPC_BBNS_SN, | ||
68 | TILE_OPC_BBNST, | ||
69 | TILE_OPC_BBNST_SN, | ||
70 | TILE_OPC_BBS, | ||
71 | TILE_OPC_BBS_SN, | ||
72 | TILE_OPC_BBST, | ||
73 | TILE_OPC_BBST_SN, | ||
74 | TILE_OPC_BGEZ, | ||
75 | TILE_OPC_BGEZ_SN, | ||
76 | TILE_OPC_BGEZT, | ||
77 | TILE_OPC_BGEZT_SN, | ||
78 | TILE_OPC_BGZ, | ||
79 | TILE_OPC_BGZ_SN, | ||
80 | TILE_OPC_BGZT, | ||
81 | TILE_OPC_BGZT_SN, | ||
82 | TILE_OPC_BITX, | ||
83 | TILE_OPC_BITX_SN, | ||
84 | TILE_OPC_BLEZ, | ||
85 | TILE_OPC_BLEZ_SN, | ||
86 | TILE_OPC_BLEZT, | ||
87 | TILE_OPC_BLEZT_SN, | ||
88 | TILE_OPC_BLZ, | ||
89 | TILE_OPC_BLZ_SN, | ||
90 | TILE_OPC_BLZT, | ||
91 | TILE_OPC_BLZT_SN, | ||
92 | TILE_OPC_BNZ, | ||
93 | TILE_OPC_BNZ_SN, | ||
94 | TILE_OPC_BNZT, | ||
95 | TILE_OPC_BNZT_SN, | ||
96 | TILE_OPC_BYTEX, | ||
97 | TILE_OPC_BYTEX_SN, | ||
98 | TILE_OPC_BZ, | ||
99 | TILE_OPC_BZ_SN, | ||
100 | TILE_OPC_BZT, | ||
101 | TILE_OPC_BZT_SN, | ||
102 | TILE_OPC_CLZ, | ||
103 | TILE_OPC_CLZ_SN, | ||
104 | TILE_OPC_CRC32_32, | ||
105 | TILE_OPC_CRC32_32_SN, | ||
106 | TILE_OPC_CRC32_8, | ||
107 | TILE_OPC_CRC32_8_SN, | ||
108 | TILE_OPC_CTZ, | ||
109 | TILE_OPC_CTZ_SN, | ||
110 | TILE_OPC_DRAIN, | ||
111 | TILE_OPC_DTLBPR, | ||
112 | TILE_OPC_DWORD_ALIGN, | ||
113 | TILE_OPC_DWORD_ALIGN_SN, | ||
114 | TILE_OPC_FINV, | ||
115 | TILE_OPC_FLUSH, | ||
116 | TILE_OPC_FNOP, | ||
117 | TILE_OPC_ICOH, | ||
118 | TILE_OPC_ILL, | ||
119 | TILE_OPC_INTHB, | ||
120 | TILE_OPC_INTHB_SN, | ||
121 | TILE_OPC_INTHH, | ||
122 | TILE_OPC_INTHH_SN, | ||
123 | TILE_OPC_INTLB, | ||
124 | TILE_OPC_INTLB_SN, | ||
125 | TILE_OPC_INTLH, | ||
126 | TILE_OPC_INTLH_SN, | ||
127 | TILE_OPC_INV, | ||
128 | TILE_OPC_IRET, | ||
129 | TILE_OPC_JALB, | ||
130 | TILE_OPC_JALF, | ||
131 | TILE_OPC_JALR, | ||
132 | TILE_OPC_JALRP, | ||
133 | TILE_OPC_JB, | ||
134 | TILE_OPC_JF, | ||
135 | TILE_OPC_JR, | ||
136 | TILE_OPC_JRP, | ||
137 | TILE_OPC_LB, | ||
138 | TILE_OPC_LB_SN, | ||
139 | TILE_OPC_LB_U, | ||
140 | TILE_OPC_LB_U_SN, | ||
141 | TILE_OPC_LBADD, | ||
142 | TILE_OPC_LBADD_SN, | ||
143 | TILE_OPC_LBADD_U, | ||
144 | TILE_OPC_LBADD_U_SN, | ||
145 | TILE_OPC_LH, | ||
146 | TILE_OPC_LH_SN, | ||
147 | TILE_OPC_LH_U, | ||
148 | TILE_OPC_LH_U_SN, | ||
149 | TILE_OPC_LHADD, | ||
150 | TILE_OPC_LHADD_SN, | ||
151 | TILE_OPC_LHADD_U, | ||
152 | TILE_OPC_LHADD_U_SN, | ||
153 | TILE_OPC_LNK, | ||
154 | TILE_OPC_LNK_SN, | ||
155 | TILE_OPC_LW, | ||
156 | TILE_OPC_LW_SN, | ||
157 | TILE_OPC_LW_NA, | ||
158 | TILE_OPC_LW_NA_SN, | ||
159 | TILE_OPC_LWADD, | ||
160 | TILE_OPC_LWADD_SN, | ||
161 | TILE_OPC_LWADD_NA, | ||
162 | TILE_OPC_LWADD_NA_SN, | ||
163 | TILE_OPC_MAXB_U, | ||
164 | TILE_OPC_MAXB_U_SN, | ||
165 | TILE_OPC_MAXH, | ||
166 | TILE_OPC_MAXH_SN, | ||
167 | TILE_OPC_MAXIB_U, | ||
168 | TILE_OPC_MAXIB_U_SN, | ||
169 | TILE_OPC_MAXIH, | ||
170 | TILE_OPC_MAXIH_SN, | ||
171 | TILE_OPC_MF, | ||
172 | TILE_OPC_MFSPR, | ||
173 | TILE_OPC_MINB_U, | ||
174 | TILE_OPC_MINB_U_SN, | ||
175 | TILE_OPC_MINH, | ||
176 | TILE_OPC_MINH_SN, | ||
177 | TILE_OPC_MINIB_U, | ||
178 | TILE_OPC_MINIB_U_SN, | ||
179 | TILE_OPC_MINIH, | ||
180 | TILE_OPC_MINIH_SN, | ||
181 | TILE_OPC_MM, | ||
182 | TILE_OPC_MNZ, | ||
183 | TILE_OPC_MNZ_SN, | ||
184 | TILE_OPC_MNZB, | ||
185 | TILE_OPC_MNZB_SN, | ||
186 | TILE_OPC_MNZH, | ||
187 | TILE_OPC_MNZH_SN, | ||
188 | TILE_OPC_MTSPR, | ||
189 | TILE_OPC_MULHH_SS, | ||
190 | TILE_OPC_MULHH_SS_SN, | ||
191 | TILE_OPC_MULHH_SU, | ||
192 | TILE_OPC_MULHH_SU_SN, | ||
193 | TILE_OPC_MULHH_UU, | ||
194 | TILE_OPC_MULHH_UU_SN, | ||
195 | TILE_OPC_MULHHA_SS, | ||
196 | TILE_OPC_MULHHA_SS_SN, | ||
197 | TILE_OPC_MULHHA_SU, | ||
198 | TILE_OPC_MULHHA_SU_SN, | ||
199 | TILE_OPC_MULHHA_UU, | ||
200 | TILE_OPC_MULHHA_UU_SN, | ||
201 | TILE_OPC_MULHHSA_UU, | ||
202 | TILE_OPC_MULHHSA_UU_SN, | ||
203 | TILE_OPC_MULHL_SS, | ||
204 | TILE_OPC_MULHL_SS_SN, | ||
205 | TILE_OPC_MULHL_SU, | ||
206 | TILE_OPC_MULHL_SU_SN, | ||
207 | TILE_OPC_MULHL_US, | ||
208 | TILE_OPC_MULHL_US_SN, | ||
209 | TILE_OPC_MULHL_UU, | ||
210 | TILE_OPC_MULHL_UU_SN, | ||
211 | TILE_OPC_MULHLA_SS, | ||
212 | TILE_OPC_MULHLA_SS_SN, | ||
213 | TILE_OPC_MULHLA_SU, | ||
214 | TILE_OPC_MULHLA_SU_SN, | ||
215 | TILE_OPC_MULHLA_US, | ||
216 | TILE_OPC_MULHLA_US_SN, | ||
217 | TILE_OPC_MULHLA_UU, | ||
218 | TILE_OPC_MULHLA_UU_SN, | ||
219 | TILE_OPC_MULHLSA_UU, | ||
220 | TILE_OPC_MULHLSA_UU_SN, | ||
221 | TILE_OPC_MULLL_SS, | ||
222 | TILE_OPC_MULLL_SS_SN, | ||
223 | TILE_OPC_MULLL_SU, | ||
224 | TILE_OPC_MULLL_SU_SN, | ||
225 | TILE_OPC_MULLL_UU, | ||
226 | TILE_OPC_MULLL_UU_SN, | ||
227 | TILE_OPC_MULLLA_SS, | ||
228 | TILE_OPC_MULLLA_SS_SN, | ||
229 | TILE_OPC_MULLLA_SU, | ||
230 | TILE_OPC_MULLLA_SU_SN, | ||
231 | TILE_OPC_MULLLA_UU, | ||
232 | TILE_OPC_MULLLA_UU_SN, | ||
233 | TILE_OPC_MULLLSA_UU, | ||
234 | TILE_OPC_MULLLSA_UU_SN, | ||
235 | TILE_OPC_MVNZ, | ||
236 | TILE_OPC_MVNZ_SN, | ||
237 | TILE_OPC_MVZ, | ||
238 | TILE_OPC_MVZ_SN, | ||
239 | TILE_OPC_MZ, | ||
240 | TILE_OPC_MZ_SN, | ||
241 | TILE_OPC_MZB, | ||
242 | TILE_OPC_MZB_SN, | ||
243 | TILE_OPC_MZH, | ||
244 | TILE_OPC_MZH_SN, | ||
245 | TILE_OPC_NAP, | ||
246 | TILE_OPC_NOP, | ||
247 | TILE_OPC_NOR, | ||
248 | TILE_OPC_NOR_SN, | ||
249 | TILE_OPC_OR, | ||
250 | TILE_OPC_OR_SN, | ||
251 | TILE_OPC_ORI, | ||
252 | TILE_OPC_ORI_SN, | ||
253 | TILE_OPC_PACKBS_U, | ||
254 | TILE_OPC_PACKBS_U_SN, | ||
255 | TILE_OPC_PACKHB, | ||
256 | TILE_OPC_PACKHB_SN, | ||
257 | TILE_OPC_PACKHS, | ||
258 | TILE_OPC_PACKHS_SN, | ||
259 | TILE_OPC_PACKLB, | ||
260 | TILE_OPC_PACKLB_SN, | ||
261 | TILE_OPC_PCNT, | ||
262 | TILE_OPC_PCNT_SN, | ||
263 | TILE_OPC_RL, | ||
264 | TILE_OPC_RL_SN, | ||
265 | TILE_OPC_RLI, | ||
266 | TILE_OPC_RLI_SN, | ||
267 | TILE_OPC_S1A, | ||
268 | TILE_OPC_S1A_SN, | ||
269 | TILE_OPC_S2A, | ||
270 | TILE_OPC_S2A_SN, | ||
271 | TILE_OPC_S3A, | ||
272 | TILE_OPC_S3A_SN, | ||
273 | TILE_OPC_SADAB_U, | ||
274 | TILE_OPC_SADAB_U_SN, | ||
275 | TILE_OPC_SADAH, | ||
276 | TILE_OPC_SADAH_SN, | ||
277 | TILE_OPC_SADAH_U, | ||
278 | TILE_OPC_SADAH_U_SN, | ||
279 | TILE_OPC_SADB_U, | ||
280 | TILE_OPC_SADB_U_SN, | ||
281 | TILE_OPC_SADH, | ||
282 | TILE_OPC_SADH_SN, | ||
283 | TILE_OPC_SADH_U, | ||
284 | TILE_OPC_SADH_U_SN, | ||
285 | TILE_OPC_SB, | ||
286 | TILE_OPC_SBADD, | ||
287 | TILE_OPC_SEQ, | ||
288 | TILE_OPC_SEQ_SN, | ||
289 | TILE_OPC_SEQB, | ||
290 | TILE_OPC_SEQB_SN, | ||
291 | TILE_OPC_SEQH, | ||
292 | TILE_OPC_SEQH_SN, | ||
293 | TILE_OPC_SEQI, | ||
294 | TILE_OPC_SEQI_SN, | ||
295 | TILE_OPC_SEQIB, | ||
296 | TILE_OPC_SEQIB_SN, | ||
297 | TILE_OPC_SEQIH, | ||
298 | TILE_OPC_SEQIH_SN, | ||
299 | TILE_OPC_SH, | ||
300 | TILE_OPC_SHADD, | ||
301 | TILE_OPC_SHL, | ||
302 | TILE_OPC_SHL_SN, | ||
303 | TILE_OPC_SHLB, | ||
304 | TILE_OPC_SHLB_SN, | ||
305 | TILE_OPC_SHLH, | ||
306 | TILE_OPC_SHLH_SN, | ||
307 | TILE_OPC_SHLI, | ||
308 | TILE_OPC_SHLI_SN, | ||
309 | TILE_OPC_SHLIB, | ||
310 | TILE_OPC_SHLIB_SN, | ||
311 | TILE_OPC_SHLIH, | ||
312 | TILE_OPC_SHLIH_SN, | ||
313 | TILE_OPC_SHR, | ||
314 | TILE_OPC_SHR_SN, | ||
315 | TILE_OPC_SHRB, | ||
316 | TILE_OPC_SHRB_SN, | ||
317 | TILE_OPC_SHRH, | ||
318 | TILE_OPC_SHRH_SN, | ||
319 | TILE_OPC_SHRI, | ||
320 | TILE_OPC_SHRI_SN, | ||
321 | TILE_OPC_SHRIB, | ||
322 | TILE_OPC_SHRIB_SN, | ||
323 | TILE_OPC_SHRIH, | ||
324 | TILE_OPC_SHRIH_SN, | ||
325 | TILE_OPC_SLT, | ||
326 | TILE_OPC_SLT_SN, | ||
327 | TILE_OPC_SLT_U, | ||
328 | TILE_OPC_SLT_U_SN, | ||
329 | TILE_OPC_SLTB, | ||
330 | TILE_OPC_SLTB_SN, | ||
331 | TILE_OPC_SLTB_U, | ||
332 | TILE_OPC_SLTB_U_SN, | ||
333 | TILE_OPC_SLTE, | ||
334 | TILE_OPC_SLTE_SN, | ||
335 | TILE_OPC_SLTE_U, | ||
336 | TILE_OPC_SLTE_U_SN, | ||
337 | TILE_OPC_SLTEB, | ||
338 | TILE_OPC_SLTEB_SN, | ||
339 | TILE_OPC_SLTEB_U, | ||
340 | TILE_OPC_SLTEB_U_SN, | ||
341 | TILE_OPC_SLTEH, | ||
342 | TILE_OPC_SLTEH_SN, | ||
343 | TILE_OPC_SLTEH_U, | ||
344 | TILE_OPC_SLTEH_U_SN, | ||
345 | TILE_OPC_SLTH, | ||
346 | TILE_OPC_SLTH_SN, | ||
347 | TILE_OPC_SLTH_U, | ||
348 | TILE_OPC_SLTH_U_SN, | ||
349 | TILE_OPC_SLTI, | ||
350 | TILE_OPC_SLTI_SN, | ||
351 | TILE_OPC_SLTI_U, | ||
352 | TILE_OPC_SLTI_U_SN, | ||
353 | TILE_OPC_SLTIB, | ||
354 | TILE_OPC_SLTIB_SN, | ||
355 | TILE_OPC_SLTIB_U, | ||
356 | TILE_OPC_SLTIB_U_SN, | ||
357 | TILE_OPC_SLTIH, | ||
358 | TILE_OPC_SLTIH_SN, | ||
359 | TILE_OPC_SLTIH_U, | ||
360 | TILE_OPC_SLTIH_U_SN, | ||
361 | TILE_OPC_SNE, | ||
362 | TILE_OPC_SNE_SN, | ||
363 | TILE_OPC_SNEB, | ||
364 | TILE_OPC_SNEB_SN, | ||
365 | TILE_OPC_SNEH, | ||
366 | TILE_OPC_SNEH_SN, | ||
367 | TILE_OPC_SRA, | ||
368 | TILE_OPC_SRA_SN, | ||
369 | TILE_OPC_SRAB, | ||
370 | TILE_OPC_SRAB_SN, | ||
371 | TILE_OPC_SRAH, | ||
372 | TILE_OPC_SRAH_SN, | ||
373 | TILE_OPC_SRAI, | ||
374 | TILE_OPC_SRAI_SN, | ||
375 | TILE_OPC_SRAIB, | ||
376 | TILE_OPC_SRAIB_SN, | ||
377 | TILE_OPC_SRAIH, | ||
378 | TILE_OPC_SRAIH_SN, | ||
379 | TILE_OPC_SUB, | ||
380 | TILE_OPC_SUB_SN, | ||
381 | TILE_OPC_SUBB, | ||
382 | TILE_OPC_SUBB_SN, | ||
383 | TILE_OPC_SUBBS_U, | ||
384 | TILE_OPC_SUBBS_U_SN, | ||
385 | TILE_OPC_SUBH, | ||
386 | TILE_OPC_SUBH_SN, | ||
387 | TILE_OPC_SUBHS, | ||
388 | TILE_OPC_SUBHS_SN, | ||
389 | TILE_OPC_SUBS, | ||
390 | TILE_OPC_SUBS_SN, | ||
391 | TILE_OPC_SW, | ||
392 | TILE_OPC_SWADD, | ||
393 | TILE_OPC_SWINT0, | ||
394 | TILE_OPC_SWINT1, | ||
395 | TILE_OPC_SWINT2, | ||
396 | TILE_OPC_SWINT3, | ||
397 | TILE_OPC_TBLIDXB0, | ||
398 | TILE_OPC_TBLIDXB0_SN, | ||
399 | TILE_OPC_TBLIDXB1, | ||
400 | TILE_OPC_TBLIDXB1_SN, | ||
401 | TILE_OPC_TBLIDXB2, | ||
402 | TILE_OPC_TBLIDXB2_SN, | ||
403 | TILE_OPC_TBLIDXB3, | ||
404 | TILE_OPC_TBLIDXB3_SN, | ||
405 | TILE_OPC_TNS, | ||
406 | TILE_OPC_TNS_SN, | ||
407 | TILE_OPC_WH64, | ||
408 | TILE_OPC_XOR, | ||
409 | TILE_OPC_XOR_SN, | ||
410 | TILE_OPC_XORI, | ||
411 | TILE_OPC_XORI_SN, | ||
412 | TILE_OPC_NONE | ||
413 | } tile_mnemonic; | ||
414 | |||
415 | /* 64-bit pattern for a { bpt ; nop } bundle. */ | ||
416 | #define TILE_BPT_BUNDLE 0x400b3cae70166000ULL | ||
417 | |||
418 | |||
419 | #define TILE_ELF_MACHINE_CODE EM_TILEPRO | ||
420 | |||
421 | #define TILE_ELF_NAME "elf32-tilepro" | ||
422 | |||
423 | |||
424 | static __inline unsigned int | ||
425 | get_BrOff_SN(tile_bundle_bits num) | ||
426 | { | ||
427 | const unsigned int n = (unsigned int)num; | ||
428 | return (((n >> 0)) & 0x3ff); | ||
429 | } | ||
430 | |||
431 | static __inline unsigned int | ||
432 | get_BrOff_X1(tile_bundle_bits n) | ||
433 | { | ||
434 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
435 | (((unsigned int)(n >> 20)) & 0x00018000); | ||
436 | } | ||
437 | |||
438 | static __inline unsigned int | ||
439 | get_BrType_X1(tile_bundle_bits n) | ||
440 | { | ||
441 | return (((unsigned int)(n >> 31)) & 0xf); | ||
442 | } | ||
443 | |||
444 | static __inline unsigned int | ||
445 | get_Dest_Imm8_X1(tile_bundle_bits n) | ||
446 | { | ||
447 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
448 | (((unsigned int)(n >> 43)) & 0x000000c0); | ||
449 | } | ||
450 | |||
451 | static __inline unsigned int | ||
452 | get_Dest_SN(tile_bundle_bits num) | ||
453 | { | ||
454 | const unsigned int n = (unsigned int)num; | ||
455 | return (((n >> 2)) & 0x3); | ||
456 | } | ||
457 | |||
458 | static __inline unsigned int | ||
459 | get_Dest_X0(tile_bundle_bits num) | ||
460 | { | ||
461 | const unsigned int n = (unsigned int)num; | ||
462 | return (((n >> 0)) & 0x3f); | ||
463 | } | ||
464 | |||
465 | static __inline unsigned int | ||
466 | get_Dest_X1(tile_bundle_bits n) | ||
467 | { | ||
468 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
469 | } | ||
470 | |||
471 | static __inline unsigned int | ||
472 | get_Dest_Y0(tile_bundle_bits num) | ||
473 | { | ||
474 | const unsigned int n = (unsigned int)num; | ||
475 | return (((n >> 0)) & 0x3f); | ||
476 | } | ||
477 | |||
478 | static __inline unsigned int | ||
479 | get_Dest_Y1(tile_bundle_bits n) | ||
480 | { | ||
481 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
482 | } | ||
483 | |||
484 | static __inline unsigned int | ||
485 | get_Imm16_X0(tile_bundle_bits num) | ||
486 | { | ||
487 | const unsigned int n = (unsigned int)num; | ||
488 | return (((n >> 12)) & 0xffff); | ||
489 | } | ||
490 | |||
491 | static __inline unsigned int | ||
492 | get_Imm16_X1(tile_bundle_bits n) | ||
493 | { | ||
494 | return (((unsigned int)(n >> 43)) & 0xffff); | ||
495 | } | ||
496 | |||
497 | static __inline unsigned int | ||
498 | get_Imm8_SN(tile_bundle_bits num) | ||
499 | { | ||
500 | const unsigned int n = (unsigned int)num; | ||
501 | return (((n >> 0)) & 0xff); | ||
502 | } | ||
503 | |||
504 | static __inline unsigned int | ||
505 | get_Imm8_X0(tile_bundle_bits num) | ||
506 | { | ||
507 | const unsigned int n = (unsigned int)num; | ||
508 | return (((n >> 12)) & 0xff); | ||
509 | } | ||
510 | |||
511 | static __inline unsigned int | ||
512 | get_Imm8_X1(tile_bundle_bits n) | ||
513 | { | ||
514 | return (((unsigned int)(n >> 43)) & 0xff); | ||
515 | } | ||
516 | |||
517 | static __inline unsigned int | ||
518 | get_Imm8_Y0(tile_bundle_bits num) | ||
519 | { | ||
520 | const unsigned int n = (unsigned int)num; | ||
521 | return (((n >> 12)) & 0xff); | ||
522 | } | ||
523 | |||
524 | static __inline unsigned int | ||
525 | get_Imm8_Y1(tile_bundle_bits n) | ||
526 | { | ||
527 | return (((unsigned int)(n >> 43)) & 0xff); | ||
528 | } | ||
529 | |||
530 | static __inline unsigned int | ||
531 | get_ImmOpcodeExtension_X0(tile_bundle_bits num) | ||
532 | { | ||
533 | const unsigned int n = (unsigned int)num; | ||
534 | return (((n >> 20)) & 0x7f); | ||
535 | } | ||
536 | |||
537 | static __inline unsigned int | ||
538 | get_ImmOpcodeExtension_X1(tile_bundle_bits n) | ||
539 | { | ||
540 | return (((unsigned int)(n >> 51)) & 0x7f); | ||
541 | } | ||
542 | |||
543 | static __inline unsigned int | ||
544 | get_ImmRROpcodeExtension_SN(tile_bundle_bits num) | ||
545 | { | ||
546 | const unsigned int n = (unsigned int)num; | ||
547 | return (((n >> 8)) & 0x3); | ||
548 | } | ||
549 | |||
550 | static __inline unsigned int | ||
551 | get_JOffLong_X1(tile_bundle_bits n) | ||
552 | { | ||
553 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
554 | (((unsigned int)(n >> 20)) & 0x00018000) | | ||
555 | (((unsigned int)(n >> 14)) & 0x001e0000) | | ||
556 | (((unsigned int)(n >> 16)) & 0x07e00000) | | ||
557 | (((unsigned int)(n >> 31)) & 0x18000000); | ||
558 | } | ||
559 | |||
560 | static __inline unsigned int | ||
561 | get_JOff_X1(tile_bundle_bits n) | ||
562 | { | ||
563 | return (((unsigned int)(n >> 43)) & 0x00007fff) | | ||
564 | (((unsigned int)(n >> 20)) & 0x00018000) | | ||
565 | (((unsigned int)(n >> 14)) & 0x001e0000) | | ||
566 | (((unsigned int)(n >> 16)) & 0x07e00000) | | ||
567 | (((unsigned int)(n >> 31)) & 0x08000000); | ||
568 | } | ||
569 | |||
570 | static __inline unsigned int | ||
571 | get_MF_Imm15_X1(tile_bundle_bits n) | ||
572 | { | ||
573 | return (((unsigned int)(n >> 37)) & 0x00003fff) | | ||
574 | (((unsigned int)(n >> 44)) & 0x00004000); | ||
575 | } | ||
576 | |||
577 | static __inline unsigned int | ||
578 | get_MMEnd_X0(tile_bundle_bits num) | ||
579 | { | ||
580 | const unsigned int n = (unsigned int)num; | ||
581 | return (((n >> 18)) & 0x1f); | ||
582 | } | ||
583 | |||
584 | static __inline unsigned int | ||
585 | get_MMEnd_X1(tile_bundle_bits n) | ||
586 | { | ||
587 | return (((unsigned int)(n >> 49)) & 0x1f); | ||
588 | } | ||
589 | |||
590 | static __inline unsigned int | ||
591 | get_MMStart_X0(tile_bundle_bits num) | ||
592 | { | ||
593 | const unsigned int n = (unsigned int)num; | ||
594 | return (((n >> 23)) & 0x1f); | ||
595 | } | ||
596 | |||
597 | static __inline unsigned int | ||
598 | get_MMStart_X1(tile_bundle_bits n) | ||
599 | { | ||
600 | return (((unsigned int)(n >> 54)) & 0x1f); | ||
601 | } | ||
602 | |||
603 | static __inline unsigned int | ||
604 | get_MT_Imm15_X1(tile_bundle_bits n) | ||
605 | { | ||
606 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
607 | (((unsigned int)(n >> 37)) & 0x00003fc0) | | ||
608 | (((unsigned int)(n >> 44)) & 0x00004000); | ||
609 | } | ||
610 | |||
611 | static __inline unsigned int | ||
612 | get_Mode(tile_bundle_bits n) | ||
613 | { | ||
614 | return (((unsigned int)(n >> 63)) & 0x1); | ||
615 | } | ||
616 | |||
617 | static __inline unsigned int | ||
618 | get_NoRegOpcodeExtension_SN(tile_bundle_bits num) | ||
619 | { | ||
620 | const unsigned int n = (unsigned int)num; | ||
621 | return (((n >> 0)) & 0xf); | ||
622 | } | ||
623 | |||
624 | static __inline unsigned int | ||
625 | get_Opcode_SN(tile_bundle_bits num) | ||
626 | { | ||
627 | const unsigned int n = (unsigned int)num; | ||
628 | return (((n >> 10)) & 0x3f); | ||
629 | } | ||
630 | |||
631 | static __inline unsigned int | ||
632 | get_Opcode_X0(tile_bundle_bits num) | ||
633 | { | ||
634 | const unsigned int n = (unsigned int)num; | ||
635 | return (((n >> 28)) & 0x7); | ||
636 | } | ||
637 | |||
638 | static __inline unsigned int | ||
639 | get_Opcode_X1(tile_bundle_bits n) | ||
640 | { | ||
641 | return (((unsigned int)(n >> 59)) & 0xf); | ||
642 | } | ||
643 | |||
644 | static __inline unsigned int | ||
645 | get_Opcode_Y0(tile_bundle_bits num) | ||
646 | { | ||
647 | const unsigned int n = (unsigned int)num; | ||
648 | return (((n >> 27)) & 0xf); | ||
649 | } | ||
650 | |||
651 | static __inline unsigned int | ||
652 | get_Opcode_Y1(tile_bundle_bits n) | ||
653 | { | ||
654 | return (((unsigned int)(n >> 59)) & 0xf); | ||
655 | } | ||
656 | |||
657 | static __inline unsigned int | ||
658 | get_Opcode_Y2(tile_bundle_bits n) | ||
659 | { | ||
660 | return (((unsigned int)(n >> 56)) & 0x7); | ||
661 | } | ||
662 | |||
663 | static __inline unsigned int | ||
664 | get_RROpcodeExtension_SN(tile_bundle_bits num) | ||
665 | { | ||
666 | const unsigned int n = (unsigned int)num; | ||
667 | return (((n >> 4)) & 0xf); | ||
668 | } | ||
669 | |||
670 | static __inline unsigned int | ||
671 | get_RRROpcodeExtension_X0(tile_bundle_bits num) | ||
672 | { | ||
673 | const unsigned int n = (unsigned int)num; | ||
674 | return (((n >> 18)) & 0x1ff); | ||
675 | } | ||
676 | |||
677 | static __inline unsigned int | ||
678 | get_RRROpcodeExtension_X1(tile_bundle_bits n) | ||
679 | { | ||
680 | return (((unsigned int)(n >> 49)) & 0x1ff); | ||
681 | } | ||
682 | |||
683 | static __inline unsigned int | ||
684 | get_RRROpcodeExtension_Y0(tile_bundle_bits num) | ||
685 | { | ||
686 | const unsigned int n = (unsigned int)num; | ||
687 | return (((n >> 18)) & 0x3); | ||
688 | } | ||
689 | |||
690 | static __inline unsigned int | ||
691 | get_RRROpcodeExtension_Y1(tile_bundle_bits n) | ||
692 | { | ||
693 | return (((unsigned int)(n >> 49)) & 0x3); | ||
694 | } | ||
695 | |||
696 | static __inline unsigned int | ||
697 | get_RouteOpcodeExtension_SN(tile_bundle_bits num) | ||
698 | { | ||
699 | const unsigned int n = (unsigned int)num; | ||
700 | return (((n >> 0)) & 0x3ff); | ||
701 | } | ||
702 | |||
703 | static __inline unsigned int | ||
704 | get_S_X0(tile_bundle_bits num) | ||
705 | { | ||
706 | const unsigned int n = (unsigned int)num; | ||
707 | return (((n >> 27)) & 0x1); | ||
708 | } | ||
709 | |||
710 | static __inline unsigned int | ||
711 | get_S_X1(tile_bundle_bits n) | ||
712 | { | ||
713 | return (((unsigned int)(n >> 58)) & 0x1); | ||
714 | } | ||
715 | |||
716 | static __inline unsigned int | ||
717 | get_ShAmt_X0(tile_bundle_bits num) | ||
718 | { | ||
719 | const unsigned int n = (unsigned int)num; | ||
720 | return (((n >> 12)) & 0x1f); | ||
721 | } | ||
722 | |||
723 | static __inline unsigned int | ||
724 | get_ShAmt_X1(tile_bundle_bits n) | ||
725 | { | ||
726 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
727 | } | ||
728 | |||
729 | static __inline unsigned int | ||
730 | get_ShAmt_Y0(tile_bundle_bits num) | ||
731 | { | ||
732 | const unsigned int n = (unsigned int)num; | ||
733 | return (((n >> 12)) & 0x1f); | ||
734 | } | ||
735 | |||
736 | static __inline unsigned int | ||
737 | get_ShAmt_Y1(tile_bundle_bits n) | ||
738 | { | ||
739 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
740 | } | ||
741 | |||
742 | static __inline unsigned int | ||
743 | get_SrcA_X0(tile_bundle_bits num) | ||
744 | { | ||
745 | const unsigned int n = (unsigned int)num; | ||
746 | return (((n >> 6)) & 0x3f); | ||
747 | } | ||
748 | |||
749 | static __inline unsigned int | ||
750 | get_SrcA_X1(tile_bundle_bits n) | ||
751 | { | ||
752 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
753 | } | ||
754 | |||
755 | static __inline unsigned int | ||
756 | get_SrcA_Y0(tile_bundle_bits num) | ||
757 | { | ||
758 | const unsigned int n = (unsigned int)num; | ||
759 | return (((n >> 6)) & 0x3f); | ||
760 | } | ||
761 | |||
762 | static __inline unsigned int | ||
763 | get_SrcA_Y1(tile_bundle_bits n) | ||
764 | { | ||
765 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
766 | } | ||
767 | |||
768 | static __inline unsigned int | ||
769 | get_SrcA_Y2(tile_bundle_bits n) | ||
770 | { | ||
771 | return (((n >> 26)) & 0x00000001) | | ||
772 | (((unsigned int)(n >> 50)) & 0x0000003e); | ||
773 | } | ||
774 | |||
775 | static __inline unsigned int | ||
776 | get_SrcBDest_Y2(tile_bundle_bits num) | ||
777 | { | ||
778 | const unsigned int n = (unsigned int)num; | ||
779 | return (((n >> 20)) & 0x3f); | ||
780 | } | ||
781 | |||
782 | static __inline unsigned int | ||
783 | get_SrcB_X0(tile_bundle_bits num) | ||
784 | { | ||
785 | const unsigned int n = (unsigned int)num; | ||
786 | return (((n >> 12)) & 0x3f); | ||
787 | } | ||
788 | |||
789 | static __inline unsigned int | ||
790 | get_SrcB_X1(tile_bundle_bits n) | ||
791 | { | ||
792 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
793 | } | ||
794 | |||
795 | static __inline unsigned int | ||
796 | get_SrcB_Y0(tile_bundle_bits num) | ||
797 | { | ||
798 | const unsigned int n = (unsigned int)num; | ||
799 | return (((n >> 12)) & 0x3f); | ||
800 | } | ||
801 | |||
802 | static __inline unsigned int | ||
803 | get_SrcB_Y1(tile_bundle_bits n) | ||
804 | { | ||
805 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
806 | } | ||
807 | |||
808 | static __inline unsigned int | ||
809 | get_Src_SN(tile_bundle_bits num) | ||
810 | { | ||
811 | const unsigned int n = (unsigned int)num; | ||
812 | return (((n >> 0)) & 0x3); | ||
813 | } | ||
814 | |||
815 | static __inline unsigned int | ||
816 | get_UnOpcodeExtension_X0(tile_bundle_bits num) | ||
817 | { | ||
818 | const unsigned int n = (unsigned int)num; | ||
819 | return (((n >> 12)) & 0x1f); | ||
820 | } | ||
821 | |||
822 | static __inline unsigned int | ||
823 | get_UnOpcodeExtension_X1(tile_bundle_bits n) | ||
824 | { | ||
825 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
826 | } | ||
827 | |||
828 | static __inline unsigned int | ||
829 | get_UnOpcodeExtension_Y0(tile_bundle_bits num) | ||
830 | { | ||
831 | const unsigned int n = (unsigned int)num; | ||
832 | return (((n >> 12)) & 0x1f); | ||
833 | } | ||
834 | |||
835 | static __inline unsigned int | ||
836 | get_UnOpcodeExtension_Y1(tile_bundle_bits n) | ||
837 | { | ||
838 | return (((unsigned int)(n >> 43)) & 0x1f); | ||
839 | } | ||
840 | |||
841 | static __inline unsigned int | ||
842 | get_UnShOpcodeExtension_X0(tile_bundle_bits num) | ||
843 | { | ||
844 | const unsigned int n = (unsigned int)num; | ||
845 | return (((n >> 17)) & 0x3ff); | ||
846 | } | ||
847 | |||
848 | static __inline unsigned int | ||
849 | get_UnShOpcodeExtension_X1(tile_bundle_bits n) | ||
850 | { | ||
851 | return (((unsigned int)(n >> 48)) & 0x3ff); | ||
852 | } | ||
853 | |||
854 | static __inline unsigned int | ||
855 | get_UnShOpcodeExtension_Y0(tile_bundle_bits num) | ||
856 | { | ||
857 | const unsigned int n = (unsigned int)num; | ||
858 | return (((n >> 17)) & 0x7); | ||
859 | } | ||
860 | |||
861 | static __inline unsigned int | ||
862 | get_UnShOpcodeExtension_Y1(tile_bundle_bits n) | ||
863 | { | ||
864 | return (((unsigned int)(n >> 48)) & 0x7); | ||
865 | } | ||
866 | |||
867 | |||
868 | static __inline int | ||
869 | sign_extend(int n, int num_bits) | ||
870 | { | ||
871 | int shift = (int)(sizeof(int) * 8 - num_bits); | ||
872 | return (n << shift) >> shift; | ||
873 | } | ||
874 | |||
875 | |||
876 | |||
877 | static __inline tile_bundle_bits | ||
878 | create_BrOff_SN(int num) | ||
879 | { | ||
880 | const unsigned int n = (unsigned int)num; | ||
881 | return ((n & 0x3ff) << 0); | ||
882 | } | ||
883 | |||
884 | static __inline tile_bundle_bits | ||
885 | create_BrOff_X1(int num) | ||
886 | { | ||
887 | const unsigned int n = (unsigned int)num; | ||
888 | return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | | ||
889 | (((tile_bundle_bits)(n & 0x00018000)) << 20); | ||
890 | } | ||
891 | |||
892 | static __inline tile_bundle_bits | ||
893 | create_BrType_X1(int num) | ||
894 | { | ||
895 | const unsigned int n = (unsigned int)num; | ||
896 | return (((tile_bundle_bits)(n & 0xf)) << 31); | ||
897 | } | ||
898 | |||
899 | static __inline tile_bundle_bits | ||
900 | create_Dest_Imm8_X1(int num) | ||
901 | { | ||
902 | const unsigned int n = (unsigned int)num; | ||
903 | return (((tile_bundle_bits)(n & 0x0000003f)) << 31) | | ||
904 | (((tile_bundle_bits)(n & 0x000000c0)) << 43); | ||
905 | } | ||
906 | |||
907 | static __inline tile_bundle_bits | ||
908 | create_Dest_SN(int num) | ||
909 | { | ||
910 | const unsigned int n = (unsigned int)num; | ||
911 | return ((n & 0x3) << 2); | ||
912 | } | ||
913 | |||
914 | static __inline tile_bundle_bits | ||
915 | create_Dest_X0(int num) | ||
916 | { | ||
917 | const unsigned int n = (unsigned int)num; | ||
918 | return ((n & 0x3f) << 0); | ||
919 | } | ||
920 | |||
921 | static __inline tile_bundle_bits | ||
922 | create_Dest_X1(int num) | ||
923 | { | ||
924 | const unsigned int n = (unsigned int)num; | ||
925 | return (((tile_bundle_bits)(n & 0x3f)) << 31); | ||
926 | } | ||
927 | |||
928 | static __inline tile_bundle_bits | ||
929 | create_Dest_Y0(int num) | ||
930 | { | ||
931 | const unsigned int n = (unsigned int)num; | ||
932 | return ((n & 0x3f) << 0); | ||
933 | } | ||
934 | |||
935 | static __inline tile_bundle_bits | ||
936 | create_Dest_Y1(int num) | ||
937 | { | ||
938 | const unsigned int n = (unsigned int)num; | ||
939 | return (((tile_bundle_bits)(n & 0x3f)) << 31); | ||
940 | } | ||
941 | |||
942 | static __inline tile_bundle_bits | ||
943 | create_Imm16_X0(int num) | ||
944 | { | ||
945 | const unsigned int n = (unsigned int)num; | ||
946 | return ((n & 0xffff) << 12); | ||
947 | } | ||
948 | |||
949 | static __inline tile_bundle_bits | ||
950 | create_Imm16_X1(int num) | ||
951 | { | ||
952 | const unsigned int n = (unsigned int)num; | ||
953 | return (((tile_bundle_bits)(n & 0xffff)) << 43); | ||
954 | } | ||
955 | |||
956 | static __inline tile_bundle_bits | ||
957 | create_Imm8_SN(int num) | ||
958 | { | ||
959 | const unsigned int n = (unsigned int)num; | ||
960 | return ((n & 0xff) << 0); | ||
961 | } | ||
962 | |||
963 | static __inline tile_bundle_bits | ||
964 | create_Imm8_X0(int num) | ||
965 | { | ||
966 | const unsigned int n = (unsigned int)num; | ||
967 | return ((n & 0xff) << 12); | ||
968 | } | ||
969 | |||
970 | static __inline tile_bundle_bits | ||
971 | create_Imm8_X1(int num) | ||
972 | { | ||
973 | const unsigned int n = (unsigned int)num; | ||
974 | return (((tile_bundle_bits)(n & 0xff)) << 43); | ||
975 | } | ||
976 | |||
977 | static __inline tile_bundle_bits | ||
978 | create_Imm8_Y0(int num) | ||
979 | { | ||
980 | const unsigned int n = (unsigned int)num; | ||
981 | return ((n & 0xff) << 12); | ||
982 | } | ||
983 | |||
984 | static __inline tile_bundle_bits | ||
985 | create_Imm8_Y1(int num) | ||
986 | { | ||
987 | const unsigned int n = (unsigned int)num; | ||
988 | return (((tile_bundle_bits)(n & 0xff)) << 43); | ||
989 | } | ||
990 | |||
991 | static __inline tile_bundle_bits | ||
992 | create_ImmOpcodeExtension_X0(int num) | ||
993 | { | ||
994 | const unsigned int n = (unsigned int)num; | ||
995 | return ((n & 0x7f) << 20); | ||
996 | } | ||
997 | |||
998 | static __inline tile_bundle_bits | ||
999 | create_ImmOpcodeExtension_X1(int num) | ||
1000 | { | ||
1001 | const unsigned int n = (unsigned int)num; | ||
1002 | return (((tile_bundle_bits)(n & 0x7f)) << 51); | ||
1003 | } | ||
1004 | |||
1005 | static __inline tile_bundle_bits | ||
1006 | create_ImmRROpcodeExtension_SN(int num) | ||
1007 | { | ||
1008 | const unsigned int n = (unsigned int)num; | ||
1009 | return ((n & 0x3) << 8); | ||
1010 | } | ||
1011 | |||
1012 | static __inline tile_bundle_bits | ||
1013 | create_JOffLong_X1(int num) | ||
1014 | { | ||
1015 | const unsigned int n = (unsigned int)num; | ||
1016 | return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | | ||
1017 | (((tile_bundle_bits)(n & 0x00018000)) << 20) | | ||
1018 | (((tile_bundle_bits)(n & 0x001e0000)) << 14) | | ||
1019 | (((tile_bundle_bits)(n & 0x07e00000)) << 16) | | ||
1020 | (((tile_bundle_bits)(n & 0x18000000)) << 31); | ||
1021 | } | ||
1022 | |||
1023 | static __inline tile_bundle_bits | ||
1024 | create_JOff_X1(int num) | ||
1025 | { | ||
1026 | const unsigned int n = (unsigned int)num; | ||
1027 | return (((tile_bundle_bits)(n & 0x00007fff)) << 43) | | ||
1028 | (((tile_bundle_bits)(n & 0x00018000)) << 20) | | ||
1029 | (((tile_bundle_bits)(n & 0x001e0000)) << 14) | | ||
1030 | (((tile_bundle_bits)(n & 0x07e00000)) << 16) | | ||
1031 | (((tile_bundle_bits)(n & 0x08000000)) << 31); | ||
1032 | } | ||
1033 | |||
1034 | static __inline tile_bundle_bits | ||
1035 | create_MF_Imm15_X1(int num) | ||
1036 | { | ||
1037 | const unsigned int n = (unsigned int)num; | ||
1038 | return (((tile_bundle_bits)(n & 0x00003fff)) << 37) | | ||
1039 | (((tile_bundle_bits)(n & 0x00004000)) << 44); | ||
1040 | } | ||
1041 | |||
1042 | static __inline tile_bundle_bits | ||
1043 | create_MMEnd_X0(int num) | ||
1044 | { | ||
1045 | const unsigned int n = (unsigned int)num; | ||
1046 | return ((n & 0x1f) << 18); | ||
1047 | } | ||
1048 | |||
1049 | static __inline tile_bundle_bits | ||
1050 | create_MMEnd_X1(int num) | ||
1051 | { | ||
1052 | const unsigned int n = (unsigned int)num; | ||
1053 | return (((tile_bundle_bits)(n & 0x1f)) << 49); | ||
1054 | } | ||
1055 | |||
1056 | static __inline tile_bundle_bits | ||
1057 | create_MMStart_X0(int num) | ||
1058 | { | ||
1059 | const unsigned int n = (unsigned int)num; | ||
1060 | return ((n & 0x1f) << 23); | ||
1061 | } | ||
1062 | |||
1063 | static __inline tile_bundle_bits | ||
1064 | create_MMStart_X1(int num) | ||
1065 | { | ||
1066 | const unsigned int n = (unsigned int)num; | ||
1067 | return (((tile_bundle_bits)(n & 0x1f)) << 54); | ||
1068 | } | ||
1069 | |||
1070 | static __inline tile_bundle_bits | ||
1071 | create_MT_Imm15_X1(int num) | ||
1072 | { | ||
1073 | const unsigned int n = (unsigned int)num; | ||
1074 | return (((tile_bundle_bits)(n & 0x0000003f)) << 31) | | ||
1075 | (((tile_bundle_bits)(n & 0x00003fc0)) << 37) | | ||
1076 | (((tile_bundle_bits)(n & 0x00004000)) << 44); | ||
1077 | } | ||
1078 | |||
1079 | static __inline tile_bundle_bits | ||
1080 | create_Mode(int num) | ||
1081 | { | ||
1082 | const unsigned int n = (unsigned int)num; | ||
1083 | return (((tile_bundle_bits)(n & 0x1)) << 63); | ||
1084 | } | ||
1085 | |||
1086 | static __inline tile_bundle_bits | ||
1087 | create_NoRegOpcodeExtension_SN(int num) | ||
1088 | { | ||
1089 | const unsigned int n = (unsigned int)num; | ||
1090 | return ((n & 0xf) << 0); | ||
1091 | } | ||
1092 | |||
1093 | static __inline tile_bundle_bits | ||
1094 | create_Opcode_SN(int num) | ||
1095 | { | ||
1096 | const unsigned int n = (unsigned int)num; | ||
1097 | return ((n & 0x3f) << 10); | ||
1098 | } | ||
1099 | |||
1100 | static __inline tile_bundle_bits | ||
1101 | create_Opcode_X0(int num) | ||
1102 | { | ||
1103 | const unsigned int n = (unsigned int)num; | ||
1104 | return ((n & 0x7) << 28); | ||
1105 | } | ||
1106 | |||
1107 | static __inline tile_bundle_bits | ||
1108 | create_Opcode_X1(int num) | ||
1109 | { | ||
1110 | const unsigned int n = (unsigned int)num; | ||
1111 | return (((tile_bundle_bits)(n & 0xf)) << 59); | ||
1112 | } | ||
1113 | |||
1114 | static __inline tile_bundle_bits | ||
1115 | create_Opcode_Y0(int num) | ||
1116 | { | ||
1117 | const unsigned int n = (unsigned int)num; | ||
1118 | return ((n & 0xf) << 27); | ||
1119 | } | ||
1120 | |||
1121 | static __inline tile_bundle_bits | ||
1122 | create_Opcode_Y1(int num) | ||
1123 | { | ||
1124 | const unsigned int n = (unsigned int)num; | ||
1125 | return (((tile_bundle_bits)(n & 0xf)) << 59); | ||
1126 | } | ||
1127 | |||
1128 | static __inline tile_bundle_bits | ||
1129 | create_Opcode_Y2(int num) | ||
1130 | { | ||
1131 | const unsigned int n = (unsigned int)num; | ||
1132 | return (((tile_bundle_bits)(n & 0x7)) << 56); | ||
1133 | } | ||
1134 | |||
1135 | static __inline tile_bundle_bits | ||
1136 | create_RROpcodeExtension_SN(int num) | ||
1137 | { | ||
1138 | const unsigned int n = (unsigned int)num; | ||
1139 | return ((n & 0xf) << 4); | ||
1140 | } | ||
1141 | |||
1142 | static __inline tile_bundle_bits | ||
1143 | create_RRROpcodeExtension_X0(int num) | ||
1144 | { | ||
1145 | const unsigned int n = (unsigned int)num; | ||
1146 | return ((n & 0x1ff) << 18); | ||
1147 | } | ||
1148 | |||
1149 | static __inline tile_bundle_bits | ||
1150 | create_RRROpcodeExtension_X1(int num) | ||
1151 | { | ||
1152 | const unsigned int n = (unsigned int)num; | ||
1153 | return (((tile_bundle_bits)(n & 0x1ff)) << 49); | ||
1154 | } | ||
1155 | |||
1156 | static __inline tile_bundle_bits | ||
1157 | create_RRROpcodeExtension_Y0(int num) | ||
1158 | { | ||
1159 | const unsigned int n = (unsigned int)num; | ||
1160 | return ((n & 0x3) << 18); | ||
1161 | } | ||
1162 | |||
1163 | static __inline tile_bundle_bits | ||
1164 | create_RRROpcodeExtension_Y1(int num) | ||
1165 | { | ||
1166 | const unsigned int n = (unsigned int)num; | ||
1167 | return (((tile_bundle_bits)(n & 0x3)) << 49); | ||
1168 | } | ||
1169 | |||
1170 | static __inline tile_bundle_bits | ||
1171 | create_RouteOpcodeExtension_SN(int num) | ||
1172 | { | ||
1173 | const unsigned int n = (unsigned int)num; | ||
1174 | return ((n & 0x3ff) << 0); | ||
1175 | } | ||
1176 | |||
1177 | static __inline tile_bundle_bits | ||
1178 | create_S_X0(int num) | ||
1179 | { | ||
1180 | const unsigned int n = (unsigned int)num; | ||
1181 | return ((n & 0x1) << 27); | ||
1182 | } | ||
1183 | |||
1184 | static __inline tile_bundle_bits | ||
1185 | create_S_X1(int num) | ||
1186 | { | ||
1187 | const unsigned int n = (unsigned int)num; | ||
1188 | return (((tile_bundle_bits)(n & 0x1)) << 58); | ||
1189 | } | ||
1190 | |||
1191 | static __inline tile_bundle_bits | ||
1192 | create_ShAmt_X0(int num) | ||
1193 | { | ||
1194 | const unsigned int n = (unsigned int)num; | ||
1195 | return ((n & 0x1f) << 12); | ||
1196 | } | ||
1197 | |||
1198 | static __inline tile_bundle_bits | ||
1199 | create_ShAmt_X1(int num) | ||
1200 | { | ||
1201 | const unsigned int n = (unsigned int)num; | ||
1202 | return (((tile_bundle_bits)(n & 0x1f)) << 43); | ||
1203 | } | ||
1204 | |||
1205 | static __inline tile_bundle_bits | ||
1206 | create_ShAmt_Y0(int num) | ||
1207 | { | ||
1208 | const unsigned int n = (unsigned int)num; | ||
1209 | return ((n & 0x1f) << 12); | ||
1210 | } | ||
1211 | |||
1212 | static __inline tile_bundle_bits | ||
1213 | create_ShAmt_Y1(int num) | ||
1214 | { | ||
1215 | const unsigned int n = (unsigned int)num; | ||
1216 | return (((tile_bundle_bits)(n & 0x1f)) << 43); | ||
1217 | } | ||
1218 | |||
1219 | static __inline tile_bundle_bits | ||
1220 | create_SrcA_X0(int num) | ||
1221 | { | ||
1222 | const unsigned int n = (unsigned int)num; | ||
1223 | return ((n & 0x3f) << 6); | ||
1224 | } | ||
1225 | |||
1226 | static __inline tile_bundle_bits | ||
1227 | create_SrcA_X1(int num) | ||
1228 | { | ||
1229 | const unsigned int n = (unsigned int)num; | ||
1230 | return (((tile_bundle_bits)(n & 0x3f)) << 37); | ||
1231 | } | ||
1232 | |||
1233 | static __inline tile_bundle_bits | ||
1234 | create_SrcA_Y0(int num) | ||
1235 | { | ||
1236 | const unsigned int n = (unsigned int)num; | ||
1237 | return ((n & 0x3f) << 6); | ||
1238 | } | ||
1239 | |||
1240 | static __inline tile_bundle_bits | ||
1241 | create_SrcA_Y1(int num) | ||
1242 | { | ||
1243 | const unsigned int n = (unsigned int)num; | ||
1244 | return (((tile_bundle_bits)(n & 0x3f)) << 37); | ||
1245 | } | ||
1246 | |||
1247 | static __inline tile_bundle_bits | ||
1248 | create_SrcA_Y2(int num) | ||
1249 | { | ||
1250 | const unsigned int n = (unsigned int)num; | ||
1251 | return ((n & 0x00000001) << 26) | | ||
1252 | (((tile_bundle_bits)(n & 0x0000003e)) << 50); | ||
1253 | } | ||
1254 | |||
1255 | static __inline tile_bundle_bits | ||
1256 | create_SrcBDest_Y2(int num) | ||
1257 | { | ||
1258 | const unsigned int n = (unsigned int)num; | ||
1259 | return ((n & 0x3f) << 20); | ||
1260 | } | ||
1261 | |||
1262 | static __inline tile_bundle_bits | ||
1263 | create_SrcB_X0(int num) | ||
1264 | { | ||
1265 | const unsigned int n = (unsigned int)num; | ||
1266 | return ((n & 0x3f) << 12); | ||
1267 | } | ||
1268 | |||
1269 | static __inline tile_bundle_bits | ||
1270 | create_SrcB_X1(int num) | ||
1271 | { | ||
1272 | const unsigned int n = (unsigned int)num; | ||
1273 | return (((tile_bundle_bits)(n & 0x3f)) << 43); | ||
1274 | } | ||
1275 | |||
1276 | static __inline tile_bundle_bits | ||
1277 | create_SrcB_Y0(int num) | ||
1278 | { | ||
1279 | const unsigned int n = (unsigned int)num; | ||
1280 | return ((n & 0x3f) << 12); | ||
1281 | } | ||
1282 | |||
1283 | static __inline tile_bundle_bits | ||
1284 | create_SrcB_Y1(int num) | ||
1285 | { | ||
1286 | const unsigned int n = (unsigned int)num; | ||
1287 | return (((tile_bundle_bits)(n & 0x3f)) << 43); | ||
1288 | } | ||
1289 | |||
1290 | static __inline tile_bundle_bits | ||
1291 | create_Src_SN(int num) | ||
1292 | { | ||
1293 | const unsigned int n = (unsigned int)num; | ||
1294 | return ((n & 0x3) << 0); | ||
1295 | } | ||
1296 | |||
1297 | static __inline tile_bundle_bits | ||
1298 | create_UnOpcodeExtension_X0(int num) | ||
1299 | { | ||
1300 | const unsigned int n = (unsigned int)num; | ||
1301 | return ((n & 0x1f) << 12); | ||
1302 | } | ||
1303 | |||
1304 | static __inline tile_bundle_bits | ||
1305 | create_UnOpcodeExtension_X1(int num) | ||
1306 | { | ||
1307 | const unsigned int n = (unsigned int)num; | ||
1308 | return (((tile_bundle_bits)(n & 0x1f)) << 43); | ||
1309 | } | ||
1310 | |||
1311 | static __inline tile_bundle_bits | ||
1312 | create_UnOpcodeExtension_Y0(int num) | ||
1313 | { | ||
1314 | const unsigned int n = (unsigned int)num; | ||
1315 | return ((n & 0x1f) << 12); | ||
1316 | } | ||
1317 | |||
1318 | static __inline tile_bundle_bits | ||
1319 | create_UnOpcodeExtension_Y1(int num) | ||
1320 | { | ||
1321 | const unsigned int n = (unsigned int)num; | ||
1322 | return (((tile_bundle_bits)(n & 0x1f)) << 43); | ||
1323 | } | ||
1324 | |||
1325 | static __inline tile_bundle_bits | ||
1326 | create_UnShOpcodeExtension_X0(int num) | ||
1327 | { | ||
1328 | const unsigned int n = (unsigned int)num; | ||
1329 | return ((n & 0x3ff) << 17); | ||
1330 | } | ||
1331 | |||
1332 | static __inline tile_bundle_bits | ||
1333 | create_UnShOpcodeExtension_X1(int num) | ||
1334 | { | ||
1335 | const unsigned int n = (unsigned int)num; | ||
1336 | return (((tile_bundle_bits)(n & 0x3ff)) << 48); | ||
1337 | } | ||
1338 | |||
1339 | static __inline tile_bundle_bits | ||
1340 | create_UnShOpcodeExtension_Y0(int num) | ||
1341 | { | ||
1342 | const unsigned int n = (unsigned int)num; | ||
1343 | return ((n & 0x7) << 17); | ||
1344 | } | ||
1345 | |||
1346 | static __inline tile_bundle_bits | ||
1347 | create_UnShOpcodeExtension_Y1(int num) | ||
1348 | { | ||
1349 | const unsigned int n = (unsigned int)num; | ||
1350 | return (((tile_bundle_bits)(n & 0x7)) << 48); | ||
1351 | } | ||
1352 | |||
1353 | |||
1354 | |||
1355 | typedef enum | ||
1356 | { | ||
1357 | TILE_PIPELINE_X0, | ||
1358 | TILE_PIPELINE_X1, | ||
1359 | TILE_PIPELINE_Y0, | ||
1360 | TILE_PIPELINE_Y1, | ||
1361 | TILE_PIPELINE_Y2, | ||
1362 | } tile_pipeline; | ||
1363 | |||
1364 | #define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1) | ||
1365 | |||
1366 | typedef enum | ||
1367 | { | ||
1368 | TILE_OP_TYPE_REGISTER, | ||
1369 | TILE_OP_TYPE_IMMEDIATE, | ||
1370 | TILE_OP_TYPE_ADDRESS, | ||
1371 | TILE_OP_TYPE_SPR | ||
1372 | } tile_operand_type; | ||
1373 | |||
1374 | /* This is the bit that determines if a bundle is in the Y encoding. */ | ||
1375 | #define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63) | ||
1376 | |||
1377 | enum | ||
1378 | { | ||
1379 | /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ | ||
1380 | TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3, | ||
1381 | |||
1382 | /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ | ||
1383 | TILE_NUM_PIPELINE_ENCODINGS = 5, | ||
1384 | |||
1385 | /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */ | ||
1386 | TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3, | ||
1387 | |||
1388 | /* Instructions take this many bytes. */ | ||
1389 | TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES, | ||
1390 | |||
1391 | /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */ | ||
1392 | TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, | ||
1393 | |||
1394 | /* Bundles should be aligned modulo this number of bytes. */ | ||
1395 | TILE_BUNDLE_ALIGNMENT_IN_BYTES = | ||
1396 | (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), | ||
1397 | |||
1398 | /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */ | ||
1399 | TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1, | ||
1400 | |||
1401 | /* Static network instructions take this many bytes. */ | ||
1402 | TILE_SN_INSTRUCTION_SIZE_IN_BYTES = | ||
1403 | (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES), | ||
1404 | |||
1405 | /* Number of registers (some are magic, such as network I/O). */ | ||
1406 | TILE_NUM_REGISTERS = 64, | ||
1407 | |||
1408 | /* Number of static network registers. */ | ||
1409 | TILE_NUM_SN_REGISTERS = 4 | ||
1410 | }; | ||
1411 | |||
1412 | |||
1413 | struct tile_operand | ||
1414 | { | ||
1415 | /* Is this operand a register, immediate or address? */ | ||
1416 | tile_operand_type type; | ||
1417 | |||
1418 | /* The default relocation type for this operand. */ | ||
1419 | signed int default_reloc : 16; | ||
1420 | |||
1421 | /* How many bits is this value? (used for range checking) */ | ||
1422 | unsigned int num_bits : 5; | ||
1423 | |||
1424 | /* Is the value signed? (used for range checking) */ | ||
1425 | unsigned int is_signed : 1; | ||
1426 | |||
1427 | /* Is this operand a source register? */ | ||
1428 | unsigned int is_src_reg : 1; | ||
1429 | |||
1430 | /* Is this operand written? (i.e. is it a destination register) */ | ||
1431 | unsigned int is_dest_reg : 1; | ||
1432 | |||
1433 | /* Is this operand PC-relative? */ | ||
1434 | unsigned int is_pc_relative : 1; | ||
1435 | |||
1436 | /* By how many bits do we right shift the value before inserting? */ | ||
1437 | unsigned int rightshift : 2; | ||
1438 | |||
1439 | /* Return the bits for this operand to be ORed into an existing bundle. */ | ||
1440 | tile_bundle_bits (*insert) (int op); | ||
1441 | |||
1442 | /* Extract this operand and return it. */ | ||
1443 | unsigned int (*extract) (tile_bundle_bits bundle); | ||
1444 | }; | ||
1445 | |||
1446 | |||
1447 | extern const struct tile_operand tile_operands[]; | ||
1448 | |||
1449 | /* One finite-state machine per pipe for rapid instruction decoding. */ | ||
1450 | extern const unsigned short * const | ||
1451 | tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS]; | ||
1452 | |||
1453 | |||
1454 | struct tile_opcode | ||
1455 | { | ||
1456 | /* The opcode mnemonic, e.g. "add" */ | ||
1457 | const char *name; | ||
1458 | |||
1459 | /* The enum value for this mnemonic. */ | ||
1460 | tile_mnemonic mnemonic; | ||
1461 | |||
1462 | /* A bit mask of which of the five pipes this instruction | ||
1463 | is compatible with: | ||
1464 | X0 0x01 | ||
1465 | X1 0x02 | ||
1466 | Y0 0x04 | ||
1467 | Y1 0x08 | ||
1468 | Y2 0x10 */ | ||
1469 | unsigned char pipes; | ||
1470 | |||
1471 | /* How many operands are there? */ | ||
1472 | unsigned char num_operands; | ||
1473 | |||
1474 | /* Which register does this write implicitly, or TREG_ZERO if none? */ | ||
1475 | unsigned char implicitly_written_register; | ||
1476 | |||
1477 | /* Can this be bundled with other instructions (almost always true). */ | ||
1478 | unsigned char can_bundle; | ||
1479 | |||
1480 | /* The description of the operands. Each of these is an | ||
1481 | * index into the tile_operands[] table. */ | ||
1482 | unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS]; | ||
1483 | |||
1484 | }; | ||
1485 | |||
1486 | extern const struct tile_opcode tile_opcodes[]; | ||
1487 | |||
1488 | |||
1489 | /* Used for non-textual disassembly into structs. */ | ||
1490 | struct tile_decoded_instruction | ||
1491 | { | ||
1492 | const struct tile_opcode *opcode; | ||
1493 | const struct tile_operand *operands[TILE_MAX_OPERANDS]; | ||
1494 | int operand_values[TILE_MAX_OPERANDS]; | ||
1495 | }; | ||
1496 | |||
1497 | |||
1498 | /* Disassemble a bundle into a struct for machine processing. */ | ||
1499 | extern int parse_insn_tile(tile_bundle_bits bits, | ||
1500 | unsigned int pc, | ||
1501 | struct tile_decoded_instruction | ||
1502 | decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]); | ||
1503 | |||
1504 | |||
1505 | /* Given a set of bundle bits and a specific pipe, returns which | ||
1506 | * instruction the bundle contains in that pipe. | ||
1507 | */ | ||
1508 | extern const struct tile_opcode * | ||
1509 | find_opcode(tile_bundle_bits bits, tile_pipeline pipe); | ||
1510 | |||
1511 | |||
1512 | |||
1513 | #endif /* opcode_tile_h */ | ||
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h deleted file mode 100644 index c0633466cd5c..000000000000 --- a/arch/tile/include/asm/opcode-tile_64.h +++ /dev/null | |||
@@ -1,1248 +0,0 @@ | |||
1 | /* tile.h -- Header file for TILE opcode table | ||
2 | Copyright (C) 2005 Free Software Foundation, Inc. | ||
3 | Contributed by Tilera Corp. */ | ||
4 | |||
5 | #ifndef opcode_tile_h | ||
6 | #define opcode_tile_h | ||
7 | |||
8 | typedef unsigned long long tilegx_bundle_bits; | ||
9 | |||
10 | |||
11 | enum | ||
12 | { | ||
13 | TILEGX_MAX_OPERANDS = 4 /* bfexts */ | ||
14 | }; | ||
15 | |||
16 | typedef enum | ||
17 | { | ||
18 | TILEGX_OPC_BPT, | ||
19 | TILEGX_OPC_INFO, | ||
20 | TILEGX_OPC_INFOL, | ||
21 | TILEGX_OPC_MOVE, | ||
22 | TILEGX_OPC_MOVEI, | ||
23 | TILEGX_OPC_MOVELI, | ||
24 | TILEGX_OPC_PREFETCH, | ||
25 | TILEGX_OPC_PREFETCH_ADD_L1, | ||
26 | TILEGX_OPC_PREFETCH_ADD_L1_FAULT, | ||
27 | TILEGX_OPC_PREFETCH_ADD_L2, | ||
28 | TILEGX_OPC_PREFETCH_ADD_L2_FAULT, | ||
29 | TILEGX_OPC_PREFETCH_ADD_L3, | ||
30 | TILEGX_OPC_PREFETCH_ADD_L3_FAULT, | ||
31 | TILEGX_OPC_PREFETCH_L1, | ||
32 | TILEGX_OPC_PREFETCH_L1_FAULT, | ||
33 | TILEGX_OPC_PREFETCH_L2, | ||
34 | TILEGX_OPC_PREFETCH_L2_FAULT, | ||
35 | TILEGX_OPC_PREFETCH_L3, | ||
36 | TILEGX_OPC_PREFETCH_L3_FAULT, | ||
37 | TILEGX_OPC_RAISE, | ||
38 | TILEGX_OPC_ADD, | ||
39 | TILEGX_OPC_ADDI, | ||
40 | TILEGX_OPC_ADDLI, | ||
41 | TILEGX_OPC_ADDX, | ||
42 | TILEGX_OPC_ADDXI, | ||
43 | TILEGX_OPC_ADDXLI, | ||
44 | TILEGX_OPC_ADDXSC, | ||
45 | TILEGX_OPC_AND, | ||
46 | TILEGX_OPC_ANDI, | ||
47 | TILEGX_OPC_BEQZ, | ||
48 | TILEGX_OPC_BEQZT, | ||
49 | TILEGX_OPC_BFEXTS, | ||
50 | TILEGX_OPC_BFEXTU, | ||
51 | TILEGX_OPC_BFINS, | ||
52 | TILEGX_OPC_BGEZ, | ||
53 | TILEGX_OPC_BGEZT, | ||
54 | TILEGX_OPC_BGTZ, | ||
55 | TILEGX_OPC_BGTZT, | ||
56 | TILEGX_OPC_BLBC, | ||
57 | TILEGX_OPC_BLBCT, | ||
58 | TILEGX_OPC_BLBS, | ||
59 | TILEGX_OPC_BLBST, | ||
60 | TILEGX_OPC_BLEZ, | ||
61 | TILEGX_OPC_BLEZT, | ||
62 | TILEGX_OPC_BLTZ, | ||
63 | TILEGX_OPC_BLTZT, | ||
64 | TILEGX_OPC_BNEZ, | ||
65 | TILEGX_OPC_BNEZT, | ||
66 | TILEGX_OPC_CLZ, | ||
67 | TILEGX_OPC_CMOVEQZ, | ||
68 | TILEGX_OPC_CMOVNEZ, | ||
69 | TILEGX_OPC_CMPEQ, | ||
70 | TILEGX_OPC_CMPEQI, | ||
71 | TILEGX_OPC_CMPEXCH, | ||
72 | TILEGX_OPC_CMPEXCH4, | ||
73 | TILEGX_OPC_CMPLES, | ||
74 | TILEGX_OPC_CMPLEU, | ||
75 | TILEGX_OPC_CMPLTS, | ||
76 | TILEGX_OPC_CMPLTSI, | ||
77 | TILEGX_OPC_CMPLTU, | ||
78 | TILEGX_OPC_CMPLTUI, | ||
79 | TILEGX_OPC_CMPNE, | ||
80 | TILEGX_OPC_CMUL, | ||
81 | TILEGX_OPC_CMULA, | ||
82 | TILEGX_OPC_CMULAF, | ||
83 | TILEGX_OPC_CMULF, | ||
84 | TILEGX_OPC_CMULFR, | ||
85 | TILEGX_OPC_CMULH, | ||
86 | TILEGX_OPC_CMULHR, | ||
87 | TILEGX_OPC_CRC32_32, | ||
88 | TILEGX_OPC_CRC32_8, | ||
89 | TILEGX_OPC_CTZ, | ||
90 | TILEGX_OPC_DBLALIGN, | ||
91 | TILEGX_OPC_DBLALIGN2, | ||
92 | TILEGX_OPC_DBLALIGN4, | ||
93 | TILEGX_OPC_DBLALIGN6, | ||
94 | TILEGX_OPC_DRAIN, | ||
95 | TILEGX_OPC_DTLBPR, | ||
96 | TILEGX_OPC_EXCH, | ||
97 | TILEGX_OPC_EXCH4, | ||
98 | TILEGX_OPC_FDOUBLE_ADD_FLAGS, | ||
99 | TILEGX_OPC_FDOUBLE_ADDSUB, | ||
100 | TILEGX_OPC_FDOUBLE_MUL_FLAGS, | ||
101 | TILEGX_OPC_FDOUBLE_PACK1, | ||
102 | TILEGX_OPC_FDOUBLE_PACK2, | ||
103 | TILEGX_OPC_FDOUBLE_SUB_FLAGS, | ||
104 | TILEGX_OPC_FDOUBLE_UNPACK_MAX, | ||
105 | TILEGX_OPC_FDOUBLE_UNPACK_MIN, | ||
106 | TILEGX_OPC_FETCHADD, | ||
107 | TILEGX_OPC_FETCHADD4, | ||
108 | TILEGX_OPC_FETCHADDGEZ, | ||
109 | TILEGX_OPC_FETCHADDGEZ4, | ||
110 | TILEGX_OPC_FETCHAND, | ||
111 | TILEGX_OPC_FETCHAND4, | ||
112 | TILEGX_OPC_FETCHOR, | ||
113 | TILEGX_OPC_FETCHOR4, | ||
114 | TILEGX_OPC_FINV, | ||
115 | TILEGX_OPC_FLUSH, | ||
116 | TILEGX_OPC_FLUSHWB, | ||
117 | TILEGX_OPC_FNOP, | ||
118 | TILEGX_OPC_FSINGLE_ADD1, | ||
119 | TILEGX_OPC_FSINGLE_ADDSUB2, | ||
120 | TILEGX_OPC_FSINGLE_MUL1, | ||
121 | TILEGX_OPC_FSINGLE_MUL2, | ||
122 | TILEGX_OPC_FSINGLE_PACK1, | ||
123 | TILEGX_OPC_FSINGLE_PACK2, | ||
124 | TILEGX_OPC_FSINGLE_SUB1, | ||
125 | TILEGX_OPC_ICOH, | ||
126 | TILEGX_OPC_ILL, | ||
127 | TILEGX_OPC_INV, | ||
128 | TILEGX_OPC_IRET, | ||
129 | TILEGX_OPC_J, | ||
130 | TILEGX_OPC_JAL, | ||
131 | TILEGX_OPC_JALR, | ||
132 | TILEGX_OPC_JALRP, | ||
133 | TILEGX_OPC_JR, | ||
134 | TILEGX_OPC_JRP, | ||
135 | TILEGX_OPC_LD, | ||
136 | TILEGX_OPC_LD1S, | ||
137 | TILEGX_OPC_LD1S_ADD, | ||
138 | TILEGX_OPC_LD1U, | ||
139 | TILEGX_OPC_LD1U_ADD, | ||
140 | TILEGX_OPC_LD2S, | ||
141 | TILEGX_OPC_LD2S_ADD, | ||
142 | TILEGX_OPC_LD2U, | ||
143 | TILEGX_OPC_LD2U_ADD, | ||
144 | TILEGX_OPC_LD4S, | ||
145 | TILEGX_OPC_LD4S_ADD, | ||
146 | TILEGX_OPC_LD4U, | ||
147 | TILEGX_OPC_LD4U_ADD, | ||
148 | TILEGX_OPC_LD_ADD, | ||
149 | TILEGX_OPC_LDNA, | ||
150 | TILEGX_OPC_LDNA_ADD, | ||
151 | TILEGX_OPC_LDNT, | ||
152 | TILEGX_OPC_LDNT1S, | ||
153 | TILEGX_OPC_LDNT1S_ADD, | ||
154 | TILEGX_OPC_LDNT1U, | ||
155 | TILEGX_OPC_LDNT1U_ADD, | ||
156 | TILEGX_OPC_LDNT2S, | ||
157 | TILEGX_OPC_LDNT2S_ADD, | ||
158 | TILEGX_OPC_LDNT2U, | ||
159 | TILEGX_OPC_LDNT2U_ADD, | ||
160 | TILEGX_OPC_LDNT4S, | ||
161 | TILEGX_OPC_LDNT4S_ADD, | ||
162 | TILEGX_OPC_LDNT4U, | ||
163 | TILEGX_OPC_LDNT4U_ADD, | ||
164 | TILEGX_OPC_LDNT_ADD, | ||
165 | TILEGX_OPC_LNK, | ||
166 | TILEGX_OPC_MF, | ||
167 | TILEGX_OPC_MFSPR, | ||
168 | TILEGX_OPC_MM, | ||
169 | TILEGX_OPC_MNZ, | ||
170 | TILEGX_OPC_MTSPR, | ||
171 | TILEGX_OPC_MUL_HS_HS, | ||
172 | TILEGX_OPC_MUL_HS_HU, | ||
173 | TILEGX_OPC_MUL_HS_LS, | ||
174 | TILEGX_OPC_MUL_HS_LU, | ||
175 | TILEGX_OPC_MUL_HU_HU, | ||
176 | TILEGX_OPC_MUL_HU_LS, | ||
177 | TILEGX_OPC_MUL_HU_LU, | ||
178 | TILEGX_OPC_MUL_LS_LS, | ||
179 | TILEGX_OPC_MUL_LS_LU, | ||
180 | TILEGX_OPC_MUL_LU_LU, | ||
181 | TILEGX_OPC_MULA_HS_HS, | ||
182 | TILEGX_OPC_MULA_HS_HU, | ||
183 | TILEGX_OPC_MULA_HS_LS, | ||
184 | TILEGX_OPC_MULA_HS_LU, | ||
185 | TILEGX_OPC_MULA_HU_HU, | ||
186 | TILEGX_OPC_MULA_HU_LS, | ||
187 | TILEGX_OPC_MULA_HU_LU, | ||
188 | TILEGX_OPC_MULA_LS_LS, | ||
189 | TILEGX_OPC_MULA_LS_LU, | ||
190 | TILEGX_OPC_MULA_LU_LU, | ||
191 | TILEGX_OPC_MULAX, | ||
192 | TILEGX_OPC_MULX, | ||
193 | TILEGX_OPC_MZ, | ||
194 | TILEGX_OPC_NAP, | ||
195 | TILEGX_OPC_NOP, | ||
196 | TILEGX_OPC_NOR, | ||
197 | TILEGX_OPC_OR, | ||
198 | TILEGX_OPC_ORI, | ||
199 | TILEGX_OPC_PCNT, | ||
200 | TILEGX_OPC_REVBITS, | ||
201 | TILEGX_OPC_REVBYTES, | ||
202 | TILEGX_OPC_ROTL, | ||
203 | TILEGX_OPC_ROTLI, | ||
204 | TILEGX_OPC_SHL, | ||
205 | TILEGX_OPC_SHL16INSLI, | ||
206 | TILEGX_OPC_SHL1ADD, | ||
207 | TILEGX_OPC_SHL1ADDX, | ||
208 | TILEGX_OPC_SHL2ADD, | ||
209 | TILEGX_OPC_SHL2ADDX, | ||
210 | TILEGX_OPC_SHL3ADD, | ||
211 | TILEGX_OPC_SHL3ADDX, | ||
212 | TILEGX_OPC_SHLI, | ||
213 | TILEGX_OPC_SHLX, | ||
214 | TILEGX_OPC_SHLXI, | ||
215 | TILEGX_OPC_SHRS, | ||
216 | TILEGX_OPC_SHRSI, | ||
217 | TILEGX_OPC_SHRU, | ||
218 | TILEGX_OPC_SHRUI, | ||
219 | TILEGX_OPC_SHRUX, | ||
220 | TILEGX_OPC_SHRUXI, | ||
221 | TILEGX_OPC_SHUFFLEBYTES, | ||
222 | TILEGX_OPC_ST, | ||
223 | TILEGX_OPC_ST1, | ||
224 | TILEGX_OPC_ST1_ADD, | ||
225 | TILEGX_OPC_ST2, | ||
226 | TILEGX_OPC_ST2_ADD, | ||
227 | TILEGX_OPC_ST4, | ||
228 | TILEGX_OPC_ST4_ADD, | ||
229 | TILEGX_OPC_ST_ADD, | ||
230 | TILEGX_OPC_STNT, | ||
231 | TILEGX_OPC_STNT1, | ||
232 | TILEGX_OPC_STNT1_ADD, | ||
233 | TILEGX_OPC_STNT2, | ||
234 | TILEGX_OPC_STNT2_ADD, | ||
235 | TILEGX_OPC_STNT4, | ||
236 | TILEGX_OPC_STNT4_ADD, | ||
237 | TILEGX_OPC_STNT_ADD, | ||
238 | TILEGX_OPC_SUB, | ||
239 | TILEGX_OPC_SUBX, | ||
240 | TILEGX_OPC_SUBXSC, | ||
241 | TILEGX_OPC_SWINT0, | ||
242 | TILEGX_OPC_SWINT1, | ||
243 | TILEGX_OPC_SWINT2, | ||
244 | TILEGX_OPC_SWINT3, | ||
245 | TILEGX_OPC_TBLIDXB0, | ||
246 | TILEGX_OPC_TBLIDXB1, | ||
247 | TILEGX_OPC_TBLIDXB2, | ||
248 | TILEGX_OPC_TBLIDXB3, | ||
249 | TILEGX_OPC_V1ADD, | ||
250 | TILEGX_OPC_V1ADDI, | ||
251 | TILEGX_OPC_V1ADDUC, | ||
252 | TILEGX_OPC_V1ADIFFU, | ||
253 | TILEGX_OPC_V1AVGU, | ||
254 | TILEGX_OPC_V1CMPEQ, | ||
255 | TILEGX_OPC_V1CMPEQI, | ||
256 | TILEGX_OPC_V1CMPLES, | ||
257 | TILEGX_OPC_V1CMPLEU, | ||
258 | TILEGX_OPC_V1CMPLTS, | ||
259 | TILEGX_OPC_V1CMPLTSI, | ||
260 | TILEGX_OPC_V1CMPLTU, | ||
261 | TILEGX_OPC_V1CMPLTUI, | ||
262 | TILEGX_OPC_V1CMPNE, | ||
263 | TILEGX_OPC_V1DDOTPU, | ||
264 | TILEGX_OPC_V1DDOTPUA, | ||
265 | TILEGX_OPC_V1DDOTPUS, | ||
266 | TILEGX_OPC_V1DDOTPUSA, | ||
267 | TILEGX_OPC_V1DOTP, | ||
268 | TILEGX_OPC_V1DOTPA, | ||
269 | TILEGX_OPC_V1DOTPU, | ||
270 | TILEGX_OPC_V1DOTPUA, | ||
271 | TILEGX_OPC_V1DOTPUS, | ||
272 | TILEGX_OPC_V1DOTPUSA, | ||
273 | TILEGX_OPC_V1INT_H, | ||
274 | TILEGX_OPC_V1INT_L, | ||
275 | TILEGX_OPC_V1MAXU, | ||
276 | TILEGX_OPC_V1MAXUI, | ||
277 | TILEGX_OPC_V1MINU, | ||
278 | TILEGX_OPC_V1MINUI, | ||
279 | TILEGX_OPC_V1MNZ, | ||
280 | TILEGX_OPC_V1MULTU, | ||
281 | TILEGX_OPC_V1MULU, | ||
282 | TILEGX_OPC_V1MULUS, | ||
283 | TILEGX_OPC_V1MZ, | ||
284 | TILEGX_OPC_V1SADAU, | ||
285 | TILEGX_OPC_V1SADU, | ||
286 | TILEGX_OPC_V1SHL, | ||
287 | TILEGX_OPC_V1SHLI, | ||
288 | TILEGX_OPC_V1SHRS, | ||
289 | TILEGX_OPC_V1SHRSI, | ||
290 | TILEGX_OPC_V1SHRU, | ||
291 | TILEGX_OPC_V1SHRUI, | ||
292 | TILEGX_OPC_V1SUB, | ||
293 | TILEGX_OPC_V1SUBUC, | ||
294 | TILEGX_OPC_V2ADD, | ||
295 | TILEGX_OPC_V2ADDI, | ||
296 | TILEGX_OPC_V2ADDSC, | ||
297 | TILEGX_OPC_V2ADIFFS, | ||
298 | TILEGX_OPC_V2AVGS, | ||
299 | TILEGX_OPC_V2CMPEQ, | ||
300 | TILEGX_OPC_V2CMPEQI, | ||
301 | TILEGX_OPC_V2CMPLES, | ||
302 | TILEGX_OPC_V2CMPLEU, | ||
303 | TILEGX_OPC_V2CMPLTS, | ||
304 | TILEGX_OPC_V2CMPLTSI, | ||
305 | TILEGX_OPC_V2CMPLTU, | ||
306 | TILEGX_OPC_V2CMPLTUI, | ||
307 | TILEGX_OPC_V2CMPNE, | ||
308 | TILEGX_OPC_V2DOTP, | ||
309 | TILEGX_OPC_V2DOTPA, | ||
310 | TILEGX_OPC_V2INT_H, | ||
311 | TILEGX_OPC_V2INT_L, | ||
312 | TILEGX_OPC_V2MAXS, | ||
313 | TILEGX_OPC_V2MAXSI, | ||
314 | TILEGX_OPC_V2MINS, | ||
315 | TILEGX_OPC_V2MINSI, | ||
316 | TILEGX_OPC_V2MNZ, | ||
317 | TILEGX_OPC_V2MULFSC, | ||
318 | TILEGX_OPC_V2MULS, | ||
319 | TILEGX_OPC_V2MULTS, | ||
320 | TILEGX_OPC_V2MZ, | ||
321 | TILEGX_OPC_V2PACKH, | ||
322 | TILEGX_OPC_V2PACKL, | ||
323 | TILEGX_OPC_V2PACKUC, | ||
324 | TILEGX_OPC_V2SADAS, | ||
325 | TILEGX_OPC_V2SADAU, | ||
326 | TILEGX_OPC_V2SADS, | ||
327 | TILEGX_OPC_V2SADU, | ||
328 | TILEGX_OPC_V2SHL, | ||
329 | TILEGX_OPC_V2SHLI, | ||
330 | TILEGX_OPC_V2SHLSC, | ||
331 | TILEGX_OPC_V2SHRS, | ||
332 | TILEGX_OPC_V2SHRSI, | ||
333 | TILEGX_OPC_V2SHRU, | ||
334 | TILEGX_OPC_V2SHRUI, | ||
335 | TILEGX_OPC_V2SUB, | ||
336 | TILEGX_OPC_V2SUBSC, | ||
337 | TILEGX_OPC_V4ADD, | ||
338 | TILEGX_OPC_V4ADDSC, | ||
339 | TILEGX_OPC_V4INT_H, | ||
340 | TILEGX_OPC_V4INT_L, | ||
341 | TILEGX_OPC_V4PACKSC, | ||
342 | TILEGX_OPC_V4SHL, | ||
343 | TILEGX_OPC_V4SHLSC, | ||
344 | TILEGX_OPC_V4SHRS, | ||
345 | TILEGX_OPC_V4SHRU, | ||
346 | TILEGX_OPC_V4SUB, | ||
347 | TILEGX_OPC_V4SUBSC, | ||
348 | TILEGX_OPC_WH64, | ||
349 | TILEGX_OPC_XOR, | ||
350 | TILEGX_OPC_XORI, | ||
351 | TILEGX_OPC_NONE | ||
352 | } tilegx_mnemonic; | ||
353 | |||
354 | /* 64-bit pattern for a { bpt ; nop } bundle. */ | ||
355 | #define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL | ||
356 | |||
357 | |||
358 | #define TILE_ELF_MACHINE_CODE EM_TILE64 | ||
359 | |||
360 | #define TILE_ELF_NAME "elf32-tile64" | ||
361 | |||
362 | |||
363 | static __inline unsigned int | ||
364 | get_BFEnd_X0(tilegx_bundle_bits num) | ||
365 | { | ||
366 | const unsigned int n = (unsigned int)num; | ||
367 | return (((n >> 12)) & 0x3f); | ||
368 | } | ||
369 | |||
370 | static __inline unsigned int | ||
371 | get_BFOpcodeExtension_X0(tilegx_bundle_bits num) | ||
372 | { | ||
373 | const unsigned int n = (unsigned int)num; | ||
374 | return (((n >> 24)) & 0xf); | ||
375 | } | ||
376 | |||
377 | static __inline unsigned int | ||
378 | get_BFStart_X0(tilegx_bundle_bits num) | ||
379 | { | ||
380 | const unsigned int n = (unsigned int)num; | ||
381 | return (((n >> 18)) & 0x3f); | ||
382 | } | ||
383 | |||
384 | static __inline unsigned int | ||
385 | get_BrOff_X1(tilegx_bundle_bits n) | ||
386 | { | ||
387 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
388 | (((unsigned int)(n >> 37)) & 0x0001ffc0); | ||
389 | } | ||
390 | |||
391 | static __inline unsigned int | ||
392 | get_BrType_X1(tilegx_bundle_bits n) | ||
393 | { | ||
394 | return (((unsigned int)(n >> 54)) & 0x1f); | ||
395 | } | ||
396 | |||
397 | static __inline unsigned int | ||
398 | get_Dest_Imm8_X1(tilegx_bundle_bits n) | ||
399 | { | ||
400 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
401 | (((unsigned int)(n >> 43)) & 0x000000c0); | ||
402 | } | ||
403 | |||
404 | static __inline unsigned int | ||
405 | get_Dest_X0(tilegx_bundle_bits num) | ||
406 | { | ||
407 | const unsigned int n = (unsigned int)num; | ||
408 | return (((n >> 0)) & 0x3f); | ||
409 | } | ||
410 | |||
411 | static __inline unsigned int | ||
412 | get_Dest_X1(tilegx_bundle_bits n) | ||
413 | { | ||
414 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
415 | } | ||
416 | |||
417 | static __inline unsigned int | ||
418 | get_Dest_Y0(tilegx_bundle_bits num) | ||
419 | { | ||
420 | const unsigned int n = (unsigned int)num; | ||
421 | return (((n >> 0)) & 0x3f); | ||
422 | } | ||
423 | |||
424 | static __inline unsigned int | ||
425 | get_Dest_Y1(tilegx_bundle_bits n) | ||
426 | { | ||
427 | return (((unsigned int)(n >> 31)) & 0x3f); | ||
428 | } | ||
429 | |||
430 | static __inline unsigned int | ||
431 | get_Imm16_X0(tilegx_bundle_bits num) | ||
432 | { | ||
433 | const unsigned int n = (unsigned int)num; | ||
434 | return (((n >> 12)) & 0xffff); | ||
435 | } | ||
436 | |||
437 | static __inline unsigned int | ||
438 | get_Imm16_X1(tilegx_bundle_bits n) | ||
439 | { | ||
440 | return (((unsigned int)(n >> 43)) & 0xffff); | ||
441 | } | ||
442 | |||
443 | static __inline unsigned int | ||
444 | get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num) | ||
445 | { | ||
446 | const unsigned int n = (unsigned int)num; | ||
447 | return (((n >> 20)) & 0xff); | ||
448 | } | ||
449 | |||
450 | static __inline unsigned int | ||
451 | get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n) | ||
452 | { | ||
453 | return (((unsigned int)(n >> 51)) & 0xff); | ||
454 | } | ||
455 | |||
456 | static __inline unsigned int | ||
457 | get_Imm8_X0(tilegx_bundle_bits num) | ||
458 | { | ||
459 | const unsigned int n = (unsigned int)num; | ||
460 | return (((n >> 12)) & 0xff); | ||
461 | } | ||
462 | |||
463 | static __inline unsigned int | ||
464 | get_Imm8_X1(tilegx_bundle_bits n) | ||
465 | { | ||
466 | return (((unsigned int)(n >> 43)) & 0xff); | ||
467 | } | ||
468 | |||
469 | static __inline unsigned int | ||
470 | get_Imm8_Y0(tilegx_bundle_bits num) | ||
471 | { | ||
472 | const unsigned int n = (unsigned int)num; | ||
473 | return (((n >> 12)) & 0xff); | ||
474 | } | ||
475 | |||
476 | static __inline unsigned int | ||
477 | get_Imm8_Y1(tilegx_bundle_bits n) | ||
478 | { | ||
479 | return (((unsigned int)(n >> 43)) & 0xff); | ||
480 | } | ||
481 | |||
482 | static __inline unsigned int | ||
483 | get_JumpOff_X1(tilegx_bundle_bits n) | ||
484 | { | ||
485 | return (((unsigned int)(n >> 31)) & 0x7ffffff); | ||
486 | } | ||
487 | |||
488 | static __inline unsigned int | ||
489 | get_JumpOpcodeExtension_X1(tilegx_bundle_bits n) | ||
490 | { | ||
491 | return (((unsigned int)(n >> 58)) & 0x1); | ||
492 | } | ||
493 | |||
494 | static __inline unsigned int | ||
495 | get_MF_Imm14_X1(tilegx_bundle_bits n) | ||
496 | { | ||
497 | return (((unsigned int)(n >> 37)) & 0x3fff); | ||
498 | } | ||
499 | |||
500 | static __inline unsigned int | ||
501 | get_MT_Imm14_X1(tilegx_bundle_bits n) | ||
502 | { | ||
503 | return (((unsigned int)(n >> 31)) & 0x0000003f) | | ||
504 | (((unsigned int)(n >> 37)) & 0x00003fc0); | ||
505 | } | ||
506 | |||
507 | static __inline unsigned int | ||
508 | get_Mode(tilegx_bundle_bits n) | ||
509 | { | ||
510 | return (((unsigned int)(n >> 62)) & 0x3); | ||
511 | } | ||
512 | |||
513 | static __inline unsigned int | ||
514 | get_Opcode_X0(tilegx_bundle_bits num) | ||
515 | { | ||
516 | const unsigned int n = (unsigned int)num; | ||
517 | return (((n >> 28)) & 0x7); | ||
518 | } | ||
519 | |||
520 | static __inline unsigned int | ||
521 | get_Opcode_X1(tilegx_bundle_bits n) | ||
522 | { | ||
523 | return (((unsigned int)(n >> 59)) & 0x7); | ||
524 | } | ||
525 | |||
526 | static __inline unsigned int | ||
527 | get_Opcode_Y0(tilegx_bundle_bits num) | ||
528 | { | ||
529 | const unsigned int n = (unsigned int)num; | ||
530 | return (((n >> 27)) & 0xf); | ||
531 | } | ||
532 | |||
533 | static __inline unsigned int | ||
534 | get_Opcode_Y1(tilegx_bundle_bits n) | ||
535 | { | ||
536 | return (((unsigned int)(n >> 58)) & 0xf); | ||
537 | } | ||
538 | |||
539 | static __inline unsigned int | ||
540 | get_Opcode_Y2(tilegx_bundle_bits n) | ||
541 | { | ||
542 | return (((n >> 26)) & 0x00000001) | | ||
543 | (((unsigned int)(n >> 56)) & 0x00000002); | ||
544 | } | ||
545 | |||
546 | static __inline unsigned int | ||
547 | get_RRROpcodeExtension_X0(tilegx_bundle_bits num) | ||
548 | { | ||
549 | const unsigned int n = (unsigned int)num; | ||
550 | return (((n >> 18)) & 0x3ff); | ||
551 | } | ||
552 | |||
553 | static __inline unsigned int | ||
554 | get_RRROpcodeExtension_X1(tilegx_bundle_bits n) | ||
555 | { | ||
556 | return (((unsigned int)(n >> 49)) & 0x3ff); | ||
557 | } | ||
558 | |||
559 | static __inline unsigned int | ||
560 | get_RRROpcodeExtension_Y0(tilegx_bundle_bits num) | ||
561 | { | ||
562 | const unsigned int n = (unsigned int)num; | ||
563 | return (((n >> 18)) & 0x3); | ||
564 | } | ||
565 | |||
566 | static __inline unsigned int | ||
567 | get_RRROpcodeExtension_Y1(tilegx_bundle_bits n) | ||
568 | { | ||
569 | return (((unsigned int)(n >> 49)) & 0x3); | ||
570 | } | ||
571 | |||
572 | static __inline unsigned int | ||
573 | get_ShAmt_X0(tilegx_bundle_bits num) | ||
574 | { | ||
575 | const unsigned int n = (unsigned int)num; | ||
576 | return (((n >> 12)) & 0x3f); | ||
577 | } | ||
578 | |||
579 | static __inline unsigned int | ||
580 | get_ShAmt_X1(tilegx_bundle_bits n) | ||
581 | { | ||
582 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
583 | } | ||
584 | |||
585 | static __inline unsigned int | ||
586 | get_ShAmt_Y0(tilegx_bundle_bits num) | ||
587 | { | ||
588 | const unsigned int n = (unsigned int)num; | ||
589 | return (((n >> 12)) & 0x3f); | ||
590 | } | ||
591 | |||
592 | static __inline unsigned int | ||
593 | get_ShAmt_Y1(tilegx_bundle_bits n) | ||
594 | { | ||
595 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
596 | } | ||
597 | |||
598 | static __inline unsigned int | ||
599 | get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num) | ||
600 | { | ||
601 | const unsigned int n = (unsigned int)num; | ||
602 | return (((n >> 18)) & 0x3ff); | ||
603 | } | ||
604 | |||
605 | static __inline unsigned int | ||
606 | get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n) | ||
607 | { | ||
608 | return (((unsigned int)(n >> 49)) & 0x3ff); | ||
609 | } | ||
610 | |||
611 | static __inline unsigned int | ||
612 | get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num) | ||
613 | { | ||
614 | const unsigned int n = (unsigned int)num; | ||
615 | return (((n >> 18)) & 0x3); | ||
616 | } | ||
617 | |||
618 | static __inline unsigned int | ||
619 | get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n) | ||
620 | { | ||
621 | return (((unsigned int)(n >> 49)) & 0x3); | ||
622 | } | ||
623 | |||
624 | static __inline unsigned int | ||
625 | get_SrcA_X0(tilegx_bundle_bits num) | ||
626 | { | ||
627 | const unsigned int n = (unsigned int)num; | ||
628 | return (((n >> 6)) & 0x3f); | ||
629 | } | ||
630 | |||
631 | static __inline unsigned int | ||
632 | get_SrcA_X1(tilegx_bundle_bits n) | ||
633 | { | ||
634 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
635 | } | ||
636 | |||
637 | static __inline unsigned int | ||
638 | get_SrcA_Y0(tilegx_bundle_bits num) | ||
639 | { | ||
640 | const unsigned int n = (unsigned int)num; | ||
641 | return (((n >> 6)) & 0x3f); | ||
642 | } | ||
643 | |||
644 | static __inline unsigned int | ||
645 | get_SrcA_Y1(tilegx_bundle_bits n) | ||
646 | { | ||
647 | return (((unsigned int)(n >> 37)) & 0x3f); | ||
648 | } | ||
649 | |||
650 | static __inline unsigned int | ||
651 | get_SrcA_Y2(tilegx_bundle_bits num) | ||
652 | { | ||
653 | const unsigned int n = (unsigned int)num; | ||
654 | return (((n >> 20)) & 0x3f); | ||
655 | } | ||
656 | |||
657 | static __inline unsigned int | ||
658 | get_SrcBDest_Y2(tilegx_bundle_bits n) | ||
659 | { | ||
660 | return (((unsigned int)(n >> 51)) & 0x3f); | ||
661 | } | ||
662 | |||
663 | static __inline unsigned int | ||
664 | get_SrcB_X0(tilegx_bundle_bits num) | ||
665 | { | ||
666 | const unsigned int n = (unsigned int)num; | ||
667 | return (((n >> 12)) & 0x3f); | ||
668 | } | ||
669 | |||
670 | static __inline unsigned int | ||
671 | get_SrcB_X1(tilegx_bundle_bits n) | ||
672 | { | ||
673 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
674 | } | ||
675 | |||
676 | static __inline unsigned int | ||
677 | get_SrcB_Y0(tilegx_bundle_bits num) | ||
678 | { | ||
679 | const unsigned int n = (unsigned int)num; | ||
680 | return (((n >> 12)) & 0x3f); | ||
681 | } | ||
682 | |||
683 | static __inline unsigned int | ||
684 | get_SrcB_Y1(tilegx_bundle_bits n) | ||
685 | { | ||
686 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
687 | } | ||
688 | |||
689 | static __inline unsigned int | ||
690 | get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num) | ||
691 | { | ||
692 | const unsigned int n = (unsigned int)num; | ||
693 | return (((n >> 12)) & 0x3f); | ||
694 | } | ||
695 | |||
696 | static __inline unsigned int | ||
697 | get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n) | ||
698 | { | ||
699 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
700 | } | ||
701 | |||
702 | static __inline unsigned int | ||
703 | get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num) | ||
704 | { | ||
705 | const unsigned int n = (unsigned int)num; | ||
706 | return (((n >> 12)) & 0x3f); | ||
707 | } | ||
708 | |||
709 | static __inline unsigned int | ||
710 | get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n) | ||
711 | { | ||
712 | return (((unsigned int)(n >> 43)) & 0x3f); | ||
713 | } | ||
714 | |||
715 | |||
716 | static __inline int | ||
717 | sign_extend(int n, int num_bits) | ||
718 | { | ||
719 | int shift = (int)(sizeof(int) * 8 - num_bits); | ||
720 | return (n << shift) >> shift; | ||
721 | } | ||
722 | |||
723 | |||
724 | |||
725 | static __inline tilegx_bundle_bits | ||
726 | create_BFEnd_X0(int num) | ||
727 | { | ||
728 | const unsigned int n = (unsigned int)num; | ||
729 | return ((n & 0x3f) << 12); | ||
730 | } | ||
731 | |||
732 | static __inline tilegx_bundle_bits | ||
733 | create_BFOpcodeExtension_X0(int num) | ||
734 | { | ||
735 | const unsigned int n = (unsigned int)num; | ||
736 | return ((n & 0xf) << 24); | ||
737 | } | ||
738 | |||
739 | static __inline tilegx_bundle_bits | ||
740 | create_BFStart_X0(int num) | ||
741 | { | ||
742 | const unsigned int n = (unsigned int)num; | ||
743 | return ((n & 0x3f) << 18); | ||
744 | } | ||
745 | |||
746 | static __inline tilegx_bundle_bits | ||
747 | create_BrOff_X1(int num) | ||
748 | { | ||
749 | const unsigned int n = (unsigned int)num; | ||
750 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
751 | (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37); | ||
752 | } | ||
753 | |||
754 | static __inline tilegx_bundle_bits | ||
755 | create_BrType_X1(int num) | ||
756 | { | ||
757 | const unsigned int n = (unsigned int)num; | ||
758 | return (((tilegx_bundle_bits)(n & 0x1f)) << 54); | ||
759 | } | ||
760 | |||
761 | static __inline tilegx_bundle_bits | ||
762 | create_Dest_Imm8_X1(int num) | ||
763 | { | ||
764 | const unsigned int n = (unsigned int)num; | ||
765 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
766 | (((tilegx_bundle_bits)(n & 0x000000c0)) << 43); | ||
767 | } | ||
768 | |||
769 | static __inline tilegx_bundle_bits | ||
770 | create_Dest_X0(int num) | ||
771 | { | ||
772 | const unsigned int n = (unsigned int)num; | ||
773 | return ((n & 0x3f) << 0); | ||
774 | } | ||
775 | |||
776 | static __inline tilegx_bundle_bits | ||
777 | create_Dest_X1(int num) | ||
778 | { | ||
779 | const unsigned int n = (unsigned int)num; | ||
780 | return (((tilegx_bundle_bits)(n & 0x3f)) << 31); | ||
781 | } | ||
782 | |||
783 | static __inline tilegx_bundle_bits | ||
784 | create_Dest_Y0(int num) | ||
785 | { | ||
786 | const unsigned int n = (unsigned int)num; | ||
787 | return ((n & 0x3f) << 0); | ||
788 | } | ||
789 | |||
790 | static __inline tilegx_bundle_bits | ||
791 | create_Dest_Y1(int num) | ||
792 | { | ||
793 | const unsigned int n = (unsigned int)num; | ||
794 | return (((tilegx_bundle_bits)(n & 0x3f)) << 31); | ||
795 | } | ||
796 | |||
797 | static __inline tilegx_bundle_bits | ||
798 | create_Imm16_X0(int num) | ||
799 | { | ||
800 | const unsigned int n = (unsigned int)num; | ||
801 | return ((n & 0xffff) << 12); | ||
802 | } | ||
803 | |||
804 | static __inline tilegx_bundle_bits | ||
805 | create_Imm16_X1(int num) | ||
806 | { | ||
807 | const unsigned int n = (unsigned int)num; | ||
808 | return (((tilegx_bundle_bits)(n & 0xffff)) << 43); | ||
809 | } | ||
810 | |||
811 | static __inline tilegx_bundle_bits | ||
812 | create_Imm8OpcodeExtension_X0(int num) | ||
813 | { | ||
814 | const unsigned int n = (unsigned int)num; | ||
815 | return ((n & 0xff) << 20); | ||
816 | } | ||
817 | |||
818 | static __inline tilegx_bundle_bits | ||
819 | create_Imm8OpcodeExtension_X1(int num) | ||
820 | { | ||
821 | const unsigned int n = (unsigned int)num; | ||
822 | return (((tilegx_bundle_bits)(n & 0xff)) << 51); | ||
823 | } | ||
824 | |||
825 | static __inline tilegx_bundle_bits | ||
826 | create_Imm8_X0(int num) | ||
827 | { | ||
828 | const unsigned int n = (unsigned int)num; | ||
829 | return ((n & 0xff) << 12); | ||
830 | } | ||
831 | |||
832 | static __inline tilegx_bundle_bits | ||
833 | create_Imm8_X1(int num) | ||
834 | { | ||
835 | const unsigned int n = (unsigned int)num; | ||
836 | return (((tilegx_bundle_bits)(n & 0xff)) << 43); | ||
837 | } | ||
838 | |||
839 | static __inline tilegx_bundle_bits | ||
840 | create_Imm8_Y0(int num) | ||
841 | { | ||
842 | const unsigned int n = (unsigned int)num; | ||
843 | return ((n & 0xff) << 12); | ||
844 | } | ||
845 | |||
846 | static __inline tilegx_bundle_bits | ||
847 | create_Imm8_Y1(int num) | ||
848 | { | ||
849 | const unsigned int n = (unsigned int)num; | ||
850 | return (((tilegx_bundle_bits)(n & 0xff)) << 43); | ||
851 | } | ||
852 | |||
853 | static __inline tilegx_bundle_bits | ||
854 | create_JumpOff_X1(int num) | ||
855 | { | ||
856 | const unsigned int n = (unsigned int)num; | ||
857 | return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31); | ||
858 | } | ||
859 | |||
860 | static __inline tilegx_bundle_bits | ||
861 | create_JumpOpcodeExtension_X1(int num) | ||
862 | { | ||
863 | const unsigned int n = (unsigned int)num; | ||
864 | return (((tilegx_bundle_bits)(n & 0x1)) << 58); | ||
865 | } | ||
866 | |||
867 | static __inline tilegx_bundle_bits | ||
868 | create_MF_Imm14_X1(int num) | ||
869 | { | ||
870 | const unsigned int n = (unsigned int)num; | ||
871 | return (((tilegx_bundle_bits)(n & 0x3fff)) << 37); | ||
872 | } | ||
873 | |||
874 | static __inline tilegx_bundle_bits | ||
875 | create_MT_Imm14_X1(int num) | ||
876 | { | ||
877 | const unsigned int n = (unsigned int)num; | ||
878 | return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) | | ||
879 | (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37); | ||
880 | } | ||
881 | |||
882 | static __inline tilegx_bundle_bits | ||
883 | create_Mode(int num) | ||
884 | { | ||
885 | const unsigned int n = (unsigned int)num; | ||
886 | return (((tilegx_bundle_bits)(n & 0x3)) << 62); | ||
887 | } | ||
888 | |||
889 | static __inline tilegx_bundle_bits | ||
890 | create_Opcode_X0(int num) | ||
891 | { | ||
892 | const unsigned int n = (unsigned int)num; | ||
893 | return ((n & 0x7) << 28); | ||
894 | } | ||
895 | |||
896 | static __inline tilegx_bundle_bits | ||
897 | create_Opcode_X1(int num) | ||
898 | { | ||
899 | const unsigned int n = (unsigned int)num; | ||
900 | return (((tilegx_bundle_bits)(n & 0x7)) << 59); | ||
901 | } | ||
902 | |||
903 | static __inline tilegx_bundle_bits | ||
904 | create_Opcode_Y0(int num) | ||
905 | { | ||
906 | const unsigned int n = (unsigned int)num; | ||
907 | return ((n & 0xf) << 27); | ||
908 | } | ||
909 | |||
910 | static __inline tilegx_bundle_bits | ||
911 | create_Opcode_Y1(int num) | ||
912 | { | ||
913 | const unsigned int n = (unsigned int)num; | ||
914 | return (((tilegx_bundle_bits)(n & 0xf)) << 58); | ||
915 | } | ||
916 | |||
917 | static __inline tilegx_bundle_bits | ||
918 | create_Opcode_Y2(int num) | ||
919 | { | ||
920 | const unsigned int n = (unsigned int)num; | ||
921 | return ((n & 0x00000001) << 26) | | ||
922 | (((tilegx_bundle_bits)(n & 0x00000002)) << 56); | ||
923 | } | ||
924 | |||
925 | static __inline tilegx_bundle_bits | ||
926 | create_RRROpcodeExtension_X0(int num) | ||
927 | { | ||
928 | const unsigned int n = (unsigned int)num; | ||
929 | return ((n & 0x3ff) << 18); | ||
930 | } | ||
931 | |||
932 | static __inline tilegx_bundle_bits | ||
933 | create_RRROpcodeExtension_X1(int num) | ||
934 | { | ||
935 | const unsigned int n = (unsigned int)num; | ||
936 | return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); | ||
937 | } | ||
938 | |||
939 | static __inline tilegx_bundle_bits | ||
940 | create_RRROpcodeExtension_Y0(int num) | ||
941 | { | ||
942 | const unsigned int n = (unsigned int)num; | ||
943 | return ((n & 0x3) << 18); | ||
944 | } | ||
945 | |||
946 | static __inline tilegx_bundle_bits | ||
947 | create_RRROpcodeExtension_Y1(int num) | ||
948 | { | ||
949 | const unsigned int n = (unsigned int)num; | ||
950 | return (((tilegx_bundle_bits)(n & 0x3)) << 49); | ||
951 | } | ||
952 | |||
953 | static __inline tilegx_bundle_bits | ||
954 | create_ShAmt_X0(int num) | ||
955 | { | ||
956 | const unsigned int n = (unsigned int)num; | ||
957 | return ((n & 0x3f) << 12); | ||
958 | } | ||
959 | |||
960 | static __inline tilegx_bundle_bits | ||
961 | create_ShAmt_X1(int num) | ||
962 | { | ||
963 | const unsigned int n = (unsigned int)num; | ||
964 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
965 | } | ||
966 | |||
967 | static __inline tilegx_bundle_bits | ||
968 | create_ShAmt_Y0(int num) | ||
969 | { | ||
970 | const unsigned int n = (unsigned int)num; | ||
971 | return ((n & 0x3f) << 12); | ||
972 | } | ||
973 | |||
974 | static __inline tilegx_bundle_bits | ||
975 | create_ShAmt_Y1(int num) | ||
976 | { | ||
977 | const unsigned int n = (unsigned int)num; | ||
978 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
979 | } | ||
980 | |||
981 | static __inline tilegx_bundle_bits | ||
982 | create_ShiftOpcodeExtension_X0(int num) | ||
983 | { | ||
984 | const unsigned int n = (unsigned int)num; | ||
985 | return ((n & 0x3ff) << 18); | ||
986 | } | ||
987 | |||
988 | static __inline tilegx_bundle_bits | ||
989 | create_ShiftOpcodeExtension_X1(int num) | ||
990 | { | ||
991 | const unsigned int n = (unsigned int)num; | ||
992 | return (((tilegx_bundle_bits)(n & 0x3ff)) << 49); | ||
993 | } | ||
994 | |||
995 | static __inline tilegx_bundle_bits | ||
996 | create_ShiftOpcodeExtension_Y0(int num) | ||
997 | { | ||
998 | const unsigned int n = (unsigned int)num; | ||
999 | return ((n & 0x3) << 18); | ||
1000 | } | ||
1001 | |||
1002 | static __inline tilegx_bundle_bits | ||
1003 | create_ShiftOpcodeExtension_Y1(int num) | ||
1004 | { | ||
1005 | const unsigned int n = (unsigned int)num; | ||
1006 | return (((tilegx_bundle_bits)(n & 0x3)) << 49); | ||
1007 | } | ||
1008 | |||
1009 | static __inline tilegx_bundle_bits | ||
1010 | create_SrcA_X0(int num) | ||
1011 | { | ||
1012 | const unsigned int n = (unsigned int)num; | ||
1013 | return ((n & 0x3f) << 6); | ||
1014 | } | ||
1015 | |||
1016 | static __inline tilegx_bundle_bits | ||
1017 | create_SrcA_X1(int num) | ||
1018 | { | ||
1019 | const unsigned int n = (unsigned int)num; | ||
1020 | return (((tilegx_bundle_bits)(n & 0x3f)) << 37); | ||
1021 | } | ||
1022 | |||
1023 | static __inline tilegx_bundle_bits | ||
1024 | create_SrcA_Y0(int num) | ||
1025 | { | ||
1026 | const unsigned int n = (unsigned int)num; | ||
1027 | return ((n & 0x3f) << 6); | ||
1028 | } | ||
1029 | |||
1030 | static __inline tilegx_bundle_bits | ||
1031 | create_SrcA_Y1(int num) | ||
1032 | { | ||
1033 | const unsigned int n = (unsigned int)num; | ||
1034 | return (((tilegx_bundle_bits)(n & 0x3f)) << 37); | ||
1035 | } | ||
1036 | |||
1037 | static __inline tilegx_bundle_bits | ||
1038 | create_SrcA_Y2(int num) | ||
1039 | { | ||
1040 | const unsigned int n = (unsigned int)num; | ||
1041 | return ((n & 0x3f) << 20); | ||
1042 | } | ||
1043 | |||
1044 | static __inline tilegx_bundle_bits | ||
1045 | create_SrcBDest_Y2(int num) | ||
1046 | { | ||
1047 | const unsigned int n = (unsigned int)num; | ||
1048 | return (((tilegx_bundle_bits)(n & 0x3f)) << 51); | ||
1049 | } | ||
1050 | |||
1051 | static __inline tilegx_bundle_bits | ||
1052 | create_SrcB_X0(int num) | ||
1053 | { | ||
1054 | const unsigned int n = (unsigned int)num; | ||
1055 | return ((n & 0x3f) << 12); | ||
1056 | } | ||
1057 | |||
1058 | static __inline tilegx_bundle_bits | ||
1059 | create_SrcB_X1(int num) | ||
1060 | { | ||
1061 | const unsigned int n = (unsigned int)num; | ||
1062 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
1063 | } | ||
1064 | |||
1065 | static __inline tilegx_bundle_bits | ||
1066 | create_SrcB_Y0(int num) | ||
1067 | { | ||
1068 | const unsigned int n = (unsigned int)num; | ||
1069 | return ((n & 0x3f) << 12); | ||
1070 | } | ||
1071 | |||
1072 | static __inline tilegx_bundle_bits | ||
1073 | create_SrcB_Y1(int num) | ||
1074 | { | ||
1075 | const unsigned int n = (unsigned int)num; | ||
1076 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
1077 | } | ||
1078 | |||
1079 | static __inline tilegx_bundle_bits | ||
1080 | create_UnaryOpcodeExtension_X0(int num) | ||
1081 | { | ||
1082 | const unsigned int n = (unsigned int)num; | ||
1083 | return ((n & 0x3f) << 12); | ||
1084 | } | ||
1085 | |||
1086 | static __inline tilegx_bundle_bits | ||
1087 | create_UnaryOpcodeExtension_X1(int num) | ||
1088 | { | ||
1089 | const unsigned int n = (unsigned int)num; | ||
1090 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
1091 | } | ||
1092 | |||
1093 | static __inline tilegx_bundle_bits | ||
1094 | create_UnaryOpcodeExtension_Y0(int num) | ||
1095 | { | ||
1096 | const unsigned int n = (unsigned int)num; | ||
1097 | return ((n & 0x3f) << 12); | ||
1098 | } | ||
1099 | |||
1100 | static __inline tilegx_bundle_bits | ||
1101 | create_UnaryOpcodeExtension_Y1(int num) | ||
1102 | { | ||
1103 | const unsigned int n = (unsigned int)num; | ||
1104 | return (((tilegx_bundle_bits)(n & 0x3f)) << 43); | ||
1105 | } | ||
1106 | |||
1107 | |||
1108 | typedef enum | ||
1109 | { | ||
1110 | TILEGX_PIPELINE_X0, | ||
1111 | TILEGX_PIPELINE_X1, | ||
1112 | TILEGX_PIPELINE_Y0, | ||
1113 | TILEGX_PIPELINE_Y1, | ||
1114 | TILEGX_PIPELINE_Y2, | ||
1115 | } tilegx_pipeline; | ||
1116 | |||
1117 | #define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1) | ||
1118 | |||
1119 | typedef enum | ||
1120 | { | ||
1121 | TILEGX_OP_TYPE_REGISTER, | ||
1122 | TILEGX_OP_TYPE_IMMEDIATE, | ||
1123 | TILEGX_OP_TYPE_ADDRESS, | ||
1124 | TILEGX_OP_TYPE_SPR | ||
1125 | } tilegx_operand_type; | ||
1126 | |||
1127 | /* These are the bits that determine if a bundle is in the X encoding. */ | ||
1128 | #define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62) | ||
1129 | |||
1130 | enum | ||
1131 | { | ||
1132 | /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */ | ||
1133 | TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3, | ||
1134 | |||
1135 | /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */ | ||
1136 | TILEGX_NUM_PIPELINE_ENCODINGS = 5, | ||
1137 | |||
1138 | /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */ | ||
1139 | TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3, | ||
1140 | |||
1141 | /* Instructions take this many bytes. */ | ||
1142 | TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES, | ||
1143 | |||
1144 | /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */ | ||
1145 | TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3, | ||
1146 | |||
1147 | /* Bundles should be aligned modulo this number of bytes. */ | ||
1148 | TILEGX_BUNDLE_ALIGNMENT_IN_BYTES = | ||
1149 | (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES), | ||
1150 | |||
1151 | /* Number of registers (some are magic, such as network I/O). */ | ||
1152 | TILEGX_NUM_REGISTERS = 64, | ||
1153 | }; | ||
1154 | |||
1155 | |||
1156 | struct tilegx_operand | ||
1157 | { | ||
1158 | /* Is this operand a register, immediate or address? */ | ||
1159 | tilegx_operand_type type; | ||
1160 | |||
1161 | /* The default relocation type for this operand. */ | ||
1162 | signed int default_reloc : 16; | ||
1163 | |||
1164 | /* How many bits is this value? (used for range checking) */ | ||
1165 | unsigned int num_bits : 5; | ||
1166 | |||
1167 | /* Is the value signed? (used for range checking) */ | ||
1168 | unsigned int is_signed : 1; | ||
1169 | |||
1170 | /* Is this operand a source register? */ | ||
1171 | unsigned int is_src_reg : 1; | ||
1172 | |||
1173 | /* Is this operand written? (i.e. is it a destination register) */ | ||
1174 | unsigned int is_dest_reg : 1; | ||
1175 | |||
1176 | /* Is this operand PC-relative? */ | ||
1177 | unsigned int is_pc_relative : 1; | ||
1178 | |||
1179 | /* By how many bits do we right shift the value before inserting? */ | ||
1180 | unsigned int rightshift : 2; | ||
1181 | |||
1182 | /* Return the bits for this operand to be ORed into an existing bundle. */ | ||
1183 | tilegx_bundle_bits (*insert) (int op); | ||
1184 | |||
1185 | /* Extract this operand and return it. */ | ||
1186 | unsigned int (*extract) (tilegx_bundle_bits bundle); | ||
1187 | }; | ||
1188 | |||
1189 | |||
1190 | extern const struct tilegx_operand tilegx_operands[]; | ||
1191 | |||
1192 | /* One finite-state machine per pipe for rapid instruction decoding. */ | ||
1193 | extern const unsigned short * const | ||
1194 | tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS]; | ||
1195 | |||
1196 | |||
1197 | struct tilegx_opcode | ||
1198 | { | ||
1199 | /* The opcode mnemonic, e.g. "add" */ | ||
1200 | const char *name; | ||
1201 | |||
1202 | /* The enum value for this mnemonic. */ | ||
1203 | tilegx_mnemonic mnemonic; | ||
1204 | |||
1205 | /* A bit mask of which of the five pipes this instruction | ||
1206 | is compatible with: | ||
1207 | X0 0x01 | ||
1208 | X1 0x02 | ||
1209 | Y0 0x04 | ||
1210 | Y1 0x08 | ||
1211 | Y2 0x10 */ | ||
1212 | unsigned char pipes; | ||
1213 | |||
1214 | /* How many operands are there? */ | ||
1215 | unsigned char num_operands; | ||
1216 | |||
1217 | /* Which register does this write implicitly, or TREG_ZERO if none? */ | ||
1218 | unsigned char implicitly_written_register; | ||
1219 | |||
1220 | /* Can this be bundled with other instructions (almost always true). */ | ||
1221 | unsigned char can_bundle; | ||
1222 | |||
1223 | /* The description of the operands. Each of these is an | ||
1224 | * index into the tilegx_operands[] table. */ | ||
1225 | unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS]; | ||
1226 | |||
1227 | }; | ||
1228 | |||
1229 | extern const struct tilegx_opcode tilegx_opcodes[]; | ||
1230 | |||
1231 | /* Used for non-textual disassembly into structs. */ | ||
1232 | struct tilegx_decoded_instruction | ||
1233 | { | ||
1234 | const struct tilegx_opcode *opcode; | ||
1235 | const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS]; | ||
1236 | long long operand_values[TILEGX_MAX_OPERANDS]; | ||
1237 | }; | ||
1238 | |||
1239 | |||
1240 | /* Disassemble a bundle into a struct for machine processing. */ | ||
1241 | extern int parse_insn_tilegx(tilegx_bundle_bits bits, | ||
1242 | unsigned long long pc, | ||
1243 | struct tilegx_decoded_instruction | ||
1244 | decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]); | ||
1245 | |||
1246 | |||
1247 | |||
1248 | #endif /* opcode_tilegx_h */ | ||
diff --git a/arch/tile/include/asm/opcode_constants_32.h b/arch/tile/include/asm/opcode_constants_32.h deleted file mode 100644 index 227d033b180c..000000000000 --- a/arch/tile/include/asm/opcode_constants_32.h +++ /dev/null | |||
@@ -1,480 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or | ||
5 | * modify it under the terms of the GNU General Public License | ||
6 | * as published by the Free Software Foundation, version 2. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but | ||
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
11 | * NON INFRINGEMENT. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /* This file is machine-generated; DO NOT EDIT! */ | ||
16 | |||
17 | |||
18 | #ifndef _TILE_OPCODE_CONSTANTS_H | ||
19 | #define _TILE_OPCODE_CONSTANTS_H | ||
20 | enum | ||
21 | { | ||
22 | ADDBS_U_SPECIAL_0_OPCODE_X0 = 98, | ||
23 | ADDBS_U_SPECIAL_0_OPCODE_X1 = 68, | ||
24 | ADDB_SPECIAL_0_OPCODE_X0 = 1, | ||
25 | ADDB_SPECIAL_0_OPCODE_X1 = 1, | ||
26 | ADDHS_SPECIAL_0_OPCODE_X0 = 99, | ||
27 | ADDHS_SPECIAL_0_OPCODE_X1 = 69, | ||
28 | ADDH_SPECIAL_0_OPCODE_X0 = 2, | ||
29 | ADDH_SPECIAL_0_OPCODE_X1 = 2, | ||
30 | ADDIB_IMM_0_OPCODE_X0 = 1, | ||
31 | ADDIB_IMM_0_OPCODE_X1 = 1, | ||
32 | ADDIH_IMM_0_OPCODE_X0 = 2, | ||
33 | ADDIH_IMM_0_OPCODE_X1 = 2, | ||
34 | ADDI_IMM_0_OPCODE_X0 = 3, | ||
35 | ADDI_IMM_0_OPCODE_X1 = 3, | ||
36 | ADDI_IMM_1_OPCODE_SN = 1, | ||
37 | ADDI_OPCODE_Y0 = 9, | ||
38 | ADDI_OPCODE_Y1 = 7, | ||
39 | ADDLIS_OPCODE_X0 = 1, | ||
40 | ADDLIS_OPCODE_X1 = 2, | ||
41 | ADDLI_OPCODE_X0 = 2, | ||
42 | ADDLI_OPCODE_X1 = 3, | ||
43 | ADDS_SPECIAL_0_OPCODE_X0 = 96, | ||
44 | ADDS_SPECIAL_0_OPCODE_X1 = 66, | ||
45 | ADD_SPECIAL_0_OPCODE_X0 = 3, | ||
46 | ADD_SPECIAL_0_OPCODE_X1 = 3, | ||
47 | ADD_SPECIAL_0_OPCODE_Y0 = 0, | ||
48 | ADD_SPECIAL_0_OPCODE_Y1 = 0, | ||
49 | ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4, | ||
50 | ADIFFH_SPECIAL_0_OPCODE_X0 = 5, | ||
51 | ANDI_IMM_0_OPCODE_X0 = 1, | ||
52 | ANDI_IMM_0_OPCODE_X1 = 4, | ||
53 | ANDI_OPCODE_Y0 = 10, | ||
54 | ANDI_OPCODE_Y1 = 8, | ||
55 | AND_SPECIAL_0_OPCODE_X0 = 6, | ||
56 | AND_SPECIAL_0_OPCODE_X1 = 4, | ||
57 | AND_SPECIAL_2_OPCODE_Y0 = 0, | ||
58 | AND_SPECIAL_2_OPCODE_Y1 = 0, | ||
59 | AULI_OPCODE_X0 = 3, | ||
60 | AULI_OPCODE_X1 = 4, | ||
61 | AVGB_U_SPECIAL_0_OPCODE_X0 = 7, | ||
62 | AVGH_SPECIAL_0_OPCODE_X0 = 8, | ||
63 | BBNST_BRANCH_OPCODE_X1 = 15, | ||
64 | BBNS_BRANCH_OPCODE_X1 = 14, | ||
65 | BBNS_OPCODE_SN = 63, | ||
66 | BBST_BRANCH_OPCODE_X1 = 13, | ||
67 | BBS_BRANCH_OPCODE_X1 = 12, | ||
68 | BBS_OPCODE_SN = 62, | ||
69 | BGEZT_BRANCH_OPCODE_X1 = 7, | ||
70 | BGEZ_BRANCH_OPCODE_X1 = 6, | ||
71 | BGEZ_OPCODE_SN = 61, | ||
72 | BGZT_BRANCH_OPCODE_X1 = 5, | ||
73 | BGZ_BRANCH_OPCODE_X1 = 4, | ||
74 | BGZ_OPCODE_SN = 58, | ||
75 | BITX_UN_0_SHUN_0_OPCODE_X0 = 1, | ||
76 | BITX_UN_0_SHUN_0_OPCODE_Y0 = 1, | ||
77 | BLEZT_BRANCH_OPCODE_X1 = 11, | ||
78 | BLEZ_BRANCH_OPCODE_X1 = 10, | ||
79 | BLEZ_OPCODE_SN = 59, | ||
80 | BLZT_BRANCH_OPCODE_X1 = 9, | ||
81 | BLZ_BRANCH_OPCODE_X1 = 8, | ||
82 | BLZ_OPCODE_SN = 60, | ||
83 | BNZT_BRANCH_OPCODE_X1 = 3, | ||
84 | BNZ_BRANCH_OPCODE_X1 = 2, | ||
85 | BNZ_OPCODE_SN = 57, | ||
86 | BPT_NOREG_RR_IMM_0_OPCODE_SN = 1, | ||
87 | BRANCH_OPCODE_X1 = 5, | ||
88 | BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2, | ||
89 | BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2, | ||
90 | BZT_BRANCH_OPCODE_X1 = 1, | ||
91 | BZ_BRANCH_OPCODE_X1 = 0, | ||
92 | BZ_OPCODE_SN = 56, | ||
93 | CLZ_UN_0_SHUN_0_OPCODE_X0 = 3, | ||
94 | CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3, | ||
95 | CRC32_32_SPECIAL_0_OPCODE_X0 = 9, | ||
96 | CRC32_8_SPECIAL_0_OPCODE_X0 = 10, | ||
97 | CTZ_UN_0_SHUN_0_OPCODE_X0 = 4, | ||
98 | CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4, | ||
99 | DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1, | ||
100 | DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2, | ||
101 | DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95, | ||
102 | FINV_UN_0_SHUN_0_OPCODE_X1 = 3, | ||
103 | FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4, | ||
104 | FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3, | ||
105 | FNOP_UN_0_SHUN_0_OPCODE_X0 = 5, | ||
106 | FNOP_UN_0_SHUN_0_OPCODE_X1 = 5, | ||
107 | FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5, | ||
108 | FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1, | ||
109 | HALT_NOREG_RR_IMM_0_OPCODE_SN = 0, | ||
110 | ICOH_UN_0_SHUN_0_OPCODE_X1 = 6, | ||
111 | ILL_UN_0_SHUN_0_OPCODE_X1 = 7, | ||
112 | ILL_UN_0_SHUN_0_OPCODE_Y1 = 2, | ||
113 | IMM_0_OPCODE_SN = 0, | ||
114 | IMM_0_OPCODE_X0 = 4, | ||
115 | IMM_0_OPCODE_X1 = 6, | ||
116 | IMM_1_OPCODE_SN = 1, | ||
117 | IMM_OPCODE_0_X0 = 5, | ||
118 | INTHB_SPECIAL_0_OPCODE_X0 = 11, | ||
119 | INTHB_SPECIAL_0_OPCODE_X1 = 5, | ||
120 | INTHH_SPECIAL_0_OPCODE_X0 = 12, | ||
121 | INTHH_SPECIAL_0_OPCODE_X1 = 6, | ||
122 | INTLB_SPECIAL_0_OPCODE_X0 = 13, | ||
123 | INTLB_SPECIAL_0_OPCODE_X1 = 7, | ||
124 | INTLH_SPECIAL_0_OPCODE_X0 = 14, | ||
125 | INTLH_SPECIAL_0_OPCODE_X1 = 8, | ||
126 | INV_UN_0_SHUN_0_OPCODE_X1 = 8, | ||
127 | IRET_UN_0_SHUN_0_OPCODE_X1 = 9, | ||
128 | JALB_OPCODE_X1 = 13, | ||
129 | JALF_OPCODE_X1 = 12, | ||
130 | JALRP_SPECIAL_0_OPCODE_X1 = 9, | ||
131 | JALRR_IMM_1_OPCODE_SN = 3, | ||
132 | JALR_RR_IMM_0_OPCODE_SN = 5, | ||
133 | JALR_SPECIAL_0_OPCODE_X1 = 10, | ||
134 | JB_OPCODE_X1 = 11, | ||
135 | JF_OPCODE_X1 = 10, | ||
136 | JRP_SPECIAL_0_OPCODE_X1 = 11, | ||
137 | JRR_IMM_1_OPCODE_SN = 2, | ||
138 | JR_RR_IMM_0_OPCODE_SN = 4, | ||
139 | JR_SPECIAL_0_OPCODE_X1 = 12, | ||
140 | LBADD_IMM_0_OPCODE_X1 = 22, | ||
141 | LBADD_U_IMM_0_OPCODE_X1 = 23, | ||
142 | LB_OPCODE_Y2 = 0, | ||
143 | LB_UN_0_SHUN_0_OPCODE_X1 = 10, | ||
144 | LB_U_OPCODE_Y2 = 1, | ||
145 | LB_U_UN_0_SHUN_0_OPCODE_X1 = 11, | ||
146 | LHADD_IMM_0_OPCODE_X1 = 24, | ||
147 | LHADD_U_IMM_0_OPCODE_X1 = 25, | ||
148 | LH_OPCODE_Y2 = 2, | ||
149 | LH_UN_0_SHUN_0_OPCODE_X1 = 12, | ||
150 | LH_U_OPCODE_Y2 = 3, | ||
151 | LH_U_UN_0_SHUN_0_OPCODE_X1 = 13, | ||
152 | LNK_SPECIAL_0_OPCODE_X1 = 13, | ||
153 | LWADD_IMM_0_OPCODE_X1 = 26, | ||
154 | LWADD_NA_IMM_0_OPCODE_X1 = 27, | ||
155 | LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24, | ||
156 | LW_OPCODE_Y2 = 4, | ||
157 | LW_UN_0_SHUN_0_OPCODE_X1 = 14, | ||
158 | MAXB_U_SPECIAL_0_OPCODE_X0 = 15, | ||
159 | MAXB_U_SPECIAL_0_OPCODE_X1 = 14, | ||
160 | MAXH_SPECIAL_0_OPCODE_X0 = 16, | ||
161 | MAXH_SPECIAL_0_OPCODE_X1 = 15, | ||
162 | MAXIB_U_IMM_0_OPCODE_X0 = 4, | ||
163 | MAXIB_U_IMM_0_OPCODE_X1 = 5, | ||
164 | MAXIH_IMM_0_OPCODE_X0 = 5, | ||
165 | MAXIH_IMM_0_OPCODE_X1 = 6, | ||
166 | MFSPR_IMM_0_OPCODE_X1 = 7, | ||
167 | MF_UN_0_SHUN_0_OPCODE_X1 = 15, | ||
168 | MINB_U_SPECIAL_0_OPCODE_X0 = 17, | ||
169 | MINB_U_SPECIAL_0_OPCODE_X1 = 16, | ||
170 | MINH_SPECIAL_0_OPCODE_X0 = 18, | ||
171 | MINH_SPECIAL_0_OPCODE_X1 = 17, | ||
172 | MINIB_U_IMM_0_OPCODE_X0 = 6, | ||
173 | MINIB_U_IMM_0_OPCODE_X1 = 8, | ||
174 | MINIH_IMM_0_OPCODE_X0 = 7, | ||
175 | MINIH_IMM_0_OPCODE_X1 = 9, | ||
176 | MM_OPCODE_X0 = 6, | ||
177 | MM_OPCODE_X1 = 7, | ||
178 | MNZB_SPECIAL_0_OPCODE_X0 = 19, | ||
179 | MNZB_SPECIAL_0_OPCODE_X1 = 18, | ||
180 | MNZH_SPECIAL_0_OPCODE_X0 = 20, | ||
181 | MNZH_SPECIAL_0_OPCODE_X1 = 19, | ||
182 | MNZ_SPECIAL_0_OPCODE_X0 = 21, | ||
183 | MNZ_SPECIAL_0_OPCODE_X1 = 20, | ||
184 | MNZ_SPECIAL_1_OPCODE_Y0 = 0, | ||
185 | MNZ_SPECIAL_1_OPCODE_Y1 = 1, | ||
186 | MOVEI_IMM_1_OPCODE_SN = 0, | ||
187 | MOVE_RR_IMM_0_OPCODE_SN = 8, | ||
188 | MTSPR_IMM_0_OPCODE_X1 = 10, | ||
189 | MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22, | ||
190 | MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0, | ||
191 | MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23, | ||
192 | MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24, | ||
193 | MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1, | ||
194 | MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25, | ||
195 | MULHH_SS_SPECIAL_0_OPCODE_X0 = 26, | ||
196 | MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0, | ||
197 | MULHH_SU_SPECIAL_0_OPCODE_X0 = 27, | ||
198 | MULHH_UU_SPECIAL_0_OPCODE_X0 = 28, | ||
199 | MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1, | ||
200 | MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29, | ||
201 | MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30, | ||
202 | MULHLA_US_SPECIAL_0_OPCODE_X0 = 31, | ||
203 | MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32, | ||
204 | MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33, | ||
205 | MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0, | ||
206 | MULHL_SS_SPECIAL_0_OPCODE_X0 = 34, | ||
207 | MULHL_SU_SPECIAL_0_OPCODE_X0 = 35, | ||
208 | MULHL_US_SPECIAL_0_OPCODE_X0 = 36, | ||
209 | MULHL_UU_SPECIAL_0_OPCODE_X0 = 37, | ||
210 | MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38, | ||
211 | MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2, | ||
212 | MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39, | ||
213 | MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40, | ||
214 | MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3, | ||
215 | MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41, | ||
216 | MULLL_SS_SPECIAL_0_OPCODE_X0 = 42, | ||
217 | MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2, | ||
218 | MULLL_SU_SPECIAL_0_OPCODE_X0 = 43, | ||
219 | MULLL_UU_SPECIAL_0_OPCODE_X0 = 44, | ||
220 | MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3, | ||
221 | MVNZ_SPECIAL_0_OPCODE_X0 = 45, | ||
222 | MVNZ_SPECIAL_1_OPCODE_Y0 = 1, | ||
223 | MVZ_SPECIAL_0_OPCODE_X0 = 46, | ||
224 | MVZ_SPECIAL_1_OPCODE_Y0 = 2, | ||
225 | MZB_SPECIAL_0_OPCODE_X0 = 47, | ||
226 | MZB_SPECIAL_0_OPCODE_X1 = 21, | ||
227 | MZH_SPECIAL_0_OPCODE_X0 = 48, | ||
228 | MZH_SPECIAL_0_OPCODE_X1 = 22, | ||
229 | MZ_SPECIAL_0_OPCODE_X0 = 49, | ||
230 | MZ_SPECIAL_0_OPCODE_X1 = 23, | ||
231 | MZ_SPECIAL_1_OPCODE_Y0 = 3, | ||
232 | MZ_SPECIAL_1_OPCODE_Y1 = 2, | ||
233 | NAP_UN_0_SHUN_0_OPCODE_X1 = 16, | ||
234 | NOP_NOREG_RR_IMM_0_OPCODE_SN = 2, | ||
235 | NOP_UN_0_SHUN_0_OPCODE_X0 = 6, | ||
236 | NOP_UN_0_SHUN_0_OPCODE_X1 = 17, | ||
237 | NOP_UN_0_SHUN_0_OPCODE_Y0 = 6, | ||
238 | NOP_UN_0_SHUN_0_OPCODE_Y1 = 3, | ||
239 | NOREG_RR_IMM_0_OPCODE_SN = 0, | ||
240 | NOR_SPECIAL_0_OPCODE_X0 = 50, | ||
241 | NOR_SPECIAL_0_OPCODE_X1 = 24, | ||
242 | NOR_SPECIAL_2_OPCODE_Y0 = 1, | ||
243 | NOR_SPECIAL_2_OPCODE_Y1 = 1, | ||
244 | ORI_IMM_0_OPCODE_X0 = 8, | ||
245 | ORI_IMM_0_OPCODE_X1 = 11, | ||
246 | ORI_OPCODE_Y0 = 11, | ||
247 | ORI_OPCODE_Y1 = 9, | ||
248 | OR_SPECIAL_0_OPCODE_X0 = 51, | ||
249 | OR_SPECIAL_0_OPCODE_X1 = 25, | ||
250 | OR_SPECIAL_2_OPCODE_Y0 = 2, | ||
251 | OR_SPECIAL_2_OPCODE_Y1 = 2, | ||
252 | PACKBS_U_SPECIAL_0_OPCODE_X0 = 103, | ||
253 | PACKBS_U_SPECIAL_0_OPCODE_X1 = 73, | ||
254 | PACKHB_SPECIAL_0_OPCODE_X0 = 52, | ||
255 | PACKHB_SPECIAL_0_OPCODE_X1 = 26, | ||
256 | PACKHS_SPECIAL_0_OPCODE_X0 = 102, | ||
257 | PACKHS_SPECIAL_0_OPCODE_X1 = 72, | ||
258 | PACKLB_SPECIAL_0_OPCODE_X0 = 53, | ||
259 | PACKLB_SPECIAL_0_OPCODE_X1 = 27, | ||
260 | PCNT_UN_0_SHUN_0_OPCODE_X0 = 7, | ||
261 | PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7, | ||
262 | RLI_SHUN_0_OPCODE_X0 = 1, | ||
263 | RLI_SHUN_0_OPCODE_X1 = 1, | ||
264 | RLI_SHUN_0_OPCODE_Y0 = 1, | ||
265 | RLI_SHUN_0_OPCODE_Y1 = 1, | ||
266 | RL_SPECIAL_0_OPCODE_X0 = 54, | ||
267 | RL_SPECIAL_0_OPCODE_X1 = 28, | ||
268 | RL_SPECIAL_3_OPCODE_Y0 = 0, | ||
269 | RL_SPECIAL_3_OPCODE_Y1 = 0, | ||
270 | RR_IMM_0_OPCODE_SN = 0, | ||
271 | S1A_SPECIAL_0_OPCODE_X0 = 55, | ||
272 | S1A_SPECIAL_0_OPCODE_X1 = 29, | ||
273 | S1A_SPECIAL_0_OPCODE_Y0 = 1, | ||
274 | S1A_SPECIAL_0_OPCODE_Y1 = 1, | ||
275 | S2A_SPECIAL_0_OPCODE_X0 = 56, | ||
276 | S2A_SPECIAL_0_OPCODE_X1 = 30, | ||
277 | S2A_SPECIAL_0_OPCODE_Y0 = 2, | ||
278 | S2A_SPECIAL_0_OPCODE_Y1 = 2, | ||
279 | S3A_SPECIAL_0_OPCODE_X0 = 57, | ||
280 | S3A_SPECIAL_0_OPCODE_X1 = 31, | ||
281 | S3A_SPECIAL_5_OPCODE_Y0 = 1, | ||
282 | S3A_SPECIAL_5_OPCODE_Y1 = 1, | ||
283 | SADAB_U_SPECIAL_0_OPCODE_X0 = 58, | ||
284 | SADAH_SPECIAL_0_OPCODE_X0 = 59, | ||
285 | SADAH_U_SPECIAL_0_OPCODE_X0 = 60, | ||
286 | SADB_U_SPECIAL_0_OPCODE_X0 = 61, | ||
287 | SADH_SPECIAL_0_OPCODE_X0 = 62, | ||
288 | SADH_U_SPECIAL_0_OPCODE_X0 = 63, | ||
289 | SBADD_IMM_0_OPCODE_X1 = 28, | ||
290 | SB_OPCODE_Y2 = 5, | ||
291 | SB_SPECIAL_0_OPCODE_X1 = 32, | ||
292 | SEQB_SPECIAL_0_OPCODE_X0 = 64, | ||
293 | SEQB_SPECIAL_0_OPCODE_X1 = 33, | ||
294 | SEQH_SPECIAL_0_OPCODE_X0 = 65, | ||
295 | SEQH_SPECIAL_0_OPCODE_X1 = 34, | ||
296 | SEQIB_IMM_0_OPCODE_X0 = 9, | ||
297 | SEQIB_IMM_0_OPCODE_X1 = 12, | ||
298 | SEQIH_IMM_0_OPCODE_X0 = 10, | ||
299 | SEQIH_IMM_0_OPCODE_X1 = 13, | ||
300 | SEQI_IMM_0_OPCODE_X0 = 11, | ||
301 | SEQI_IMM_0_OPCODE_X1 = 14, | ||
302 | SEQI_OPCODE_Y0 = 12, | ||
303 | SEQI_OPCODE_Y1 = 10, | ||
304 | SEQ_SPECIAL_0_OPCODE_X0 = 66, | ||
305 | SEQ_SPECIAL_0_OPCODE_X1 = 35, | ||
306 | SEQ_SPECIAL_5_OPCODE_Y0 = 2, | ||
307 | SEQ_SPECIAL_5_OPCODE_Y1 = 2, | ||
308 | SHADD_IMM_0_OPCODE_X1 = 29, | ||
309 | SHL8II_IMM_0_OPCODE_SN = 3, | ||
310 | SHLB_SPECIAL_0_OPCODE_X0 = 67, | ||
311 | SHLB_SPECIAL_0_OPCODE_X1 = 36, | ||
312 | SHLH_SPECIAL_0_OPCODE_X0 = 68, | ||
313 | SHLH_SPECIAL_0_OPCODE_X1 = 37, | ||
314 | SHLIB_SHUN_0_OPCODE_X0 = 2, | ||
315 | SHLIB_SHUN_0_OPCODE_X1 = 2, | ||
316 | SHLIH_SHUN_0_OPCODE_X0 = 3, | ||
317 | SHLIH_SHUN_0_OPCODE_X1 = 3, | ||
318 | SHLI_SHUN_0_OPCODE_X0 = 4, | ||
319 | SHLI_SHUN_0_OPCODE_X1 = 4, | ||
320 | SHLI_SHUN_0_OPCODE_Y0 = 2, | ||
321 | SHLI_SHUN_0_OPCODE_Y1 = 2, | ||
322 | SHL_SPECIAL_0_OPCODE_X0 = 69, | ||
323 | SHL_SPECIAL_0_OPCODE_X1 = 38, | ||
324 | SHL_SPECIAL_3_OPCODE_Y0 = 1, | ||
325 | SHL_SPECIAL_3_OPCODE_Y1 = 1, | ||
326 | SHR1_RR_IMM_0_OPCODE_SN = 9, | ||
327 | SHRB_SPECIAL_0_OPCODE_X0 = 70, | ||
328 | SHRB_SPECIAL_0_OPCODE_X1 = 39, | ||
329 | SHRH_SPECIAL_0_OPCODE_X0 = 71, | ||
330 | SHRH_SPECIAL_0_OPCODE_X1 = 40, | ||
331 | SHRIB_SHUN_0_OPCODE_X0 = 5, | ||
332 | SHRIB_SHUN_0_OPCODE_X1 = 5, | ||
333 | SHRIH_SHUN_0_OPCODE_X0 = 6, | ||
334 | SHRIH_SHUN_0_OPCODE_X1 = 6, | ||
335 | SHRI_SHUN_0_OPCODE_X0 = 7, | ||
336 | SHRI_SHUN_0_OPCODE_X1 = 7, | ||
337 | SHRI_SHUN_0_OPCODE_Y0 = 3, | ||
338 | SHRI_SHUN_0_OPCODE_Y1 = 3, | ||
339 | SHR_SPECIAL_0_OPCODE_X0 = 72, | ||
340 | SHR_SPECIAL_0_OPCODE_X1 = 41, | ||
341 | SHR_SPECIAL_3_OPCODE_Y0 = 2, | ||
342 | SHR_SPECIAL_3_OPCODE_Y1 = 2, | ||
343 | SHUN_0_OPCODE_X0 = 7, | ||
344 | SHUN_0_OPCODE_X1 = 8, | ||
345 | SHUN_0_OPCODE_Y0 = 13, | ||
346 | SHUN_0_OPCODE_Y1 = 11, | ||
347 | SH_OPCODE_Y2 = 6, | ||
348 | SH_SPECIAL_0_OPCODE_X1 = 42, | ||
349 | SLTB_SPECIAL_0_OPCODE_X0 = 73, | ||
350 | SLTB_SPECIAL_0_OPCODE_X1 = 43, | ||
351 | SLTB_U_SPECIAL_0_OPCODE_X0 = 74, | ||
352 | SLTB_U_SPECIAL_0_OPCODE_X1 = 44, | ||
353 | SLTEB_SPECIAL_0_OPCODE_X0 = 75, | ||
354 | SLTEB_SPECIAL_0_OPCODE_X1 = 45, | ||
355 | SLTEB_U_SPECIAL_0_OPCODE_X0 = 76, | ||
356 | SLTEB_U_SPECIAL_0_OPCODE_X1 = 46, | ||
357 | SLTEH_SPECIAL_0_OPCODE_X0 = 77, | ||
358 | SLTEH_SPECIAL_0_OPCODE_X1 = 47, | ||
359 | SLTEH_U_SPECIAL_0_OPCODE_X0 = 78, | ||
360 | SLTEH_U_SPECIAL_0_OPCODE_X1 = 48, | ||
361 | SLTE_SPECIAL_0_OPCODE_X0 = 79, | ||
362 | SLTE_SPECIAL_0_OPCODE_X1 = 49, | ||
363 | SLTE_SPECIAL_4_OPCODE_Y0 = 0, | ||
364 | SLTE_SPECIAL_4_OPCODE_Y1 = 0, | ||
365 | SLTE_U_SPECIAL_0_OPCODE_X0 = 80, | ||
366 | SLTE_U_SPECIAL_0_OPCODE_X1 = 50, | ||
367 | SLTE_U_SPECIAL_4_OPCODE_Y0 = 1, | ||
368 | SLTE_U_SPECIAL_4_OPCODE_Y1 = 1, | ||
369 | SLTH_SPECIAL_0_OPCODE_X0 = 81, | ||
370 | SLTH_SPECIAL_0_OPCODE_X1 = 51, | ||
371 | SLTH_U_SPECIAL_0_OPCODE_X0 = 82, | ||
372 | SLTH_U_SPECIAL_0_OPCODE_X1 = 52, | ||
373 | SLTIB_IMM_0_OPCODE_X0 = 12, | ||
374 | SLTIB_IMM_0_OPCODE_X1 = 15, | ||
375 | SLTIB_U_IMM_0_OPCODE_X0 = 13, | ||
376 | SLTIB_U_IMM_0_OPCODE_X1 = 16, | ||
377 | SLTIH_IMM_0_OPCODE_X0 = 14, | ||
378 | SLTIH_IMM_0_OPCODE_X1 = 17, | ||
379 | SLTIH_U_IMM_0_OPCODE_X0 = 15, | ||
380 | SLTIH_U_IMM_0_OPCODE_X1 = 18, | ||
381 | SLTI_IMM_0_OPCODE_X0 = 16, | ||
382 | SLTI_IMM_0_OPCODE_X1 = 19, | ||
383 | SLTI_OPCODE_Y0 = 14, | ||
384 | SLTI_OPCODE_Y1 = 12, | ||
385 | SLTI_U_IMM_0_OPCODE_X0 = 17, | ||
386 | SLTI_U_IMM_0_OPCODE_X1 = 20, | ||
387 | SLTI_U_OPCODE_Y0 = 15, | ||
388 | SLTI_U_OPCODE_Y1 = 13, | ||
389 | SLT_SPECIAL_0_OPCODE_X0 = 83, | ||
390 | SLT_SPECIAL_0_OPCODE_X1 = 53, | ||
391 | SLT_SPECIAL_4_OPCODE_Y0 = 2, | ||
392 | SLT_SPECIAL_4_OPCODE_Y1 = 2, | ||
393 | SLT_U_SPECIAL_0_OPCODE_X0 = 84, | ||
394 | SLT_U_SPECIAL_0_OPCODE_X1 = 54, | ||
395 | SLT_U_SPECIAL_4_OPCODE_Y0 = 3, | ||
396 | SLT_U_SPECIAL_4_OPCODE_Y1 = 3, | ||
397 | SNEB_SPECIAL_0_OPCODE_X0 = 85, | ||
398 | SNEB_SPECIAL_0_OPCODE_X1 = 55, | ||
399 | SNEH_SPECIAL_0_OPCODE_X0 = 86, | ||
400 | SNEH_SPECIAL_0_OPCODE_X1 = 56, | ||
401 | SNE_SPECIAL_0_OPCODE_X0 = 87, | ||
402 | SNE_SPECIAL_0_OPCODE_X1 = 57, | ||
403 | SNE_SPECIAL_5_OPCODE_Y0 = 3, | ||
404 | SNE_SPECIAL_5_OPCODE_Y1 = 3, | ||
405 | SPECIAL_0_OPCODE_X0 = 0, | ||
406 | SPECIAL_0_OPCODE_X1 = 1, | ||
407 | SPECIAL_0_OPCODE_Y0 = 1, | ||
408 | SPECIAL_0_OPCODE_Y1 = 1, | ||
409 | SPECIAL_1_OPCODE_Y0 = 2, | ||
410 | SPECIAL_1_OPCODE_Y1 = 2, | ||
411 | SPECIAL_2_OPCODE_Y0 = 3, | ||
412 | SPECIAL_2_OPCODE_Y1 = 3, | ||
413 | SPECIAL_3_OPCODE_Y0 = 4, | ||
414 | SPECIAL_3_OPCODE_Y1 = 4, | ||
415 | SPECIAL_4_OPCODE_Y0 = 5, | ||
416 | SPECIAL_4_OPCODE_Y1 = 5, | ||
417 | SPECIAL_5_OPCODE_Y0 = 6, | ||
418 | SPECIAL_5_OPCODE_Y1 = 6, | ||
419 | SPECIAL_6_OPCODE_Y0 = 7, | ||
420 | SPECIAL_7_OPCODE_Y0 = 8, | ||
421 | SRAB_SPECIAL_0_OPCODE_X0 = 88, | ||
422 | SRAB_SPECIAL_0_OPCODE_X1 = 58, | ||
423 | SRAH_SPECIAL_0_OPCODE_X0 = 89, | ||
424 | SRAH_SPECIAL_0_OPCODE_X1 = 59, | ||
425 | SRAIB_SHUN_0_OPCODE_X0 = 8, | ||
426 | SRAIB_SHUN_0_OPCODE_X1 = 8, | ||
427 | SRAIH_SHUN_0_OPCODE_X0 = 9, | ||
428 | SRAIH_SHUN_0_OPCODE_X1 = 9, | ||
429 | SRAI_SHUN_0_OPCODE_X0 = 10, | ||
430 | SRAI_SHUN_0_OPCODE_X1 = 10, | ||
431 | SRAI_SHUN_0_OPCODE_Y0 = 4, | ||
432 | SRAI_SHUN_0_OPCODE_Y1 = 4, | ||
433 | SRA_SPECIAL_0_OPCODE_X0 = 90, | ||
434 | SRA_SPECIAL_0_OPCODE_X1 = 60, | ||
435 | SRA_SPECIAL_3_OPCODE_Y0 = 3, | ||
436 | SRA_SPECIAL_3_OPCODE_Y1 = 3, | ||
437 | SUBBS_U_SPECIAL_0_OPCODE_X0 = 100, | ||
438 | SUBBS_U_SPECIAL_0_OPCODE_X1 = 70, | ||
439 | SUBB_SPECIAL_0_OPCODE_X0 = 91, | ||
440 | SUBB_SPECIAL_0_OPCODE_X1 = 61, | ||
441 | SUBHS_SPECIAL_0_OPCODE_X0 = 101, | ||
442 | SUBHS_SPECIAL_0_OPCODE_X1 = 71, | ||
443 | SUBH_SPECIAL_0_OPCODE_X0 = 92, | ||
444 | SUBH_SPECIAL_0_OPCODE_X1 = 62, | ||
445 | SUBS_SPECIAL_0_OPCODE_X0 = 97, | ||
446 | SUBS_SPECIAL_0_OPCODE_X1 = 67, | ||
447 | SUB_SPECIAL_0_OPCODE_X0 = 93, | ||
448 | SUB_SPECIAL_0_OPCODE_X1 = 63, | ||
449 | SUB_SPECIAL_0_OPCODE_Y0 = 3, | ||
450 | SUB_SPECIAL_0_OPCODE_Y1 = 3, | ||
451 | SWADD_IMM_0_OPCODE_X1 = 30, | ||
452 | SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18, | ||
453 | SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19, | ||
454 | SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20, | ||
455 | SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21, | ||
456 | SW_OPCODE_Y2 = 7, | ||
457 | SW_SPECIAL_0_OPCODE_X1 = 64, | ||
458 | TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8, | ||
459 | TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8, | ||
460 | TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9, | ||
461 | TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9, | ||
462 | TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10, | ||
463 | TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10, | ||
464 | TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11, | ||
465 | TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11, | ||
466 | TNS_UN_0_SHUN_0_OPCODE_X1 = 22, | ||
467 | UN_0_SHUN_0_OPCODE_X0 = 11, | ||
468 | UN_0_SHUN_0_OPCODE_X1 = 11, | ||
469 | UN_0_SHUN_0_OPCODE_Y0 = 5, | ||
470 | UN_0_SHUN_0_OPCODE_Y1 = 5, | ||
471 | WH64_UN_0_SHUN_0_OPCODE_X1 = 23, | ||
472 | XORI_IMM_0_OPCODE_X0 = 2, | ||
473 | XORI_IMM_0_OPCODE_X1 = 21, | ||
474 | XOR_SPECIAL_0_OPCODE_X0 = 94, | ||
475 | XOR_SPECIAL_0_OPCODE_X1 = 65, | ||
476 | XOR_SPECIAL_2_OPCODE_Y0 = 3, | ||
477 | XOR_SPECIAL_2_OPCODE_Y1 = 3 | ||
478 | }; | ||
479 | |||
480 | #endif /* !_TILE_OPCODE_CONSTANTS_H */ | ||
diff --git a/arch/tile/include/asm/opcode-tile.h b/arch/tile/include/asm/tile-desc.h index ba38959137d7..43849bf79dcb 100644 --- a/arch/tile/include/asm/opcode-tile.h +++ b/arch/tile/include/asm/tile-desc.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | 2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or | 4 | * This program is free software; you can redistribute it and/or |
5 | * modify it under the terms of the GNU General Public License | 5 | * modify it under the terms of the GNU General Public License |
@@ -12,19 +12,8 @@ | |||
12 | * more details. | 12 | * more details. |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #ifndef _ASM_TILE_OPCODE_TILE_H | 15 | #ifndef __tilegx__ |
16 | #define _ASM_TILE_OPCODE_TILE_H | 16 | #include <asm/tile-desc_32.h> |
17 | |||
18 | #include <arch/chip.h> | ||
19 | |||
20 | #if CHIP_WORD_SIZE() == 64 | ||
21 | #include <asm/opcode-tile_64.h> | ||
22 | #else | 17 | #else |
23 | #include <asm/opcode-tile_32.h> | 18 | #include <asm/tile-desc_64.h> |
24 | #endif | 19 | #endif |
25 | |||
26 | /* These definitions are not correct for TILE64, so just avoid them. */ | ||
27 | #undef TILE_ELF_MACHINE_CODE | ||
28 | #undef TILE_ELF_NAME | ||
29 | |||
30 | #endif /* _ASM_TILE_OPCODE_TILE_H */ | ||
diff --git a/arch/tile/include/asm/tile-desc_32.h b/arch/tile/include/asm/tile-desc_32.h new file mode 100644 index 000000000000..f09c5c43b0b2 --- /dev/null +++ b/arch/tile/include/asm/tile-desc_32.h | |||
@@ -0,0 +1,553 @@ | |||
1 | /* TILEPro opcode information. | ||
2 | * | ||
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation, version 2. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
12 | * NON INFRINGEMENT. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #ifndef opcode_tilepro_h | ||
22 | #define opcode_tilepro_h | ||
23 | |||
24 | #include <arch/opcode.h> | ||
25 | |||
26 | |||
27 | enum | ||
28 | { | ||
29 | TILEPRO_MAX_OPERANDS = 5 /* mm */ | ||
30 | }; | ||
31 | |||
32 | typedef enum | ||
33 | { | ||
34 | TILEPRO_OPC_BPT, | ||
35 | TILEPRO_OPC_INFO, | ||
36 | TILEPRO_OPC_INFOL, | ||
37 | TILEPRO_OPC_J, | ||
38 | TILEPRO_OPC_JAL, | ||
39 | TILEPRO_OPC_MOVE, | ||
40 | TILEPRO_OPC_MOVE_SN, | ||
41 | TILEPRO_OPC_MOVEI, | ||
42 | TILEPRO_OPC_MOVEI_SN, | ||
43 | TILEPRO_OPC_MOVELI, | ||
44 | TILEPRO_OPC_MOVELI_SN, | ||
45 | TILEPRO_OPC_MOVELIS, | ||
46 | TILEPRO_OPC_PREFETCH, | ||
47 | TILEPRO_OPC_RAISE, | ||
48 | TILEPRO_OPC_ADD, | ||
49 | TILEPRO_OPC_ADD_SN, | ||
50 | TILEPRO_OPC_ADDB, | ||
51 | TILEPRO_OPC_ADDB_SN, | ||
52 | TILEPRO_OPC_ADDBS_U, | ||
53 | TILEPRO_OPC_ADDBS_U_SN, | ||
54 | TILEPRO_OPC_ADDH, | ||
55 | TILEPRO_OPC_ADDH_SN, | ||
56 | TILEPRO_OPC_ADDHS, | ||
57 | TILEPRO_OPC_ADDHS_SN, | ||
58 | TILEPRO_OPC_ADDI, | ||
59 | TILEPRO_OPC_ADDI_SN, | ||
60 | TILEPRO_OPC_ADDIB, | ||
61 | TILEPRO_OPC_ADDIB_SN, | ||
62 | TILEPRO_OPC_ADDIH, | ||
63 | TILEPRO_OPC_ADDIH_SN, | ||
64 | TILEPRO_OPC_ADDLI, | ||
65 | TILEPRO_OPC_ADDLI_SN, | ||
66 | TILEPRO_OPC_ADDLIS, | ||
67 | TILEPRO_OPC_ADDS, | ||
68 | TILEPRO_OPC_ADDS_SN, | ||
69 | TILEPRO_OPC_ADIFFB_U, | ||
70 | TILEPRO_OPC_ADIFFB_U_SN, | ||
71 | TILEPRO_OPC_ADIFFH, | ||
72 | TILEPRO_OPC_ADIFFH_SN, | ||
73 | TILEPRO_OPC_AND, | ||
74 | TILEPRO_OPC_AND_SN, | ||
75 | TILEPRO_OPC_ANDI, | ||
76 | TILEPRO_OPC_ANDI_SN, | ||
77 | TILEPRO_OPC_AULI, | ||
78 | TILEPRO_OPC_AVGB_U, | ||
79 | TILEPRO_OPC_AVGB_U_SN, | ||
80 | TILEPRO_OPC_AVGH, | ||
81 | TILEPRO_OPC_AVGH_SN, | ||
82 | TILEPRO_OPC_BBNS, | ||
83 | TILEPRO_OPC_BBNS_SN, | ||
84 | TILEPRO_OPC_BBNST, | ||
85 | TILEPRO_OPC_BBNST_SN, | ||
86 | TILEPRO_OPC_BBS, | ||
87 | TILEPRO_OPC_BBS_SN, | ||
88 | TILEPRO_OPC_BBST, | ||
89 | TILEPRO_OPC_BBST_SN, | ||
90 | TILEPRO_OPC_BGEZ, | ||
91 | TILEPRO_OPC_BGEZ_SN, | ||
92 | TILEPRO_OPC_BGEZT, | ||
93 | TILEPRO_OPC_BGEZT_SN, | ||
94 | TILEPRO_OPC_BGZ, | ||
95 | TILEPRO_OPC_BGZ_SN, | ||
96 | TILEPRO_OPC_BGZT, | ||
97 | TILEPRO_OPC_BGZT_SN, | ||
98 | TILEPRO_OPC_BITX, | ||
99 | TILEPRO_OPC_BITX_SN, | ||
100 | TILEPRO_OPC_BLEZ, | ||
101 | TILEPRO_OPC_BLEZ_SN, | ||
102 | TILEPRO_OPC_BLEZT, | ||
103 | TILEPRO_OPC_BLEZT_SN, | ||
104 | TILEPRO_OPC_BLZ, | ||
105 | TILEPRO_OPC_BLZ_SN, | ||
106 | TILEPRO_OPC_BLZT, | ||
107 | TILEPRO_OPC_BLZT_SN, | ||
108 | TILEPRO_OPC_BNZ, | ||
109 | TILEPRO_OPC_BNZ_SN, | ||
110 | TILEPRO_OPC_BNZT, | ||
111 | TILEPRO_OPC_BNZT_SN, | ||
112 | TILEPRO_OPC_BYTEX, | ||
113 | TILEPRO_OPC_BYTEX_SN, | ||
114 | TILEPRO_OPC_BZ, | ||
115 | TILEPRO_OPC_BZ_SN, | ||
116 | TILEPRO_OPC_BZT, | ||
117 | TILEPRO_OPC_BZT_SN, | ||
118 | TILEPRO_OPC_CLZ, | ||
119 | TILEPRO_OPC_CLZ_SN, | ||
120 | TILEPRO_OPC_CRC32_32, | ||
121 | TILEPRO_OPC_CRC32_32_SN, | ||
122 | TILEPRO_OPC_CRC32_8, | ||
123 | TILEPRO_OPC_CRC32_8_SN, | ||
124 | TILEPRO_OPC_CTZ, | ||
125 | TILEPRO_OPC_CTZ_SN, | ||
126 | TILEPRO_OPC_DRAIN, | ||
127 | TILEPRO_OPC_DTLBPR, | ||
128 | TILEPRO_OPC_DWORD_ALIGN, | ||
129 | TILEPRO_OPC_DWORD_ALIGN_SN, | ||
130 | TILEPRO_OPC_FINV, | ||
131 | TILEPRO_OPC_FLUSH, | ||
132 | TILEPRO_OPC_FNOP, | ||
133 | TILEPRO_OPC_ICOH, | ||
134 | TILEPRO_OPC_ILL, | ||
135 | TILEPRO_OPC_INTHB, | ||
136 | TILEPRO_OPC_INTHB_SN, | ||
137 | TILEPRO_OPC_INTHH, | ||
138 | TILEPRO_OPC_INTHH_SN, | ||
139 | TILEPRO_OPC_INTLB, | ||
140 | TILEPRO_OPC_INTLB_SN, | ||
141 | TILEPRO_OPC_INTLH, | ||
142 | TILEPRO_OPC_INTLH_SN, | ||
143 | TILEPRO_OPC_INV, | ||
144 | TILEPRO_OPC_IRET, | ||
145 | TILEPRO_OPC_JALB, | ||
146 | TILEPRO_OPC_JALF, | ||
147 | TILEPRO_OPC_JALR, | ||
148 | TILEPRO_OPC_JALRP, | ||
149 | TILEPRO_OPC_JB, | ||
150 | TILEPRO_OPC_JF, | ||
151 | TILEPRO_OPC_JR, | ||
152 | TILEPRO_OPC_JRP, | ||
153 | TILEPRO_OPC_LB, | ||
154 | TILEPRO_OPC_LB_SN, | ||
155 | TILEPRO_OPC_LB_U, | ||
156 | TILEPRO_OPC_LB_U_SN, | ||
157 | TILEPRO_OPC_LBADD, | ||
158 | TILEPRO_OPC_LBADD_SN, | ||
159 | TILEPRO_OPC_LBADD_U, | ||
160 | TILEPRO_OPC_LBADD_U_SN, | ||
161 | TILEPRO_OPC_LH, | ||
162 | TILEPRO_OPC_LH_SN, | ||
163 | TILEPRO_OPC_LH_U, | ||
164 | TILEPRO_OPC_LH_U_SN, | ||
165 | TILEPRO_OPC_LHADD, | ||
166 | TILEPRO_OPC_LHADD_SN, | ||
167 | TILEPRO_OPC_LHADD_U, | ||
168 | TILEPRO_OPC_LHADD_U_SN, | ||
169 | TILEPRO_OPC_LNK, | ||
170 | TILEPRO_OPC_LNK_SN, | ||
171 | TILEPRO_OPC_LW, | ||
172 | TILEPRO_OPC_LW_SN, | ||
173 | TILEPRO_OPC_LW_NA, | ||
174 | TILEPRO_OPC_LW_NA_SN, | ||
175 | TILEPRO_OPC_LWADD, | ||
176 | TILEPRO_OPC_LWADD_SN, | ||
177 | TILEPRO_OPC_LWADD_NA, | ||
178 | TILEPRO_OPC_LWADD_NA_SN, | ||
179 | TILEPRO_OPC_MAXB_U, | ||
180 | TILEPRO_OPC_MAXB_U_SN, | ||
181 | TILEPRO_OPC_MAXH, | ||
182 | TILEPRO_OPC_MAXH_SN, | ||
183 | TILEPRO_OPC_MAXIB_U, | ||
184 | TILEPRO_OPC_MAXIB_U_SN, | ||
185 | TILEPRO_OPC_MAXIH, | ||
186 | TILEPRO_OPC_MAXIH_SN, | ||
187 | TILEPRO_OPC_MF, | ||
188 | TILEPRO_OPC_MFSPR, | ||
189 | TILEPRO_OPC_MINB_U, | ||
190 | TILEPRO_OPC_MINB_U_SN, | ||
191 | TILEPRO_OPC_MINH, | ||
192 | TILEPRO_OPC_MINH_SN, | ||
193 | TILEPRO_OPC_MINIB_U, | ||
194 | TILEPRO_OPC_MINIB_U_SN, | ||
195 | TILEPRO_OPC_MINIH, | ||
196 | TILEPRO_OPC_MINIH_SN, | ||
197 | TILEPRO_OPC_MM, | ||
198 | TILEPRO_OPC_MNZ, | ||
199 | TILEPRO_OPC_MNZ_SN, | ||
200 | TILEPRO_OPC_MNZB, | ||
201 | TILEPRO_OPC_MNZB_SN, | ||
202 | TILEPRO_OPC_MNZH, | ||
203 | TILEPRO_OPC_MNZH_SN, | ||
204 | TILEPRO_OPC_MTSPR, | ||
205 | TILEPRO_OPC_MULHH_SS, | ||
206 | TILEPRO_OPC_MULHH_SS_SN, | ||
207 | TILEPRO_OPC_MULHH_SU, | ||
208 | TILEPRO_OPC_MULHH_SU_SN, | ||
209 | TILEPRO_OPC_MULHH_UU, | ||
210 | TILEPRO_OPC_MULHH_UU_SN, | ||
211 | TILEPRO_OPC_MULHHA_SS, | ||
212 | TILEPRO_OPC_MULHHA_SS_SN, | ||
213 | TILEPRO_OPC_MULHHA_SU, | ||
214 | TILEPRO_OPC_MULHHA_SU_SN, | ||
215 | TILEPRO_OPC_MULHHA_UU, | ||
216 | TILEPRO_OPC_MULHHA_UU_SN, | ||
217 | TILEPRO_OPC_MULHHSA_UU, | ||
218 | TILEPRO_OPC_MULHHSA_UU_SN, | ||
219 | TILEPRO_OPC_MULHL_SS, | ||
220 | TILEPRO_OPC_MULHL_SS_SN, | ||
221 | TILEPRO_OPC_MULHL_SU, | ||
222 | TILEPRO_OPC_MULHL_SU_SN, | ||
223 | TILEPRO_OPC_MULHL_US, | ||
224 | TILEPRO_OPC_MULHL_US_SN, | ||
225 | TILEPRO_OPC_MULHL_UU, | ||
226 | TILEPRO_OPC_MULHL_UU_SN, | ||
227 | TILEPRO_OPC_MULHLA_SS, | ||
228 | TILEPRO_OPC_MULHLA_SS_SN, | ||
229 | TILEPRO_OPC_MULHLA_SU, | ||
230 | TILEPRO_OPC_MULHLA_SU_SN, | ||
231 | TILEPRO_OPC_MULHLA_US, | ||
232 | TILEPRO_OPC_MULHLA_US_SN, | ||
233 | TILEPRO_OPC_MULHLA_UU, | ||
234 | TILEPRO_OPC_MULHLA_UU_SN, | ||
235 | TILEPRO_OPC_MULHLSA_UU, | ||
236 | TILEPRO_OPC_MULHLSA_UU_SN, | ||
237 | TILEPRO_OPC_MULLL_SS, | ||
238 | TILEPRO_OPC_MULLL_SS_SN, | ||
239 | TILEPRO_OPC_MULLL_SU, | ||
240 | TILEPRO_OPC_MULLL_SU_SN, | ||
241 | TILEPRO_OPC_MULLL_UU, | ||
242 | TILEPRO_OPC_MULLL_UU_SN, | ||
243 | TILEPRO_OPC_MULLLA_SS, | ||
244 | TILEPRO_OPC_MULLLA_SS_SN, | ||
245 | TILEPRO_OPC_MULLLA_SU, | ||
246 | TILEPRO_OPC_MULLLA_SU_SN, | ||
247 | TILEPRO_OPC_MULLLA_UU, | ||
248 | TILEPRO_OPC_MULLLA_UU_SN, | ||
249 | TILEPRO_OPC_MULLLSA_UU, | ||
250 | TILEPRO_OPC_MULLLSA_UU_SN, | ||
251 | TILEPRO_OPC_MVNZ, | ||
252 | TILEPRO_OPC_MVNZ_SN, | ||
253 | TILEPRO_OPC_MVZ, | ||
254 | TILEPRO_OPC_MVZ_SN, | ||
255 | TILEPRO_OPC_MZ, | ||
256 | TILEPRO_OPC_MZ_SN, | ||
257 | TILEPRO_OPC_MZB, | ||
258 | TILEPRO_OPC_MZB_SN, | ||
259 | TILEPRO_OPC_MZH, | ||
260 | TILEPRO_OPC_MZH_SN, | ||
261 | TILEPRO_OPC_NAP, | ||
262 | TILEPRO_OPC_NOP, | ||
263 | TILEPRO_OPC_NOR, | ||
264 | TILEPRO_OPC_NOR_SN, | ||
265 | TILEPRO_OPC_OR, | ||
266 | TILEPRO_OPC_OR_SN, | ||
267 | TILEPRO_OPC_ORI, | ||
268 | TILEPRO_OPC_ORI_SN, | ||
269 | TILEPRO_OPC_PACKBS_U, | ||
270 | TILEPRO_OPC_PACKBS_U_SN, | ||
271 | TILEPRO_OPC_PACKHB, | ||
272 | TILEPRO_OPC_PACKHB_SN, | ||
273 | TILEPRO_OPC_PACKHS, | ||
274 | TILEPRO_OPC_PACKHS_SN, | ||
275 | TILEPRO_OPC_PACKLB, | ||
276 | TILEPRO_OPC_PACKLB_SN, | ||
277 | TILEPRO_OPC_PCNT, | ||
278 | TILEPRO_OPC_PCNT_SN, | ||
279 | TILEPRO_OPC_RL, | ||
280 | TILEPRO_OPC_RL_SN, | ||
281 | TILEPRO_OPC_RLI, | ||
282 | TILEPRO_OPC_RLI_SN, | ||
283 | TILEPRO_OPC_S1A, | ||
284 | TILEPRO_OPC_S1A_SN, | ||
285 | TILEPRO_OPC_S2A, | ||
286 | TILEPRO_OPC_S2A_SN, | ||
287 | TILEPRO_OPC_S3A, | ||
288 | TILEPRO_OPC_S3A_SN, | ||
289 | TILEPRO_OPC_SADAB_U, | ||
290 | TILEPRO_OPC_SADAB_U_SN, | ||
291 | TILEPRO_OPC_SADAH, | ||
292 | TILEPRO_OPC_SADAH_SN, | ||
293 | TILEPRO_OPC_SADAH_U, | ||
294 | TILEPRO_OPC_SADAH_U_SN, | ||
295 | TILEPRO_OPC_SADB_U, | ||
296 | TILEPRO_OPC_SADB_U_SN, | ||
297 | TILEPRO_OPC_SADH, | ||
298 | TILEPRO_OPC_SADH_SN, | ||
299 | TILEPRO_OPC_SADH_U, | ||
300 | TILEPRO_OPC_SADH_U_SN, | ||
301 | TILEPRO_OPC_SB, | ||
302 | TILEPRO_OPC_SBADD, | ||
303 | TILEPRO_OPC_SEQ, | ||
304 | TILEPRO_OPC_SEQ_SN, | ||
305 | TILEPRO_OPC_SEQB, | ||
306 | TILEPRO_OPC_SEQB_SN, | ||
307 | TILEPRO_OPC_SEQH, | ||
308 | TILEPRO_OPC_SEQH_SN, | ||
309 | TILEPRO_OPC_SEQI, | ||
310 | TILEPRO_OPC_SEQI_SN, | ||
311 | TILEPRO_OPC_SEQIB, | ||
312 | TILEPRO_OPC_SEQIB_SN, | ||
313 | TILEPRO_OPC_SEQIH, | ||
314 | TILEPRO_OPC_SEQIH_SN, | ||
315 | TILEPRO_OPC_SH, | ||
316 | TILEPRO_OPC_SHADD, | ||
317 | TILEPRO_OPC_SHL, | ||
318 | TILEPRO_OPC_SHL_SN, | ||
319 | TILEPRO_OPC_SHLB, | ||
320 | TILEPRO_OPC_SHLB_SN, | ||
321 | TILEPRO_OPC_SHLH, | ||
322 | TILEPRO_OPC_SHLH_SN, | ||
323 | TILEPRO_OPC_SHLI, | ||
324 | TILEPRO_OPC_SHLI_SN, | ||
325 | TILEPRO_OPC_SHLIB, | ||
326 | TILEPRO_OPC_SHLIB_SN, | ||
327 | TILEPRO_OPC_SHLIH, | ||
328 | TILEPRO_OPC_SHLIH_SN, | ||
329 | TILEPRO_OPC_SHR, | ||
330 | TILEPRO_OPC_SHR_SN, | ||
331 | TILEPRO_OPC_SHRB, | ||
332 | TILEPRO_OPC_SHRB_SN, | ||
333 | TILEPRO_OPC_SHRH, | ||
334 | TILEPRO_OPC_SHRH_SN, | ||
335 | TILEPRO_OPC_SHRI, | ||
336 | TILEPRO_OPC_SHRI_SN, | ||
337 | TILEPRO_OPC_SHRIB, | ||
338 | TILEPRO_OPC_SHRIB_SN, | ||
339 | TILEPRO_OPC_SHRIH, | ||
340 | TILEPRO_OPC_SHRIH_SN, | ||
341 | TILEPRO_OPC_SLT, | ||
342 | TILEPRO_OPC_SLT_SN, | ||
343 | TILEPRO_OPC_SLT_U, | ||
344 | TILEPRO_OPC_SLT_U_SN, | ||
345 | TILEPRO_OPC_SLTB, | ||
346 | TILEPRO_OPC_SLTB_SN, | ||
347 | TILEPRO_OPC_SLTB_U, | ||
348 | TILEPRO_OPC_SLTB_U_SN, | ||
349 | TILEPRO_OPC_SLTE, | ||
350 | TILEPRO_OPC_SLTE_SN, | ||
351 | TILEPRO_OPC_SLTE_U, | ||
352 | TILEPRO_OPC_SLTE_U_SN, | ||
353 | TILEPRO_OPC_SLTEB, | ||
354 | TILEPRO_OPC_SLTEB_SN, | ||
355 | TILEPRO_OPC_SLTEB_U, | ||
356 | TILEPRO_OPC_SLTEB_U_SN, | ||
357 | TILEPRO_OPC_SLTEH, | ||
358 | TILEPRO_OPC_SLTEH_SN, | ||
359 | TILEPRO_OPC_SLTEH_U, | ||
360 | TILEPRO_OPC_SLTEH_U_SN, | ||
361 | TILEPRO_OPC_SLTH, | ||
362 | TILEPRO_OPC_SLTH_SN, | ||
363 | TILEPRO_OPC_SLTH_U, | ||
364 | TILEPRO_OPC_SLTH_U_SN, | ||
365 | TILEPRO_OPC_SLTI, | ||
366 | TILEPRO_OPC_SLTI_SN, | ||
367 | TILEPRO_OPC_SLTI_U, | ||
368 | TILEPRO_OPC_SLTI_U_SN, | ||
369 | TILEPRO_OPC_SLTIB, | ||
370 | TILEPRO_OPC_SLTIB_SN, | ||
371 | TILEPRO_OPC_SLTIB_U, | ||
372 | TILEPRO_OPC_SLTIB_U_SN, | ||
373 | TILEPRO_OPC_SLTIH, | ||
374 | TILEPRO_OPC_SLTIH_SN, | ||
375 | TILEPRO_OPC_SLTIH_U, | ||
376 | TILEPRO_OPC_SLTIH_U_SN, | ||
377 | TILEPRO_OPC_SNE, | ||
378 | TILEPRO_OPC_SNE_SN, | ||
379 | TILEPRO_OPC_SNEB, | ||
380 | TILEPRO_OPC_SNEB_SN, | ||
381 | TILEPRO_OPC_SNEH, | ||
382 | TILEPRO_OPC_SNEH_SN, | ||
383 | TILEPRO_OPC_SRA, | ||
384 | TILEPRO_OPC_SRA_SN, | ||
385 | TILEPRO_OPC_SRAB, | ||
386 | TILEPRO_OPC_SRAB_SN, | ||
387 | TILEPRO_OPC_SRAH, | ||
388 | TILEPRO_OPC_SRAH_SN, | ||
389 | TILEPRO_OPC_SRAI, | ||
390 | TILEPRO_OPC_SRAI_SN, | ||
391 | TILEPRO_OPC_SRAIB, | ||
392 | TILEPRO_OPC_SRAIB_SN, | ||
393 | TILEPRO_OPC_SRAIH, | ||
394 | TILEPRO_OPC_SRAIH_SN, | ||
395 | TILEPRO_OPC_SUB, | ||
396 | TILEPRO_OPC_SUB_SN, | ||
397 | TILEPRO_OPC_SUBB, | ||
398 | TILEPRO_OPC_SUBB_SN, | ||
399 | TILEPRO_OPC_SUBBS_U, | ||
400 | TILEPRO_OPC_SUBBS_U_SN, | ||
401 | TILEPRO_OPC_SUBH, | ||
402 | TILEPRO_OPC_SUBH_SN, | ||
403 | TILEPRO_OPC_SUBHS, | ||
404 | TILEPRO_OPC_SUBHS_SN, | ||
405 | TILEPRO_OPC_SUBS, | ||
406 | TILEPRO_OPC_SUBS_SN, | ||
407 | TILEPRO_OPC_SW, | ||
408 | TILEPRO_OPC_SWADD, | ||
409 | TILEPRO_OPC_SWINT0, | ||
410 | TILEPRO_OPC_SWINT1, | ||
411 | TILEPRO_OPC_SWINT2, | ||
412 | TILEPRO_OPC_SWINT3, | ||
413 | TILEPRO_OPC_TBLIDXB0, | ||
414 | TILEPRO_OPC_TBLIDXB0_SN, | ||
415 | TILEPRO_OPC_TBLIDXB1, | ||
416 | TILEPRO_OPC_TBLIDXB1_SN, | ||
417 | TILEPRO_OPC_TBLIDXB2, | ||
418 | TILEPRO_OPC_TBLIDXB2_SN, | ||
419 | TILEPRO_OPC_TBLIDXB3, | ||
420 | TILEPRO_OPC_TBLIDXB3_SN, | ||
421 | TILEPRO_OPC_TNS, | ||
422 | TILEPRO_OPC_TNS_SN, | ||
423 | TILEPRO_OPC_WH64, | ||
424 | TILEPRO_OPC_XOR, | ||
425 | TILEPRO_OPC_XOR_SN, | ||
426 | TILEPRO_OPC_XORI, | ||
427 | TILEPRO_OPC_XORI_SN, | ||
428 | TILEPRO_OPC_NONE | ||
429 | } tilepro_mnemonic; | ||
430 | |||
431 | |||
432 | |||
433 | |||
434 | typedef enum | ||
435 | { | ||
436 | TILEPRO_PIPELINE_X0, | ||
437 | TILEPRO_PIPELINE_X1, | ||
438 | TILEPRO_PIPELINE_Y0, | ||
439 | TILEPRO_PIPELINE_Y1, | ||
440 | TILEPRO_PIPELINE_Y2, | ||
441 | } tilepro_pipeline; | ||
442 | |||
443 | #define tilepro_is_x_pipeline(p) ((int)(p) <= (int)TILEPRO_PIPELINE_X1) | ||
444 | |||
445 | typedef enum | ||
446 | { | ||
447 | TILEPRO_OP_TYPE_REGISTER, | ||
448 | TILEPRO_OP_TYPE_IMMEDIATE, | ||
449 | TILEPRO_OP_TYPE_ADDRESS, | ||
450 | TILEPRO_OP_TYPE_SPR | ||
451 | } tilepro_operand_type; | ||
452 | |||
453 | struct tilepro_operand | ||
454 | { | ||
455 | /* Is this operand a register, immediate or address? */ | ||
456 | tilepro_operand_type type; | ||
457 | |||
458 | /* The default relocation type for this operand. */ | ||
459 | signed int default_reloc : 16; | ||
460 | |||
461 | /* How many bits is this value? (used for range checking) */ | ||
462 | unsigned int num_bits : 5; | ||
463 | |||
464 | /* Is the value signed? (used for range checking) */ | ||
465 | unsigned int is_signed : 1; | ||
466 | |||
467 | /* Is this operand a source register? */ | ||
468 | unsigned int is_src_reg : 1; | ||
469 | |||
470 | /* Is this operand written? (i.e. is it a destination register) */ | ||
471 | unsigned int is_dest_reg : 1; | ||
472 | |||
473 | /* Is this operand PC-relative? */ | ||
474 | unsigned int is_pc_relative : 1; | ||
475 | |||
476 | /* By how many bits do we right shift the value before inserting? */ | ||
477 | unsigned int rightshift : 2; | ||
478 | |||
479 | /* Return the bits for this operand to be ORed into an existing bundle. */ | ||
480 | tilepro_bundle_bits (*insert) (int op); | ||
481 | |||
482 | /* Extract this operand and return it. */ | ||
483 | unsigned int (*extract) (tilepro_bundle_bits bundle); | ||
484 | }; | ||
485 | |||
486 | |||
487 | extern const struct tilepro_operand tilepro_operands[]; | ||
488 | |||
489 | /* One finite-state machine per pipe for rapid instruction decoding. */ | ||
490 | extern const unsigned short * const | ||
491 | tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS]; | ||
492 | |||
493 | |||
494 | struct tilepro_opcode | ||
495 | { | ||
496 | /* The opcode mnemonic, e.g. "add" */ | ||
497 | const char *name; | ||
498 | |||
499 | /* The enum value for this mnemonic. */ | ||
500 | tilepro_mnemonic mnemonic; | ||
501 | |||
502 | /* A bit mask of which of the five pipes this instruction | ||
503 | is compatible with: | ||
504 | X0 0x01 | ||
505 | X1 0x02 | ||
506 | Y0 0x04 | ||
507 | Y1 0x08 | ||
508 | Y2 0x10 */ | ||
509 | unsigned char pipes; | ||
510 | |||
511 | /* How many operands are there? */ | ||
512 | unsigned char num_operands; | ||
513 | |||
514 | /* Which register does this write implicitly, or TREG_ZERO if none? */ | ||
515 | unsigned char implicitly_written_register; | ||
516 | |||
517 | /* Can this be bundled with other instructions (almost always true). */ | ||
518 | unsigned char can_bundle; | ||
519 | |||
520 | /* The description of the operands. Each of these is an | ||
521 | * index into the tilepro_operands[] table. */ | ||
522 | unsigned char operands[TILEPRO_NUM_PIPELINE_ENCODINGS][TILEPRO_MAX_OPERANDS]; | ||
523 | |||
524 | }; | ||
525 | |||
526 | extern const struct tilepro_opcode tilepro_opcodes[]; | ||
527 | |||
528 | |||
529 | /* Used for non-textual disassembly into structs. */ | ||
530 | struct tilepro_decoded_instruction | ||
531 | { | ||
532 | const struct tilepro_opcode *opcode; | ||
533 | const struct tilepro_operand *operands[TILEPRO_MAX_OPERANDS]; | ||
534 | int operand_values[TILEPRO_MAX_OPERANDS]; | ||
535 | }; | ||
536 | |||
537 | |||
538 | /* Disassemble a bundle into a struct for machine processing. */ | ||
539 | extern int parse_insn_tilepro(tilepro_bundle_bits bits, | ||
540 | unsigned int pc, | ||
541 | struct tilepro_decoded_instruction | ||
542 | decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]); | ||
543 | |||
544 | |||
545 | /* Given a set of bundle bits and a specific pipe, returns which | ||
546 | * instruction the bundle contains in that pipe. | ||
547 | */ | ||
548 | extern const struct tilepro_opcode * | ||
549 | find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe); | ||
550 | |||
551 | |||
552 | |||
553 | #endif /* opcode_tilepro_h */ | ||
diff --git a/arch/tile/include/asm/tile-desc_64.h b/arch/tile/include/asm/tile-desc_64.h new file mode 100644 index 000000000000..1819efcba54d --- /dev/null +++ b/arch/tile/include/asm/tile-desc_64.h | |||
@@ -0,0 +1,483 @@ | |||
1 | /* TILE-Gx opcode information. | ||
2 | * | ||
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation, version 2. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
12 | * NON INFRINGEMENT. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #ifndef opcode_tile_h | ||
22 | #define opcode_tile_h | ||
23 | |||
24 | #include <arch/opcode.h> | ||
25 | |||
26 | |||
27 | enum | ||
28 | { | ||
29 | TILEGX_MAX_OPERANDS = 4 /* bfexts */ | ||
30 | }; | ||
31 | |||
32 | typedef enum | ||
33 | { | ||
34 | TILEGX_OPC_BPT, | ||
35 | TILEGX_OPC_INFO, | ||
36 | TILEGX_OPC_INFOL, | ||
37 | TILEGX_OPC_MOVE, | ||
38 | TILEGX_OPC_MOVEI, | ||
39 | TILEGX_OPC_MOVELI, | ||
40 | TILEGX_OPC_PREFETCH, | ||
41 | TILEGX_OPC_PREFETCH_ADD_L1, | ||
42 | TILEGX_OPC_PREFETCH_ADD_L1_FAULT, | ||
43 | TILEGX_OPC_PREFETCH_ADD_L2, | ||
44 | TILEGX_OPC_PREFETCH_ADD_L2_FAULT, | ||
45 | TILEGX_OPC_PREFETCH_ADD_L3, | ||
46 | TILEGX_OPC_PREFETCH_ADD_L3_FAULT, | ||
47 | TILEGX_OPC_PREFETCH_L1, | ||
48 | TILEGX_OPC_PREFETCH_L1_FAULT, | ||
49 | TILEGX_OPC_PREFETCH_L2, | ||
50 | TILEGX_OPC_PREFETCH_L2_FAULT, | ||
51 | TILEGX_OPC_PREFETCH_L3, | ||
52 | TILEGX_OPC_PREFETCH_L3_FAULT, | ||
53 | TILEGX_OPC_RAISE, | ||
54 | TILEGX_OPC_ADD, | ||
55 | TILEGX_OPC_ADDI, | ||
56 | TILEGX_OPC_ADDLI, | ||
57 | TILEGX_OPC_ADDX, | ||
58 | TILEGX_OPC_ADDXI, | ||
59 | TILEGX_OPC_ADDXLI, | ||
60 | TILEGX_OPC_ADDXSC, | ||
61 | TILEGX_OPC_AND, | ||
62 | TILEGX_OPC_ANDI, | ||
63 | TILEGX_OPC_BEQZ, | ||
64 | TILEGX_OPC_BEQZT, | ||
65 | TILEGX_OPC_BFEXTS, | ||
66 | TILEGX_OPC_BFEXTU, | ||
67 | TILEGX_OPC_BFINS, | ||
68 | TILEGX_OPC_BGEZ, | ||
69 | TILEGX_OPC_BGEZT, | ||
70 | TILEGX_OPC_BGTZ, | ||
71 | TILEGX_OPC_BGTZT, | ||
72 | TILEGX_OPC_BLBC, | ||
73 | TILEGX_OPC_BLBCT, | ||
74 | TILEGX_OPC_BLBS, | ||
75 | TILEGX_OPC_BLBST, | ||
76 | TILEGX_OPC_BLEZ, | ||
77 | TILEGX_OPC_BLEZT, | ||
78 | TILEGX_OPC_BLTZ, | ||
79 | TILEGX_OPC_BLTZT, | ||
80 | TILEGX_OPC_BNEZ, | ||
81 | TILEGX_OPC_BNEZT, | ||
82 | TILEGX_OPC_CLZ, | ||
83 | TILEGX_OPC_CMOVEQZ, | ||
84 | TILEGX_OPC_CMOVNEZ, | ||
85 | TILEGX_OPC_CMPEQ, | ||
86 | TILEGX_OPC_CMPEQI, | ||
87 | TILEGX_OPC_CMPEXCH, | ||
88 | TILEGX_OPC_CMPEXCH4, | ||
89 | TILEGX_OPC_CMPLES, | ||
90 | TILEGX_OPC_CMPLEU, | ||
91 | TILEGX_OPC_CMPLTS, | ||
92 | TILEGX_OPC_CMPLTSI, | ||
93 | TILEGX_OPC_CMPLTU, | ||
94 | TILEGX_OPC_CMPLTUI, | ||
95 | TILEGX_OPC_CMPNE, | ||
96 | TILEGX_OPC_CMUL, | ||
97 | TILEGX_OPC_CMULA, | ||
98 | TILEGX_OPC_CMULAF, | ||
99 | TILEGX_OPC_CMULF, | ||
100 | TILEGX_OPC_CMULFR, | ||
101 | TILEGX_OPC_CMULH, | ||
102 | TILEGX_OPC_CMULHR, | ||
103 | TILEGX_OPC_CRC32_32, | ||
104 | TILEGX_OPC_CRC32_8, | ||
105 | TILEGX_OPC_CTZ, | ||
106 | TILEGX_OPC_DBLALIGN, | ||
107 | TILEGX_OPC_DBLALIGN2, | ||
108 | TILEGX_OPC_DBLALIGN4, | ||
109 | TILEGX_OPC_DBLALIGN6, | ||
110 | TILEGX_OPC_DRAIN, | ||
111 | TILEGX_OPC_DTLBPR, | ||
112 | TILEGX_OPC_EXCH, | ||
113 | TILEGX_OPC_EXCH4, | ||
114 | TILEGX_OPC_FDOUBLE_ADD_FLAGS, | ||
115 | TILEGX_OPC_FDOUBLE_ADDSUB, | ||
116 | TILEGX_OPC_FDOUBLE_MUL_FLAGS, | ||
117 | TILEGX_OPC_FDOUBLE_PACK1, | ||
118 | TILEGX_OPC_FDOUBLE_PACK2, | ||
119 | TILEGX_OPC_FDOUBLE_SUB_FLAGS, | ||
120 | TILEGX_OPC_FDOUBLE_UNPACK_MAX, | ||
121 | TILEGX_OPC_FDOUBLE_UNPACK_MIN, | ||
122 | TILEGX_OPC_FETCHADD, | ||
123 | TILEGX_OPC_FETCHADD4, | ||
124 | TILEGX_OPC_FETCHADDGEZ, | ||
125 | TILEGX_OPC_FETCHADDGEZ4, | ||
126 | TILEGX_OPC_FETCHAND, | ||
127 | TILEGX_OPC_FETCHAND4, | ||
128 | TILEGX_OPC_FETCHOR, | ||
129 | TILEGX_OPC_FETCHOR4, | ||
130 | TILEGX_OPC_FINV, | ||
131 | TILEGX_OPC_FLUSH, | ||
132 | TILEGX_OPC_FLUSHWB, | ||
133 | TILEGX_OPC_FNOP, | ||
134 | TILEGX_OPC_FSINGLE_ADD1, | ||
135 | TILEGX_OPC_FSINGLE_ADDSUB2, | ||
136 | TILEGX_OPC_FSINGLE_MUL1, | ||
137 | TILEGX_OPC_FSINGLE_MUL2, | ||
138 | TILEGX_OPC_FSINGLE_PACK1, | ||
139 | TILEGX_OPC_FSINGLE_PACK2, | ||
140 | TILEGX_OPC_FSINGLE_SUB1, | ||
141 | TILEGX_OPC_ICOH, | ||
142 | TILEGX_OPC_ILL, | ||
143 | TILEGX_OPC_INV, | ||
144 | TILEGX_OPC_IRET, | ||
145 | TILEGX_OPC_J, | ||
146 | TILEGX_OPC_JAL, | ||
147 | TILEGX_OPC_JALR, | ||
148 | TILEGX_OPC_JALRP, | ||
149 | TILEGX_OPC_JR, | ||
150 | TILEGX_OPC_JRP, | ||
151 | TILEGX_OPC_LD, | ||
152 | TILEGX_OPC_LD1S, | ||
153 | TILEGX_OPC_LD1S_ADD, | ||
154 | TILEGX_OPC_LD1U, | ||
155 | TILEGX_OPC_LD1U_ADD, | ||
156 | TILEGX_OPC_LD2S, | ||
157 | TILEGX_OPC_LD2S_ADD, | ||
158 | TILEGX_OPC_LD2U, | ||
159 | TILEGX_OPC_LD2U_ADD, | ||
160 | TILEGX_OPC_LD4S, | ||
161 | TILEGX_OPC_LD4S_ADD, | ||
162 | TILEGX_OPC_LD4U, | ||
163 | TILEGX_OPC_LD4U_ADD, | ||
164 | TILEGX_OPC_LD_ADD, | ||
165 | TILEGX_OPC_LDNA, | ||
166 | TILEGX_OPC_LDNA_ADD, | ||
167 | TILEGX_OPC_LDNT, | ||
168 | TILEGX_OPC_LDNT1S, | ||
169 | TILEGX_OPC_LDNT1S_ADD, | ||
170 | TILEGX_OPC_LDNT1U, | ||
171 | TILEGX_OPC_LDNT1U_ADD, | ||
172 | TILEGX_OPC_LDNT2S, | ||
173 | TILEGX_OPC_LDNT2S_ADD, | ||
174 | TILEGX_OPC_LDNT2U, | ||
175 | TILEGX_OPC_LDNT2U_ADD, | ||
176 | TILEGX_OPC_LDNT4S, | ||
177 | TILEGX_OPC_LDNT4S_ADD, | ||
178 | TILEGX_OPC_LDNT4U, | ||
179 | TILEGX_OPC_LDNT4U_ADD, | ||
180 | TILEGX_OPC_LDNT_ADD, | ||
181 | TILEGX_OPC_LNK, | ||
182 | TILEGX_OPC_MF, | ||
183 | TILEGX_OPC_MFSPR, | ||
184 | TILEGX_OPC_MM, | ||
185 | TILEGX_OPC_MNZ, | ||
186 | TILEGX_OPC_MTSPR, | ||
187 | TILEGX_OPC_MUL_HS_HS, | ||
188 | TILEGX_OPC_MUL_HS_HU, | ||
189 | TILEGX_OPC_MUL_HS_LS, | ||
190 | TILEGX_OPC_MUL_HS_LU, | ||
191 | TILEGX_OPC_MUL_HU_HU, | ||
192 | TILEGX_OPC_MUL_HU_LS, | ||
193 | TILEGX_OPC_MUL_HU_LU, | ||
194 | TILEGX_OPC_MUL_LS_LS, | ||
195 | TILEGX_OPC_MUL_LS_LU, | ||
196 | TILEGX_OPC_MUL_LU_LU, | ||
197 | TILEGX_OPC_MULA_HS_HS, | ||
198 | TILEGX_OPC_MULA_HS_HU, | ||
199 | TILEGX_OPC_MULA_HS_LS, | ||
200 | TILEGX_OPC_MULA_HS_LU, | ||
201 | TILEGX_OPC_MULA_HU_HU, | ||
202 | TILEGX_OPC_MULA_HU_LS, | ||
203 | TILEGX_OPC_MULA_HU_LU, | ||
204 | TILEGX_OPC_MULA_LS_LS, | ||
205 | TILEGX_OPC_MULA_LS_LU, | ||
206 | TILEGX_OPC_MULA_LU_LU, | ||
207 | TILEGX_OPC_MULAX, | ||
208 | TILEGX_OPC_MULX, | ||
209 | TILEGX_OPC_MZ, | ||
210 | TILEGX_OPC_NAP, | ||
211 | TILEGX_OPC_NOP, | ||
212 | TILEGX_OPC_NOR, | ||
213 | TILEGX_OPC_OR, | ||
214 | TILEGX_OPC_ORI, | ||
215 | TILEGX_OPC_PCNT, | ||
216 | TILEGX_OPC_REVBITS, | ||
217 | TILEGX_OPC_REVBYTES, | ||
218 | TILEGX_OPC_ROTL, | ||
219 | TILEGX_OPC_ROTLI, | ||
220 | TILEGX_OPC_SHL, | ||
221 | TILEGX_OPC_SHL16INSLI, | ||
222 | TILEGX_OPC_SHL1ADD, | ||
223 | TILEGX_OPC_SHL1ADDX, | ||
224 | TILEGX_OPC_SHL2ADD, | ||
225 | TILEGX_OPC_SHL2ADDX, | ||
226 | TILEGX_OPC_SHL3ADD, | ||
227 | TILEGX_OPC_SHL3ADDX, | ||
228 | TILEGX_OPC_SHLI, | ||
229 | TILEGX_OPC_SHLX, | ||
230 | TILEGX_OPC_SHLXI, | ||
231 | TILEGX_OPC_SHRS, | ||
232 | TILEGX_OPC_SHRSI, | ||
233 | TILEGX_OPC_SHRU, | ||
234 | TILEGX_OPC_SHRUI, | ||
235 | TILEGX_OPC_SHRUX, | ||
236 | TILEGX_OPC_SHRUXI, | ||
237 | TILEGX_OPC_SHUFFLEBYTES, | ||
238 | TILEGX_OPC_ST, | ||
239 | TILEGX_OPC_ST1, | ||
240 | TILEGX_OPC_ST1_ADD, | ||
241 | TILEGX_OPC_ST2, | ||
242 | TILEGX_OPC_ST2_ADD, | ||
243 | TILEGX_OPC_ST4, | ||
244 | TILEGX_OPC_ST4_ADD, | ||
245 | TILEGX_OPC_ST_ADD, | ||
246 | TILEGX_OPC_STNT, | ||
247 | TILEGX_OPC_STNT1, | ||
248 | TILEGX_OPC_STNT1_ADD, | ||
249 | TILEGX_OPC_STNT2, | ||
250 | TILEGX_OPC_STNT2_ADD, | ||
251 | TILEGX_OPC_STNT4, | ||
252 | TILEGX_OPC_STNT4_ADD, | ||
253 | TILEGX_OPC_STNT_ADD, | ||
254 | TILEGX_OPC_SUB, | ||
255 | TILEGX_OPC_SUBX, | ||
256 | TILEGX_OPC_SUBXSC, | ||
257 | TILEGX_OPC_SWINT0, | ||
258 | TILEGX_OPC_SWINT1, | ||
259 | TILEGX_OPC_SWINT2, | ||
260 | TILEGX_OPC_SWINT3, | ||
261 | TILEGX_OPC_TBLIDXB0, | ||
262 | TILEGX_OPC_TBLIDXB1, | ||
263 | TILEGX_OPC_TBLIDXB2, | ||
264 | TILEGX_OPC_TBLIDXB3, | ||
265 | TILEGX_OPC_V1ADD, | ||
266 | TILEGX_OPC_V1ADDI, | ||
267 | TILEGX_OPC_V1ADDUC, | ||
268 | TILEGX_OPC_V1ADIFFU, | ||
269 | TILEGX_OPC_V1AVGU, | ||
270 | TILEGX_OPC_V1CMPEQ, | ||
271 | TILEGX_OPC_V1CMPEQI, | ||
272 | TILEGX_OPC_V1CMPLES, | ||
273 | TILEGX_OPC_V1CMPLEU, | ||
274 | TILEGX_OPC_V1CMPLTS, | ||
275 | TILEGX_OPC_V1CMPLTSI, | ||
276 | TILEGX_OPC_V1CMPLTU, | ||
277 | TILEGX_OPC_V1CMPLTUI, | ||
278 | TILEGX_OPC_V1CMPNE, | ||
279 | TILEGX_OPC_V1DDOTPU, | ||
280 | TILEGX_OPC_V1DDOTPUA, | ||
281 | TILEGX_OPC_V1DDOTPUS, | ||
282 | TILEGX_OPC_V1DDOTPUSA, | ||
283 | TILEGX_OPC_V1DOTP, | ||
284 | TILEGX_OPC_V1DOTPA, | ||
285 | TILEGX_OPC_V1DOTPU, | ||
286 | TILEGX_OPC_V1DOTPUA, | ||
287 | TILEGX_OPC_V1DOTPUS, | ||
288 | TILEGX_OPC_V1DOTPUSA, | ||
289 | TILEGX_OPC_V1INT_H, | ||
290 | TILEGX_OPC_V1INT_L, | ||
291 | TILEGX_OPC_V1MAXU, | ||
292 | TILEGX_OPC_V1MAXUI, | ||
293 | TILEGX_OPC_V1MINU, | ||
294 | TILEGX_OPC_V1MINUI, | ||
295 | TILEGX_OPC_V1MNZ, | ||
296 | TILEGX_OPC_V1MULTU, | ||
297 | TILEGX_OPC_V1MULU, | ||
298 | TILEGX_OPC_V1MULUS, | ||
299 | TILEGX_OPC_V1MZ, | ||
300 | TILEGX_OPC_V1SADAU, | ||
301 | TILEGX_OPC_V1SADU, | ||
302 | TILEGX_OPC_V1SHL, | ||
303 | TILEGX_OPC_V1SHLI, | ||
304 | TILEGX_OPC_V1SHRS, | ||
305 | TILEGX_OPC_V1SHRSI, | ||
306 | TILEGX_OPC_V1SHRU, | ||
307 | TILEGX_OPC_V1SHRUI, | ||
308 | TILEGX_OPC_V1SUB, | ||
309 | TILEGX_OPC_V1SUBUC, | ||
310 | TILEGX_OPC_V2ADD, | ||
311 | TILEGX_OPC_V2ADDI, | ||
312 | TILEGX_OPC_V2ADDSC, | ||
313 | TILEGX_OPC_V2ADIFFS, | ||
314 | TILEGX_OPC_V2AVGS, | ||
315 | TILEGX_OPC_V2CMPEQ, | ||
316 | TILEGX_OPC_V2CMPEQI, | ||
317 | TILEGX_OPC_V2CMPLES, | ||
318 | TILEGX_OPC_V2CMPLEU, | ||
319 | TILEGX_OPC_V2CMPLTS, | ||
320 | TILEGX_OPC_V2CMPLTSI, | ||
321 | TILEGX_OPC_V2CMPLTU, | ||
322 | TILEGX_OPC_V2CMPLTUI, | ||
323 | TILEGX_OPC_V2CMPNE, | ||
324 | TILEGX_OPC_V2DOTP, | ||
325 | TILEGX_OPC_V2DOTPA, | ||
326 | TILEGX_OPC_V2INT_H, | ||
327 | TILEGX_OPC_V2INT_L, | ||
328 | TILEGX_OPC_V2MAXS, | ||
329 | TILEGX_OPC_V2MAXSI, | ||
330 | TILEGX_OPC_V2MINS, | ||
331 | TILEGX_OPC_V2MINSI, | ||
332 | TILEGX_OPC_V2MNZ, | ||
333 | TILEGX_OPC_V2MULFSC, | ||
334 | TILEGX_OPC_V2MULS, | ||
335 | TILEGX_OPC_V2MULTS, | ||
336 | TILEGX_OPC_V2MZ, | ||
337 | TILEGX_OPC_V2PACKH, | ||
338 | TILEGX_OPC_V2PACKL, | ||
339 | TILEGX_OPC_V2PACKUC, | ||
340 | TILEGX_OPC_V2SADAS, | ||
341 | TILEGX_OPC_V2SADAU, | ||
342 | TILEGX_OPC_V2SADS, | ||
343 | TILEGX_OPC_V2SADU, | ||
344 | TILEGX_OPC_V2SHL, | ||
345 | TILEGX_OPC_V2SHLI, | ||
346 | TILEGX_OPC_V2SHLSC, | ||
347 | TILEGX_OPC_V2SHRS, | ||
348 | TILEGX_OPC_V2SHRSI, | ||
349 | TILEGX_OPC_V2SHRU, | ||
350 | TILEGX_OPC_V2SHRUI, | ||
351 | TILEGX_OPC_V2SUB, | ||
352 | TILEGX_OPC_V2SUBSC, | ||
353 | TILEGX_OPC_V4ADD, | ||
354 | TILEGX_OPC_V4ADDSC, | ||
355 | TILEGX_OPC_V4INT_H, | ||
356 | TILEGX_OPC_V4INT_L, | ||
357 | TILEGX_OPC_V4PACKSC, | ||
358 | TILEGX_OPC_V4SHL, | ||
359 | TILEGX_OPC_V4SHLSC, | ||
360 | TILEGX_OPC_V4SHRS, | ||
361 | TILEGX_OPC_V4SHRU, | ||
362 | TILEGX_OPC_V4SUB, | ||
363 | TILEGX_OPC_V4SUBSC, | ||
364 | TILEGX_OPC_WH64, | ||
365 | TILEGX_OPC_XOR, | ||
366 | TILEGX_OPC_XORI, | ||
367 | TILEGX_OPC_NONE | ||
368 | } tilegx_mnemonic; | ||
369 | |||
370 | |||
371 | |||
372 | typedef enum | ||
373 | { | ||
374 | TILEGX_PIPELINE_X0, | ||
375 | TILEGX_PIPELINE_X1, | ||
376 | TILEGX_PIPELINE_Y0, | ||
377 | TILEGX_PIPELINE_Y1, | ||
378 | TILEGX_PIPELINE_Y2, | ||
379 | } tilegx_pipeline; | ||
380 | |||
381 | #define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1) | ||
382 | |||
383 | typedef enum | ||
384 | { | ||
385 | TILEGX_OP_TYPE_REGISTER, | ||
386 | TILEGX_OP_TYPE_IMMEDIATE, | ||
387 | TILEGX_OP_TYPE_ADDRESS, | ||
388 | TILEGX_OP_TYPE_SPR | ||
389 | } tilegx_operand_type; | ||
390 | |||
391 | struct tilegx_operand | ||
392 | { | ||
393 | /* Is this operand a register, immediate or address? */ | ||
394 | tilegx_operand_type type; | ||
395 | |||
396 | /* The default relocation type for this operand. */ | ||
397 | signed int default_reloc : 16; | ||
398 | |||
399 | /* How many bits is this value? (used for range checking) */ | ||
400 | unsigned int num_bits : 5; | ||
401 | |||
402 | /* Is the value signed? (used for range checking) */ | ||
403 | unsigned int is_signed : 1; | ||
404 | |||
405 | /* Is this operand a source register? */ | ||
406 | unsigned int is_src_reg : 1; | ||
407 | |||
408 | /* Is this operand written? (i.e. is it a destination register) */ | ||
409 | unsigned int is_dest_reg : 1; | ||
410 | |||
411 | /* Is this operand PC-relative? */ | ||
412 | unsigned int is_pc_relative : 1; | ||
413 | |||
414 | /* By how many bits do we right shift the value before inserting? */ | ||
415 | unsigned int rightshift : 2; | ||
416 | |||
417 | /* Return the bits for this operand to be ORed into an existing bundle. */ | ||
418 | tilegx_bundle_bits (*insert) (int op); | ||
419 | |||
420 | /* Extract this operand and return it. */ | ||
421 | unsigned int (*extract) (tilegx_bundle_bits bundle); | ||
422 | }; | ||
423 | |||
424 | |||
425 | extern const struct tilegx_operand tilegx_operands[]; | ||
426 | |||
427 | /* One finite-state machine per pipe for rapid instruction decoding. */ | ||
428 | extern const unsigned short * const | ||
429 | tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS]; | ||
430 | |||
431 | |||
432 | struct tilegx_opcode | ||
433 | { | ||
434 | /* The opcode mnemonic, e.g. "add" */ | ||
435 | const char *name; | ||
436 | |||
437 | /* The enum value for this mnemonic. */ | ||
438 | tilegx_mnemonic mnemonic; | ||
439 | |||
440 | /* A bit mask of which of the five pipes this instruction | ||
441 | is compatible with: | ||
442 | X0 0x01 | ||
443 | X1 0x02 | ||
444 | Y0 0x04 | ||
445 | Y1 0x08 | ||
446 | Y2 0x10 */ | ||
447 | unsigned char pipes; | ||
448 | |||
449 | /* How many operands are there? */ | ||
450 | unsigned char num_operands; | ||
451 | |||
452 | /* Which register does this write implicitly, or TREG_ZERO if none? */ | ||
453 | unsigned char implicitly_written_register; | ||
454 | |||
455 | /* Can this be bundled with other instructions (almost always true). */ | ||
456 | unsigned char can_bundle; | ||
457 | |||
458 | /* The description of the operands. Each of these is an | ||
459 | * index into the tilegx_operands[] table. */ | ||
460 | unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS]; | ||
461 | |||
462 | }; | ||
463 | |||
464 | extern const struct tilegx_opcode tilegx_opcodes[]; | ||
465 | |||
466 | /* Used for non-textual disassembly into structs. */ | ||
467 | struct tilegx_decoded_instruction | ||
468 | { | ||
469 | const struct tilegx_opcode *opcode; | ||
470 | const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS]; | ||
471 | long long operand_values[TILEGX_MAX_OPERANDS]; | ||
472 | }; | ||
473 | |||
474 | |||
475 | /* Disassemble a bundle into a struct for machine processing. */ | ||
476 | extern int parse_insn_tilegx(tilegx_bundle_bits bits, | ||
477 | unsigned long long pc, | ||
478 | struct tilegx_decoded_instruction | ||
479 | decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]); | ||
480 | |||
481 | |||
482 | |||
483 | #endif /* opcode_tilegx_h */ | ||
diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c index 1dc71eabfc5a..9092ce8aa6b4 100644 --- a/arch/tile/kernel/backtrace.c +++ b/arch/tile/kernel/backtrace.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2010 Tilera Corporation. All Rights Reserved. | 2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or | 4 | * This program is free software; you can redistribute it and/or |
5 | * modify it under the terms of the GNU General Public License | 5 | * modify it under the terms of the GNU General Public License |
@@ -15,13 +15,11 @@ | |||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/string.h> | 16 | #include <linux/string.h> |
17 | #include <asm/backtrace.h> | 17 | #include <asm/backtrace.h> |
18 | #include <asm/opcode-tile.h> | 18 | #include <asm/tile-desc.h> |
19 | #include <arch/abi.h> | 19 | #include <arch/abi.h> |
20 | 20 | ||
21 | #ifdef __tilegx__ | 21 | #ifdef __tilegx__ |
22 | #define tile_bundle_bits tilegx_bundle_bits | ||
23 | #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE | 22 | #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE |
24 | #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES | ||
25 | #define tile_decoded_instruction tilegx_decoded_instruction | 23 | #define tile_decoded_instruction tilegx_decoded_instruction |
26 | #define tile_mnemonic tilegx_mnemonic | 24 | #define tile_mnemonic tilegx_mnemonic |
27 | #define parse_insn_tile parse_insn_tilegx | 25 | #define parse_insn_tile parse_insn_tilegx |
@@ -35,7 +33,18 @@ | |||
35 | #define OPCODE_STORE TILEGX_OPC_ST | 33 | #define OPCODE_STORE TILEGX_OPC_ST |
36 | typedef long long bt_int_reg_t; | 34 | typedef long long bt_int_reg_t; |
37 | #else | 35 | #else |
38 | #define OPCODE_STORE TILE_OPC_SW | 36 | #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE |
37 | #define tile_decoded_instruction tilepro_decoded_instruction | ||
38 | #define tile_mnemonic tilepro_mnemonic | ||
39 | #define parse_insn_tile parse_insn_tilepro | ||
40 | #define TILE_OPC_IRET TILEPRO_OPC_IRET | ||
41 | #define TILE_OPC_ADDI TILEPRO_OPC_ADDI | ||
42 | #define TILE_OPC_ADDLI TILEPRO_OPC_ADDLI | ||
43 | #define TILE_OPC_INFO TILEPRO_OPC_INFO | ||
44 | #define TILE_OPC_INFOL TILEPRO_OPC_INFOL | ||
45 | #define TILE_OPC_JRP TILEPRO_OPC_JRP | ||
46 | #define TILE_OPC_MOVE TILEPRO_OPC_MOVE | ||
47 | #define OPCODE_STORE TILEPRO_OPC_SW | ||
39 | typedef int bt_int_reg_t; | 48 | typedef int bt_int_reg_t; |
40 | #endif | 49 | #endif |
41 | 50 | ||
diff --git a/arch/tile/kernel/module.c b/arch/tile/kernel/module.c index 28fa6ece9d3a..b90ab9925674 100644 --- a/arch/tile/kernel/module.c +++ b/arch/tile/kernel/module.c | |||
@@ -20,9 +20,9 @@ | |||
20 | #include <linux/fs.h> | 20 | #include <linux/fs.h> |
21 | #include <linux/string.h> | 21 | #include <linux/string.h> |
22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
23 | #include <asm/opcode-tile.h> | ||
24 | #include <asm/pgtable.h> | 23 | #include <asm/pgtable.h> |
25 | #include <asm/homecache.h> | 24 | #include <asm/homecache.h> |
25 | #include <arch/opcode.h> | ||
26 | 26 | ||
27 | #ifdef __tilegx__ | 27 | #ifdef __tilegx__ |
28 | # define Elf_Rela Elf64_Rela | 28 | # define Elf_Rela Elf64_Rela |
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c index 4032ca8e51b6..b7a879504086 100644 --- a/arch/tile/kernel/single_step.c +++ b/arch/tile/kernel/single_step.c | |||
@@ -25,9 +25,8 @@ | |||
25 | #include <linux/types.h> | 25 | #include <linux/types.h> |
26 | #include <linux/err.h> | 26 | #include <linux/err.h> |
27 | #include <asm/cacheflush.h> | 27 | #include <asm/cacheflush.h> |
28 | #include <asm/opcode-tile.h> | ||
29 | #include <asm/opcode_constants.h> | ||
30 | #include <arch/abi.h> | 28 | #include <arch/abi.h> |
29 | #include <arch/opcode.h> | ||
31 | 30 | ||
32 | #define signExtend17(val) sign_extend((val), 17) | 31 | #define signExtend17(val) sign_extend((val), 17) |
33 | #define TILE_X1_MASK (0xffffffffULL << 31) | 32 | #define TILE_X1_MASK (0xffffffffULL << 31) |
@@ -118,7 +117,7 @@ static tile_bundle_bits rewrite_load_store_unaligned( | |||
118 | int val_reg, addr_reg, err, val; | 117 | int val_reg, addr_reg, err, val; |
119 | 118 | ||
120 | /* Get address and value registers */ | 119 | /* Get address and value registers */ |
121 | if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) { | 120 | if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) { |
122 | addr_reg = get_SrcA_Y2(bundle); | 121 | addr_reg = get_SrcA_Y2(bundle); |
123 | val_reg = get_SrcBDest_Y2(bundle); | 122 | val_reg = get_SrcBDest_Y2(bundle); |
124 | } else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) { | 123 | } else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) { |
@@ -229,7 +228,7 @@ P("\n"); | |||
229 | } | 228 | } |
230 | ++unaligned_fixup_count; | 229 | ++unaligned_fixup_count; |
231 | 230 | ||
232 | if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) { | 231 | if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) { |
233 | /* Convert the Y2 instruction to a prefetch. */ | 232 | /* Convert the Y2 instruction to a prefetch. */ |
234 | bundle &= ~(create_SrcBDest_Y2(-1) | | 233 | bundle &= ~(create_SrcBDest_Y2(-1) | |
235 | create_Opcode_Y2(-1)); | 234 | create_Opcode_Y2(-1)); |
@@ -389,7 +388,7 @@ void single_step_once(struct pt_regs *regs) | |||
389 | state->branch_next_pc = 0; | 388 | state->branch_next_pc = 0; |
390 | state->update = 0; | 389 | state->update = 0; |
391 | 390 | ||
392 | if (!(bundle & TILE_BUNDLE_Y_ENCODING_MASK)) { | 391 | if (!(bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK)) { |
393 | /* two wide, check for control flow */ | 392 | /* two wide, check for control flow */ |
394 | int opcode = get_Opcode_X1(bundle); | 393 | int opcode = get_Opcode_X1(bundle); |
395 | 394 | ||
diff --git a/arch/tile/kernel/tile-desc_32.c b/arch/tile/kernel/tile-desc_32.c index 7e31a1285788..dd7bd1d8563c 100644 --- a/arch/tile/kernel/tile-desc_32.c +++ b/arch/tile/kernel/tile-desc_32.c | |||
@@ -1,3 +1,23 @@ | |||
1 | /* TILEPro opcode information. | ||
2 | * | ||
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation, version 2. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
12 | * NON INFRINGEMENT. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
19 | */ | ||
20 | |||
1 | /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ | 21 | /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ |
2 | #define BFD_RELOC(x) -1 | 22 | #define BFD_RELOC(x) -1 |
3 | 23 | ||
@@ -6,1217 +26,1217 @@ | |||
6 | #define TREG_SN 56 | 26 | #define TREG_SN 56 |
7 | #define TREG_ZERO 63 | 27 | #define TREG_ZERO 63 |
8 | 28 | ||
9 | /* FIXME: Rename this. */ | ||
10 | #include <asm/opcode-tile.h> | ||
11 | |||
12 | #include <linux/stddef.h> | 29 | #include <linux/stddef.h> |
30 | #include <asm/tile-desc.h> | ||
13 | 31 | ||
14 | const struct tile_opcode tile_opcodes[395] = | 32 | const struct tilepro_opcode tilepro_opcodes[395] = |
15 | { | 33 | { |
16 | { "bpt", TILE_OPC_BPT, 0x2, 0, TREG_ZERO, 0, | 34 | { "bpt", TILEPRO_OPC_BPT, 0x2, 0, TREG_ZERO, 0, |
17 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 35 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
18 | }, | 36 | }, |
19 | { "info", TILE_OPC_INFO, 0xf, 1, TREG_ZERO, 1, | 37 | { "info", TILEPRO_OPC_INFO, 0xf, 1, TREG_ZERO, 1, |
20 | { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } }, | 38 | { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } }, |
21 | }, | 39 | }, |
22 | { "infol", TILE_OPC_INFOL, 0x3, 1, TREG_ZERO, 1, | 40 | { "infol", TILEPRO_OPC_INFOL, 0x3, 1, TREG_ZERO, 1, |
23 | { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } }, | 41 | { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } }, |
24 | }, | 42 | }, |
25 | { "j", TILE_OPC_J, 0x2, 1, TREG_ZERO, 1, | 43 | { "j", TILEPRO_OPC_J, 0x2, 1, TREG_ZERO, 1, |
26 | { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } }, | 44 | { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } }, |
27 | }, | 45 | }, |
28 | { "jal", TILE_OPC_JAL, 0x2, 1, TREG_LR, 1, | 46 | { "jal", TILEPRO_OPC_JAL, 0x2, 1, TREG_LR, 1, |
29 | { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } }, | 47 | { { 0, }, { 6 }, { 0, }, { 0, }, { 0, } }, |
30 | }, | 48 | }, |
31 | { "move", TILE_OPC_MOVE, 0xf, 2, TREG_ZERO, 1, | 49 | { "move", TILEPRO_OPC_MOVE, 0xf, 2, TREG_ZERO, 1, |
32 | { { 7, 8 }, { 9, 10 }, { 11, 12 }, { 13, 14 }, { 0, } }, | 50 | { { 7, 8 }, { 9, 10 }, { 11, 12 }, { 13, 14 }, { 0, } }, |
33 | }, | 51 | }, |
34 | { "move.sn", TILE_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1, | 52 | { "move.sn", TILEPRO_OPC_MOVE_SN, 0x3, 2, TREG_SN, 1, |
35 | { { 7, 8 }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 53 | { { 7, 8 }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
36 | }, | 54 | }, |
37 | { "movei", TILE_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1, | 55 | { "movei", TILEPRO_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1, |
38 | { { 7, 0 }, { 9, 1 }, { 11, 2 }, { 13, 3 }, { 0, } }, | 56 | { { 7, 0 }, { 9, 1 }, { 11, 2 }, { 13, 3 }, { 0, } }, |
39 | }, | 57 | }, |
40 | { "movei.sn", TILE_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1, | 58 | { "movei.sn", TILEPRO_OPC_MOVEI_SN, 0x3, 2, TREG_SN, 1, |
41 | { { 7, 0 }, { 9, 1 }, { 0, }, { 0, }, { 0, } }, | 59 | { { 7, 0 }, { 9, 1 }, { 0, }, { 0, }, { 0, } }, |
42 | }, | 60 | }, |
43 | { "moveli", TILE_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1, | 61 | { "moveli", TILEPRO_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1, |
44 | { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, | 62 | { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, |
45 | }, | 63 | }, |
46 | { "moveli.sn", TILE_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1, | 64 | { "moveli.sn", TILEPRO_OPC_MOVELI_SN, 0x3, 2, TREG_SN, 1, |
47 | { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, | 65 | { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, |
48 | }, | 66 | }, |
49 | { "movelis", TILE_OPC_MOVELIS, 0x3, 2, TREG_SN, 1, | 67 | { "movelis", TILEPRO_OPC_MOVELIS, 0x3, 2, TREG_SN, 1, |
50 | { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, | 68 | { { 7, 4 }, { 9, 5 }, { 0, }, { 0, }, { 0, } }, |
51 | }, | 69 | }, |
52 | { "prefetch", TILE_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1, | 70 | { "prefetch", TILEPRO_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1, |
53 | { { 0, }, { 10 }, { 0, }, { 0, }, { 15 } }, | 71 | { { 0, }, { 10 }, { 0, }, { 0, }, { 15 } }, |
54 | }, | 72 | }, |
55 | { "raise", TILE_OPC_RAISE, 0x2, 0, TREG_ZERO, 1, | 73 | { "raise", TILEPRO_OPC_RAISE, 0x2, 0, TREG_ZERO, 1, |
56 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 74 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
57 | }, | 75 | }, |
58 | { "add", TILE_OPC_ADD, 0xf, 3, TREG_ZERO, 1, | 76 | { "add", TILEPRO_OPC_ADD, 0xf, 3, TREG_ZERO, 1, |
59 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 77 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
60 | }, | 78 | }, |
61 | { "add.sn", TILE_OPC_ADD_SN, 0x3, 3, TREG_SN, 1, | 79 | { "add.sn", TILEPRO_OPC_ADD_SN, 0x3, 3, TREG_SN, 1, |
62 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 80 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
63 | }, | 81 | }, |
64 | { "addb", TILE_OPC_ADDB, 0x3, 3, TREG_ZERO, 1, | 82 | { "addb", TILEPRO_OPC_ADDB, 0x3, 3, TREG_ZERO, 1, |
65 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 83 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
66 | }, | 84 | }, |
67 | { "addb.sn", TILE_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1, | 85 | { "addb.sn", TILEPRO_OPC_ADDB_SN, 0x3, 3, TREG_SN, 1, |
68 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 86 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
69 | }, | 87 | }, |
70 | { "addbs_u", TILE_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1, | 88 | { "addbs_u", TILEPRO_OPC_ADDBS_U, 0x3, 3, TREG_ZERO, 1, |
71 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 89 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
72 | }, | 90 | }, |
73 | { "addbs_u.sn", TILE_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1, | 91 | { "addbs_u.sn", TILEPRO_OPC_ADDBS_U_SN, 0x3, 3, TREG_SN, 1, |
74 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 92 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
75 | }, | 93 | }, |
76 | { "addh", TILE_OPC_ADDH, 0x3, 3, TREG_ZERO, 1, | 94 | { "addh", TILEPRO_OPC_ADDH, 0x3, 3, TREG_ZERO, 1, |
77 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 95 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
78 | }, | 96 | }, |
79 | { "addh.sn", TILE_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1, | 97 | { "addh.sn", TILEPRO_OPC_ADDH_SN, 0x3, 3, TREG_SN, 1, |
80 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 98 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
81 | }, | 99 | }, |
82 | { "addhs", TILE_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1, | 100 | { "addhs", TILEPRO_OPC_ADDHS, 0x3, 3, TREG_ZERO, 1, |
83 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 101 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
84 | }, | 102 | }, |
85 | { "addhs.sn", TILE_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1, | 103 | { "addhs.sn", TILEPRO_OPC_ADDHS_SN, 0x3, 3, TREG_SN, 1, |
86 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 104 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
87 | }, | 105 | }, |
88 | { "addi", TILE_OPC_ADDI, 0xf, 3, TREG_ZERO, 1, | 106 | { "addi", TILEPRO_OPC_ADDI, 0xf, 3, TREG_ZERO, 1, |
89 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, | 107 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, |
90 | }, | 108 | }, |
91 | { "addi.sn", TILE_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1, | 109 | { "addi.sn", TILEPRO_OPC_ADDI_SN, 0x3, 3, TREG_SN, 1, |
92 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 110 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
93 | }, | 111 | }, |
94 | { "addib", TILE_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1, | 112 | { "addib", TILEPRO_OPC_ADDIB, 0x3, 3, TREG_ZERO, 1, |
95 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 113 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
96 | }, | 114 | }, |
97 | { "addib.sn", TILE_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1, | 115 | { "addib.sn", TILEPRO_OPC_ADDIB_SN, 0x3, 3, TREG_SN, 1, |
98 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 116 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
99 | }, | 117 | }, |
100 | { "addih", TILE_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1, | 118 | { "addih", TILEPRO_OPC_ADDIH, 0x3, 3, TREG_ZERO, 1, |
101 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 119 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
102 | }, | 120 | }, |
103 | { "addih.sn", TILE_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1, | 121 | { "addih.sn", TILEPRO_OPC_ADDIH_SN, 0x3, 3, TREG_SN, 1, |
104 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 122 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
105 | }, | 123 | }, |
106 | { "addli", TILE_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1, | 124 | { "addli", TILEPRO_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1, |
107 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, | 125 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, |
108 | }, | 126 | }, |
109 | { "addli.sn", TILE_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1, | 127 | { "addli.sn", TILEPRO_OPC_ADDLI_SN, 0x3, 3, TREG_SN, 1, |
110 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, | 128 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, |
111 | }, | 129 | }, |
112 | { "addlis", TILE_OPC_ADDLIS, 0x3, 3, TREG_SN, 1, | 130 | { "addlis", TILEPRO_OPC_ADDLIS, 0x3, 3, TREG_SN, 1, |
113 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, | 131 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, |
114 | }, | 132 | }, |
115 | { "adds", TILE_OPC_ADDS, 0x3, 3, TREG_ZERO, 1, | 133 | { "adds", TILEPRO_OPC_ADDS, 0x3, 3, TREG_ZERO, 1, |
116 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 134 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
117 | }, | 135 | }, |
118 | { "adds.sn", TILE_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1, | 136 | { "adds.sn", TILEPRO_OPC_ADDS_SN, 0x3, 3, TREG_SN, 1, |
119 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 137 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
120 | }, | 138 | }, |
121 | { "adiffb_u", TILE_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1, | 139 | { "adiffb_u", TILEPRO_OPC_ADIFFB_U, 0x1, 3, TREG_ZERO, 1, |
122 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 140 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
123 | }, | 141 | }, |
124 | { "adiffb_u.sn", TILE_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1, | 142 | { "adiffb_u.sn", TILEPRO_OPC_ADIFFB_U_SN, 0x1, 3, TREG_SN, 1, |
125 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 143 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
126 | }, | 144 | }, |
127 | { "adiffh", TILE_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1, | 145 | { "adiffh", TILEPRO_OPC_ADIFFH, 0x1, 3, TREG_ZERO, 1, |
128 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 146 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
129 | }, | 147 | }, |
130 | { "adiffh.sn", TILE_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1, | 148 | { "adiffh.sn", TILEPRO_OPC_ADIFFH_SN, 0x1, 3, TREG_SN, 1, |
131 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 149 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
132 | }, | 150 | }, |
133 | { "and", TILE_OPC_AND, 0xf, 3, TREG_ZERO, 1, | 151 | { "and", TILEPRO_OPC_AND, 0xf, 3, TREG_ZERO, 1, |
134 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 152 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
135 | }, | 153 | }, |
136 | { "and.sn", TILE_OPC_AND_SN, 0x3, 3, TREG_SN, 1, | 154 | { "and.sn", TILEPRO_OPC_AND_SN, 0x3, 3, TREG_SN, 1, |
137 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 155 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
138 | }, | 156 | }, |
139 | { "andi", TILE_OPC_ANDI, 0xf, 3, TREG_ZERO, 1, | 157 | { "andi", TILEPRO_OPC_ANDI, 0xf, 3, TREG_ZERO, 1, |
140 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, | 158 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, |
141 | }, | 159 | }, |
142 | { "andi.sn", TILE_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1, | 160 | { "andi.sn", TILEPRO_OPC_ANDI_SN, 0x3, 3, TREG_SN, 1, |
143 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 161 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
144 | }, | 162 | }, |
145 | { "auli", TILE_OPC_AULI, 0x3, 3, TREG_ZERO, 1, | 163 | { "auli", TILEPRO_OPC_AULI, 0x3, 3, TREG_ZERO, 1, |
146 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, | 164 | { { 7, 8, 4 }, { 9, 10, 5 }, { 0, }, { 0, }, { 0, } }, |
147 | }, | 165 | }, |
148 | { "avgb_u", TILE_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1, | 166 | { "avgb_u", TILEPRO_OPC_AVGB_U, 0x1, 3, TREG_ZERO, 1, |
149 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 167 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
150 | }, | 168 | }, |
151 | { "avgb_u.sn", TILE_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1, | 169 | { "avgb_u.sn", TILEPRO_OPC_AVGB_U_SN, 0x1, 3, TREG_SN, 1, |
152 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 170 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
153 | }, | 171 | }, |
154 | { "avgh", TILE_OPC_AVGH, 0x1, 3, TREG_ZERO, 1, | 172 | { "avgh", TILEPRO_OPC_AVGH, 0x1, 3, TREG_ZERO, 1, |
155 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 173 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
156 | }, | 174 | }, |
157 | { "avgh.sn", TILE_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1, | 175 | { "avgh.sn", TILEPRO_OPC_AVGH_SN, 0x1, 3, TREG_SN, 1, |
158 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 176 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
159 | }, | 177 | }, |
160 | { "bbns", TILE_OPC_BBNS, 0x2, 2, TREG_ZERO, 1, | 178 | { "bbns", TILEPRO_OPC_BBNS, 0x2, 2, TREG_ZERO, 1, |
161 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 179 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
162 | }, | 180 | }, |
163 | { "bbns.sn", TILE_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1, | 181 | { "bbns.sn", TILEPRO_OPC_BBNS_SN, 0x2, 2, TREG_SN, 1, |
164 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 182 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
165 | }, | 183 | }, |
166 | { "bbnst", TILE_OPC_BBNST, 0x2, 2, TREG_ZERO, 1, | 184 | { "bbnst", TILEPRO_OPC_BBNST, 0x2, 2, TREG_ZERO, 1, |
167 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 185 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
168 | }, | 186 | }, |
169 | { "bbnst.sn", TILE_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1, | 187 | { "bbnst.sn", TILEPRO_OPC_BBNST_SN, 0x2, 2, TREG_SN, 1, |
170 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 188 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
171 | }, | 189 | }, |
172 | { "bbs", TILE_OPC_BBS, 0x2, 2, TREG_ZERO, 1, | 190 | { "bbs", TILEPRO_OPC_BBS, 0x2, 2, TREG_ZERO, 1, |
173 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 191 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
174 | }, | 192 | }, |
175 | { "bbs.sn", TILE_OPC_BBS_SN, 0x2, 2, TREG_SN, 1, | 193 | { "bbs.sn", TILEPRO_OPC_BBS_SN, 0x2, 2, TREG_SN, 1, |
176 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 194 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
177 | }, | 195 | }, |
178 | { "bbst", TILE_OPC_BBST, 0x2, 2, TREG_ZERO, 1, | 196 | { "bbst", TILEPRO_OPC_BBST, 0x2, 2, TREG_ZERO, 1, |
179 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 197 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
180 | }, | 198 | }, |
181 | { "bbst.sn", TILE_OPC_BBST_SN, 0x2, 2, TREG_SN, 1, | 199 | { "bbst.sn", TILEPRO_OPC_BBST_SN, 0x2, 2, TREG_SN, 1, |
182 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 200 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
183 | }, | 201 | }, |
184 | { "bgez", TILE_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1, | 202 | { "bgez", TILEPRO_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1, |
185 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 203 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
186 | }, | 204 | }, |
187 | { "bgez.sn", TILE_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1, | 205 | { "bgez.sn", TILEPRO_OPC_BGEZ_SN, 0x2, 2, TREG_SN, 1, |
188 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 206 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
189 | }, | 207 | }, |
190 | { "bgezt", TILE_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1, | 208 | { "bgezt", TILEPRO_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1, |
191 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 209 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
192 | }, | 210 | }, |
193 | { "bgezt.sn", TILE_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1, | 211 | { "bgezt.sn", TILEPRO_OPC_BGEZT_SN, 0x2, 2, TREG_SN, 1, |
194 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 212 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
195 | }, | 213 | }, |
196 | { "bgz", TILE_OPC_BGZ, 0x2, 2, TREG_ZERO, 1, | 214 | { "bgz", TILEPRO_OPC_BGZ, 0x2, 2, TREG_ZERO, 1, |
197 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 215 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
198 | }, | 216 | }, |
199 | { "bgz.sn", TILE_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1, | 217 | { "bgz.sn", TILEPRO_OPC_BGZ_SN, 0x2, 2, TREG_SN, 1, |
200 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 218 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
201 | }, | 219 | }, |
202 | { "bgzt", TILE_OPC_BGZT, 0x2, 2, TREG_ZERO, 1, | 220 | { "bgzt", TILEPRO_OPC_BGZT, 0x2, 2, TREG_ZERO, 1, |
203 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 221 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
204 | }, | 222 | }, |
205 | { "bgzt.sn", TILE_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1, | 223 | { "bgzt.sn", TILEPRO_OPC_BGZT_SN, 0x2, 2, TREG_SN, 1, |
206 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 224 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
207 | }, | 225 | }, |
208 | { "bitx", TILE_OPC_BITX, 0x5, 2, TREG_ZERO, 1, | 226 | { "bitx", TILEPRO_OPC_BITX, 0x5, 2, TREG_ZERO, 1, |
209 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, | 227 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, |
210 | }, | 228 | }, |
211 | { "bitx.sn", TILE_OPC_BITX_SN, 0x1, 2, TREG_SN, 1, | 229 | { "bitx.sn", TILEPRO_OPC_BITX_SN, 0x1, 2, TREG_SN, 1, |
212 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 230 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
213 | }, | 231 | }, |
214 | { "blez", TILE_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1, | 232 | { "blez", TILEPRO_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1, |
215 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 233 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
216 | }, | 234 | }, |
217 | { "blez.sn", TILE_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1, | 235 | { "blez.sn", TILEPRO_OPC_BLEZ_SN, 0x2, 2, TREG_SN, 1, |
218 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 236 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
219 | }, | 237 | }, |
220 | { "blezt", TILE_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1, | 238 | { "blezt", TILEPRO_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1, |
221 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 239 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
222 | }, | 240 | }, |
223 | { "blezt.sn", TILE_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1, | 241 | { "blezt.sn", TILEPRO_OPC_BLEZT_SN, 0x2, 2, TREG_SN, 1, |
224 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 242 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
225 | }, | 243 | }, |
226 | { "blz", TILE_OPC_BLZ, 0x2, 2, TREG_ZERO, 1, | 244 | { "blz", TILEPRO_OPC_BLZ, 0x2, 2, TREG_ZERO, 1, |
227 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 245 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
228 | }, | 246 | }, |
229 | { "blz.sn", TILE_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1, | 247 | { "blz.sn", TILEPRO_OPC_BLZ_SN, 0x2, 2, TREG_SN, 1, |
230 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 248 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
231 | }, | 249 | }, |
232 | { "blzt", TILE_OPC_BLZT, 0x2, 2, TREG_ZERO, 1, | 250 | { "blzt", TILEPRO_OPC_BLZT, 0x2, 2, TREG_ZERO, 1, |
233 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 251 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
234 | }, | 252 | }, |
235 | { "blzt.sn", TILE_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1, | 253 | { "blzt.sn", TILEPRO_OPC_BLZT_SN, 0x2, 2, TREG_SN, 1, |
236 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 254 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
237 | }, | 255 | }, |
238 | { "bnz", TILE_OPC_BNZ, 0x2, 2, TREG_ZERO, 1, | 256 | { "bnz", TILEPRO_OPC_BNZ, 0x2, 2, TREG_ZERO, 1, |
239 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 257 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
240 | }, | 258 | }, |
241 | { "bnz.sn", TILE_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1, | 259 | { "bnz.sn", TILEPRO_OPC_BNZ_SN, 0x2, 2, TREG_SN, 1, |
242 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 260 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
243 | }, | 261 | }, |
244 | { "bnzt", TILE_OPC_BNZT, 0x2, 2, TREG_ZERO, 1, | 262 | { "bnzt", TILEPRO_OPC_BNZT, 0x2, 2, TREG_ZERO, 1, |
245 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 263 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
246 | }, | 264 | }, |
247 | { "bnzt.sn", TILE_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1, | 265 | { "bnzt.sn", TILEPRO_OPC_BNZT_SN, 0x2, 2, TREG_SN, 1, |
248 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 266 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
249 | }, | 267 | }, |
250 | { "bytex", TILE_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1, | 268 | { "bytex", TILEPRO_OPC_BYTEX, 0x5, 2, TREG_ZERO, 1, |
251 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, | 269 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, |
252 | }, | 270 | }, |
253 | { "bytex.sn", TILE_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1, | 271 | { "bytex.sn", TILEPRO_OPC_BYTEX_SN, 0x1, 2, TREG_SN, 1, |
254 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 272 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
255 | }, | 273 | }, |
256 | { "bz", TILE_OPC_BZ, 0x2, 2, TREG_ZERO, 1, | 274 | { "bz", TILEPRO_OPC_BZ, 0x2, 2, TREG_ZERO, 1, |
257 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 275 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
258 | }, | 276 | }, |
259 | { "bz.sn", TILE_OPC_BZ_SN, 0x2, 2, TREG_SN, 1, | 277 | { "bz.sn", TILEPRO_OPC_BZ_SN, 0x2, 2, TREG_SN, 1, |
260 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 278 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
261 | }, | 279 | }, |
262 | { "bzt", TILE_OPC_BZT, 0x2, 2, TREG_ZERO, 1, | 280 | { "bzt", TILEPRO_OPC_BZT, 0x2, 2, TREG_ZERO, 1, |
263 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 281 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
264 | }, | 282 | }, |
265 | { "bzt.sn", TILE_OPC_BZT_SN, 0x2, 2, TREG_SN, 1, | 283 | { "bzt.sn", TILEPRO_OPC_BZT_SN, 0x2, 2, TREG_SN, 1, |
266 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, | 284 | { { 0, }, { 10, 20 }, { 0, }, { 0, }, { 0, } }, |
267 | }, | 285 | }, |
268 | { "clz", TILE_OPC_CLZ, 0x5, 2, TREG_ZERO, 1, | 286 | { "clz", TILEPRO_OPC_CLZ, 0x5, 2, TREG_ZERO, 1, |
269 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, | 287 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, |
270 | }, | 288 | }, |
271 | { "clz.sn", TILE_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1, | 289 | { "clz.sn", TILEPRO_OPC_CLZ_SN, 0x1, 2, TREG_SN, 1, |
272 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 290 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
273 | }, | 291 | }, |
274 | { "crc32_32", TILE_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1, | 292 | { "crc32_32", TILEPRO_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1, |
275 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 293 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
276 | }, | 294 | }, |
277 | { "crc32_32.sn", TILE_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1, | 295 | { "crc32_32.sn", TILEPRO_OPC_CRC32_32_SN, 0x1, 3, TREG_SN, 1, |
278 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 296 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
279 | }, | 297 | }, |
280 | { "crc32_8", TILE_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1, | 298 | { "crc32_8", TILEPRO_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1, |
281 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 299 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
282 | }, | 300 | }, |
283 | { "crc32_8.sn", TILE_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1, | 301 | { "crc32_8.sn", TILEPRO_OPC_CRC32_8_SN, 0x1, 3, TREG_SN, 1, |
284 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 302 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
285 | }, | 303 | }, |
286 | { "ctz", TILE_OPC_CTZ, 0x5, 2, TREG_ZERO, 1, | 304 | { "ctz", TILEPRO_OPC_CTZ, 0x5, 2, TREG_ZERO, 1, |
287 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, | 305 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, |
288 | }, | 306 | }, |
289 | { "ctz.sn", TILE_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1, | 307 | { "ctz.sn", TILEPRO_OPC_CTZ_SN, 0x1, 2, TREG_SN, 1, |
290 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 308 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
291 | }, | 309 | }, |
292 | { "drain", TILE_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0, | 310 | { "drain", TILEPRO_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0, |
293 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 311 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
294 | }, | 312 | }, |
295 | { "dtlbpr", TILE_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1, | 313 | { "dtlbpr", TILEPRO_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1, |
296 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 314 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
297 | }, | 315 | }, |
298 | { "dword_align", TILE_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1, | 316 | { "dword_align", TILEPRO_OPC_DWORD_ALIGN, 0x1, 3, TREG_ZERO, 1, |
299 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 317 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
300 | }, | 318 | }, |
301 | { "dword_align.sn", TILE_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1, | 319 | { "dword_align.sn", TILEPRO_OPC_DWORD_ALIGN_SN, 0x1, 3, TREG_SN, 1, |
302 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 320 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
303 | }, | 321 | }, |
304 | { "finv", TILE_OPC_FINV, 0x2, 1, TREG_ZERO, 1, | 322 | { "finv", TILEPRO_OPC_FINV, 0x2, 1, TREG_ZERO, 1, |
305 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 323 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
306 | }, | 324 | }, |
307 | { "flush", TILE_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1, | 325 | { "flush", TILEPRO_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1, |
308 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 326 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
309 | }, | 327 | }, |
310 | { "fnop", TILE_OPC_FNOP, 0xf, 0, TREG_ZERO, 1, | 328 | { "fnop", TILEPRO_OPC_FNOP, 0xf, 0, TREG_ZERO, 1, |
311 | { { }, { }, { }, { }, { 0, } }, | 329 | { { }, { }, { }, { }, { 0, } }, |
312 | }, | 330 | }, |
313 | { "icoh", TILE_OPC_ICOH, 0x2, 1, TREG_ZERO, 1, | 331 | { "icoh", TILEPRO_OPC_ICOH, 0x2, 1, TREG_ZERO, 1, |
314 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 332 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
315 | }, | 333 | }, |
316 | { "ill", TILE_OPC_ILL, 0xa, 0, TREG_ZERO, 1, | 334 | { "ill", TILEPRO_OPC_ILL, 0xa, 0, TREG_ZERO, 1, |
317 | { { 0, }, { }, { 0, }, { }, { 0, } }, | 335 | { { 0, }, { }, { 0, }, { }, { 0, } }, |
318 | }, | 336 | }, |
319 | { "inthb", TILE_OPC_INTHB, 0x3, 3, TREG_ZERO, 1, | 337 | { "inthb", TILEPRO_OPC_INTHB, 0x3, 3, TREG_ZERO, 1, |
320 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 338 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
321 | }, | 339 | }, |
322 | { "inthb.sn", TILE_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1, | 340 | { "inthb.sn", TILEPRO_OPC_INTHB_SN, 0x3, 3, TREG_SN, 1, |
323 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 341 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
324 | }, | 342 | }, |
325 | { "inthh", TILE_OPC_INTHH, 0x3, 3, TREG_ZERO, 1, | 343 | { "inthh", TILEPRO_OPC_INTHH, 0x3, 3, TREG_ZERO, 1, |
326 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 344 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
327 | }, | 345 | }, |
328 | { "inthh.sn", TILE_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1, | 346 | { "inthh.sn", TILEPRO_OPC_INTHH_SN, 0x3, 3, TREG_SN, 1, |
329 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 347 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
330 | }, | 348 | }, |
331 | { "intlb", TILE_OPC_INTLB, 0x3, 3, TREG_ZERO, 1, | 349 | { "intlb", TILEPRO_OPC_INTLB, 0x3, 3, TREG_ZERO, 1, |
332 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 350 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
333 | }, | 351 | }, |
334 | { "intlb.sn", TILE_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1, | 352 | { "intlb.sn", TILEPRO_OPC_INTLB_SN, 0x3, 3, TREG_SN, 1, |
335 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 353 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
336 | }, | 354 | }, |
337 | { "intlh", TILE_OPC_INTLH, 0x3, 3, TREG_ZERO, 1, | 355 | { "intlh", TILEPRO_OPC_INTLH, 0x3, 3, TREG_ZERO, 1, |
338 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 356 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
339 | }, | 357 | }, |
340 | { "intlh.sn", TILE_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1, | 358 | { "intlh.sn", TILEPRO_OPC_INTLH_SN, 0x3, 3, TREG_SN, 1, |
341 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 359 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
342 | }, | 360 | }, |
343 | { "inv", TILE_OPC_INV, 0x2, 1, TREG_ZERO, 1, | 361 | { "inv", TILEPRO_OPC_INV, 0x2, 1, TREG_ZERO, 1, |
344 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 362 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
345 | }, | 363 | }, |
346 | { "iret", TILE_OPC_IRET, 0x2, 0, TREG_ZERO, 1, | 364 | { "iret", TILEPRO_OPC_IRET, 0x2, 0, TREG_ZERO, 1, |
347 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 365 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
348 | }, | 366 | }, |
349 | { "jalb", TILE_OPC_JALB, 0x2, 1, TREG_LR, 1, | 367 | { "jalb", TILEPRO_OPC_JALB, 0x2, 1, TREG_LR, 1, |
350 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, | 368 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, |
351 | }, | 369 | }, |
352 | { "jalf", TILE_OPC_JALF, 0x2, 1, TREG_LR, 1, | 370 | { "jalf", TILEPRO_OPC_JALF, 0x2, 1, TREG_LR, 1, |
353 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, | 371 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, |
354 | }, | 372 | }, |
355 | { "jalr", TILE_OPC_JALR, 0x2, 1, TREG_LR, 1, | 373 | { "jalr", TILEPRO_OPC_JALR, 0x2, 1, TREG_LR, 1, |
356 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 374 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
357 | }, | 375 | }, |
358 | { "jalrp", TILE_OPC_JALRP, 0x2, 1, TREG_LR, 1, | 376 | { "jalrp", TILEPRO_OPC_JALRP, 0x2, 1, TREG_LR, 1, |
359 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 377 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
360 | }, | 378 | }, |
361 | { "jb", TILE_OPC_JB, 0x2, 1, TREG_ZERO, 1, | 379 | { "jb", TILEPRO_OPC_JB, 0x2, 1, TREG_ZERO, 1, |
362 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, | 380 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, |
363 | }, | 381 | }, |
364 | { "jf", TILE_OPC_JF, 0x2, 1, TREG_ZERO, 1, | 382 | { "jf", TILEPRO_OPC_JF, 0x2, 1, TREG_ZERO, 1, |
365 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, | 383 | { { 0, }, { 22 }, { 0, }, { 0, }, { 0, } }, |
366 | }, | 384 | }, |
367 | { "jr", TILE_OPC_JR, 0x2, 1, TREG_ZERO, 1, | 385 | { "jr", TILEPRO_OPC_JR, 0x2, 1, TREG_ZERO, 1, |
368 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 386 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
369 | }, | 387 | }, |
370 | { "jrp", TILE_OPC_JRP, 0x2, 1, TREG_ZERO, 1, | 388 | { "jrp", TILEPRO_OPC_JRP, 0x2, 1, TREG_ZERO, 1, |
371 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 389 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
372 | }, | 390 | }, |
373 | { "lb", TILE_OPC_LB, 0x12, 2, TREG_ZERO, 1, | 391 | { "lb", TILEPRO_OPC_LB, 0x12, 2, TREG_ZERO, 1, |
374 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, | 392 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, |
375 | }, | 393 | }, |
376 | { "lb.sn", TILE_OPC_LB_SN, 0x2, 2, TREG_SN, 1, | 394 | { "lb.sn", TILEPRO_OPC_LB_SN, 0x2, 2, TREG_SN, 1, |
377 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 395 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
378 | }, | 396 | }, |
379 | { "lb_u", TILE_OPC_LB_U, 0x12, 2, TREG_ZERO, 1, | 397 | { "lb_u", TILEPRO_OPC_LB_U, 0x12, 2, TREG_ZERO, 1, |
380 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, | 398 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, |
381 | }, | 399 | }, |
382 | { "lb_u.sn", TILE_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1, | 400 | { "lb_u.sn", TILEPRO_OPC_LB_U_SN, 0x2, 2, TREG_SN, 1, |
383 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 401 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
384 | }, | 402 | }, |
385 | { "lbadd", TILE_OPC_LBADD, 0x2, 3, TREG_ZERO, 1, | 403 | { "lbadd", TILEPRO_OPC_LBADD, 0x2, 3, TREG_ZERO, 1, |
386 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 404 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
387 | }, | 405 | }, |
388 | { "lbadd.sn", TILE_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1, | 406 | { "lbadd.sn", TILEPRO_OPC_LBADD_SN, 0x2, 3, TREG_SN, 1, |
389 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 407 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
390 | }, | 408 | }, |
391 | { "lbadd_u", TILE_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1, | 409 | { "lbadd_u", TILEPRO_OPC_LBADD_U, 0x2, 3, TREG_ZERO, 1, |
392 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 410 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
393 | }, | 411 | }, |
394 | { "lbadd_u.sn", TILE_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1, | 412 | { "lbadd_u.sn", TILEPRO_OPC_LBADD_U_SN, 0x2, 3, TREG_SN, 1, |
395 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 413 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
396 | }, | 414 | }, |
397 | { "lh", TILE_OPC_LH, 0x12, 2, TREG_ZERO, 1, | 415 | { "lh", TILEPRO_OPC_LH, 0x12, 2, TREG_ZERO, 1, |
398 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, | 416 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, |
399 | }, | 417 | }, |
400 | { "lh.sn", TILE_OPC_LH_SN, 0x2, 2, TREG_SN, 1, | 418 | { "lh.sn", TILEPRO_OPC_LH_SN, 0x2, 2, TREG_SN, 1, |
401 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 419 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
402 | }, | 420 | }, |
403 | { "lh_u", TILE_OPC_LH_U, 0x12, 2, TREG_ZERO, 1, | 421 | { "lh_u", TILEPRO_OPC_LH_U, 0x12, 2, TREG_ZERO, 1, |
404 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, | 422 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, |
405 | }, | 423 | }, |
406 | { "lh_u.sn", TILE_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1, | 424 | { "lh_u.sn", TILEPRO_OPC_LH_U_SN, 0x2, 2, TREG_SN, 1, |
407 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 425 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
408 | }, | 426 | }, |
409 | { "lhadd", TILE_OPC_LHADD, 0x2, 3, TREG_ZERO, 1, | 427 | { "lhadd", TILEPRO_OPC_LHADD, 0x2, 3, TREG_ZERO, 1, |
410 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 428 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
411 | }, | 429 | }, |
412 | { "lhadd.sn", TILE_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1, | 430 | { "lhadd.sn", TILEPRO_OPC_LHADD_SN, 0x2, 3, TREG_SN, 1, |
413 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 431 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
414 | }, | 432 | }, |
415 | { "lhadd_u", TILE_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1, | 433 | { "lhadd_u", TILEPRO_OPC_LHADD_U, 0x2, 3, TREG_ZERO, 1, |
416 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 434 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
417 | }, | 435 | }, |
418 | { "lhadd_u.sn", TILE_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1, | 436 | { "lhadd_u.sn", TILEPRO_OPC_LHADD_U_SN, 0x2, 3, TREG_SN, 1, |
419 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 437 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
420 | }, | 438 | }, |
421 | { "lnk", TILE_OPC_LNK, 0x2, 1, TREG_ZERO, 1, | 439 | { "lnk", TILEPRO_OPC_LNK, 0x2, 1, TREG_ZERO, 1, |
422 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | 440 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, |
423 | }, | 441 | }, |
424 | { "lnk.sn", TILE_OPC_LNK_SN, 0x2, 1, TREG_SN, 1, | 442 | { "lnk.sn", TILEPRO_OPC_LNK_SN, 0x2, 1, TREG_SN, 1, |
425 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, | 443 | { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } }, |
426 | }, | 444 | }, |
427 | { "lw", TILE_OPC_LW, 0x12, 2, TREG_ZERO, 1, | 445 | { "lw", TILEPRO_OPC_LW, 0x12, 2, TREG_ZERO, 1, |
428 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, | 446 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 23, 15 } }, |
429 | }, | 447 | }, |
430 | { "lw.sn", TILE_OPC_LW_SN, 0x2, 2, TREG_SN, 1, | 448 | { "lw.sn", TILEPRO_OPC_LW_SN, 0x2, 2, TREG_SN, 1, |
431 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 449 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
432 | }, | 450 | }, |
433 | { "lw_na", TILE_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1, | 451 | { "lw_na", TILEPRO_OPC_LW_NA, 0x2, 2, TREG_ZERO, 1, |
434 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 452 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
435 | }, | 453 | }, |
436 | { "lw_na.sn", TILE_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1, | 454 | { "lw_na.sn", TILEPRO_OPC_LW_NA_SN, 0x2, 2, TREG_SN, 1, |
437 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 455 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
438 | }, | 456 | }, |
439 | { "lwadd", TILE_OPC_LWADD, 0x2, 3, TREG_ZERO, 1, | 457 | { "lwadd", TILEPRO_OPC_LWADD, 0x2, 3, TREG_ZERO, 1, |
440 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 458 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
441 | }, | 459 | }, |
442 | { "lwadd.sn", TILE_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1, | 460 | { "lwadd.sn", TILEPRO_OPC_LWADD_SN, 0x2, 3, TREG_SN, 1, |
443 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 461 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
444 | }, | 462 | }, |
445 | { "lwadd_na", TILE_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1, | 463 | { "lwadd_na", TILEPRO_OPC_LWADD_NA, 0x2, 3, TREG_ZERO, 1, |
446 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 464 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
447 | }, | 465 | }, |
448 | { "lwadd_na.sn", TILE_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1, | 466 | { "lwadd_na.sn", TILEPRO_OPC_LWADD_NA_SN, 0x2, 3, TREG_SN, 1, |
449 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, | 467 | { { 0, }, { 9, 24, 1 }, { 0, }, { 0, }, { 0, } }, |
450 | }, | 468 | }, |
451 | { "maxb_u", TILE_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1, | 469 | { "maxb_u", TILEPRO_OPC_MAXB_U, 0x3, 3, TREG_ZERO, 1, |
452 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 470 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
453 | }, | 471 | }, |
454 | { "maxb_u.sn", TILE_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1, | 472 | { "maxb_u.sn", TILEPRO_OPC_MAXB_U_SN, 0x3, 3, TREG_SN, 1, |
455 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 473 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
456 | }, | 474 | }, |
457 | { "maxh", TILE_OPC_MAXH, 0x3, 3, TREG_ZERO, 1, | 475 | { "maxh", TILEPRO_OPC_MAXH, 0x3, 3, TREG_ZERO, 1, |
458 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 476 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
459 | }, | 477 | }, |
460 | { "maxh.sn", TILE_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1, | 478 | { "maxh.sn", TILEPRO_OPC_MAXH_SN, 0x3, 3, TREG_SN, 1, |
461 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 479 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
462 | }, | 480 | }, |
463 | { "maxib_u", TILE_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1, | 481 | { "maxib_u", TILEPRO_OPC_MAXIB_U, 0x3, 3, TREG_ZERO, 1, |
464 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 482 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
465 | }, | 483 | }, |
466 | { "maxib_u.sn", TILE_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1, | 484 | { "maxib_u.sn", TILEPRO_OPC_MAXIB_U_SN, 0x3, 3, TREG_SN, 1, |
467 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 485 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
468 | }, | 486 | }, |
469 | { "maxih", TILE_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1, | 487 | { "maxih", TILEPRO_OPC_MAXIH, 0x3, 3, TREG_ZERO, 1, |
470 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 488 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
471 | }, | 489 | }, |
472 | { "maxih.sn", TILE_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1, | 490 | { "maxih.sn", TILEPRO_OPC_MAXIH_SN, 0x3, 3, TREG_SN, 1, |
473 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 491 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
474 | }, | 492 | }, |
475 | { "mf", TILE_OPC_MF, 0x2, 0, TREG_ZERO, 1, | 493 | { "mf", TILEPRO_OPC_MF, 0x2, 0, TREG_ZERO, 1, |
476 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 494 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
477 | }, | 495 | }, |
478 | { "mfspr", TILE_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1, | 496 | { "mfspr", TILEPRO_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1, |
479 | { { 0, }, { 9, 25 }, { 0, }, { 0, }, { 0, } }, | 497 | { { 0, }, { 9, 25 }, { 0, }, { 0, }, { 0, } }, |
480 | }, | 498 | }, |
481 | { "minb_u", TILE_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1, | 499 | { "minb_u", TILEPRO_OPC_MINB_U, 0x3, 3, TREG_ZERO, 1, |
482 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 500 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
483 | }, | 501 | }, |
484 | { "minb_u.sn", TILE_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1, | 502 | { "minb_u.sn", TILEPRO_OPC_MINB_U_SN, 0x3, 3, TREG_SN, 1, |
485 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 503 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
486 | }, | 504 | }, |
487 | { "minh", TILE_OPC_MINH, 0x3, 3, TREG_ZERO, 1, | 505 | { "minh", TILEPRO_OPC_MINH, 0x3, 3, TREG_ZERO, 1, |
488 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 506 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
489 | }, | 507 | }, |
490 | { "minh.sn", TILE_OPC_MINH_SN, 0x3, 3, TREG_SN, 1, | 508 | { "minh.sn", TILEPRO_OPC_MINH_SN, 0x3, 3, TREG_SN, 1, |
491 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 509 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
492 | }, | 510 | }, |
493 | { "minib_u", TILE_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1, | 511 | { "minib_u", TILEPRO_OPC_MINIB_U, 0x3, 3, TREG_ZERO, 1, |
494 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 512 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
495 | }, | 513 | }, |
496 | { "minib_u.sn", TILE_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1, | 514 | { "minib_u.sn", TILEPRO_OPC_MINIB_U_SN, 0x3, 3, TREG_SN, 1, |
497 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 515 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
498 | }, | 516 | }, |
499 | { "minih", TILE_OPC_MINIH, 0x3, 3, TREG_ZERO, 1, | 517 | { "minih", TILEPRO_OPC_MINIH, 0x3, 3, TREG_ZERO, 1, |
500 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 518 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
501 | }, | 519 | }, |
502 | { "minih.sn", TILE_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1, | 520 | { "minih.sn", TILEPRO_OPC_MINIH_SN, 0x3, 3, TREG_SN, 1, |
503 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 521 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
504 | }, | 522 | }, |
505 | { "mm", TILE_OPC_MM, 0x3, 5, TREG_ZERO, 1, | 523 | { "mm", TILEPRO_OPC_MM, 0x3, 5, TREG_ZERO, 1, |
506 | { { 7, 8, 16, 26, 27 }, { 9, 10, 17, 28, 29 }, { 0, }, { 0, }, { 0, } }, | 524 | { { 7, 8, 16, 26, 27 }, { 9, 10, 17, 28, 29 }, { 0, }, { 0, }, { 0, } }, |
507 | }, | 525 | }, |
508 | { "mnz", TILE_OPC_MNZ, 0xf, 3, TREG_ZERO, 1, | 526 | { "mnz", TILEPRO_OPC_MNZ, 0xf, 3, TREG_ZERO, 1, |
509 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 527 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
510 | }, | 528 | }, |
511 | { "mnz.sn", TILE_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1, | 529 | { "mnz.sn", TILEPRO_OPC_MNZ_SN, 0x3, 3, TREG_SN, 1, |
512 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 530 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
513 | }, | 531 | }, |
514 | { "mnzb", TILE_OPC_MNZB, 0x3, 3, TREG_ZERO, 1, | 532 | { "mnzb", TILEPRO_OPC_MNZB, 0x3, 3, TREG_ZERO, 1, |
515 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 533 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
516 | }, | 534 | }, |
517 | { "mnzb.sn", TILE_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1, | 535 | { "mnzb.sn", TILEPRO_OPC_MNZB_SN, 0x3, 3, TREG_SN, 1, |
518 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 536 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
519 | }, | 537 | }, |
520 | { "mnzh", TILE_OPC_MNZH, 0x3, 3, TREG_ZERO, 1, | 538 | { "mnzh", TILEPRO_OPC_MNZH, 0x3, 3, TREG_ZERO, 1, |
521 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 539 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
522 | }, | 540 | }, |
523 | { "mnzh.sn", TILE_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1, | 541 | { "mnzh.sn", TILEPRO_OPC_MNZH_SN, 0x3, 3, TREG_SN, 1, |
524 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 542 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
525 | }, | 543 | }, |
526 | { "mtspr", TILE_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1, | 544 | { "mtspr", TILEPRO_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1, |
527 | { { 0, }, { 30, 10 }, { 0, }, { 0, }, { 0, } }, | 545 | { { 0, }, { 30, 10 }, { 0, }, { 0, }, { 0, } }, |
528 | }, | 546 | }, |
529 | { "mulhh_ss", TILE_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1, | 547 | { "mulhh_ss", TILEPRO_OPC_MULHH_SS, 0x5, 3, TREG_ZERO, 1, |
530 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, | 548 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, |
531 | }, | 549 | }, |
532 | { "mulhh_ss.sn", TILE_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1, | 550 | { "mulhh_ss.sn", TILEPRO_OPC_MULHH_SS_SN, 0x1, 3, TREG_SN, 1, |
533 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 551 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
534 | }, | 552 | }, |
535 | { "mulhh_su", TILE_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1, | 553 | { "mulhh_su", TILEPRO_OPC_MULHH_SU, 0x1, 3, TREG_ZERO, 1, |
536 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 554 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
537 | }, | 555 | }, |
538 | { "mulhh_su.sn", TILE_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1, | 556 | { "mulhh_su.sn", TILEPRO_OPC_MULHH_SU_SN, 0x1, 3, TREG_SN, 1, |
539 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 557 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
540 | }, | 558 | }, |
541 | { "mulhh_uu", TILE_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1, | 559 | { "mulhh_uu", TILEPRO_OPC_MULHH_UU, 0x5, 3, TREG_ZERO, 1, |
542 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, | 560 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, |
543 | }, | 561 | }, |
544 | { "mulhh_uu.sn", TILE_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1, | 562 | { "mulhh_uu.sn", TILEPRO_OPC_MULHH_UU_SN, 0x1, 3, TREG_SN, 1, |
545 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 563 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
546 | }, | 564 | }, |
547 | { "mulhha_ss", TILE_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1, | 565 | { "mulhha_ss", TILEPRO_OPC_MULHHA_SS, 0x5, 3, TREG_ZERO, 1, |
548 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, | 566 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, |
549 | }, | 567 | }, |
550 | { "mulhha_ss.sn", TILE_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1, | 568 | { "mulhha_ss.sn", TILEPRO_OPC_MULHHA_SS_SN, 0x1, 3, TREG_SN, 1, |
551 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 569 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
552 | }, | 570 | }, |
553 | { "mulhha_su", TILE_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1, | 571 | { "mulhha_su", TILEPRO_OPC_MULHHA_SU, 0x1, 3, TREG_ZERO, 1, |
554 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 572 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
555 | }, | 573 | }, |
556 | { "mulhha_su.sn", TILE_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1, | 574 | { "mulhha_su.sn", TILEPRO_OPC_MULHHA_SU_SN, 0x1, 3, TREG_SN, 1, |
557 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 575 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
558 | }, | 576 | }, |
559 | { "mulhha_uu", TILE_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1, | 577 | { "mulhha_uu", TILEPRO_OPC_MULHHA_UU, 0x5, 3, TREG_ZERO, 1, |
560 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, | 578 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, |
561 | }, | 579 | }, |
562 | { "mulhha_uu.sn", TILE_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1, | 580 | { "mulhha_uu.sn", TILEPRO_OPC_MULHHA_UU_SN, 0x1, 3, TREG_SN, 1, |
563 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 581 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
564 | }, | 582 | }, |
565 | { "mulhhsa_uu", TILE_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1, | 583 | { "mulhhsa_uu", TILEPRO_OPC_MULHHSA_UU, 0x1, 3, TREG_ZERO, 1, |
566 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 584 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
567 | }, | 585 | }, |
568 | { "mulhhsa_uu.sn", TILE_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1, | 586 | { "mulhhsa_uu.sn", TILEPRO_OPC_MULHHSA_UU_SN, 0x1, 3, TREG_SN, 1, |
569 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 587 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
570 | }, | 588 | }, |
571 | { "mulhl_ss", TILE_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1, | 589 | { "mulhl_ss", TILEPRO_OPC_MULHL_SS, 0x1, 3, TREG_ZERO, 1, |
572 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 590 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
573 | }, | 591 | }, |
574 | { "mulhl_ss.sn", TILE_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1, | 592 | { "mulhl_ss.sn", TILEPRO_OPC_MULHL_SS_SN, 0x1, 3, TREG_SN, 1, |
575 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 593 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
576 | }, | 594 | }, |
577 | { "mulhl_su", TILE_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1, | 595 | { "mulhl_su", TILEPRO_OPC_MULHL_SU, 0x1, 3, TREG_ZERO, 1, |
578 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 596 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
579 | }, | 597 | }, |
580 | { "mulhl_su.sn", TILE_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1, | 598 | { "mulhl_su.sn", TILEPRO_OPC_MULHL_SU_SN, 0x1, 3, TREG_SN, 1, |
581 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 599 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
582 | }, | 600 | }, |
583 | { "mulhl_us", TILE_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1, | 601 | { "mulhl_us", TILEPRO_OPC_MULHL_US, 0x1, 3, TREG_ZERO, 1, |
584 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 602 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
585 | }, | 603 | }, |
586 | { "mulhl_us.sn", TILE_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1, | 604 | { "mulhl_us.sn", TILEPRO_OPC_MULHL_US_SN, 0x1, 3, TREG_SN, 1, |
587 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 605 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
588 | }, | 606 | }, |
589 | { "mulhl_uu", TILE_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1, | 607 | { "mulhl_uu", TILEPRO_OPC_MULHL_UU, 0x1, 3, TREG_ZERO, 1, |
590 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 608 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
591 | }, | 609 | }, |
592 | { "mulhl_uu.sn", TILE_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1, | 610 | { "mulhl_uu.sn", TILEPRO_OPC_MULHL_UU_SN, 0x1, 3, TREG_SN, 1, |
593 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 611 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
594 | }, | 612 | }, |
595 | { "mulhla_ss", TILE_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1, | 613 | { "mulhla_ss", TILEPRO_OPC_MULHLA_SS, 0x1, 3, TREG_ZERO, 1, |
596 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 614 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
597 | }, | 615 | }, |
598 | { "mulhla_ss.sn", TILE_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1, | 616 | { "mulhla_ss.sn", TILEPRO_OPC_MULHLA_SS_SN, 0x1, 3, TREG_SN, 1, |
599 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 617 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
600 | }, | 618 | }, |
601 | { "mulhla_su", TILE_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1, | 619 | { "mulhla_su", TILEPRO_OPC_MULHLA_SU, 0x1, 3, TREG_ZERO, 1, |
602 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 620 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
603 | }, | 621 | }, |
604 | { "mulhla_su.sn", TILE_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1, | 622 | { "mulhla_su.sn", TILEPRO_OPC_MULHLA_SU_SN, 0x1, 3, TREG_SN, 1, |
605 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 623 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
606 | }, | 624 | }, |
607 | { "mulhla_us", TILE_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1, | 625 | { "mulhla_us", TILEPRO_OPC_MULHLA_US, 0x1, 3, TREG_ZERO, 1, |
608 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 626 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
609 | }, | 627 | }, |
610 | { "mulhla_us.sn", TILE_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1, | 628 | { "mulhla_us.sn", TILEPRO_OPC_MULHLA_US_SN, 0x1, 3, TREG_SN, 1, |
611 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 629 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
612 | }, | 630 | }, |
613 | { "mulhla_uu", TILE_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1, | 631 | { "mulhla_uu", TILEPRO_OPC_MULHLA_UU, 0x1, 3, TREG_ZERO, 1, |
614 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 632 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
615 | }, | 633 | }, |
616 | { "mulhla_uu.sn", TILE_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1, | 634 | { "mulhla_uu.sn", TILEPRO_OPC_MULHLA_UU_SN, 0x1, 3, TREG_SN, 1, |
617 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 635 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
618 | }, | 636 | }, |
619 | { "mulhlsa_uu", TILE_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1, | 637 | { "mulhlsa_uu", TILEPRO_OPC_MULHLSA_UU, 0x5, 3, TREG_ZERO, 1, |
620 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, | 638 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, |
621 | }, | 639 | }, |
622 | { "mulhlsa_uu.sn", TILE_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1, | 640 | { "mulhlsa_uu.sn", TILEPRO_OPC_MULHLSA_UU_SN, 0x1, 3, TREG_SN, 1, |
623 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 641 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
624 | }, | 642 | }, |
625 | { "mulll_ss", TILE_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1, | 643 | { "mulll_ss", TILEPRO_OPC_MULLL_SS, 0x5, 3, TREG_ZERO, 1, |
626 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, | 644 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, |
627 | }, | 645 | }, |
628 | { "mulll_ss.sn", TILE_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1, | 646 | { "mulll_ss.sn", TILEPRO_OPC_MULLL_SS_SN, 0x1, 3, TREG_SN, 1, |
629 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 647 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
630 | }, | 648 | }, |
631 | { "mulll_su", TILE_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1, | 649 | { "mulll_su", TILEPRO_OPC_MULLL_SU, 0x1, 3, TREG_ZERO, 1, |
632 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 650 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
633 | }, | 651 | }, |
634 | { "mulll_su.sn", TILE_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1, | 652 | { "mulll_su.sn", TILEPRO_OPC_MULLL_SU_SN, 0x1, 3, TREG_SN, 1, |
635 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 653 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
636 | }, | 654 | }, |
637 | { "mulll_uu", TILE_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1, | 655 | { "mulll_uu", TILEPRO_OPC_MULLL_UU, 0x5, 3, TREG_ZERO, 1, |
638 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, | 656 | { { 7, 8, 16 }, { 0, }, { 11, 12, 18 }, { 0, }, { 0, } }, |
639 | }, | 657 | }, |
640 | { "mulll_uu.sn", TILE_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1, | 658 | { "mulll_uu.sn", TILEPRO_OPC_MULLL_UU_SN, 0x1, 3, TREG_SN, 1, |
641 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 659 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
642 | }, | 660 | }, |
643 | { "mullla_ss", TILE_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1, | 661 | { "mullla_ss", TILEPRO_OPC_MULLLA_SS, 0x5, 3, TREG_ZERO, 1, |
644 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, | 662 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, |
645 | }, | 663 | }, |
646 | { "mullla_ss.sn", TILE_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1, | 664 | { "mullla_ss.sn", TILEPRO_OPC_MULLLA_SS_SN, 0x1, 3, TREG_SN, 1, |
647 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 665 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
648 | }, | 666 | }, |
649 | { "mullla_su", TILE_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1, | 667 | { "mullla_su", TILEPRO_OPC_MULLLA_SU, 0x1, 3, TREG_ZERO, 1, |
650 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 668 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
651 | }, | 669 | }, |
652 | { "mullla_su.sn", TILE_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1, | 670 | { "mullla_su.sn", TILEPRO_OPC_MULLLA_SU_SN, 0x1, 3, TREG_SN, 1, |
653 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 671 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
654 | }, | 672 | }, |
655 | { "mullla_uu", TILE_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1, | 673 | { "mullla_uu", TILEPRO_OPC_MULLLA_UU, 0x5, 3, TREG_ZERO, 1, |
656 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, | 674 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, |
657 | }, | 675 | }, |
658 | { "mullla_uu.sn", TILE_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1, | 676 | { "mullla_uu.sn", TILEPRO_OPC_MULLLA_UU_SN, 0x1, 3, TREG_SN, 1, |
659 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 677 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
660 | }, | 678 | }, |
661 | { "mulllsa_uu", TILE_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1, | 679 | { "mulllsa_uu", TILEPRO_OPC_MULLLSA_UU, 0x1, 3, TREG_ZERO, 1, |
662 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 680 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
663 | }, | 681 | }, |
664 | { "mulllsa_uu.sn", TILE_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1, | 682 | { "mulllsa_uu.sn", TILEPRO_OPC_MULLLSA_UU_SN, 0x1, 3, TREG_SN, 1, |
665 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 683 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
666 | }, | 684 | }, |
667 | { "mvnz", TILE_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1, | 685 | { "mvnz", TILEPRO_OPC_MVNZ, 0x5, 3, TREG_ZERO, 1, |
668 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, | 686 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, |
669 | }, | 687 | }, |
670 | { "mvnz.sn", TILE_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1, | 688 | { "mvnz.sn", TILEPRO_OPC_MVNZ_SN, 0x1, 3, TREG_SN, 1, |
671 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 689 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
672 | }, | 690 | }, |
673 | { "mvz", TILE_OPC_MVZ, 0x5, 3, TREG_ZERO, 1, | 691 | { "mvz", TILEPRO_OPC_MVZ, 0x5, 3, TREG_ZERO, 1, |
674 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, | 692 | { { 21, 8, 16 }, { 0, }, { 31, 12, 18 }, { 0, }, { 0, } }, |
675 | }, | 693 | }, |
676 | { "mvz.sn", TILE_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1, | 694 | { "mvz.sn", TILEPRO_OPC_MVZ_SN, 0x1, 3, TREG_SN, 1, |
677 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 695 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
678 | }, | 696 | }, |
679 | { "mz", TILE_OPC_MZ, 0xf, 3, TREG_ZERO, 1, | 697 | { "mz", TILEPRO_OPC_MZ, 0xf, 3, TREG_ZERO, 1, |
680 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 698 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
681 | }, | 699 | }, |
682 | { "mz.sn", TILE_OPC_MZ_SN, 0x3, 3, TREG_SN, 1, | 700 | { "mz.sn", TILEPRO_OPC_MZ_SN, 0x3, 3, TREG_SN, 1, |
683 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 701 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
684 | }, | 702 | }, |
685 | { "mzb", TILE_OPC_MZB, 0x3, 3, TREG_ZERO, 1, | 703 | { "mzb", TILEPRO_OPC_MZB, 0x3, 3, TREG_ZERO, 1, |
686 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 704 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
687 | }, | 705 | }, |
688 | { "mzb.sn", TILE_OPC_MZB_SN, 0x3, 3, TREG_SN, 1, | 706 | { "mzb.sn", TILEPRO_OPC_MZB_SN, 0x3, 3, TREG_SN, 1, |
689 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 707 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
690 | }, | 708 | }, |
691 | { "mzh", TILE_OPC_MZH, 0x3, 3, TREG_ZERO, 1, | 709 | { "mzh", TILEPRO_OPC_MZH, 0x3, 3, TREG_ZERO, 1, |
692 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 710 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
693 | }, | 711 | }, |
694 | { "mzh.sn", TILE_OPC_MZH_SN, 0x3, 3, TREG_SN, 1, | 712 | { "mzh.sn", TILEPRO_OPC_MZH_SN, 0x3, 3, TREG_SN, 1, |
695 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 713 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
696 | }, | 714 | }, |
697 | { "nap", TILE_OPC_NAP, 0x2, 0, TREG_ZERO, 0, | 715 | { "nap", TILEPRO_OPC_NAP, 0x2, 0, TREG_ZERO, 0, |
698 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 716 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
699 | }, | 717 | }, |
700 | { "nop", TILE_OPC_NOP, 0xf, 0, TREG_ZERO, 1, | 718 | { "nop", TILEPRO_OPC_NOP, 0xf, 0, TREG_ZERO, 1, |
701 | { { }, { }, { }, { }, { 0, } }, | 719 | { { }, { }, { }, { }, { 0, } }, |
702 | }, | 720 | }, |
703 | { "nor", TILE_OPC_NOR, 0xf, 3, TREG_ZERO, 1, | 721 | { "nor", TILEPRO_OPC_NOR, 0xf, 3, TREG_ZERO, 1, |
704 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 722 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
705 | }, | 723 | }, |
706 | { "nor.sn", TILE_OPC_NOR_SN, 0x3, 3, TREG_SN, 1, | 724 | { "nor.sn", TILEPRO_OPC_NOR_SN, 0x3, 3, TREG_SN, 1, |
707 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 725 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
708 | }, | 726 | }, |
709 | { "or", TILE_OPC_OR, 0xf, 3, TREG_ZERO, 1, | 727 | { "or", TILEPRO_OPC_OR, 0xf, 3, TREG_ZERO, 1, |
710 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 728 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
711 | }, | 729 | }, |
712 | { "or.sn", TILE_OPC_OR_SN, 0x3, 3, TREG_SN, 1, | 730 | { "or.sn", TILEPRO_OPC_OR_SN, 0x3, 3, TREG_SN, 1, |
713 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 731 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
714 | }, | 732 | }, |
715 | { "ori", TILE_OPC_ORI, 0xf, 3, TREG_ZERO, 1, | 733 | { "ori", TILEPRO_OPC_ORI, 0xf, 3, TREG_ZERO, 1, |
716 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, | 734 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, |
717 | }, | 735 | }, |
718 | { "ori.sn", TILE_OPC_ORI_SN, 0x3, 3, TREG_SN, 1, | 736 | { "ori.sn", TILEPRO_OPC_ORI_SN, 0x3, 3, TREG_SN, 1, |
719 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 737 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
720 | }, | 738 | }, |
721 | { "packbs_u", TILE_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1, | 739 | { "packbs_u", TILEPRO_OPC_PACKBS_U, 0x3, 3, TREG_ZERO, 1, |
722 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 740 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
723 | }, | 741 | }, |
724 | { "packbs_u.sn", TILE_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1, | 742 | { "packbs_u.sn", TILEPRO_OPC_PACKBS_U_SN, 0x3, 3, TREG_SN, 1, |
725 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 743 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
726 | }, | 744 | }, |
727 | { "packhb", TILE_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1, | 745 | { "packhb", TILEPRO_OPC_PACKHB, 0x3, 3, TREG_ZERO, 1, |
728 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 746 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
729 | }, | 747 | }, |
730 | { "packhb.sn", TILE_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1, | 748 | { "packhb.sn", TILEPRO_OPC_PACKHB_SN, 0x3, 3, TREG_SN, 1, |
731 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 749 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
732 | }, | 750 | }, |
733 | { "packhs", TILE_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1, | 751 | { "packhs", TILEPRO_OPC_PACKHS, 0x3, 3, TREG_ZERO, 1, |
734 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 752 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
735 | }, | 753 | }, |
736 | { "packhs.sn", TILE_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1, | 754 | { "packhs.sn", TILEPRO_OPC_PACKHS_SN, 0x3, 3, TREG_SN, 1, |
737 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 755 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
738 | }, | 756 | }, |
739 | { "packlb", TILE_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1, | 757 | { "packlb", TILEPRO_OPC_PACKLB, 0x3, 3, TREG_ZERO, 1, |
740 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 758 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
741 | }, | 759 | }, |
742 | { "packlb.sn", TILE_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1, | 760 | { "packlb.sn", TILEPRO_OPC_PACKLB_SN, 0x3, 3, TREG_SN, 1, |
743 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 761 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
744 | }, | 762 | }, |
745 | { "pcnt", TILE_OPC_PCNT, 0x5, 2, TREG_ZERO, 1, | 763 | { "pcnt", TILEPRO_OPC_PCNT, 0x5, 2, TREG_ZERO, 1, |
746 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, | 764 | { { 7, 8 }, { 0, }, { 11, 12 }, { 0, }, { 0, } }, |
747 | }, | 765 | }, |
748 | { "pcnt.sn", TILE_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1, | 766 | { "pcnt.sn", TILEPRO_OPC_PCNT_SN, 0x1, 2, TREG_SN, 1, |
749 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 767 | { { 7, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
750 | }, | 768 | }, |
751 | { "rl", TILE_OPC_RL, 0xf, 3, TREG_ZERO, 1, | 769 | { "rl", TILEPRO_OPC_RL, 0xf, 3, TREG_ZERO, 1, |
752 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 770 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
753 | }, | 771 | }, |
754 | { "rl.sn", TILE_OPC_RL_SN, 0x3, 3, TREG_SN, 1, | 772 | { "rl.sn", TILEPRO_OPC_RL_SN, 0x3, 3, TREG_SN, 1, |
755 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 773 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
756 | }, | 774 | }, |
757 | { "rli", TILE_OPC_RLI, 0xf, 3, TREG_ZERO, 1, | 775 | { "rli", TILEPRO_OPC_RLI, 0xf, 3, TREG_ZERO, 1, |
758 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, | 776 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, |
759 | }, | 777 | }, |
760 | { "rli.sn", TILE_OPC_RLI_SN, 0x3, 3, TREG_SN, 1, | 778 | { "rli.sn", TILEPRO_OPC_RLI_SN, 0x3, 3, TREG_SN, 1, |
761 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 779 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
762 | }, | 780 | }, |
763 | { "s1a", TILE_OPC_S1A, 0xf, 3, TREG_ZERO, 1, | 781 | { "s1a", TILEPRO_OPC_S1A, 0xf, 3, TREG_ZERO, 1, |
764 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 782 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
765 | }, | 783 | }, |
766 | { "s1a.sn", TILE_OPC_S1A_SN, 0x3, 3, TREG_SN, 1, | 784 | { "s1a.sn", TILEPRO_OPC_S1A_SN, 0x3, 3, TREG_SN, 1, |
767 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 785 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
768 | }, | 786 | }, |
769 | { "s2a", TILE_OPC_S2A, 0xf, 3, TREG_ZERO, 1, | 787 | { "s2a", TILEPRO_OPC_S2A, 0xf, 3, TREG_ZERO, 1, |
770 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 788 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
771 | }, | 789 | }, |
772 | { "s2a.sn", TILE_OPC_S2A_SN, 0x3, 3, TREG_SN, 1, | 790 | { "s2a.sn", TILEPRO_OPC_S2A_SN, 0x3, 3, TREG_SN, 1, |
773 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 791 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
774 | }, | 792 | }, |
775 | { "s3a", TILE_OPC_S3A, 0xf, 3, TREG_ZERO, 1, | 793 | { "s3a", TILEPRO_OPC_S3A, 0xf, 3, TREG_ZERO, 1, |
776 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 794 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
777 | }, | 795 | }, |
778 | { "s3a.sn", TILE_OPC_S3A_SN, 0x3, 3, TREG_SN, 1, | 796 | { "s3a.sn", TILEPRO_OPC_S3A_SN, 0x3, 3, TREG_SN, 1, |
779 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 797 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
780 | }, | 798 | }, |
781 | { "sadab_u", TILE_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1, | 799 | { "sadab_u", TILEPRO_OPC_SADAB_U, 0x1, 3, TREG_ZERO, 1, |
782 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 800 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
783 | }, | 801 | }, |
784 | { "sadab_u.sn", TILE_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1, | 802 | { "sadab_u.sn", TILEPRO_OPC_SADAB_U_SN, 0x1, 3, TREG_SN, 1, |
785 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 803 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
786 | }, | 804 | }, |
787 | { "sadah", TILE_OPC_SADAH, 0x1, 3, TREG_ZERO, 1, | 805 | { "sadah", TILEPRO_OPC_SADAH, 0x1, 3, TREG_ZERO, 1, |
788 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 806 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
789 | }, | 807 | }, |
790 | { "sadah.sn", TILE_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1, | 808 | { "sadah.sn", TILEPRO_OPC_SADAH_SN, 0x1, 3, TREG_SN, 1, |
791 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 809 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
792 | }, | 810 | }, |
793 | { "sadah_u", TILE_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1, | 811 | { "sadah_u", TILEPRO_OPC_SADAH_U, 0x1, 3, TREG_ZERO, 1, |
794 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 812 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
795 | }, | 813 | }, |
796 | { "sadah_u.sn", TILE_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1, | 814 | { "sadah_u.sn", TILEPRO_OPC_SADAH_U_SN, 0x1, 3, TREG_SN, 1, |
797 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 815 | { { 21, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
798 | }, | 816 | }, |
799 | { "sadb_u", TILE_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1, | 817 | { "sadb_u", TILEPRO_OPC_SADB_U, 0x1, 3, TREG_ZERO, 1, |
800 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 818 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
801 | }, | 819 | }, |
802 | { "sadb_u.sn", TILE_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1, | 820 | { "sadb_u.sn", TILEPRO_OPC_SADB_U_SN, 0x1, 3, TREG_SN, 1, |
803 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 821 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
804 | }, | 822 | }, |
805 | { "sadh", TILE_OPC_SADH, 0x1, 3, TREG_ZERO, 1, | 823 | { "sadh", TILEPRO_OPC_SADH, 0x1, 3, TREG_ZERO, 1, |
806 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 824 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
807 | }, | 825 | }, |
808 | { "sadh.sn", TILE_OPC_SADH_SN, 0x1, 3, TREG_SN, 1, | 826 | { "sadh.sn", TILEPRO_OPC_SADH_SN, 0x1, 3, TREG_SN, 1, |
809 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 827 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
810 | }, | 828 | }, |
811 | { "sadh_u", TILE_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1, | 829 | { "sadh_u", TILEPRO_OPC_SADH_U, 0x1, 3, TREG_ZERO, 1, |
812 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 830 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
813 | }, | 831 | }, |
814 | { "sadh_u.sn", TILE_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1, | 832 | { "sadh_u.sn", TILEPRO_OPC_SADH_U_SN, 0x1, 3, TREG_SN, 1, |
815 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 833 | { { 7, 8, 16 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
816 | }, | 834 | }, |
817 | { "sb", TILE_OPC_SB, 0x12, 2, TREG_ZERO, 1, | 835 | { "sb", TILEPRO_OPC_SB, 0x12, 2, TREG_ZERO, 1, |
818 | { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, | 836 | { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, |
819 | }, | 837 | }, |
820 | { "sbadd", TILE_OPC_SBADD, 0x2, 3, TREG_ZERO, 1, | 838 | { "sbadd", TILEPRO_OPC_SBADD, 0x2, 3, TREG_ZERO, 1, |
821 | { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, | 839 | { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, |
822 | }, | 840 | }, |
823 | { "seq", TILE_OPC_SEQ, 0xf, 3, TREG_ZERO, 1, | 841 | { "seq", TILEPRO_OPC_SEQ, 0xf, 3, TREG_ZERO, 1, |
824 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 842 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
825 | }, | 843 | }, |
826 | { "seq.sn", TILE_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1, | 844 | { "seq.sn", TILEPRO_OPC_SEQ_SN, 0x3, 3, TREG_SN, 1, |
827 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 845 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
828 | }, | 846 | }, |
829 | { "seqb", TILE_OPC_SEQB, 0x3, 3, TREG_ZERO, 1, | 847 | { "seqb", TILEPRO_OPC_SEQB, 0x3, 3, TREG_ZERO, 1, |
830 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 848 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
831 | }, | 849 | }, |
832 | { "seqb.sn", TILE_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1, | 850 | { "seqb.sn", TILEPRO_OPC_SEQB_SN, 0x3, 3, TREG_SN, 1, |
833 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 851 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
834 | }, | 852 | }, |
835 | { "seqh", TILE_OPC_SEQH, 0x3, 3, TREG_ZERO, 1, | 853 | { "seqh", TILEPRO_OPC_SEQH, 0x3, 3, TREG_ZERO, 1, |
836 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 854 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
837 | }, | 855 | }, |
838 | { "seqh.sn", TILE_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1, | 856 | { "seqh.sn", TILEPRO_OPC_SEQH_SN, 0x3, 3, TREG_SN, 1, |
839 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 857 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
840 | }, | 858 | }, |
841 | { "seqi", TILE_OPC_SEQI, 0xf, 3, TREG_ZERO, 1, | 859 | { "seqi", TILEPRO_OPC_SEQI, 0xf, 3, TREG_ZERO, 1, |
842 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, | 860 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, |
843 | }, | 861 | }, |
844 | { "seqi.sn", TILE_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1, | 862 | { "seqi.sn", TILEPRO_OPC_SEQI_SN, 0x3, 3, TREG_SN, 1, |
845 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 863 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
846 | }, | 864 | }, |
847 | { "seqib", TILE_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1, | 865 | { "seqib", TILEPRO_OPC_SEQIB, 0x3, 3, TREG_ZERO, 1, |
848 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 866 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
849 | }, | 867 | }, |
850 | { "seqib.sn", TILE_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1, | 868 | { "seqib.sn", TILEPRO_OPC_SEQIB_SN, 0x3, 3, TREG_SN, 1, |
851 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 869 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
852 | }, | 870 | }, |
853 | { "seqih", TILE_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1, | 871 | { "seqih", TILEPRO_OPC_SEQIH, 0x3, 3, TREG_ZERO, 1, |
854 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 872 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
855 | }, | 873 | }, |
856 | { "seqih.sn", TILE_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1, | 874 | { "seqih.sn", TILEPRO_OPC_SEQIH_SN, 0x3, 3, TREG_SN, 1, |
857 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 875 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
858 | }, | 876 | }, |
859 | { "sh", TILE_OPC_SH, 0x12, 2, TREG_ZERO, 1, | 877 | { "sh", TILEPRO_OPC_SH, 0x12, 2, TREG_ZERO, 1, |
860 | { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, | 878 | { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, |
861 | }, | 879 | }, |
862 | { "shadd", TILE_OPC_SHADD, 0x2, 3, TREG_ZERO, 1, | 880 | { "shadd", TILEPRO_OPC_SHADD, 0x2, 3, TREG_ZERO, 1, |
863 | { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, | 881 | { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, |
864 | }, | 882 | }, |
865 | { "shl", TILE_OPC_SHL, 0xf, 3, TREG_ZERO, 1, | 883 | { "shl", TILEPRO_OPC_SHL, 0xf, 3, TREG_ZERO, 1, |
866 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 884 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
867 | }, | 885 | }, |
868 | { "shl.sn", TILE_OPC_SHL_SN, 0x3, 3, TREG_SN, 1, | 886 | { "shl.sn", TILEPRO_OPC_SHL_SN, 0x3, 3, TREG_SN, 1, |
869 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 887 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
870 | }, | 888 | }, |
871 | { "shlb", TILE_OPC_SHLB, 0x3, 3, TREG_ZERO, 1, | 889 | { "shlb", TILEPRO_OPC_SHLB, 0x3, 3, TREG_ZERO, 1, |
872 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 890 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
873 | }, | 891 | }, |
874 | { "shlb.sn", TILE_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1, | 892 | { "shlb.sn", TILEPRO_OPC_SHLB_SN, 0x3, 3, TREG_SN, 1, |
875 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 893 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
876 | }, | 894 | }, |
877 | { "shlh", TILE_OPC_SHLH, 0x3, 3, TREG_ZERO, 1, | 895 | { "shlh", TILEPRO_OPC_SHLH, 0x3, 3, TREG_ZERO, 1, |
878 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 896 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
879 | }, | 897 | }, |
880 | { "shlh.sn", TILE_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1, | 898 | { "shlh.sn", TILEPRO_OPC_SHLH_SN, 0x3, 3, TREG_SN, 1, |
881 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 899 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
882 | }, | 900 | }, |
883 | { "shli", TILE_OPC_SHLI, 0xf, 3, TREG_ZERO, 1, | 901 | { "shli", TILEPRO_OPC_SHLI, 0xf, 3, TREG_ZERO, 1, |
884 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, | 902 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, |
885 | }, | 903 | }, |
886 | { "shli.sn", TILE_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1, | 904 | { "shli.sn", TILEPRO_OPC_SHLI_SN, 0x3, 3, TREG_SN, 1, |
887 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 905 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
888 | }, | 906 | }, |
889 | { "shlib", TILE_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1, | 907 | { "shlib", TILEPRO_OPC_SHLIB, 0x3, 3, TREG_ZERO, 1, |
890 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 908 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
891 | }, | 909 | }, |
892 | { "shlib.sn", TILE_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1, | 910 | { "shlib.sn", TILEPRO_OPC_SHLIB_SN, 0x3, 3, TREG_SN, 1, |
893 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 911 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
894 | }, | 912 | }, |
895 | { "shlih", TILE_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1, | 913 | { "shlih", TILEPRO_OPC_SHLIH, 0x3, 3, TREG_ZERO, 1, |
896 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 914 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
897 | }, | 915 | }, |
898 | { "shlih.sn", TILE_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1, | 916 | { "shlih.sn", TILEPRO_OPC_SHLIH_SN, 0x3, 3, TREG_SN, 1, |
899 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 917 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
900 | }, | 918 | }, |
901 | { "shr", TILE_OPC_SHR, 0xf, 3, TREG_ZERO, 1, | 919 | { "shr", TILEPRO_OPC_SHR, 0xf, 3, TREG_ZERO, 1, |
902 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 920 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
903 | }, | 921 | }, |
904 | { "shr.sn", TILE_OPC_SHR_SN, 0x3, 3, TREG_SN, 1, | 922 | { "shr.sn", TILEPRO_OPC_SHR_SN, 0x3, 3, TREG_SN, 1, |
905 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 923 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
906 | }, | 924 | }, |
907 | { "shrb", TILE_OPC_SHRB, 0x3, 3, TREG_ZERO, 1, | 925 | { "shrb", TILEPRO_OPC_SHRB, 0x3, 3, TREG_ZERO, 1, |
908 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 926 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
909 | }, | 927 | }, |
910 | { "shrb.sn", TILE_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1, | 928 | { "shrb.sn", TILEPRO_OPC_SHRB_SN, 0x3, 3, TREG_SN, 1, |
911 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 929 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
912 | }, | 930 | }, |
913 | { "shrh", TILE_OPC_SHRH, 0x3, 3, TREG_ZERO, 1, | 931 | { "shrh", TILEPRO_OPC_SHRH, 0x3, 3, TREG_ZERO, 1, |
914 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 932 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
915 | }, | 933 | }, |
916 | { "shrh.sn", TILE_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1, | 934 | { "shrh.sn", TILEPRO_OPC_SHRH_SN, 0x3, 3, TREG_SN, 1, |
917 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 935 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
918 | }, | 936 | }, |
919 | { "shri", TILE_OPC_SHRI, 0xf, 3, TREG_ZERO, 1, | 937 | { "shri", TILEPRO_OPC_SHRI, 0xf, 3, TREG_ZERO, 1, |
920 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, | 938 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, |
921 | }, | 939 | }, |
922 | { "shri.sn", TILE_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1, | 940 | { "shri.sn", TILEPRO_OPC_SHRI_SN, 0x3, 3, TREG_SN, 1, |
923 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 941 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
924 | }, | 942 | }, |
925 | { "shrib", TILE_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1, | 943 | { "shrib", TILEPRO_OPC_SHRIB, 0x3, 3, TREG_ZERO, 1, |
926 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 944 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
927 | }, | 945 | }, |
928 | { "shrib.sn", TILE_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1, | 946 | { "shrib.sn", TILEPRO_OPC_SHRIB_SN, 0x3, 3, TREG_SN, 1, |
929 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 947 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
930 | }, | 948 | }, |
931 | { "shrih", TILE_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1, | 949 | { "shrih", TILEPRO_OPC_SHRIH, 0x3, 3, TREG_ZERO, 1, |
932 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 950 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
933 | }, | 951 | }, |
934 | { "shrih.sn", TILE_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1, | 952 | { "shrih.sn", TILEPRO_OPC_SHRIH_SN, 0x3, 3, TREG_SN, 1, |
935 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 953 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
936 | }, | 954 | }, |
937 | { "slt", TILE_OPC_SLT, 0xf, 3, TREG_ZERO, 1, | 955 | { "slt", TILEPRO_OPC_SLT, 0xf, 3, TREG_ZERO, 1, |
938 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 956 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
939 | }, | 957 | }, |
940 | { "slt.sn", TILE_OPC_SLT_SN, 0x3, 3, TREG_SN, 1, | 958 | { "slt.sn", TILEPRO_OPC_SLT_SN, 0x3, 3, TREG_SN, 1, |
941 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 959 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
942 | }, | 960 | }, |
943 | { "slt_u", TILE_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1, | 961 | { "slt_u", TILEPRO_OPC_SLT_U, 0xf, 3, TREG_ZERO, 1, |
944 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 962 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
945 | }, | 963 | }, |
946 | { "slt_u.sn", TILE_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1, | 964 | { "slt_u.sn", TILEPRO_OPC_SLT_U_SN, 0x3, 3, TREG_SN, 1, |
947 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 965 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
948 | }, | 966 | }, |
949 | { "sltb", TILE_OPC_SLTB, 0x3, 3, TREG_ZERO, 1, | 967 | { "sltb", TILEPRO_OPC_SLTB, 0x3, 3, TREG_ZERO, 1, |
950 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 968 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
951 | }, | 969 | }, |
952 | { "sltb.sn", TILE_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1, | 970 | { "sltb.sn", TILEPRO_OPC_SLTB_SN, 0x3, 3, TREG_SN, 1, |
953 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 971 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
954 | }, | 972 | }, |
955 | { "sltb_u", TILE_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1, | 973 | { "sltb_u", TILEPRO_OPC_SLTB_U, 0x3, 3, TREG_ZERO, 1, |
956 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 974 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
957 | }, | 975 | }, |
958 | { "sltb_u.sn", TILE_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1, | 976 | { "sltb_u.sn", TILEPRO_OPC_SLTB_U_SN, 0x3, 3, TREG_SN, 1, |
959 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 977 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
960 | }, | 978 | }, |
961 | { "slte", TILE_OPC_SLTE, 0xf, 3, TREG_ZERO, 1, | 979 | { "slte", TILEPRO_OPC_SLTE, 0xf, 3, TREG_ZERO, 1, |
962 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 980 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
963 | }, | 981 | }, |
964 | { "slte.sn", TILE_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1, | 982 | { "slte.sn", TILEPRO_OPC_SLTE_SN, 0x3, 3, TREG_SN, 1, |
965 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 983 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
966 | }, | 984 | }, |
967 | { "slte_u", TILE_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1, | 985 | { "slte_u", TILEPRO_OPC_SLTE_U, 0xf, 3, TREG_ZERO, 1, |
968 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 986 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
969 | }, | 987 | }, |
970 | { "slte_u.sn", TILE_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1, | 988 | { "slte_u.sn", TILEPRO_OPC_SLTE_U_SN, 0x3, 3, TREG_SN, 1, |
971 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 989 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
972 | }, | 990 | }, |
973 | { "slteb", TILE_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1, | 991 | { "slteb", TILEPRO_OPC_SLTEB, 0x3, 3, TREG_ZERO, 1, |
974 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 992 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
975 | }, | 993 | }, |
976 | { "slteb.sn", TILE_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1, | 994 | { "slteb.sn", TILEPRO_OPC_SLTEB_SN, 0x3, 3, TREG_SN, 1, |
977 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 995 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
978 | }, | 996 | }, |
979 | { "slteb_u", TILE_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1, | 997 | { "slteb_u", TILEPRO_OPC_SLTEB_U, 0x3, 3, TREG_ZERO, 1, |
980 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 998 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
981 | }, | 999 | }, |
982 | { "slteb_u.sn", TILE_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1, | 1000 | { "slteb_u.sn", TILEPRO_OPC_SLTEB_U_SN, 0x3, 3, TREG_SN, 1, |
983 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1001 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
984 | }, | 1002 | }, |
985 | { "slteh", TILE_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1, | 1003 | { "slteh", TILEPRO_OPC_SLTEH, 0x3, 3, TREG_ZERO, 1, |
986 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1004 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
987 | }, | 1005 | }, |
988 | { "slteh.sn", TILE_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1, | 1006 | { "slteh.sn", TILEPRO_OPC_SLTEH_SN, 0x3, 3, TREG_SN, 1, |
989 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1007 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
990 | }, | 1008 | }, |
991 | { "slteh_u", TILE_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1, | 1009 | { "slteh_u", TILEPRO_OPC_SLTEH_U, 0x3, 3, TREG_ZERO, 1, |
992 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1010 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
993 | }, | 1011 | }, |
994 | { "slteh_u.sn", TILE_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1, | 1012 | { "slteh_u.sn", TILEPRO_OPC_SLTEH_U_SN, 0x3, 3, TREG_SN, 1, |
995 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1013 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
996 | }, | 1014 | }, |
997 | { "slth", TILE_OPC_SLTH, 0x3, 3, TREG_ZERO, 1, | 1015 | { "slth", TILEPRO_OPC_SLTH, 0x3, 3, TREG_ZERO, 1, |
998 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1016 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
999 | }, | 1017 | }, |
1000 | { "slth.sn", TILE_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1, | 1018 | { "slth.sn", TILEPRO_OPC_SLTH_SN, 0x3, 3, TREG_SN, 1, |
1001 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1019 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1002 | }, | 1020 | }, |
1003 | { "slth_u", TILE_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1, | 1021 | { "slth_u", TILEPRO_OPC_SLTH_U, 0x3, 3, TREG_ZERO, 1, |
1004 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1022 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1005 | }, | 1023 | }, |
1006 | { "slth_u.sn", TILE_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1, | 1024 | { "slth_u.sn", TILEPRO_OPC_SLTH_U_SN, 0x3, 3, TREG_SN, 1, |
1007 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1025 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1008 | }, | 1026 | }, |
1009 | { "slti", TILE_OPC_SLTI, 0xf, 3, TREG_ZERO, 1, | 1027 | { "slti", TILEPRO_OPC_SLTI, 0xf, 3, TREG_ZERO, 1, |
1010 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, | 1028 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, |
1011 | }, | 1029 | }, |
1012 | { "slti.sn", TILE_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1, | 1030 | { "slti.sn", TILEPRO_OPC_SLTI_SN, 0x3, 3, TREG_SN, 1, |
1013 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1031 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1014 | }, | 1032 | }, |
1015 | { "slti_u", TILE_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1, | 1033 | { "slti_u", TILEPRO_OPC_SLTI_U, 0xf, 3, TREG_ZERO, 1, |
1016 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, | 1034 | { { 7, 8, 0 }, { 9, 10, 1 }, { 11, 12, 2 }, { 13, 14, 3 }, { 0, } }, |
1017 | }, | 1035 | }, |
1018 | { "slti_u.sn", TILE_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1, | 1036 | { "slti_u.sn", TILEPRO_OPC_SLTI_U_SN, 0x3, 3, TREG_SN, 1, |
1019 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1037 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1020 | }, | 1038 | }, |
1021 | { "sltib", TILE_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1, | 1039 | { "sltib", TILEPRO_OPC_SLTIB, 0x3, 3, TREG_ZERO, 1, |
1022 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1040 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1023 | }, | 1041 | }, |
1024 | { "sltib.sn", TILE_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1, | 1042 | { "sltib.sn", TILEPRO_OPC_SLTIB_SN, 0x3, 3, TREG_SN, 1, |
1025 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1043 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1026 | }, | 1044 | }, |
1027 | { "sltib_u", TILE_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1, | 1045 | { "sltib_u", TILEPRO_OPC_SLTIB_U, 0x3, 3, TREG_ZERO, 1, |
1028 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1046 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1029 | }, | 1047 | }, |
1030 | { "sltib_u.sn", TILE_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1, | 1048 | { "sltib_u.sn", TILEPRO_OPC_SLTIB_U_SN, 0x3, 3, TREG_SN, 1, |
1031 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1049 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1032 | }, | 1050 | }, |
1033 | { "sltih", TILE_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1, | 1051 | { "sltih", TILEPRO_OPC_SLTIH, 0x3, 3, TREG_ZERO, 1, |
1034 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1052 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1035 | }, | 1053 | }, |
1036 | { "sltih.sn", TILE_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1, | 1054 | { "sltih.sn", TILEPRO_OPC_SLTIH_SN, 0x3, 3, TREG_SN, 1, |
1037 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1055 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1038 | }, | 1056 | }, |
1039 | { "sltih_u", TILE_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1, | 1057 | { "sltih_u", TILEPRO_OPC_SLTIH_U, 0x3, 3, TREG_ZERO, 1, |
1040 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1058 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1041 | }, | 1059 | }, |
1042 | { "sltih_u.sn", TILE_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1, | 1060 | { "sltih_u.sn", TILEPRO_OPC_SLTIH_U_SN, 0x3, 3, TREG_SN, 1, |
1043 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1061 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1044 | }, | 1062 | }, |
1045 | { "sne", TILE_OPC_SNE, 0xf, 3, TREG_ZERO, 1, | 1063 | { "sne", TILEPRO_OPC_SNE, 0xf, 3, TREG_ZERO, 1, |
1046 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 1064 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
1047 | }, | 1065 | }, |
1048 | { "sne.sn", TILE_OPC_SNE_SN, 0x3, 3, TREG_SN, 1, | 1066 | { "sne.sn", TILEPRO_OPC_SNE_SN, 0x3, 3, TREG_SN, 1, |
1049 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1067 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1050 | }, | 1068 | }, |
1051 | { "sneb", TILE_OPC_SNEB, 0x3, 3, TREG_ZERO, 1, | 1069 | { "sneb", TILEPRO_OPC_SNEB, 0x3, 3, TREG_ZERO, 1, |
1052 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1070 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1053 | }, | 1071 | }, |
1054 | { "sneb.sn", TILE_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1, | 1072 | { "sneb.sn", TILEPRO_OPC_SNEB_SN, 0x3, 3, TREG_SN, 1, |
1055 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1073 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1056 | }, | 1074 | }, |
1057 | { "sneh", TILE_OPC_SNEH, 0x3, 3, TREG_ZERO, 1, | 1075 | { "sneh", TILEPRO_OPC_SNEH, 0x3, 3, TREG_ZERO, 1, |
1058 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1076 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1059 | }, | 1077 | }, |
1060 | { "sneh.sn", TILE_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1, | 1078 | { "sneh.sn", TILEPRO_OPC_SNEH_SN, 0x3, 3, TREG_SN, 1, |
1061 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1079 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1062 | }, | 1080 | }, |
1063 | { "sra", TILE_OPC_SRA, 0xf, 3, TREG_ZERO, 1, | 1081 | { "sra", TILEPRO_OPC_SRA, 0xf, 3, TREG_ZERO, 1, |
1064 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 1082 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
1065 | }, | 1083 | }, |
1066 | { "sra.sn", TILE_OPC_SRA_SN, 0x3, 3, TREG_SN, 1, | 1084 | { "sra.sn", TILEPRO_OPC_SRA_SN, 0x3, 3, TREG_SN, 1, |
1067 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1085 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1068 | }, | 1086 | }, |
1069 | { "srab", TILE_OPC_SRAB, 0x3, 3, TREG_ZERO, 1, | 1087 | { "srab", TILEPRO_OPC_SRAB, 0x3, 3, TREG_ZERO, 1, |
1070 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1088 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1071 | }, | 1089 | }, |
1072 | { "srab.sn", TILE_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1, | 1090 | { "srab.sn", TILEPRO_OPC_SRAB_SN, 0x3, 3, TREG_SN, 1, |
1073 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1091 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1074 | }, | 1092 | }, |
1075 | { "srah", TILE_OPC_SRAH, 0x3, 3, TREG_ZERO, 1, | 1093 | { "srah", TILEPRO_OPC_SRAH, 0x3, 3, TREG_ZERO, 1, |
1076 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1094 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1077 | }, | 1095 | }, |
1078 | { "srah.sn", TILE_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1, | 1096 | { "srah.sn", TILEPRO_OPC_SRAH_SN, 0x3, 3, TREG_SN, 1, |
1079 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1097 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1080 | }, | 1098 | }, |
1081 | { "srai", TILE_OPC_SRAI, 0xf, 3, TREG_ZERO, 1, | 1099 | { "srai", TILEPRO_OPC_SRAI, 0xf, 3, TREG_ZERO, 1, |
1082 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, | 1100 | { { 7, 8, 32 }, { 9, 10, 33 }, { 11, 12, 34 }, { 13, 14, 35 }, { 0, } }, |
1083 | }, | 1101 | }, |
1084 | { "srai.sn", TILE_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1, | 1102 | { "srai.sn", TILEPRO_OPC_SRAI_SN, 0x3, 3, TREG_SN, 1, |
1085 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 1103 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
1086 | }, | 1104 | }, |
1087 | { "sraib", TILE_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1, | 1105 | { "sraib", TILEPRO_OPC_SRAIB, 0x3, 3, TREG_ZERO, 1, |
1088 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 1106 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
1089 | }, | 1107 | }, |
1090 | { "sraib.sn", TILE_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1, | 1108 | { "sraib.sn", TILEPRO_OPC_SRAIB_SN, 0x3, 3, TREG_SN, 1, |
1091 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 1109 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
1092 | }, | 1110 | }, |
1093 | { "sraih", TILE_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1, | 1111 | { "sraih", TILEPRO_OPC_SRAIH, 0x3, 3, TREG_ZERO, 1, |
1094 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 1112 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
1095 | }, | 1113 | }, |
1096 | { "sraih.sn", TILE_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1, | 1114 | { "sraih.sn", TILEPRO_OPC_SRAIH_SN, 0x3, 3, TREG_SN, 1, |
1097 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, | 1115 | { { 7, 8, 32 }, { 9, 10, 33 }, { 0, }, { 0, }, { 0, } }, |
1098 | }, | 1116 | }, |
1099 | { "sub", TILE_OPC_SUB, 0xf, 3, TREG_ZERO, 1, | 1117 | { "sub", TILEPRO_OPC_SUB, 0xf, 3, TREG_ZERO, 1, |
1100 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 1118 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
1101 | }, | 1119 | }, |
1102 | { "sub.sn", TILE_OPC_SUB_SN, 0x3, 3, TREG_SN, 1, | 1120 | { "sub.sn", TILEPRO_OPC_SUB_SN, 0x3, 3, TREG_SN, 1, |
1103 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1121 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1104 | }, | 1122 | }, |
1105 | { "subb", TILE_OPC_SUBB, 0x3, 3, TREG_ZERO, 1, | 1123 | { "subb", TILEPRO_OPC_SUBB, 0x3, 3, TREG_ZERO, 1, |
1106 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1124 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1107 | }, | 1125 | }, |
1108 | { "subb.sn", TILE_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1, | 1126 | { "subb.sn", TILEPRO_OPC_SUBB_SN, 0x3, 3, TREG_SN, 1, |
1109 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1127 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1110 | }, | 1128 | }, |
1111 | { "subbs_u", TILE_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1, | 1129 | { "subbs_u", TILEPRO_OPC_SUBBS_U, 0x3, 3, TREG_ZERO, 1, |
1112 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1130 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1113 | }, | 1131 | }, |
1114 | { "subbs_u.sn", TILE_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1, | 1132 | { "subbs_u.sn", TILEPRO_OPC_SUBBS_U_SN, 0x3, 3, TREG_SN, 1, |
1115 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1133 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1116 | }, | 1134 | }, |
1117 | { "subh", TILE_OPC_SUBH, 0x3, 3, TREG_ZERO, 1, | 1135 | { "subh", TILEPRO_OPC_SUBH, 0x3, 3, TREG_ZERO, 1, |
1118 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1136 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1119 | }, | 1137 | }, |
1120 | { "subh.sn", TILE_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1, | 1138 | { "subh.sn", TILEPRO_OPC_SUBH_SN, 0x3, 3, TREG_SN, 1, |
1121 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1139 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1122 | }, | 1140 | }, |
1123 | { "subhs", TILE_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1, | 1141 | { "subhs", TILEPRO_OPC_SUBHS, 0x3, 3, TREG_ZERO, 1, |
1124 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1142 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1125 | }, | 1143 | }, |
1126 | { "subhs.sn", TILE_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1, | 1144 | { "subhs.sn", TILEPRO_OPC_SUBHS_SN, 0x3, 3, TREG_SN, 1, |
1127 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1145 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1128 | }, | 1146 | }, |
1129 | { "subs", TILE_OPC_SUBS, 0x3, 3, TREG_ZERO, 1, | 1147 | { "subs", TILEPRO_OPC_SUBS, 0x3, 3, TREG_ZERO, 1, |
1130 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1148 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1131 | }, | 1149 | }, |
1132 | { "subs.sn", TILE_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1, | 1150 | { "subs.sn", TILEPRO_OPC_SUBS_SN, 0x3, 3, TREG_SN, 1, |
1133 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1151 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1134 | }, | 1152 | }, |
1135 | { "sw", TILE_OPC_SW, 0x12, 2, TREG_ZERO, 1, | 1153 | { "sw", TILEPRO_OPC_SW, 0x12, 2, TREG_ZERO, 1, |
1136 | { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, | 1154 | { { 0, }, { 10, 17 }, { 0, }, { 0, }, { 15, 36 } }, |
1137 | }, | 1155 | }, |
1138 | { "swadd", TILE_OPC_SWADD, 0x2, 3, TREG_ZERO, 1, | 1156 | { "swadd", TILEPRO_OPC_SWADD, 0x2, 3, TREG_ZERO, 1, |
1139 | { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, | 1157 | { { 0, }, { 24, 17, 37 }, { 0, }, { 0, }, { 0, } }, |
1140 | }, | 1158 | }, |
1141 | { "swint0", TILE_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0, | 1159 | { "swint0", TILEPRO_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0, |
1142 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 1160 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
1143 | }, | 1161 | }, |
1144 | { "swint1", TILE_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0, | 1162 | { "swint1", TILEPRO_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0, |
1145 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 1163 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
1146 | }, | 1164 | }, |
1147 | { "swint2", TILE_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0, | 1165 | { "swint2", TILEPRO_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0, |
1148 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 1166 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
1149 | }, | 1167 | }, |
1150 | { "swint3", TILE_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0, | 1168 | { "swint3", TILEPRO_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0, |
1151 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, | 1169 | { { 0, }, { }, { 0, }, { 0, }, { 0, } }, |
1152 | }, | 1170 | }, |
1153 | { "tblidxb0", TILE_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1, | 1171 | { "tblidxb0", TILEPRO_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1, |
1154 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, | 1172 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, |
1155 | }, | 1173 | }, |
1156 | { "tblidxb0.sn", TILE_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1, | 1174 | { "tblidxb0.sn", TILEPRO_OPC_TBLIDXB0_SN, 0x1, 2, TREG_SN, 1, |
1157 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 1175 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
1158 | }, | 1176 | }, |
1159 | { "tblidxb1", TILE_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1, | 1177 | { "tblidxb1", TILEPRO_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1, |
1160 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, | 1178 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, |
1161 | }, | 1179 | }, |
1162 | { "tblidxb1.sn", TILE_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1, | 1180 | { "tblidxb1.sn", TILEPRO_OPC_TBLIDXB1_SN, 0x1, 2, TREG_SN, 1, |
1163 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 1181 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
1164 | }, | 1182 | }, |
1165 | { "tblidxb2", TILE_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1, | 1183 | { "tblidxb2", TILEPRO_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1, |
1166 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, | 1184 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, |
1167 | }, | 1185 | }, |
1168 | { "tblidxb2.sn", TILE_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1, | 1186 | { "tblidxb2.sn", TILEPRO_OPC_TBLIDXB2_SN, 0x1, 2, TREG_SN, 1, |
1169 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 1187 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
1170 | }, | 1188 | }, |
1171 | { "tblidxb3", TILE_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1, | 1189 | { "tblidxb3", TILEPRO_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1, |
1172 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, | 1190 | { { 21, 8 }, { 0, }, { 31, 12 }, { 0, }, { 0, } }, |
1173 | }, | 1191 | }, |
1174 | { "tblidxb3.sn", TILE_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1, | 1192 | { "tblidxb3.sn", TILEPRO_OPC_TBLIDXB3_SN, 0x1, 2, TREG_SN, 1, |
1175 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, | 1193 | { { 21, 8 }, { 0, }, { 0, }, { 0, }, { 0, } }, |
1176 | }, | 1194 | }, |
1177 | { "tns", TILE_OPC_TNS, 0x2, 2, TREG_ZERO, 1, | 1195 | { "tns", TILEPRO_OPC_TNS, 0x2, 2, TREG_ZERO, 1, |
1178 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 1196 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
1179 | }, | 1197 | }, |
1180 | { "tns.sn", TILE_OPC_TNS_SN, 0x2, 2, TREG_SN, 1, | 1198 | { "tns.sn", TILEPRO_OPC_TNS_SN, 0x2, 2, TREG_SN, 1, |
1181 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, | 1199 | { { 0, }, { 9, 10 }, { 0, }, { 0, }, { 0, } }, |
1182 | }, | 1200 | }, |
1183 | { "wh64", TILE_OPC_WH64, 0x2, 1, TREG_ZERO, 1, | 1201 | { "wh64", TILEPRO_OPC_WH64, 0x2, 1, TREG_ZERO, 1, |
1184 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, | 1202 | { { 0, }, { 10 }, { 0, }, { 0, }, { 0, } }, |
1185 | }, | 1203 | }, |
1186 | { "xor", TILE_OPC_XOR, 0xf, 3, TREG_ZERO, 1, | 1204 | { "xor", TILEPRO_OPC_XOR, 0xf, 3, TREG_ZERO, 1, |
1187 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, | 1205 | { { 7, 8, 16 }, { 9, 10, 17 }, { 11, 12, 18 }, { 13, 14, 19 }, { 0, } }, |
1188 | }, | 1206 | }, |
1189 | { "xor.sn", TILE_OPC_XOR_SN, 0x3, 3, TREG_SN, 1, | 1207 | { "xor.sn", TILEPRO_OPC_XOR_SN, 0x3, 3, TREG_SN, 1, |
1190 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, | 1208 | { { 7, 8, 16 }, { 9, 10, 17 }, { 0, }, { 0, }, { 0, } }, |
1191 | }, | 1209 | }, |
1192 | { "xori", TILE_OPC_XORI, 0x3, 3, TREG_ZERO, 1, | 1210 | { "xori", TILEPRO_OPC_XORI, 0x3, 3, TREG_ZERO, 1, |
1193 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1211 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1194 | }, | 1212 | }, |
1195 | { "xori.sn", TILE_OPC_XORI_SN, 0x3, 3, TREG_SN, 1, | 1213 | { "xori.sn", TILEPRO_OPC_XORI_SN, 0x3, 3, TREG_SN, 1, |
1196 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, | 1214 | { { 7, 8, 0 }, { 9, 10, 1 }, { 0, }, { 0, }, { 0, } }, |
1197 | }, | 1215 | }, |
1198 | { NULL, TILE_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } }, | 1216 | { NULL, TILEPRO_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } }, |
1199 | } | 1217 | } |
1200 | }; | 1218 | }; |
1201 | #define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6)) | 1219 | #define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6)) |
1202 | #define CHILD(array_index) (TILE_OPC_NONE + (array_index)) | 1220 | #define CHILD(array_index) (TILEPRO_OPC_NONE + (array_index)) |
1203 | 1221 | ||
1204 | static const unsigned short decode_X0_fsm[1153] = | 1222 | static const unsigned short decode_X0_fsm[1153] = |
1205 | { | 1223 | { |
1206 | BITFIELD(22, 9) /* index 0 */, | 1224 | BITFIELD(22, 9) /* index 0 */, |
1207 | CHILD(513), CHILD(530), CHILD(547), CHILD(564), CHILD(596), CHILD(613), | 1225 | CHILD(513), CHILD(530), CHILD(547), CHILD(564), CHILD(596), CHILD(613), |
1208 | CHILD(630), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1226 | CHILD(630), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1209 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1227 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1210 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1228 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1211 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1229 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1212 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1230 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1213 | TILE_OPC_NONE, CHILD(663), CHILD(680), CHILD(697), CHILD(714), CHILD(746), | 1231 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1214 | CHILD(763), CHILD(780), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1232 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(663), CHILD(680), CHILD(697), |
1215 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1233 | CHILD(714), CHILD(746), CHILD(763), CHILD(780), TILEPRO_OPC_NONE, |
1216 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1234 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1217 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1235 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1218 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1236 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1219 | TILE_OPC_NONE, TILE_OPC_NONE, CHILD(813), CHILD(813), CHILD(813), | 1237 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1238 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1239 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1220 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), | 1240 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), |
1221 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), | 1241 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), |
1222 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), | 1242 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), |
@@ -1227,7 +1247,8 @@ static const unsigned short decode_X0_fsm[1153] = | |||
1227 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), | 1247 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), |
1228 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), | 1248 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), |
1229 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), | 1249 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(813), |
1230 | CHILD(813), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | 1250 | CHILD(813), CHILD(813), CHILD(813), CHILD(813), CHILD(828), CHILD(828), |
1251 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | ||
1231 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | 1252 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), |
1232 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | 1253 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), |
1233 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | 1254 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), |
@@ -1237,7 +1258,7 @@ static const unsigned short decode_X0_fsm[1153] = | |||
1237 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | 1258 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), |
1238 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | 1259 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), |
1239 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), | 1260 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), |
1240 | CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(828), CHILD(843), | 1261 | CHILD(828), CHILD(828), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1241 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1262 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1242 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1263 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1243 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1264 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
@@ -1248,333 +1269,371 @@ static const unsigned short decode_X0_fsm[1153] = | |||
1248 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1269 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1249 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1270 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1250 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1271 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1251 | CHILD(843), CHILD(843), CHILD(843), CHILD(873), CHILD(878), CHILD(883), | 1272 | CHILD(873), CHILD(878), CHILD(883), CHILD(903), CHILD(908), |
1252 | CHILD(903), CHILD(908), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1273 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1253 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1274 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1254 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1275 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1255 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1276 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1256 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1277 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1257 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(913), | 1278 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1258 | CHILD(918), CHILD(923), CHILD(943), CHILD(948), TILE_OPC_NONE, | 1279 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(913), |
1259 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1280 | CHILD(918), CHILD(923), CHILD(943), CHILD(948), TILEPRO_OPC_NONE, |
1260 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1281 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1261 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1282 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1262 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1283 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1263 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1284 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1264 | TILE_OPC_NONE, CHILD(953), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1285 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1265 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1286 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1266 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1287 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(953), TILEPRO_OPC_NONE, |
1267 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1288 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1268 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1289 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1269 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1290 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1270 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(988), TILE_OPC_NONE, | 1291 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1271 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1292 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1272 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1293 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1273 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1294 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1274 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1295 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(988), TILEPRO_OPC_NONE, |
1275 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1296 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1276 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1297 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1277 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1298 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1278 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1299 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1279 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1300 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1280 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1301 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1281 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1302 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1282 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1303 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1283 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1304 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1284 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1305 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1285 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1306 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1286 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1307 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1287 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1308 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1288 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1309 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1289 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, CHILD(993), | 1310 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1290 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1311 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1291 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1312 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1292 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1313 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1293 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1314 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1294 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1315 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1295 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1316 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1296 | TILE_OPC_NONE, CHILD(1076), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1317 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1297 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1318 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1298 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1319 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(993), TILEPRO_OPC_NONE, |
1299 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1320 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1300 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1321 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1301 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1322 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1302 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1323 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1324 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1325 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1326 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1327 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1076), TILEPRO_OPC_NONE, | ||
1328 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1329 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1330 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1331 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1332 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1333 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1334 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1335 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1303 | BITFIELD(18, 4) /* index 513 */, | 1336 | BITFIELD(18, 4) /* index 513 */, |
1304 | TILE_OPC_NONE, TILE_OPC_ADDB, TILE_OPC_ADDH, TILE_OPC_ADD, | 1337 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB, TILEPRO_OPC_ADDH, TILEPRO_OPC_ADD, |
1305 | TILE_OPC_ADIFFB_U, TILE_OPC_ADIFFH, TILE_OPC_AND, TILE_OPC_AVGB_U, | 1338 | TILEPRO_OPC_ADIFFB_U, TILEPRO_OPC_ADIFFH, TILEPRO_OPC_AND, |
1306 | TILE_OPC_AVGH, TILE_OPC_CRC32_32, TILE_OPC_CRC32_8, TILE_OPC_INTHB, | 1339 | TILEPRO_OPC_AVGB_U, TILEPRO_OPC_AVGH, TILEPRO_OPC_CRC32_32, |
1307 | TILE_OPC_INTHH, TILE_OPC_INTLB, TILE_OPC_INTLH, TILE_OPC_MAXB_U, | 1340 | TILEPRO_OPC_CRC32_8, TILEPRO_OPC_INTHB, TILEPRO_OPC_INTHH, |
1341 | TILEPRO_OPC_INTLB, TILEPRO_OPC_INTLH, TILEPRO_OPC_MAXB_U, | ||
1308 | BITFIELD(18, 4) /* index 530 */, | 1342 | BITFIELD(18, 4) /* index 530 */, |
1309 | TILE_OPC_MAXH, TILE_OPC_MINB_U, TILE_OPC_MINH, TILE_OPC_MNZB, TILE_OPC_MNZH, | 1343 | TILEPRO_OPC_MAXH, TILEPRO_OPC_MINB_U, TILEPRO_OPC_MINH, TILEPRO_OPC_MNZB, |
1310 | TILE_OPC_MNZ, TILE_OPC_MULHHA_SS, TILE_OPC_MULHHA_SU, TILE_OPC_MULHHA_UU, | 1344 | TILEPRO_OPC_MNZH, TILEPRO_OPC_MNZ, TILEPRO_OPC_MULHHA_SS, |
1311 | TILE_OPC_MULHHSA_UU, TILE_OPC_MULHH_SS, TILE_OPC_MULHH_SU, | 1345 | TILEPRO_OPC_MULHHA_SU, TILEPRO_OPC_MULHHA_UU, TILEPRO_OPC_MULHHSA_UU, |
1312 | TILE_OPC_MULHH_UU, TILE_OPC_MULHLA_SS, TILE_OPC_MULHLA_SU, | 1346 | TILEPRO_OPC_MULHH_SS, TILEPRO_OPC_MULHH_SU, TILEPRO_OPC_MULHH_UU, |
1313 | TILE_OPC_MULHLA_US, | 1347 | TILEPRO_OPC_MULHLA_SS, TILEPRO_OPC_MULHLA_SU, TILEPRO_OPC_MULHLA_US, |
1314 | BITFIELD(18, 4) /* index 547 */, | 1348 | BITFIELD(18, 4) /* index 547 */, |
1315 | TILE_OPC_MULHLA_UU, TILE_OPC_MULHLSA_UU, TILE_OPC_MULHL_SS, | 1349 | TILEPRO_OPC_MULHLA_UU, TILEPRO_OPC_MULHLSA_UU, TILEPRO_OPC_MULHL_SS, |
1316 | TILE_OPC_MULHL_SU, TILE_OPC_MULHL_US, TILE_OPC_MULHL_UU, TILE_OPC_MULLLA_SS, | 1350 | TILEPRO_OPC_MULHL_SU, TILEPRO_OPC_MULHL_US, TILEPRO_OPC_MULHL_UU, |
1317 | TILE_OPC_MULLLA_SU, TILE_OPC_MULLLA_UU, TILE_OPC_MULLLSA_UU, | 1351 | TILEPRO_OPC_MULLLA_SS, TILEPRO_OPC_MULLLA_SU, TILEPRO_OPC_MULLLA_UU, |
1318 | TILE_OPC_MULLL_SS, TILE_OPC_MULLL_SU, TILE_OPC_MULLL_UU, TILE_OPC_MVNZ, | 1352 | TILEPRO_OPC_MULLLSA_UU, TILEPRO_OPC_MULLL_SS, TILEPRO_OPC_MULLL_SU, |
1319 | TILE_OPC_MVZ, TILE_OPC_MZB, | 1353 | TILEPRO_OPC_MULLL_UU, TILEPRO_OPC_MVNZ, TILEPRO_OPC_MVZ, TILEPRO_OPC_MZB, |
1320 | BITFIELD(18, 4) /* index 564 */, | 1354 | BITFIELD(18, 4) /* index 564 */, |
1321 | TILE_OPC_MZH, TILE_OPC_MZ, TILE_OPC_NOR, CHILD(581), TILE_OPC_PACKHB, | 1355 | TILEPRO_OPC_MZH, TILEPRO_OPC_MZ, TILEPRO_OPC_NOR, CHILD(581), |
1322 | TILE_OPC_PACKLB, TILE_OPC_RL, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_S3A, | 1356 | TILEPRO_OPC_PACKHB, TILEPRO_OPC_PACKLB, TILEPRO_OPC_RL, TILEPRO_OPC_S1A, |
1323 | TILE_OPC_SADAB_U, TILE_OPC_SADAH, TILE_OPC_SADAH_U, TILE_OPC_SADB_U, | 1357 | TILEPRO_OPC_S2A, TILEPRO_OPC_S3A, TILEPRO_OPC_SADAB_U, TILEPRO_OPC_SADAH, |
1324 | TILE_OPC_SADH, TILE_OPC_SADH_U, | 1358 | TILEPRO_OPC_SADAH_U, TILEPRO_OPC_SADB_U, TILEPRO_OPC_SADH, |
1359 | TILEPRO_OPC_SADH_U, | ||
1325 | BITFIELD(12, 2) /* index 581 */, | 1360 | BITFIELD(12, 2) /* index 581 */, |
1326 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(586), | 1361 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(586), |
1327 | BITFIELD(14, 2) /* index 586 */, | 1362 | BITFIELD(14, 2) /* index 586 */, |
1328 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(591), | 1363 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(591), |
1329 | BITFIELD(16, 2) /* index 591 */, | 1364 | BITFIELD(16, 2) /* index 591 */, |
1330 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, | 1365 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, |
1331 | BITFIELD(18, 4) /* index 596 */, | 1366 | BITFIELD(18, 4) /* index 596 */, |
1332 | TILE_OPC_SEQB, TILE_OPC_SEQH, TILE_OPC_SEQ, TILE_OPC_SHLB, TILE_OPC_SHLH, | 1367 | TILEPRO_OPC_SEQB, TILEPRO_OPC_SEQH, TILEPRO_OPC_SEQ, TILEPRO_OPC_SHLB, |
1333 | TILE_OPC_SHL, TILE_OPC_SHRB, TILE_OPC_SHRH, TILE_OPC_SHR, TILE_OPC_SLTB, | 1368 | TILEPRO_OPC_SHLH, TILEPRO_OPC_SHL, TILEPRO_OPC_SHRB, TILEPRO_OPC_SHRH, |
1334 | TILE_OPC_SLTB_U, TILE_OPC_SLTEB, TILE_OPC_SLTEB_U, TILE_OPC_SLTEH, | 1369 | TILEPRO_OPC_SHR, TILEPRO_OPC_SLTB, TILEPRO_OPC_SLTB_U, TILEPRO_OPC_SLTEB, |
1335 | TILE_OPC_SLTEH_U, TILE_OPC_SLTE, | 1370 | TILEPRO_OPC_SLTEB_U, TILEPRO_OPC_SLTEH, TILEPRO_OPC_SLTEH_U, |
1371 | TILEPRO_OPC_SLTE, | ||
1336 | BITFIELD(18, 4) /* index 613 */, | 1372 | BITFIELD(18, 4) /* index 613 */, |
1337 | TILE_OPC_SLTE_U, TILE_OPC_SLTH, TILE_OPC_SLTH_U, TILE_OPC_SLT, | 1373 | TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLTH, TILEPRO_OPC_SLTH_U, TILEPRO_OPC_SLT, |
1338 | TILE_OPC_SLT_U, TILE_OPC_SNEB, TILE_OPC_SNEH, TILE_OPC_SNE, TILE_OPC_SRAB, | 1374 | TILEPRO_OPC_SLT_U, TILEPRO_OPC_SNEB, TILEPRO_OPC_SNEH, TILEPRO_OPC_SNE, |
1339 | TILE_OPC_SRAH, TILE_OPC_SRA, TILE_OPC_SUBB, TILE_OPC_SUBH, TILE_OPC_SUB, | 1375 | TILEPRO_OPC_SRAB, TILEPRO_OPC_SRAH, TILEPRO_OPC_SRA, TILEPRO_OPC_SUBB, |
1340 | TILE_OPC_XOR, TILE_OPC_DWORD_ALIGN, | 1376 | TILEPRO_OPC_SUBH, TILEPRO_OPC_SUB, TILEPRO_OPC_XOR, TILEPRO_OPC_DWORD_ALIGN, |
1341 | BITFIELD(18, 3) /* index 630 */, | 1377 | BITFIELD(18, 3) /* index 630 */, |
1342 | CHILD(639), CHILD(642), CHILD(645), CHILD(648), CHILD(651), CHILD(654), | 1378 | CHILD(639), CHILD(642), CHILD(645), CHILD(648), CHILD(651), CHILD(654), |
1343 | CHILD(657), CHILD(660), | 1379 | CHILD(657), CHILD(660), |
1344 | BITFIELD(21, 1) /* index 639 */, | 1380 | BITFIELD(21, 1) /* index 639 */, |
1345 | TILE_OPC_ADDS, TILE_OPC_NONE, | 1381 | TILEPRO_OPC_ADDS, TILEPRO_OPC_NONE, |
1346 | BITFIELD(21, 1) /* index 642 */, | 1382 | BITFIELD(21, 1) /* index 642 */, |
1347 | TILE_OPC_SUBS, TILE_OPC_NONE, | 1383 | TILEPRO_OPC_SUBS, TILEPRO_OPC_NONE, |
1348 | BITFIELD(21, 1) /* index 645 */, | 1384 | BITFIELD(21, 1) /* index 645 */, |
1349 | TILE_OPC_ADDBS_U, TILE_OPC_NONE, | 1385 | TILEPRO_OPC_ADDBS_U, TILEPRO_OPC_NONE, |
1350 | BITFIELD(21, 1) /* index 648 */, | 1386 | BITFIELD(21, 1) /* index 648 */, |
1351 | TILE_OPC_ADDHS, TILE_OPC_NONE, | 1387 | TILEPRO_OPC_ADDHS, TILEPRO_OPC_NONE, |
1352 | BITFIELD(21, 1) /* index 651 */, | 1388 | BITFIELD(21, 1) /* index 651 */, |
1353 | TILE_OPC_SUBBS_U, TILE_OPC_NONE, | 1389 | TILEPRO_OPC_SUBBS_U, TILEPRO_OPC_NONE, |
1354 | BITFIELD(21, 1) /* index 654 */, | 1390 | BITFIELD(21, 1) /* index 654 */, |
1355 | TILE_OPC_SUBHS, TILE_OPC_NONE, | 1391 | TILEPRO_OPC_SUBHS, TILEPRO_OPC_NONE, |
1356 | BITFIELD(21, 1) /* index 657 */, | 1392 | BITFIELD(21, 1) /* index 657 */, |
1357 | TILE_OPC_PACKHS, TILE_OPC_NONE, | 1393 | TILEPRO_OPC_PACKHS, TILEPRO_OPC_NONE, |
1358 | BITFIELD(21, 1) /* index 660 */, | 1394 | BITFIELD(21, 1) /* index 660 */, |
1359 | TILE_OPC_PACKBS_U, TILE_OPC_NONE, | 1395 | TILEPRO_OPC_PACKBS_U, TILEPRO_OPC_NONE, |
1360 | BITFIELD(18, 4) /* index 663 */, | 1396 | BITFIELD(18, 4) /* index 663 */, |
1361 | TILE_OPC_NONE, TILE_OPC_ADDB_SN, TILE_OPC_ADDH_SN, TILE_OPC_ADD_SN, | 1397 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB_SN, TILEPRO_OPC_ADDH_SN, |
1362 | TILE_OPC_ADIFFB_U_SN, TILE_OPC_ADIFFH_SN, TILE_OPC_AND_SN, | 1398 | TILEPRO_OPC_ADD_SN, TILEPRO_OPC_ADIFFB_U_SN, TILEPRO_OPC_ADIFFH_SN, |
1363 | TILE_OPC_AVGB_U_SN, TILE_OPC_AVGH_SN, TILE_OPC_CRC32_32_SN, | 1399 | TILEPRO_OPC_AND_SN, TILEPRO_OPC_AVGB_U_SN, TILEPRO_OPC_AVGH_SN, |
1364 | TILE_OPC_CRC32_8_SN, TILE_OPC_INTHB_SN, TILE_OPC_INTHH_SN, | 1400 | TILEPRO_OPC_CRC32_32_SN, TILEPRO_OPC_CRC32_8_SN, TILEPRO_OPC_INTHB_SN, |
1365 | TILE_OPC_INTLB_SN, TILE_OPC_INTLH_SN, TILE_OPC_MAXB_U_SN, | 1401 | TILEPRO_OPC_INTHH_SN, TILEPRO_OPC_INTLB_SN, TILEPRO_OPC_INTLH_SN, |
1402 | TILEPRO_OPC_MAXB_U_SN, | ||
1366 | BITFIELD(18, 4) /* index 680 */, | 1403 | BITFIELD(18, 4) /* index 680 */, |
1367 | TILE_OPC_MAXH_SN, TILE_OPC_MINB_U_SN, TILE_OPC_MINH_SN, TILE_OPC_MNZB_SN, | 1404 | TILEPRO_OPC_MAXH_SN, TILEPRO_OPC_MINB_U_SN, TILEPRO_OPC_MINH_SN, |
1368 | TILE_OPC_MNZH_SN, TILE_OPC_MNZ_SN, TILE_OPC_MULHHA_SS_SN, | 1405 | TILEPRO_OPC_MNZB_SN, TILEPRO_OPC_MNZH_SN, TILEPRO_OPC_MNZ_SN, |
1369 | TILE_OPC_MULHHA_SU_SN, TILE_OPC_MULHHA_UU_SN, TILE_OPC_MULHHSA_UU_SN, | 1406 | TILEPRO_OPC_MULHHA_SS_SN, TILEPRO_OPC_MULHHA_SU_SN, |
1370 | TILE_OPC_MULHH_SS_SN, TILE_OPC_MULHH_SU_SN, TILE_OPC_MULHH_UU_SN, | 1407 | TILEPRO_OPC_MULHHA_UU_SN, TILEPRO_OPC_MULHHSA_UU_SN, |
1371 | TILE_OPC_MULHLA_SS_SN, TILE_OPC_MULHLA_SU_SN, TILE_OPC_MULHLA_US_SN, | 1408 | TILEPRO_OPC_MULHH_SS_SN, TILEPRO_OPC_MULHH_SU_SN, TILEPRO_OPC_MULHH_UU_SN, |
1409 | TILEPRO_OPC_MULHLA_SS_SN, TILEPRO_OPC_MULHLA_SU_SN, | ||
1410 | TILEPRO_OPC_MULHLA_US_SN, | ||
1372 | BITFIELD(18, 4) /* index 697 */, | 1411 | BITFIELD(18, 4) /* index 697 */, |
1373 | TILE_OPC_MULHLA_UU_SN, TILE_OPC_MULHLSA_UU_SN, TILE_OPC_MULHL_SS_SN, | 1412 | TILEPRO_OPC_MULHLA_UU_SN, TILEPRO_OPC_MULHLSA_UU_SN, |
1374 | TILE_OPC_MULHL_SU_SN, TILE_OPC_MULHL_US_SN, TILE_OPC_MULHL_UU_SN, | 1413 | TILEPRO_OPC_MULHL_SS_SN, TILEPRO_OPC_MULHL_SU_SN, TILEPRO_OPC_MULHL_US_SN, |
1375 | TILE_OPC_MULLLA_SS_SN, TILE_OPC_MULLLA_SU_SN, TILE_OPC_MULLLA_UU_SN, | 1414 | TILEPRO_OPC_MULHL_UU_SN, TILEPRO_OPC_MULLLA_SS_SN, TILEPRO_OPC_MULLLA_SU_SN, |
1376 | TILE_OPC_MULLLSA_UU_SN, TILE_OPC_MULLL_SS_SN, TILE_OPC_MULLL_SU_SN, | 1415 | TILEPRO_OPC_MULLLA_UU_SN, TILEPRO_OPC_MULLLSA_UU_SN, |
1377 | TILE_OPC_MULLL_UU_SN, TILE_OPC_MVNZ_SN, TILE_OPC_MVZ_SN, TILE_OPC_MZB_SN, | 1416 | TILEPRO_OPC_MULLL_SS_SN, TILEPRO_OPC_MULLL_SU_SN, TILEPRO_OPC_MULLL_UU_SN, |
1417 | TILEPRO_OPC_MVNZ_SN, TILEPRO_OPC_MVZ_SN, TILEPRO_OPC_MZB_SN, | ||
1378 | BITFIELD(18, 4) /* index 714 */, | 1418 | BITFIELD(18, 4) /* index 714 */, |
1379 | TILE_OPC_MZH_SN, TILE_OPC_MZ_SN, TILE_OPC_NOR_SN, CHILD(731), | 1419 | TILEPRO_OPC_MZH_SN, TILEPRO_OPC_MZ_SN, TILEPRO_OPC_NOR_SN, CHILD(731), |
1380 | TILE_OPC_PACKHB_SN, TILE_OPC_PACKLB_SN, TILE_OPC_RL_SN, TILE_OPC_S1A_SN, | 1420 | TILEPRO_OPC_PACKHB_SN, TILEPRO_OPC_PACKLB_SN, TILEPRO_OPC_RL_SN, |
1381 | TILE_OPC_S2A_SN, TILE_OPC_S3A_SN, TILE_OPC_SADAB_U_SN, TILE_OPC_SADAH_SN, | 1421 | TILEPRO_OPC_S1A_SN, TILEPRO_OPC_S2A_SN, TILEPRO_OPC_S3A_SN, |
1382 | TILE_OPC_SADAH_U_SN, TILE_OPC_SADB_U_SN, TILE_OPC_SADH_SN, | 1422 | TILEPRO_OPC_SADAB_U_SN, TILEPRO_OPC_SADAH_SN, TILEPRO_OPC_SADAH_U_SN, |
1383 | TILE_OPC_SADH_U_SN, | 1423 | TILEPRO_OPC_SADB_U_SN, TILEPRO_OPC_SADH_SN, TILEPRO_OPC_SADH_U_SN, |
1384 | BITFIELD(12, 2) /* index 731 */, | 1424 | BITFIELD(12, 2) /* index 731 */, |
1385 | TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(736), | 1425 | TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(736), |
1386 | BITFIELD(14, 2) /* index 736 */, | 1426 | BITFIELD(14, 2) /* index 736 */, |
1387 | TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(741), | 1427 | TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(741), |
1388 | BITFIELD(16, 2) /* index 741 */, | 1428 | BITFIELD(16, 2) /* index 741 */, |
1389 | TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_MOVE_SN, | 1429 | TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, |
1430 | TILEPRO_OPC_MOVE_SN, | ||
1390 | BITFIELD(18, 4) /* index 746 */, | 1431 | BITFIELD(18, 4) /* index 746 */, |
1391 | TILE_OPC_SEQB_SN, TILE_OPC_SEQH_SN, TILE_OPC_SEQ_SN, TILE_OPC_SHLB_SN, | 1432 | TILEPRO_OPC_SEQB_SN, TILEPRO_OPC_SEQH_SN, TILEPRO_OPC_SEQ_SN, |
1392 | TILE_OPC_SHLH_SN, TILE_OPC_SHL_SN, TILE_OPC_SHRB_SN, TILE_OPC_SHRH_SN, | 1433 | TILEPRO_OPC_SHLB_SN, TILEPRO_OPC_SHLH_SN, TILEPRO_OPC_SHL_SN, |
1393 | TILE_OPC_SHR_SN, TILE_OPC_SLTB_SN, TILE_OPC_SLTB_U_SN, TILE_OPC_SLTEB_SN, | 1434 | TILEPRO_OPC_SHRB_SN, TILEPRO_OPC_SHRH_SN, TILEPRO_OPC_SHR_SN, |
1394 | TILE_OPC_SLTEB_U_SN, TILE_OPC_SLTEH_SN, TILE_OPC_SLTEH_U_SN, | 1435 | TILEPRO_OPC_SLTB_SN, TILEPRO_OPC_SLTB_U_SN, TILEPRO_OPC_SLTEB_SN, |
1395 | TILE_OPC_SLTE_SN, | 1436 | TILEPRO_OPC_SLTEB_U_SN, TILEPRO_OPC_SLTEH_SN, TILEPRO_OPC_SLTEH_U_SN, |
1437 | TILEPRO_OPC_SLTE_SN, | ||
1396 | BITFIELD(18, 4) /* index 763 */, | 1438 | BITFIELD(18, 4) /* index 763 */, |
1397 | TILE_OPC_SLTE_U_SN, TILE_OPC_SLTH_SN, TILE_OPC_SLTH_U_SN, TILE_OPC_SLT_SN, | 1439 | TILEPRO_OPC_SLTE_U_SN, TILEPRO_OPC_SLTH_SN, TILEPRO_OPC_SLTH_U_SN, |
1398 | TILE_OPC_SLT_U_SN, TILE_OPC_SNEB_SN, TILE_OPC_SNEH_SN, TILE_OPC_SNE_SN, | 1440 | TILEPRO_OPC_SLT_SN, TILEPRO_OPC_SLT_U_SN, TILEPRO_OPC_SNEB_SN, |
1399 | TILE_OPC_SRAB_SN, TILE_OPC_SRAH_SN, TILE_OPC_SRA_SN, TILE_OPC_SUBB_SN, | 1441 | TILEPRO_OPC_SNEH_SN, TILEPRO_OPC_SNE_SN, TILEPRO_OPC_SRAB_SN, |
1400 | TILE_OPC_SUBH_SN, TILE_OPC_SUB_SN, TILE_OPC_XOR_SN, TILE_OPC_DWORD_ALIGN_SN, | 1442 | TILEPRO_OPC_SRAH_SN, TILEPRO_OPC_SRA_SN, TILEPRO_OPC_SUBB_SN, |
1443 | TILEPRO_OPC_SUBH_SN, TILEPRO_OPC_SUB_SN, TILEPRO_OPC_XOR_SN, | ||
1444 | TILEPRO_OPC_DWORD_ALIGN_SN, | ||
1401 | BITFIELD(18, 3) /* index 780 */, | 1445 | BITFIELD(18, 3) /* index 780 */, |
1402 | CHILD(789), CHILD(792), CHILD(795), CHILD(798), CHILD(801), CHILD(804), | 1446 | CHILD(789), CHILD(792), CHILD(795), CHILD(798), CHILD(801), CHILD(804), |
1403 | CHILD(807), CHILD(810), | 1447 | CHILD(807), CHILD(810), |
1404 | BITFIELD(21, 1) /* index 789 */, | 1448 | BITFIELD(21, 1) /* index 789 */, |
1405 | TILE_OPC_ADDS_SN, TILE_OPC_NONE, | 1449 | TILEPRO_OPC_ADDS_SN, TILEPRO_OPC_NONE, |
1406 | BITFIELD(21, 1) /* index 792 */, | 1450 | BITFIELD(21, 1) /* index 792 */, |
1407 | TILE_OPC_SUBS_SN, TILE_OPC_NONE, | 1451 | TILEPRO_OPC_SUBS_SN, TILEPRO_OPC_NONE, |
1408 | BITFIELD(21, 1) /* index 795 */, | 1452 | BITFIELD(21, 1) /* index 795 */, |
1409 | TILE_OPC_ADDBS_U_SN, TILE_OPC_NONE, | 1453 | TILEPRO_OPC_ADDBS_U_SN, TILEPRO_OPC_NONE, |
1410 | BITFIELD(21, 1) /* index 798 */, | 1454 | BITFIELD(21, 1) /* index 798 */, |
1411 | TILE_OPC_ADDHS_SN, TILE_OPC_NONE, | 1455 | TILEPRO_OPC_ADDHS_SN, TILEPRO_OPC_NONE, |
1412 | BITFIELD(21, 1) /* index 801 */, | 1456 | BITFIELD(21, 1) /* index 801 */, |
1413 | TILE_OPC_SUBBS_U_SN, TILE_OPC_NONE, | 1457 | TILEPRO_OPC_SUBBS_U_SN, TILEPRO_OPC_NONE, |
1414 | BITFIELD(21, 1) /* index 804 */, | 1458 | BITFIELD(21, 1) /* index 804 */, |
1415 | TILE_OPC_SUBHS_SN, TILE_OPC_NONE, | 1459 | TILEPRO_OPC_SUBHS_SN, TILEPRO_OPC_NONE, |
1416 | BITFIELD(21, 1) /* index 807 */, | 1460 | BITFIELD(21, 1) /* index 807 */, |
1417 | TILE_OPC_PACKHS_SN, TILE_OPC_NONE, | 1461 | TILEPRO_OPC_PACKHS_SN, TILEPRO_OPC_NONE, |
1418 | BITFIELD(21, 1) /* index 810 */, | 1462 | BITFIELD(21, 1) /* index 810 */, |
1419 | TILE_OPC_PACKBS_U_SN, TILE_OPC_NONE, | 1463 | TILEPRO_OPC_PACKBS_U_SN, TILEPRO_OPC_NONE, |
1420 | BITFIELD(6, 2) /* index 813 */, | 1464 | BITFIELD(6, 2) /* index 813 */, |
1421 | TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(818), | 1465 | TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, |
1466 | CHILD(818), | ||
1422 | BITFIELD(8, 2) /* index 818 */, | 1467 | BITFIELD(8, 2) /* index 818 */, |
1423 | TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(823), | 1468 | TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, |
1469 | CHILD(823), | ||
1424 | BITFIELD(10, 2) /* index 823 */, | 1470 | BITFIELD(10, 2) /* index 823 */, |
1425 | TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_MOVELI_SN, | 1471 | TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, |
1472 | TILEPRO_OPC_MOVELI_SN, | ||
1426 | BITFIELD(6, 2) /* index 828 */, | 1473 | BITFIELD(6, 2) /* index 828 */, |
1427 | TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(833), | 1474 | TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(833), |
1428 | BITFIELD(8, 2) /* index 833 */, | 1475 | BITFIELD(8, 2) /* index 833 */, |
1429 | TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(838), | 1476 | TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(838), |
1430 | BITFIELD(10, 2) /* index 838 */, | 1477 | BITFIELD(10, 2) /* index 838 */, |
1431 | TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_MOVELI, | 1478 | TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_MOVELI, |
1432 | BITFIELD(0, 2) /* index 843 */, | 1479 | BITFIELD(0, 2) /* index 843 */, |
1433 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(848), | 1480 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(848), |
1434 | BITFIELD(2, 2) /* index 848 */, | 1481 | BITFIELD(2, 2) /* index 848 */, |
1435 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(853), | 1482 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(853), |
1436 | BITFIELD(4, 2) /* index 853 */, | 1483 | BITFIELD(4, 2) /* index 853 */, |
1437 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(858), | 1484 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(858), |
1438 | BITFIELD(6, 2) /* index 858 */, | 1485 | BITFIELD(6, 2) /* index 858 */, |
1439 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(863), | 1486 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(863), |
1440 | BITFIELD(8, 2) /* index 863 */, | 1487 | BITFIELD(8, 2) /* index 863 */, |
1441 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(868), | 1488 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(868), |
1442 | BITFIELD(10, 2) /* index 868 */, | 1489 | BITFIELD(10, 2) /* index 868 */, |
1443 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_INFOL, | 1490 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_INFOL, |
1444 | BITFIELD(20, 2) /* index 873 */, | 1491 | BITFIELD(20, 2) /* index 873 */, |
1445 | TILE_OPC_NONE, TILE_OPC_ADDIB, TILE_OPC_ADDIH, TILE_OPC_ADDI, | 1492 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB, TILEPRO_OPC_ADDIH, TILEPRO_OPC_ADDI, |
1446 | BITFIELD(20, 2) /* index 878 */, | 1493 | BITFIELD(20, 2) /* index 878 */, |
1447 | TILE_OPC_MAXIB_U, TILE_OPC_MAXIH, TILE_OPC_MINIB_U, TILE_OPC_MINIH, | 1494 | TILEPRO_OPC_MAXIB_U, TILEPRO_OPC_MAXIH, TILEPRO_OPC_MINIB_U, |
1495 | TILEPRO_OPC_MINIH, | ||
1448 | BITFIELD(20, 2) /* index 883 */, | 1496 | BITFIELD(20, 2) /* index 883 */, |
1449 | CHILD(888), TILE_OPC_SEQIB, TILE_OPC_SEQIH, TILE_OPC_SEQI, | 1497 | CHILD(888), TILEPRO_OPC_SEQIB, TILEPRO_OPC_SEQIH, TILEPRO_OPC_SEQI, |
1450 | BITFIELD(6, 2) /* index 888 */, | 1498 | BITFIELD(6, 2) /* index 888 */, |
1451 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(893), | 1499 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(893), |
1452 | BITFIELD(8, 2) /* index 893 */, | 1500 | BITFIELD(8, 2) /* index 893 */, |
1453 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(898), | 1501 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(898), |
1454 | BITFIELD(10, 2) /* index 898 */, | 1502 | BITFIELD(10, 2) /* index 898 */, |
1455 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, | 1503 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, |
1456 | BITFIELD(20, 2) /* index 903 */, | 1504 | BITFIELD(20, 2) /* index 903 */, |
1457 | TILE_OPC_SLTIB, TILE_OPC_SLTIB_U, TILE_OPC_SLTIH, TILE_OPC_SLTIH_U, | 1505 | TILEPRO_OPC_SLTIB, TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH, |
1506 | TILEPRO_OPC_SLTIH_U, | ||
1458 | BITFIELD(20, 2) /* index 908 */, | 1507 | BITFIELD(20, 2) /* index 908 */, |
1459 | TILE_OPC_SLTI, TILE_OPC_SLTI_U, TILE_OPC_NONE, TILE_OPC_NONE, | 1508 | TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1460 | BITFIELD(20, 2) /* index 913 */, | 1509 | BITFIELD(20, 2) /* index 913 */, |
1461 | TILE_OPC_NONE, TILE_OPC_ADDIB_SN, TILE_OPC_ADDIH_SN, TILE_OPC_ADDI_SN, | 1510 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN, |
1511 | TILEPRO_OPC_ADDI_SN, | ||
1462 | BITFIELD(20, 2) /* index 918 */, | 1512 | BITFIELD(20, 2) /* index 918 */, |
1463 | TILE_OPC_MAXIB_U_SN, TILE_OPC_MAXIH_SN, TILE_OPC_MINIB_U_SN, | 1513 | TILEPRO_OPC_MAXIB_U_SN, TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MINIB_U_SN, |
1464 | TILE_OPC_MINIH_SN, | 1514 | TILEPRO_OPC_MINIH_SN, |
1465 | BITFIELD(20, 2) /* index 923 */, | 1515 | BITFIELD(20, 2) /* index 923 */, |
1466 | CHILD(928), TILE_OPC_SEQIB_SN, TILE_OPC_SEQIH_SN, TILE_OPC_SEQI_SN, | 1516 | CHILD(928), TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN, |
1467 | BITFIELD(6, 2) /* index 928 */, | 1517 | BITFIELD(6, 2) /* index 928 */, |
1468 | TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(933), | 1518 | TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(933), |
1469 | BITFIELD(8, 2) /* index 933 */, | 1519 | BITFIELD(8, 2) /* index 933 */, |
1470 | TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(938), | 1520 | TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(938), |
1471 | BITFIELD(10, 2) /* index 938 */, | 1521 | BITFIELD(10, 2) /* index 938 */, |
1472 | TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_MOVEI_SN, | 1522 | TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, |
1523 | TILEPRO_OPC_MOVEI_SN, | ||
1473 | BITFIELD(20, 2) /* index 943 */, | 1524 | BITFIELD(20, 2) /* index 943 */, |
1474 | TILE_OPC_SLTIB_SN, TILE_OPC_SLTIB_U_SN, TILE_OPC_SLTIH_SN, | 1525 | TILEPRO_OPC_SLTIB_SN, TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN, |
1475 | TILE_OPC_SLTIH_U_SN, | 1526 | TILEPRO_OPC_SLTIH_U_SN, |
1476 | BITFIELD(20, 2) /* index 948 */, | 1527 | BITFIELD(20, 2) /* index 948 */, |
1477 | TILE_OPC_SLTI_SN, TILE_OPC_SLTI_U_SN, TILE_OPC_NONE, TILE_OPC_NONE, | 1528 | TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_NONE, |
1529 | TILEPRO_OPC_NONE, | ||
1478 | BITFIELD(20, 2) /* index 953 */, | 1530 | BITFIELD(20, 2) /* index 953 */, |
1479 | TILE_OPC_NONE, CHILD(958), TILE_OPC_XORI, TILE_OPC_NONE, | 1531 | TILEPRO_OPC_NONE, CHILD(958), TILEPRO_OPC_XORI, TILEPRO_OPC_NONE, |
1480 | BITFIELD(0, 2) /* index 958 */, | 1532 | BITFIELD(0, 2) /* index 958 */, |
1481 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(963), | 1533 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(963), |
1482 | BITFIELD(2, 2) /* index 963 */, | 1534 | BITFIELD(2, 2) /* index 963 */, |
1483 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(968), | 1535 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(968), |
1484 | BITFIELD(4, 2) /* index 968 */, | 1536 | BITFIELD(4, 2) /* index 968 */, |
1485 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(973), | 1537 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(973), |
1486 | BITFIELD(6, 2) /* index 973 */, | 1538 | BITFIELD(6, 2) /* index 973 */, |
1487 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(978), | 1539 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(978), |
1488 | BITFIELD(8, 2) /* index 978 */, | 1540 | BITFIELD(8, 2) /* index 978 */, |
1489 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(983), | 1541 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(983), |
1490 | BITFIELD(10, 2) /* index 983 */, | 1542 | BITFIELD(10, 2) /* index 983 */, |
1491 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, | 1543 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, |
1492 | BITFIELD(20, 2) /* index 988 */, | 1544 | BITFIELD(20, 2) /* index 988 */, |
1493 | TILE_OPC_NONE, TILE_OPC_ANDI_SN, TILE_OPC_XORI_SN, TILE_OPC_NONE, | 1545 | TILEPRO_OPC_NONE, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_XORI_SN, |
1546 | TILEPRO_OPC_NONE, | ||
1494 | BITFIELD(17, 5) /* index 993 */, | 1547 | BITFIELD(17, 5) /* index 993 */, |
1495 | TILE_OPC_NONE, TILE_OPC_RLI, TILE_OPC_SHLIB, TILE_OPC_SHLIH, TILE_OPC_SHLI, | 1548 | TILEPRO_OPC_NONE, TILEPRO_OPC_RLI, TILEPRO_OPC_SHLIB, TILEPRO_OPC_SHLIH, |
1496 | TILE_OPC_SHRIB, TILE_OPC_SHRIH, TILE_OPC_SHRI, TILE_OPC_SRAIB, | 1549 | TILEPRO_OPC_SHLI, TILEPRO_OPC_SHRIB, TILEPRO_OPC_SHRIH, TILEPRO_OPC_SHRI, |
1497 | TILE_OPC_SRAIH, TILE_OPC_SRAI, CHILD(1026), TILE_OPC_NONE, TILE_OPC_NONE, | 1550 | TILEPRO_OPC_SRAIB, TILEPRO_OPC_SRAIH, TILEPRO_OPC_SRAI, CHILD(1026), |
1498 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1551 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1499 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1552 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1500 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1553 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1501 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1554 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1555 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1502 | BITFIELD(12, 4) /* index 1026 */, | 1556 | BITFIELD(12, 4) /* index 1026 */, |
1503 | TILE_OPC_NONE, CHILD(1043), CHILD(1046), CHILD(1049), CHILD(1052), | 1557 | TILEPRO_OPC_NONE, CHILD(1043), CHILD(1046), CHILD(1049), CHILD(1052), |
1504 | CHILD(1055), CHILD(1058), CHILD(1061), CHILD(1064), CHILD(1067), | 1558 | CHILD(1055), CHILD(1058), CHILD(1061), CHILD(1064), CHILD(1067), |
1505 | CHILD(1070), CHILD(1073), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1559 | CHILD(1070), CHILD(1073), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1506 | TILE_OPC_NONE, | 1560 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1507 | BITFIELD(16, 1) /* index 1043 */, | 1561 | BITFIELD(16, 1) /* index 1043 */, |
1508 | TILE_OPC_BITX, TILE_OPC_NONE, | 1562 | TILEPRO_OPC_BITX, TILEPRO_OPC_NONE, |
1509 | BITFIELD(16, 1) /* index 1046 */, | 1563 | BITFIELD(16, 1) /* index 1046 */, |
1510 | TILE_OPC_BYTEX, TILE_OPC_NONE, | 1564 | TILEPRO_OPC_BYTEX, TILEPRO_OPC_NONE, |
1511 | BITFIELD(16, 1) /* index 1049 */, | 1565 | BITFIELD(16, 1) /* index 1049 */, |
1512 | TILE_OPC_CLZ, TILE_OPC_NONE, | 1566 | TILEPRO_OPC_CLZ, TILEPRO_OPC_NONE, |
1513 | BITFIELD(16, 1) /* index 1052 */, | 1567 | BITFIELD(16, 1) /* index 1052 */, |
1514 | TILE_OPC_CTZ, TILE_OPC_NONE, | 1568 | TILEPRO_OPC_CTZ, TILEPRO_OPC_NONE, |
1515 | BITFIELD(16, 1) /* index 1055 */, | 1569 | BITFIELD(16, 1) /* index 1055 */, |
1516 | TILE_OPC_FNOP, TILE_OPC_NONE, | 1570 | TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE, |
1517 | BITFIELD(16, 1) /* index 1058 */, | 1571 | BITFIELD(16, 1) /* index 1058 */, |
1518 | TILE_OPC_NOP, TILE_OPC_NONE, | 1572 | TILEPRO_OPC_NOP, TILEPRO_OPC_NONE, |
1519 | BITFIELD(16, 1) /* index 1061 */, | 1573 | BITFIELD(16, 1) /* index 1061 */, |
1520 | TILE_OPC_PCNT, TILE_OPC_NONE, | 1574 | TILEPRO_OPC_PCNT, TILEPRO_OPC_NONE, |
1521 | BITFIELD(16, 1) /* index 1064 */, | 1575 | BITFIELD(16, 1) /* index 1064 */, |
1522 | TILE_OPC_TBLIDXB0, TILE_OPC_NONE, | 1576 | TILEPRO_OPC_TBLIDXB0, TILEPRO_OPC_NONE, |
1523 | BITFIELD(16, 1) /* index 1067 */, | 1577 | BITFIELD(16, 1) /* index 1067 */, |
1524 | TILE_OPC_TBLIDXB1, TILE_OPC_NONE, | 1578 | TILEPRO_OPC_TBLIDXB1, TILEPRO_OPC_NONE, |
1525 | BITFIELD(16, 1) /* index 1070 */, | 1579 | BITFIELD(16, 1) /* index 1070 */, |
1526 | TILE_OPC_TBLIDXB2, TILE_OPC_NONE, | 1580 | TILEPRO_OPC_TBLIDXB2, TILEPRO_OPC_NONE, |
1527 | BITFIELD(16, 1) /* index 1073 */, | 1581 | BITFIELD(16, 1) /* index 1073 */, |
1528 | TILE_OPC_TBLIDXB3, TILE_OPC_NONE, | 1582 | TILEPRO_OPC_TBLIDXB3, TILEPRO_OPC_NONE, |
1529 | BITFIELD(17, 5) /* index 1076 */, | 1583 | BITFIELD(17, 5) /* index 1076 */, |
1530 | TILE_OPC_NONE, TILE_OPC_RLI_SN, TILE_OPC_SHLIB_SN, TILE_OPC_SHLIH_SN, | 1584 | TILEPRO_OPC_NONE, TILEPRO_OPC_RLI_SN, TILEPRO_OPC_SHLIB_SN, |
1531 | TILE_OPC_SHLI_SN, TILE_OPC_SHRIB_SN, TILE_OPC_SHRIH_SN, TILE_OPC_SHRI_SN, | 1585 | TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_SHRIB_SN, |
1532 | TILE_OPC_SRAIB_SN, TILE_OPC_SRAIH_SN, TILE_OPC_SRAI_SN, CHILD(1109), | 1586 | TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_SRAIB_SN, |
1533 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1587 | TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_SRAI_SN, CHILD(1109), TILEPRO_OPC_NONE, |
1534 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1588 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1535 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1589 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1536 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1590 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1591 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1592 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1537 | BITFIELD(12, 4) /* index 1109 */, | 1593 | BITFIELD(12, 4) /* index 1109 */, |
1538 | TILE_OPC_NONE, CHILD(1126), CHILD(1129), CHILD(1132), CHILD(1135), | 1594 | TILEPRO_OPC_NONE, CHILD(1126), CHILD(1129), CHILD(1132), CHILD(1135), |
1539 | CHILD(1055), CHILD(1058), CHILD(1138), CHILD(1141), CHILD(1144), | 1595 | CHILD(1055), CHILD(1058), CHILD(1138), CHILD(1141), CHILD(1144), |
1540 | CHILD(1147), CHILD(1150), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1596 | CHILD(1147), CHILD(1150), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1541 | TILE_OPC_NONE, | 1597 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1542 | BITFIELD(16, 1) /* index 1126 */, | 1598 | BITFIELD(16, 1) /* index 1126 */, |
1543 | TILE_OPC_BITX_SN, TILE_OPC_NONE, | 1599 | TILEPRO_OPC_BITX_SN, TILEPRO_OPC_NONE, |
1544 | BITFIELD(16, 1) /* index 1129 */, | 1600 | BITFIELD(16, 1) /* index 1129 */, |
1545 | TILE_OPC_BYTEX_SN, TILE_OPC_NONE, | 1601 | TILEPRO_OPC_BYTEX_SN, TILEPRO_OPC_NONE, |
1546 | BITFIELD(16, 1) /* index 1132 */, | 1602 | BITFIELD(16, 1) /* index 1132 */, |
1547 | TILE_OPC_CLZ_SN, TILE_OPC_NONE, | 1603 | TILEPRO_OPC_CLZ_SN, TILEPRO_OPC_NONE, |
1548 | BITFIELD(16, 1) /* index 1135 */, | 1604 | BITFIELD(16, 1) /* index 1135 */, |
1549 | TILE_OPC_CTZ_SN, TILE_OPC_NONE, | 1605 | TILEPRO_OPC_CTZ_SN, TILEPRO_OPC_NONE, |
1550 | BITFIELD(16, 1) /* index 1138 */, | 1606 | BITFIELD(16, 1) /* index 1138 */, |
1551 | TILE_OPC_PCNT_SN, TILE_OPC_NONE, | 1607 | TILEPRO_OPC_PCNT_SN, TILEPRO_OPC_NONE, |
1552 | BITFIELD(16, 1) /* index 1141 */, | 1608 | BITFIELD(16, 1) /* index 1141 */, |
1553 | TILE_OPC_TBLIDXB0_SN, TILE_OPC_NONE, | 1609 | TILEPRO_OPC_TBLIDXB0_SN, TILEPRO_OPC_NONE, |
1554 | BITFIELD(16, 1) /* index 1144 */, | 1610 | BITFIELD(16, 1) /* index 1144 */, |
1555 | TILE_OPC_TBLIDXB1_SN, TILE_OPC_NONE, | 1611 | TILEPRO_OPC_TBLIDXB1_SN, TILEPRO_OPC_NONE, |
1556 | BITFIELD(16, 1) /* index 1147 */, | 1612 | BITFIELD(16, 1) /* index 1147 */, |
1557 | TILE_OPC_TBLIDXB2_SN, TILE_OPC_NONE, | 1613 | TILEPRO_OPC_TBLIDXB2_SN, TILEPRO_OPC_NONE, |
1558 | BITFIELD(16, 1) /* index 1150 */, | 1614 | BITFIELD(16, 1) /* index 1150 */, |
1559 | TILE_OPC_TBLIDXB3_SN, TILE_OPC_NONE, | 1615 | TILEPRO_OPC_TBLIDXB3_SN, TILEPRO_OPC_NONE, |
1560 | }; | 1616 | }; |
1561 | 1617 | ||
1562 | static const unsigned short decode_X1_fsm[1540] = | 1618 | static const unsigned short decode_X1_fsm[1540] = |
1563 | { | 1619 | { |
1564 | BITFIELD(54, 9) /* index 0 */, | 1620 | BITFIELD(54, 9) /* index 0 */, |
1565 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1621 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1566 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1622 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1567 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1623 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1568 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1624 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1569 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1625 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1570 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1626 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1571 | TILE_OPC_NONE, TILE_OPC_NONE, CHILD(513), CHILD(561), CHILD(594), | 1627 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1572 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1628 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1573 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1629 | CHILD(513), CHILD(561), CHILD(594), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1574 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(641), CHILD(689), | 1630 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1575 | CHILD(722), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1631 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1576 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1632 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(641), |
1577 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(766), | 1633 | CHILD(689), CHILD(722), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1634 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1635 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1636 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(766), | ||
1578 | CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), | 1637 | CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), |
1579 | CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), | 1638 | CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), |
1580 | CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), | 1639 | CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), CHILD(766), |
@@ -1596,594 +1655,641 @@ static const unsigned short decode_X1_fsm[1540] = | |||
1596 | CHILD(826), CHILD(826), CHILD(826), CHILD(843), CHILD(843), CHILD(843), | 1655 | CHILD(826), CHILD(826), CHILD(826), CHILD(843), CHILD(843), CHILD(843), |
1597 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1656 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1598 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), | 1657 | CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), CHILD(843), |
1599 | CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932), TILE_OPC_NONE, | 1658 | CHILD(843), CHILD(860), CHILD(899), CHILD(923), CHILD(932), |
1600 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1659 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1601 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1660 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1602 | TILE_OPC_NONE, CHILD(941), CHILD(950), CHILD(974), CHILD(983), | 1661 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1603 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1662 | CHILD(941), CHILD(950), CHILD(974), CHILD(983), TILEPRO_OPC_NONE, |
1604 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1663 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1605 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1664 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1606 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1665 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_MM, |
1607 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1666 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1608 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1667 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1609 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1668 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1610 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, | 1669 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1611 | TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, TILE_OPC_MM, CHILD(992), | 1670 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1612 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1671 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1613 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1672 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, |
1614 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1673 | TILEPRO_OPC_MM, TILEPRO_OPC_MM, TILEPRO_OPC_MM, CHILD(992), |
1615 | CHILD(1334), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1674 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1616 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1675 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1617 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1676 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1618 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1677 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, CHILD(1334), |
1619 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1678 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1620 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1679 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1621 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1680 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1622 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1681 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1623 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1682 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1624 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_J, TILE_OPC_J, | 1683 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1625 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1684 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1626 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1685 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1627 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1686 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1628 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1687 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1629 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1688 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1630 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1689 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_J, |
1631 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1690 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1632 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1691 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1633 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1692 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1634 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, TILE_OPC_J, | 1693 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1635 | TILE_OPC_J, TILE_OPC_J, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1694 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1636 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1695 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1637 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1696 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1638 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1697 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1639 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1698 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1640 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1699 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1641 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1700 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1642 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1701 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, |
1643 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1702 | TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_J, TILEPRO_OPC_JAL, |
1644 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1703 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1645 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1704 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1646 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1705 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1647 | TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, TILE_OPC_JAL, | 1706 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1648 | TILE_OPC_JAL, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1707 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1649 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1708 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1650 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1709 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1651 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1710 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1652 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1711 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1653 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1712 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1654 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1713 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1655 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1714 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1656 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1715 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1657 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1716 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1658 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1717 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, |
1659 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1718 | TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_JAL, TILEPRO_OPC_NONE, |
1660 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1719 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1720 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1721 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1722 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1723 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1724 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1725 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1726 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1727 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1728 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1729 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1730 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1731 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1732 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1733 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1734 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1661 | BITFIELD(49, 5) /* index 513 */, | 1735 | BITFIELD(49, 5) /* index 513 */, |
1662 | TILE_OPC_NONE, TILE_OPC_ADDB, TILE_OPC_ADDH, TILE_OPC_ADD, TILE_OPC_AND, | 1736 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB, TILEPRO_OPC_ADDH, TILEPRO_OPC_ADD, |
1663 | TILE_OPC_INTHB, TILE_OPC_INTHH, TILE_OPC_INTLB, TILE_OPC_INTLH, | 1737 | TILEPRO_OPC_AND, TILEPRO_OPC_INTHB, TILEPRO_OPC_INTHH, TILEPRO_OPC_INTLB, |
1664 | TILE_OPC_JALRP, TILE_OPC_JALR, TILE_OPC_JRP, TILE_OPC_JR, TILE_OPC_LNK, | 1738 | TILEPRO_OPC_INTLH, TILEPRO_OPC_JALRP, TILEPRO_OPC_JALR, TILEPRO_OPC_JRP, |
1665 | TILE_OPC_MAXB_U, TILE_OPC_MAXH, TILE_OPC_MINB_U, TILE_OPC_MINH, | 1739 | TILEPRO_OPC_JR, TILEPRO_OPC_LNK, TILEPRO_OPC_MAXB_U, TILEPRO_OPC_MAXH, |
1666 | TILE_OPC_MNZB, TILE_OPC_MNZH, TILE_OPC_MNZ, TILE_OPC_MZB, TILE_OPC_MZH, | 1740 | TILEPRO_OPC_MINB_U, TILEPRO_OPC_MINH, TILEPRO_OPC_MNZB, TILEPRO_OPC_MNZH, |
1667 | TILE_OPC_MZ, TILE_OPC_NOR, CHILD(546), TILE_OPC_PACKHB, TILE_OPC_PACKLB, | 1741 | TILEPRO_OPC_MNZ, TILEPRO_OPC_MZB, TILEPRO_OPC_MZH, TILEPRO_OPC_MZ, |
1668 | TILE_OPC_RL, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_S3A, | 1742 | TILEPRO_OPC_NOR, CHILD(546), TILEPRO_OPC_PACKHB, TILEPRO_OPC_PACKLB, |
1743 | TILEPRO_OPC_RL, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_S3A, | ||
1669 | BITFIELD(43, 2) /* index 546 */, | 1744 | BITFIELD(43, 2) /* index 546 */, |
1670 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(551), | 1745 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(551), |
1671 | BITFIELD(45, 2) /* index 551 */, | 1746 | BITFIELD(45, 2) /* index 551 */, |
1672 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(556), | 1747 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(556), |
1673 | BITFIELD(47, 2) /* index 556 */, | 1748 | BITFIELD(47, 2) /* index 556 */, |
1674 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, | 1749 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, |
1675 | BITFIELD(49, 5) /* index 561 */, | 1750 | BITFIELD(49, 5) /* index 561 */, |
1676 | TILE_OPC_SB, TILE_OPC_SEQB, TILE_OPC_SEQH, TILE_OPC_SEQ, TILE_OPC_SHLB, | 1751 | TILEPRO_OPC_SB, TILEPRO_OPC_SEQB, TILEPRO_OPC_SEQH, TILEPRO_OPC_SEQ, |
1677 | TILE_OPC_SHLH, TILE_OPC_SHL, TILE_OPC_SHRB, TILE_OPC_SHRH, TILE_OPC_SHR, | 1752 | TILEPRO_OPC_SHLB, TILEPRO_OPC_SHLH, TILEPRO_OPC_SHL, TILEPRO_OPC_SHRB, |
1678 | TILE_OPC_SH, TILE_OPC_SLTB, TILE_OPC_SLTB_U, TILE_OPC_SLTEB, | 1753 | TILEPRO_OPC_SHRH, TILEPRO_OPC_SHR, TILEPRO_OPC_SH, TILEPRO_OPC_SLTB, |
1679 | TILE_OPC_SLTEB_U, TILE_OPC_SLTEH, TILE_OPC_SLTEH_U, TILE_OPC_SLTE, | 1754 | TILEPRO_OPC_SLTB_U, TILEPRO_OPC_SLTEB, TILEPRO_OPC_SLTEB_U, |
1680 | TILE_OPC_SLTE_U, TILE_OPC_SLTH, TILE_OPC_SLTH_U, TILE_OPC_SLT, | 1755 | TILEPRO_OPC_SLTEH, TILEPRO_OPC_SLTEH_U, TILEPRO_OPC_SLTE, |
1681 | TILE_OPC_SLT_U, TILE_OPC_SNEB, TILE_OPC_SNEH, TILE_OPC_SNE, TILE_OPC_SRAB, | 1756 | TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLTH, TILEPRO_OPC_SLTH_U, TILEPRO_OPC_SLT, |
1682 | TILE_OPC_SRAH, TILE_OPC_SRA, TILE_OPC_SUBB, TILE_OPC_SUBH, TILE_OPC_SUB, | 1757 | TILEPRO_OPC_SLT_U, TILEPRO_OPC_SNEB, TILEPRO_OPC_SNEH, TILEPRO_OPC_SNE, |
1758 | TILEPRO_OPC_SRAB, TILEPRO_OPC_SRAH, TILEPRO_OPC_SRA, TILEPRO_OPC_SUBB, | ||
1759 | TILEPRO_OPC_SUBH, TILEPRO_OPC_SUB, | ||
1683 | BITFIELD(49, 4) /* index 594 */, | 1760 | BITFIELD(49, 4) /* index 594 */, |
1684 | CHILD(611), CHILD(614), CHILD(617), CHILD(620), CHILD(623), CHILD(626), | 1761 | CHILD(611), CHILD(614), CHILD(617), CHILD(620), CHILD(623), CHILD(626), |
1685 | CHILD(629), CHILD(632), CHILD(635), CHILD(638), TILE_OPC_NONE, | 1762 | CHILD(629), CHILD(632), CHILD(635), CHILD(638), TILEPRO_OPC_NONE, |
1686 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1763 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1764 | TILEPRO_OPC_NONE, | ||
1687 | BITFIELD(53, 1) /* index 611 */, | 1765 | BITFIELD(53, 1) /* index 611 */, |
1688 | TILE_OPC_SW, TILE_OPC_NONE, | 1766 | TILEPRO_OPC_SW, TILEPRO_OPC_NONE, |
1689 | BITFIELD(53, 1) /* index 614 */, | 1767 | BITFIELD(53, 1) /* index 614 */, |
1690 | TILE_OPC_XOR, TILE_OPC_NONE, | 1768 | TILEPRO_OPC_XOR, TILEPRO_OPC_NONE, |
1691 | BITFIELD(53, 1) /* index 617 */, | 1769 | BITFIELD(53, 1) /* index 617 */, |
1692 | TILE_OPC_ADDS, TILE_OPC_NONE, | 1770 | TILEPRO_OPC_ADDS, TILEPRO_OPC_NONE, |
1693 | BITFIELD(53, 1) /* index 620 */, | 1771 | BITFIELD(53, 1) /* index 620 */, |
1694 | TILE_OPC_SUBS, TILE_OPC_NONE, | 1772 | TILEPRO_OPC_SUBS, TILEPRO_OPC_NONE, |
1695 | BITFIELD(53, 1) /* index 623 */, | 1773 | BITFIELD(53, 1) /* index 623 */, |
1696 | TILE_OPC_ADDBS_U, TILE_OPC_NONE, | 1774 | TILEPRO_OPC_ADDBS_U, TILEPRO_OPC_NONE, |
1697 | BITFIELD(53, 1) /* index 626 */, | 1775 | BITFIELD(53, 1) /* index 626 */, |
1698 | TILE_OPC_ADDHS, TILE_OPC_NONE, | 1776 | TILEPRO_OPC_ADDHS, TILEPRO_OPC_NONE, |
1699 | BITFIELD(53, 1) /* index 629 */, | 1777 | BITFIELD(53, 1) /* index 629 */, |
1700 | TILE_OPC_SUBBS_U, TILE_OPC_NONE, | 1778 | TILEPRO_OPC_SUBBS_U, TILEPRO_OPC_NONE, |
1701 | BITFIELD(53, 1) /* index 632 */, | 1779 | BITFIELD(53, 1) /* index 632 */, |
1702 | TILE_OPC_SUBHS, TILE_OPC_NONE, | 1780 | TILEPRO_OPC_SUBHS, TILEPRO_OPC_NONE, |
1703 | BITFIELD(53, 1) /* index 635 */, | 1781 | BITFIELD(53, 1) /* index 635 */, |
1704 | TILE_OPC_PACKHS, TILE_OPC_NONE, | 1782 | TILEPRO_OPC_PACKHS, TILEPRO_OPC_NONE, |
1705 | BITFIELD(53, 1) /* index 638 */, | 1783 | BITFIELD(53, 1) /* index 638 */, |
1706 | TILE_OPC_PACKBS_U, TILE_OPC_NONE, | 1784 | TILEPRO_OPC_PACKBS_U, TILEPRO_OPC_NONE, |
1707 | BITFIELD(49, 5) /* index 641 */, | 1785 | BITFIELD(49, 5) /* index 641 */, |
1708 | TILE_OPC_NONE, TILE_OPC_ADDB_SN, TILE_OPC_ADDH_SN, TILE_OPC_ADD_SN, | 1786 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDB_SN, TILEPRO_OPC_ADDH_SN, |
1709 | TILE_OPC_AND_SN, TILE_OPC_INTHB_SN, TILE_OPC_INTHH_SN, TILE_OPC_INTLB_SN, | 1787 | TILEPRO_OPC_ADD_SN, TILEPRO_OPC_AND_SN, TILEPRO_OPC_INTHB_SN, |
1710 | TILE_OPC_INTLH_SN, TILE_OPC_JALRP, TILE_OPC_JALR, TILE_OPC_JRP, TILE_OPC_JR, | 1788 | TILEPRO_OPC_INTHH_SN, TILEPRO_OPC_INTLB_SN, TILEPRO_OPC_INTLH_SN, |
1711 | TILE_OPC_LNK_SN, TILE_OPC_MAXB_U_SN, TILE_OPC_MAXH_SN, TILE_OPC_MINB_U_SN, | 1789 | TILEPRO_OPC_JALRP, TILEPRO_OPC_JALR, TILEPRO_OPC_JRP, TILEPRO_OPC_JR, |
1712 | TILE_OPC_MINH_SN, TILE_OPC_MNZB_SN, TILE_OPC_MNZH_SN, TILE_OPC_MNZ_SN, | 1790 | TILEPRO_OPC_LNK_SN, TILEPRO_OPC_MAXB_U_SN, TILEPRO_OPC_MAXH_SN, |
1713 | TILE_OPC_MZB_SN, TILE_OPC_MZH_SN, TILE_OPC_MZ_SN, TILE_OPC_NOR_SN, | 1791 | TILEPRO_OPC_MINB_U_SN, TILEPRO_OPC_MINH_SN, TILEPRO_OPC_MNZB_SN, |
1714 | CHILD(674), TILE_OPC_PACKHB_SN, TILE_OPC_PACKLB_SN, TILE_OPC_RL_SN, | 1792 | TILEPRO_OPC_MNZH_SN, TILEPRO_OPC_MNZ_SN, TILEPRO_OPC_MZB_SN, |
1715 | TILE_OPC_S1A_SN, TILE_OPC_S2A_SN, TILE_OPC_S3A_SN, | 1793 | TILEPRO_OPC_MZH_SN, TILEPRO_OPC_MZ_SN, TILEPRO_OPC_NOR_SN, CHILD(674), |
1794 | TILEPRO_OPC_PACKHB_SN, TILEPRO_OPC_PACKLB_SN, TILEPRO_OPC_RL_SN, | ||
1795 | TILEPRO_OPC_S1A_SN, TILEPRO_OPC_S2A_SN, TILEPRO_OPC_S3A_SN, | ||
1716 | BITFIELD(43, 2) /* index 674 */, | 1796 | BITFIELD(43, 2) /* index 674 */, |
1717 | TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(679), | 1797 | TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(679), |
1718 | BITFIELD(45, 2) /* index 679 */, | 1798 | BITFIELD(45, 2) /* index 679 */, |
1719 | TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, CHILD(684), | 1799 | TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, CHILD(684), |
1720 | BITFIELD(47, 2) /* index 684 */, | 1800 | BITFIELD(47, 2) /* index 684 */, |
1721 | TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_OR_SN, TILE_OPC_MOVE_SN, | 1801 | TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, TILEPRO_OPC_OR_SN, |
1802 | TILEPRO_OPC_MOVE_SN, | ||
1722 | BITFIELD(49, 5) /* index 689 */, | 1803 | BITFIELD(49, 5) /* index 689 */, |
1723 | TILE_OPC_SB, TILE_OPC_SEQB_SN, TILE_OPC_SEQH_SN, TILE_OPC_SEQ_SN, | 1804 | TILEPRO_OPC_SB, TILEPRO_OPC_SEQB_SN, TILEPRO_OPC_SEQH_SN, |
1724 | TILE_OPC_SHLB_SN, TILE_OPC_SHLH_SN, TILE_OPC_SHL_SN, TILE_OPC_SHRB_SN, | 1805 | TILEPRO_OPC_SEQ_SN, TILEPRO_OPC_SHLB_SN, TILEPRO_OPC_SHLH_SN, |
1725 | TILE_OPC_SHRH_SN, TILE_OPC_SHR_SN, TILE_OPC_SH, TILE_OPC_SLTB_SN, | 1806 | TILEPRO_OPC_SHL_SN, TILEPRO_OPC_SHRB_SN, TILEPRO_OPC_SHRH_SN, |
1726 | TILE_OPC_SLTB_U_SN, TILE_OPC_SLTEB_SN, TILE_OPC_SLTEB_U_SN, | 1807 | TILEPRO_OPC_SHR_SN, TILEPRO_OPC_SH, TILEPRO_OPC_SLTB_SN, |
1727 | TILE_OPC_SLTEH_SN, TILE_OPC_SLTEH_U_SN, TILE_OPC_SLTE_SN, | 1808 | TILEPRO_OPC_SLTB_U_SN, TILEPRO_OPC_SLTEB_SN, TILEPRO_OPC_SLTEB_U_SN, |
1728 | TILE_OPC_SLTE_U_SN, TILE_OPC_SLTH_SN, TILE_OPC_SLTH_U_SN, TILE_OPC_SLT_SN, | 1809 | TILEPRO_OPC_SLTEH_SN, TILEPRO_OPC_SLTEH_U_SN, TILEPRO_OPC_SLTE_SN, |
1729 | TILE_OPC_SLT_U_SN, TILE_OPC_SNEB_SN, TILE_OPC_SNEH_SN, TILE_OPC_SNE_SN, | 1810 | TILEPRO_OPC_SLTE_U_SN, TILEPRO_OPC_SLTH_SN, TILEPRO_OPC_SLTH_U_SN, |
1730 | TILE_OPC_SRAB_SN, TILE_OPC_SRAH_SN, TILE_OPC_SRA_SN, TILE_OPC_SUBB_SN, | 1811 | TILEPRO_OPC_SLT_SN, TILEPRO_OPC_SLT_U_SN, TILEPRO_OPC_SNEB_SN, |
1731 | TILE_OPC_SUBH_SN, TILE_OPC_SUB_SN, | 1812 | TILEPRO_OPC_SNEH_SN, TILEPRO_OPC_SNE_SN, TILEPRO_OPC_SRAB_SN, |
1813 | TILEPRO_OPC_SRAH_SN, TILEPRO_OPC_SRA_SN, TILEPRO_OPC_SUBB_SN, | ||
1814 | TILEPRO_OPC_SUBH_SN, TILEPRO_OPC_SUB_SN, | ||
1732 | BITFIELD(49, 4) /* index 722 */, | 1815 | BITFIELD(49, 4) /* index 722 */, |
1733 | CHILD(611), CHILD(739), CHILD(742), CHILD(745), CHILD(748), CHILD(751), | 1816 | CHILD(611), CHILD(739), CHILD(742), CHILD(745), CHILD(748), CHILD(751), |
1734 | CHILD(754), CHILD(757), CHILD(760), CHILD(763), TILE_OPC_NONE, | 1817 | CHILD(754), CHILD(757), CHILD(760), CHILD(763), TILEPRO_OPC_NONE, |
1735 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1818 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1819 | TILEPRO_OPC_NONE, | ||
1736 | BITFIELD(53, 1) /* index 739 */, | 1820 | BITFIELD(53, 1) /* index 739 */, |
1737 | TILE_OPC_XOR_SN, TILE_OPC_NONE, | 1821 | TILEPRO_OPC_XOR_SN, TILEPRO_OPC_NONE, |
1738 | BITFIELD(53, 1) /* index 742 */, | 1822 | BITFIELD(53, 1) /* index 742 */, |
1739 | TILE_OPC_ADDS_SN, TILE_OPC_NONE, | 1823 | TILEPRO_OPC_ADDS_SN, TILEPRO_OPC_NONE, |
1740 | BITFIELD(53, 1) /* index 745 */, | 1824 | BITFIELD(53, 1) /* index 745 */, |
1741 | TILE_OPC_SUBS_SN, TILE_OPC_NONE, | 1825 | TILEPRO_OPC_SUBS_SN, TILEPRO_OPC_NONE, |
1742 | BITFIELD(53, 1) /* index 748 */, | 1826 | BITFIELD(53, 1) /* index 748 */, |
1743 | TILE_OPC_ADDBS_U_SN, TILE_OPC_NONE, | 1827 | TILEPRO_OPC_ADDBS_U_SN, TILEPRO_OPC_NONE, |
1744 | BITFIELD(53, 1) /* index 751 */, | 1828 | BITFIELD(53, 1) /* index 751 */, |
1745 | TILE_OPC_ADDHS_SN, TILE_OPC_NONE, | 1829 | TILEPRO_OPC_ADDHS_SN, TILEPRO_OPC_NONE, |
1746 | BITFIELD(53, 1) /* index 754 */, | 1830 | BITFIELD(53, 1) /* index 754 */, |
1747 | TILE_OPC_SUBBS_U_SN, TILE_OPC_NONE, | 1831 | TILEPRO_OPC_SUBBS_U_SN, TILEPRO_OPC_NONE, |
1748 | BITFIELD(53, 1) /* index 757 */, | 1832 | BITFIELD(53, 1) /* index 757 */, |
1749 | TILE_OPC_SUBHS_SN, TILE_OPC_NONE, | 1833 | TILEPRO_OPC_SUBHS_SN, TILEPRO_OPC_NONE, |
1750 | BITFIELD(53, 1) /* index 760 */, | 1834 | BITFIELD(53, 1) /* index 760 */, |
1751 | TILE_OPC_PACKHS_SN, TILE_OPC_NONE, | 1835 | TILEPRO_OPC_PACKHS_SN, TILEPRO_OPC_NONE, |
1752 | BITFIELD(53, 1) /* index 763 */, | 1836 | BITFIELD(53, 1) /* index 763 */, |
1753 | TILE_OPC_PACKBS_U_SN, TILE_OPC_NONE, | 1837 | TILEPRO_OPC_PACKBS_U_SN, TILEPRO_OPC_NONE, |
1754 | BITFIELD(37, 2) /* index 766 */, | 1838 | BITFIELD(37, 2) /* index 766 */, |
1755 | TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(771), | 1839 | TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, |
1840 | CHILD(771), | ||
1756 | BITFIELD(39, 2) /* index 771 */, | 1841 | BITFIELD(39, 2) /* index 771 */, |
1757 | TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, CHILD(776), | 1842 | TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, |
1843 | CHILD(776), | ||
1758 | BITFIELD(41, 2) /* index 776 */, | 1844 | BITFIELD(41, 2) /* index 776 */, |
1759 | TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_ADDLI_SN, TILE_OPC_MOVELI_SN, | 1845 | TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, TILEPRO_OPC_ADDLI_SN, |
1846 | TILEPRO_OPC_MOVELI_SN, | ||
1760 | BITFIELD(37, 2) /* index 781 */, | 1847 | BITFIELD(37, 2) /* index 781 */, |
1761 | TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(786), | 1848 | TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(786), |
1762 | BITFIELD(39, 2) /* index 786 */, | 1849 | BITFIELD(39, 2) /* index 786 */, |
1763 | TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, CHILD(791), | 1850 | TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, CHILD(791), |
1764 | BITFIELD(41, 2) /* index 791 */, | 1851 | BITFIELD(41, 2) /* index 791 */, |
1765 | TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_ADDLI, TILE_OPC_MOVELI, | 1852 | TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_ADDLI, TILEPRO_OPC_MOVELI, |
1766 | BITFIELD(31, 2) /* index 796 */, | 1853 | BITFIELD(31, 2) /* index 796 */, |
1767 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(801), | 1854 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(801), |
1768 | BITFIELD(33, 2) /* index 801 */, | 1855 | BITFIELD(33, 2) /* index 801 */, |
1769 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(806), | 1856 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(806), |
1770 | BITFIELD(35, 2) /* index 806 */, | 1857 | BITFIELD(35, 2) /* index 806 */, |
1771 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(811), | 1858 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(811), |
1772 | BITFIELD(37, 2) /* index 811 */, | 1859 | BITFIELD(37, 2) /* index 811 */, |
1773 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(816), | 1860 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(816), |
1774 | BITFIELD(39, 2) /* index 816 */, | 1861 | BITFIELD(39, 2) /* index 816 */, |
1775 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, CHILD(821), | 1862 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, CHILD(821), |
1776 | BITFIELD(41, 2) /* index 821 */, | 1863 | BITFIELD(41, 2) /* index 821 */, |
1777 | TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_AULI, TILE_OPC_INFOL, | 1864 | TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_AULI, TILEPRO_OPC_INFOL, |
1778 | BITFIELD(31, 4) /* index 826 */, | 1865 | BITFIELD(31, 4) /* index 826 */, |
1779 | TILE_OPC_BZ, TILE_OPC_BZT, TILE_OPC_BNZ, TILE_OPC_BNZT, TILE_OPC_BGZ, | 1866 | TILEPRO_OPC_BZ, TILEPRO_OPC_BZT, TILEPRO_OPC_BNZ, TILEPRO_OPC_BNZT, |
1780 | TILE_OPC_BGZT, TILE_OPC_BGEZ, TILE_OPC_BGEZT, TILE_OPC_BLZ, TILE_OPC_BLZT, | 1867 | TILEPRO_OPC_BGZ, TILEPRO_OPC_BGZT, TILEPRO_OPC_BGEZ, TILEPRO_OPC_BGEZT, |
1781 | TILE_OPC_BLEZ, TILE_OPC_BLEZT, TILE_OPC_BBS, TILE_OPC_BBST, TILE_OPC_BBNS, | 1868 | TILEPRO_OPC_BLZ, TILEPRO_OPC_BLZT, TILEPRO_OPC_BLEZ, TILEPRO_OPC_BLEZT, |
1782 | TILE_OPC_BBNST, | 1869 | TILEPRO_OPC_BBS, TILEPRO_OPC_BBST, TILEPRO_OPC_BBNS, TILEPRO_OPC_BBNST, |
1783 | BITFIELD(31, 4) /* index 843 */, | 1870 | BITFIELD(31, 4) /* index 843 */, |
1784 | TILE_OPC_BZ_SN, TILE_OPC_BZT_SN, TILE_OPC_BNZ_SN, TILE_OPC_BNZT_SN, | 1871 | TILEPRO_OPC_BZ_SN, TILEPRO_OPC_BZT_SN, TILEPRO_OPC_BNZ_SN, |
1785 | TILE_OPC_BGZ_SN, TILE_OPC_BGZT_SN, TILE_OPC_BGEZ_SN, TILE_OPC_BGEZT_SN, | 1872 | TILEPRO_OPC_BNZT_SN, TILEPRO_OPC_BGZ_SN, TILEPRO_OPC_BGZT_SN, |
1786 | TILE_OPC_BLZ_SN, TILE_OPC_BLZT_SN, TILE_OPC_BLEZ_SN, TILE_OPC_BLEZT_SN, | 1873 | TILEPRO_OPC_BGEZ_SN, TILEPRO_OPC_BGEZT_SN, TILEPRO_OPC_BLZ_SN, |
1787 | TILE_OPC_BBS_SN, TILE_OPC_BBST_SN, TILE_OPC_BBNS_SN, TILE_OPC_BBNST_SN, | 1874 | TILEPRO_OPC_BLZT_SN, TILEPRO_OPC_BLEZ_SN, TILEPRO_OPC_BLEZT_SN, |
1875 | TILEPRO_OPC_BBS_SN, TILEPRO_OPC_BBST_SN, TILEPRO_OPC_BBNS_SN, | ||
1876 | TILEPRO_OPC_BBNST_SN, | ||
1788 | BITFIELD(51, 3) /* index 860 */, | 1877 | BITFIELD(51, 3) /* index 860 */, |
1789 | TILE_OPC_NONE, TILE_OPC_ADDIB, TILE_OPC_ADDIH, TILE_OPC_ADDI, CHILD(869), | 1878 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB, TILEPRO_OPC_ADDIH, TILEPRO_OPC_ADDI, |
1790 | TILE_OPC_MAXIB_U, TILE_OPC_MAXIH, TILE_OPC_MFSPR, | 1879 | CHILD(869), TILEPRO_OPC_MAXIB_U, TILEPRO_OPC_MAXIH, TILEPRO_OPC_MFSPR, |
1791 | BITFIELD(31, 2) /* index 869 */, | 1880 | BITFIELD(31, 2) /* index 869 */, |
1792 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(874), | 1881 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(874), |
1793 | BITFIELD(33, 2) /* index 874 */, | 1882 | BITFIELD(33, 2) /* index 874 */, |
1794 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(879), | 1883 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(879), |
1795 | BITFIELD(35, 2) /* index 879 */, | 1884 | BITFIELD(35, 2) /* index 879 */, |
1796 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(884), | 1885 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(884), |
1797 | BITFIELD(37, 2) /* index 884 */, | 1886 | BITFIELD(37, 2) /* index 884 */, |
1798 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(889), | 1887 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(889), |
1799 | BITFIELD(39, 2) /* index 889 */, | 1888 | BITFIELD(39, 2) /* index 889 */, |
1800 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(894), | 1889 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(894), |
1801 | BITFIELD(41, 2) /* index 894 */, | 1890 | BITFIELD(41, 2) /* index 894 */, |
1802 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, | 1891 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, |
1803 | BITFIELD(51, 3) /* index 899 */, | 1892 | BITFIELD(51, 3) /* index 899 */, |
1804 | TILE_OPC_MINIB_U, TILE_OPC_MINIH, TILE_OPC_MTSPR, CHILD(908), | 1893 | TILEPRO_OPC_MINIB_U, TILEPRO_OPC_MINIH, TILEPRO_OPC_MTSPR, CHILD(908), |
1805 | TILE_OPC_SEQIB, TILE_OPC_SEQIH, TILE_OPC_SEQI, TILE_OPC_SLTIB, | 1894 | TILEPRO_OPC_SEQIB, TILEPRO_OPC_SEQIH, TILEPRO_OPC_SEQI, TILEPRO_OPC_SLTIB, |
1806 | BITFIELD(37, 2) /* index 908 */, | 1895 | BITFIELD(37, 2) /* index 908 */, |
1807 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(913), | 1896 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(913), |
1808 | BITFIELD(39, 2) /* index 913 */, | 1897 | BITFIELD(39, 2) /* index 913 */, |
1809 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(918), | 1898 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(918), |
1810 | BITFIELD(41, 2) /* index 918 */, | 1899 | BITFIELD(41, 2) /* index 918 */, |
1811 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, | 1900 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, |
1812 | BITFIELD(51, 3) /* index 923 */, | 1901 | BITFIELD(51, 3) /* index 923 */, |
1813 | TILE_OPC_SLTIB_U, TILE_OPC_SLTIH, TILE_OPC_SLTIH_U, TILE_OPC_SLTI, | 1902 | TILEPRO_OPC_SLTIB_U, TILEPRO_OPC_SLTIH, TILEPRO_OPC_SLTIH_U, |
1814 | TILE_OPC_SLTI_U, TILE_OPC_XORI, TILE_OPC_LBADD, TILE_OPC_LBADD_U, | 1903 | TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_XORI, TILEPRO_OPC_LBADD, |
1904 | TILEPRO_OPC_LBADD_U, | ||
1815 | BITFIELD(51, 3) /* index 932 */, | 1905 | BITFIELD(51, 3) /* index 932 */, |
1816 | TILE_OPC_LHADD, TILE_OPC_LHADD_U, TILE_OPC_LWADD, TILE_OPC_LWADD_NA, | 1906 | TILEPRO_OPC_LHADD, TILEPRO_OPC_LHADD_U, TILEPRO_OPC_LWADD, |
1817 | TILE_OPC_SBADD, TILE_OPC_SHADD, TILE_OPC_SWADD, TILE_OPC_NONE, | 1907 | TILEPRO_OPC_LWADD_NA, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD, |
1908 | TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE, | ||
1818 | BITFIELD(51, 3) /* index 941 */, | 1909 | BITFIELD(51, 3) /* index 941 */, |
1819 | TILE_OPC_NONE, TILE_OPC_ADDIB_SN, TILE_OPC_ADDIH_SN, TILE_OPC_ADDI_SN, | 1910 | TILEPRO_OPC_NONE, TILEPRO_OPC_ADDIB_SN, TILEPRO_OPC_ADDIH_SN, |
1820 | TILE_OPC_ANDI_SN, TILE_OPC_MAXIB_U_SN, TILE_OPC_MAXIH_SN, TILE_OPC_MFSPR, | 1911 | TILEPRO_OPC_ADDI_SN, TILEPRO_OPC_ANDI_SN, TILEPRO_OPC_MAXIB_U_SN, |
1912 | TILEPRO_OPC_MAXIH_SN, TILEPRO_OPC_MFSPR, | ||
1821 | BITFIELD(51, 3) /* index 950 */, | 1913 | BITFIELD(51, 3) /* index 950 */, |
1822 | TILE_OPC_MINIB_U_SN, TILE_OPC_MINIH_SN, TILE_OPC_MTSPR, CHILD(959), | 1914 | TILEPRO_OPC_MINIB_U_SN, TILEPRO_OPC_MINIH_SN, TILEPRO_OPC_MTSPR, CHILD(959), |
1823 | TILE_OPC_SEQIB_SN, TILE_OPC_SEQIH_SN, TILE_OPC_SEQI_SN, TILE_OPC_SLTIB_SN, | 1915 | TILEPRO_OPC_SEQIB_SN, TILEPRO_OPC_SEQIH_SN, TILEPRO_OPC_SEQI_SN, |
1916 | TILEPRO_OPC_SLTIB_SN, | ||
1824 | BITFIELD(37, 2) /* index 959 */, | 1917 | BITFIELD(37, 2) /* index 959 */, |
1825 | TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(964), | 1918 | TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(964), |
1826 | BITFIELD(39, 2) /* index 964 */, | 1919 | BITFIELD(39, 2) /* index 964 */, |
1827 | TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, CHILD(969), | 1920 | TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, CHILD(969), |
1828 | BITFIELD(41, 2) /* index 969 */, | 1921 | BITFIELD(41, 2) /* index 969 */, |
1829 | TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_ORI_SN, TILE_OPC_MOVEI_SN, | 1922 | TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, TILEPRO_OPC_ORI_SN, |
1923 | TILEPRO_OPC_MOVEI_SN, | ||
1830 | BITFIELD(51, 3) /* index 974 */, | 1924 | BITFIELD(51, 3) /* index 974 */, |
1831 | TILE_OPC_SLTIB_U_SN, TILE_OPC_SLTIH_SN, TILE_OPC_SLTIH_U_SN, | 1925 | TILEPRO_OPC_SLTIB_U_SN, TILEPRO_OPC_SLTIH_SN, TILEPRO_OPC_SLTIH_U_SN, |
1832 | TILE_OPC_SLTI_SN, TILE_OPC_SLTI_U_SN, TILE_OPC_XORI_SN, TILE_OPC_LBADD_SN, | 1926 | TILEPRO_OPC_SLTI_SN, TILEPRO_OPC_SLTI_U_SN, TILEPRO_OPC_XORI_SN, |
1833 | TILE_OPC_LBADD_U_SN, | 1927 | TILEPRO_OPC_LBADD_SN, TILEPRO_OPC_LBADD_U_SN, |
1834 | BITFIELD(51, 3) /* index 983 */, | 1928 | BITFIELD(51, 3) /* index 983 */, |
1835 | TILE_OPC_LHADD_SN, TILE_OPC_LHADD_U_SN, TILE_OPC_LWADD_SN, | 1929 | TILEPRO_OPC_LHADD_SN, TILEPRO_OPC_LHADD_U_SN, TILEPRO_OPC_LWADD_SN, |
1836 | TILE_OPC_LWADD_NA_SN, TILE_OPC_SBADD, TILE_OPC_SHADD, TILE_OPC_SWADD, | 1930 | TILEPRO_OPC_LWADD_NA_SN, TILEPRO_OPC_SBADD, TILEPRO_OPC_SHADD, |
1837 | TILE_OPC_NONE, | 1931 | TILEPRO_OPC_SWADD, TILEPRO_OPC_NONE, |
1838 | BITFIELD(46, 7) /* index 992 */, | 1932 | BITFIELD(46, 7) /* index 992 */, |
1839 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1121), | 1933 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1840 | CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1124), CHILD(1124), | 1934 | CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1121), CHILD(1124), |
1841 | CHILD(1124), CHILD(1124), CHILD(1127), CHILD(1127), CHILD(1127), | 1935 | CHILD(1124), CHILD(1124), CHILD(1124), CHILD(1127), CHILD(1127), |
1842 | CHILD(1127), CHILD(1130), CHILD(1130), CHILD(1130), CHILD(1130), | 1936 | CHILD(1127), CHILD(1127), CHILD(1130), CHILD(1130), CHILD(1130), |
1843 | CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1136), | 1937 | CHILD(1130), CHILD(1133), CHILD(1133), CHILD(1133), CHILD(1133), |
1844 | CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1139), CHILD(1139), | 1938 | CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1136), CHILD(1139), |
1845 | CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142), CHILD(1142), | 1939 | CHILD(1139), CHILD(1139), CHILD(1139), CHILD(1142), CHILD(1142), |
1846 | CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145), CHILD(1145), | 1940 | CHILD(1142), CHILD(1142), CHILD(1145), CHILD(1145), CHILD(1145), |
1847 | CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1151), | 1941 | CHILD(1145), CHILD(1148), CHILD(1148), CHILD(1148), CHILD(1148), |
1848 | CHILD(1242), CHILD(1290), CHILD(1323), TILE_OPC_NONE, TILE_OPC_NONE, | 1942 | CHILD(1151), CHILD(1242), CHILD(1290), CHILD(1323), TILEPRO_OPC_NONE, |
1849 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1943 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1850 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1944 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1851 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1945 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1852 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1946 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1853 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1947 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1854 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1948 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1855 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1949 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1856 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1950 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1857 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1951 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1858 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1952 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1859 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1953 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1860 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1954 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1861 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1955 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1862 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1956 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1863 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1957 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1864 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 1958 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1959 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1960 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1961 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1962 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
1865 | BITFIELD(53, 1) /* index 1121 */, | 1963 | BITFIELD(53, 1) /* index 1121 */, |
1866 | TILE_OPC_RLI, TILE_OPC_NONE, | 1964 | TILEPRO_OPC_RLI, TILEPRO_OPC_NONE, |
1867 | BITFIELD(53, 1) /* index 1124 */, | 1965 | BITFIELD(53, 1) /* index 1124 */, |
1868 | TILE_OPC_SHLIB, TILE_OPC_NONE, | 1966 | TILEPRO_OPC_SHLIB, TILEPRO_OPC_NONE, |
1869 | BITFIELD(53, 1) /* index 1127 */, | 1967 | BITFIELD(53, 1) /* index 1127 */, |
1870 | TILE_OPC_SHLIH, TILE_OPC_NONE, | 1968 | TILEPRO_OPC_SHLIH, TILEPRO_OPC_NONE, |
1871 | BITFIELD(53, 1) /* index 1130 */, | 1969 | BITFIELD(53, 1) /* index 1130 */, |
1872 | TILE_OPC_SHLI, TILE_OPC_NONE, | 1970 | TILEPRO_OPC_SHLI, TILEPRO_OPC_NONE, |
1873 | BITFIELD(53, 1) /* index 1133 */, | 1971 | BITFIELD(53, 1) /* index 1133 */, |
1874 | TILE_OPC_SHRIB, TILE_OPC_NONE, | 1972 | TILEPRO_OPC_SHRIB, TILEPRO_OPC_NONE, |
1875 | BITFIELD(53, 1) /* index 1136 */, | 1973 | BITFIELD(53, 1) /* index 1136 */, |
1876 | TILE_OPC_SHRIH, TILE_OPC_NONE, | 1974 | TILEPRO_OPC_SHRIH, TILEPRO_OPC_NONE, |
1877 | BITFIELD(53, 1) /* index 1139 */, | 1975 | BITFIELD(53, 1) /* index 1139 */, |
1878 | TILE_OPC_SHRI, TILE_OPC_NONE, | 1976 | TILEPRO_OPC_SHRI, TILEPRO_OPC_NONE, |
1879 | BITFIELD(53, 1) /* index 1142 */, | 1977 | BITFIELD(53, 1) /* index 1142 */, |
1880 | TILE_OPC_SRAIB, TILE_OPC_NONE, | 1978 | TILEPRO_OPC_SRAIB, TILEPRO_OPC_NONE, |
1881 | BITFIELD(53, 1) /* index 1145 */, | 1979 | BITFIELD(53, 1) /* index 1145 */, |
1882 | TILE_OPC_SRAIH, TILE_OPC_NONE, | 1980 | TILEPRO_OPC_SRAIH, TILEPRO_OPC_NONE, |
1883 | BITFIELD(53, 1) /* index 1148 */, | 1981 | BITFIELD(53, 1) /* index 1148 */, |
1884 | TILE_OPC_SRAI, TILE_OPC_NONE, | 1982 | TILEPRO_OPC_SRAI, TILEPRO_OPC_NONE, |
1885 | BITFIELD(43, 3) /* index 1151 */, | 1983 | BITFIELD(43, 3) /* index 1151 */, |
1886 | TILE_OPC_NONE, CHILD(1160), CHILD(1163), CHILD(1166), CHILD(1169), | 1984 | TILEPRO_OPC_NONE, CHILD(1160), CHILD(1163), CHILD(1166), CHILD(1169), |
1887 | CHILD(1172), CHILD(1175), CHILD(1178), | 1985 | CHILD(1172), CHILD(1175), CHILD(1178), |
1888 | BITFIELD(53, 1) /* index 1160 */, | 1986 | BITFIELD(53, 1) /* index 1160 */, |
1889 | TILE_OPC_DRAIN, TILE_OPC_NONE, | 1987 | TILEPRO_OPC_DRAIN, TILEPRO_OPC_NONE, |
1890 | BITFIELD(53, 1) /* index 1163 */, | 1988 | BITFIELD(53, 1) /* index 1163 */, |
1891 | TILE_OPC_DTLBPR, TILE_OPC_NONE, | 1989 | TILEPRO_OPC_DTLBPR, TILEPRO_OPC_NONE, |
1892 | BITFIELD(53, 1) /* index 1166 */, | 1990 | BITFIELD(53, 1) /* index 1166 */, |
1893 | TILE_OPC_FINV, TILE_OPC_NONE, | 1991 | TILEPRO_OPC_FINV, TILEPRO_OPC_NONE, |
1894 | BITFIELD(53, 1) /* index 1169 */, | 1992 | BITFIELD(53, 1) /* index 1169 */, |
1895 | TILE_OPC_FLUSH, TILE_OPC_NONE, | 1993 | TILEPRO_OPC_FLUSH, TILEPRO_OPC_NONE, |
1896 | BITFIELD(53, 1) /* index 1172 */, | 1994 | BITFIELD(53, 1) /* index 1172 */, |
1897 | TILE_OPC_FNOP, TILE_OPC_NONE, | 1995 | TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE, |
1898 | BITFIELD(53, 1) /* index 1175 */, | 1996 | BITFIELD(53, 1) /* index 1175 */, |
1899 | TILE_OPC_ICOH, TILE_OPC_NONE, | 1997 | TILEPRO_OPC_ICOH, TILEPRO_OPC_NONE, |
1900 | BITFIELD(31, 2) /* index 1178 */, | 1998 | BITFIELD(31, 2) /* index 1178 */, |
1901 | CHILD(1183), CHILD(1211), CHILD(1239), CHILD(1239), | 1999 | CHILD(1183), CHILD(1211), CHILD(1239), CHILD(1239), |
1902 | BITFIELD(53, 1) /* index 1183 */, | 2000 | BITFIELD(53, 1) /* index 1183 */, |
1903 | CHILD(1186), TILE_OPC_NONE, | 2001 | CHILD(1186), TILEPRO_OPC_NONE, |
1904 | BITFIELD(33, 2) /* index 1186 */, | 2002 | BITFIELD(33, 2) /* index 1186 */, |
1905 | TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1191), | 2003 | TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1191), |
1906 | BITFIELD(35, 2) /* index 1191 */, | 2004 | BITFIELD(35, 2) /* index 1191 */, |
1907 | TILE_OPC_ILL, CHILD(1196), TILE_OPC_ILL, TILE_OPC_ILL, | 2005 | TILEPRO_OPC_ILL, CHILD(1196), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, |
1908 | BITFIELD(37, 2) /* index 1196 */, | 2006 | BITFIELD(37, 2) /* index 1196 */, |
1909 | TILE_OPC_ILL, CHILD(1201), TILE_OPC_ILL, TILE_OPC_ILL, | 2007 | TILEPRO_OPC_ILL, CHILD(1201), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, |
1910 | BITFIELD(39, 2) /* index 1201 */, | 2008 | BITFIELD(39, 2) /* index 1201 */, |
1911 | TILE_OPC_ILL, CHILD(1206), TILE_OPC_ILL, TILE_OPC_ILL, | 2009 | TILEPRO_OPC_ILL, CHILD(1206), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, |
1912 | BITFIELD(41, 2) /* index 1206 */, | 2010 | BITFIELD(41, 2) /* index 1206 */, |
1913 | TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_BPT, TILE_OPC_ILL, | 2011 | TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_BPT, TILEPRO_OPC_ILL, |
1914 | BITFIELD(53, 1) /* index 1211 */, | 2012 | BITFIELD(53, 1) /* index 1211 */, |
1915 | CHILD(1214), TILE_OPC_NONE, | 2013 | CHILD(1214), TILEPRO_OPC_NONE, |
1916 | BITFIELD(33, 2) /* index 1214 */, | 2014 | BITFIELD(33, 2) /* index 1214 */, |
1917 | TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_ILL, CHILD(1219), | 2015 | TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, CHILD(1219), |
1918 | BITFIELD(35, 2) /* index 1219 */, | 2016 | BITFIELD(35, 2) /* index 1219 */, |
1919 | TILE_OPC_ILL, CHILD(1224), TILE_OPC_ILL, TILE_OPC_ILL, | 2017 | TILEPRO_OPC_ILL, CHILD(1224), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, |
1920 | BITFIELD(37, 2) /* index 1224 */, | 2018 | BITFIELD(37, 2) /* index 1224 */, |
1921 | TILE_OPC_ILL, CHILD(1229), TILE_OPC_ILL, TILE_OPC_ILL, | 2019 | TILEPRO_OPC_ILL, CHILD(1229), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, |
1922 | BITFIELD(39, 2) /* index 1229 */, | 2020 | BITFIELD(39, 2) /* index 1229 */, |
1923 | TILE_OPC_ILL, CHILD(1234), TILE_OPC_ILL, TILE_OPC_ILL, | 2021 | TILEPRO_OPC_ILL, CHILD(1234), TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, |
1924 | BITFIELD(41, 2) /* index 1234 */, | 2022 | BITFIELD(41, 2) /* index 1234 */, |
1925 | TILE_OPC_ILL, TILE_OPC_ILL, TILE_OPC_RAISE, TILE_OPC_ILL, | 2023 | TILEPRO_OPC_ILL, TILEPRO_OPC_ILL, TILEPRO_OPC_RAISE, TILEPRO_OPC_ILL, |
1926 | BITFIELD(53, 1) /* index 1239 */, | 2024 | BITFIELD(53, 1) /* index 1239 */, |
1927 | TILE_OPC_ILL, TILE_OPC_NONE, | 2025 | TILEPRO_OPC_ILL, TILEPRO_OPC_NONE, |
1928 | BITFIELD(43, 3) /* index 1242 */, | 2026 | BITFIELD(43, 3) /* index 1242 */, |
1929 | CHILD(1251), CHILD(1254), CHILD(1257), CHILD(1275), CHILD(1278), | 2027 | CHILD(1251), CHILD(1254), CHILD(1257), CHILD(1275), CHILD(1278), |
1930 | CHILD(1281), CHILD(1284), CHILD(1287), | 2028 | CHILD(1281), CHILD(1284), CHILD(1287), |
1931 | BITFIELD(53, 1) /* index 1251 */, | 2029 | BITFIELD(53, 1) /* index 1251 */, |
1932 | TILE_OPC_INV, TILE_OPC_NONE, | 2030 | TILEPRO_OPC_INV, TILEPRO_OPC_NONE, |
1933 | BITFIELD(53, 1) /* index 1254 */, | 2031 | BITFIELD(53, 1) /* index 1254 */, |
1934 | TILE_OPC_IRET, TILE_OPC_NONE, | 2032 | TILEPRO_OPC_IRET, TILEPRO_OPC_NONE, |
1935 | BITFIELD(53, 1) /* index 1257 */, | 2033 | BITFIELD(53, 1) /* index 1257 */, |
1936 | CHILD(1260), TILE_OPC_NONE, | 2034 | CHILD(1260), TILEPRO_OPC_NONE, |
1937 | BITFIELD(31, 2) /* index 1260 */, | 2035 | BITFIELD(31, 2) /* index 1260 */, |
1938 | TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1265), | 2036 | TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1265), |
1939 | BITFIELD(33, 2) /* index 1265 */, | 2037 | BITFIELD(33, 2) /* index 1265 */, |
1940 | TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(1270), | 2038 | TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(1270), |
1941 | BITFIELD(35, 2) /* index 1270 */, | 2039 | BITFIELD(35, 2) /* index 1270 */, |
1942 | TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH, | 2040 | TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH, |
1943 | BITFIELD(53, 1) /* index 1275 */, | 2041 | BITFIELD(53, 1) /* index 1275 */, |
1944 | TILE_OPC_LB_U, TILE_OPC_NONE, | 2042 | TILEPRO_OPC_LB_U, TILEPRO_OPC_NONE, |
1945 | BITFIELD(53, 1) /* index 1278 */, | 2043 | BITFIELD(53, 1) /* index 1278 */, |
1946 | TILE_OPC_LH, TILE_OPC_NONE, | 2044 | TILEPRO_OPC_LH, TILEPRO_OPC_NONE, |
1947 | BITFIELD(53, 1) /* index 1281 */, | 2045 | BITFIELD(53, 1) /* index 1281 */, |
1948 | TILE_OPC_LH_U, TILE_OPC_NONE, | 2046 | TILEPRO_OPC_LH_U, TILEPRO_OPC_NONE, |
1949 | BITFIELD(53, 1) /* index 1284 */, | 2047 | BITFIELD(53, 1) /* index 1284 */, |
1950 | TILE_OPC_LW, TILE_OPC_NONE, | 2048 | TILEPRO_OPC_LW, TILEPRO_OPC_NONE, |
1951 | BITFIELD(53, 1) /* index 1287 */, | 2049 | BITFIELD(53, 1) /* index 1287 */, |
1952 | TILE_OPC_MF, TILE_OPC_NONE, | 2050 | TILEPRO_OPC_MF, TILEPRO_OPC_NONE, |
1953 | BITFIELD(43, 3) /* index 1290 */, | 2051 | BITFIELD(43, 3) /* index 1290 */, |
1954 | CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311), | 2052 | CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311), |
1955 | CHILD(1314), CHILD(1317), CHILD(1320), | 2053 | CHILD(1314), CHILD(1317), CHILD(1320), |
1956 | BITFIELD(53, 1) /* index 1299 */, | 2054 | BITFIELD(53, 1) /* index 1299 */, |
1957 | TILE_OPC_NAP, TILE_OPC_NONE, | 2055 | TILEPRO_OPC_NAP, TILEPRO_OPC_NONE, |
1958 | BITFIELD(53, 1) /* index 1302 */, | 2056 | BITFIELD(53, 1) /* index 1302 */, |
1959 | TILE_OPC_NOP, TILE_OPC_NONE, | 2057 | TILEPRO_OPC_NOP, TILEPRO_OPC_NONE, |
1960 | BITFIELD(53, 1) /* index 1305 */, | 2058 | BITFIELD(53, 1) /* index 1305 */, |
1961 | TILE_OPC_SWINT0, TILE_OPC_NONE, | 2059 | TILEPRO_OPC_SWINT0, TILEPRO_OPC_NONE, |
1962 | BITFIELD(53, 1) /* index 1308 */, | 2060 | BITFIELD(53, 1) /* index 1308 */, |
1963 | TILE_OPC_SWINT1, TILE_OPC_NONE, | 2061 | TILEPRO_OPC_SWINT1, TILEPRO_OPC_NONE, |
1964 | BITFIELD(53, 1) /* index 1311 */, | 2062 | BITFIELD(53, 1) /* index 1311 */, |
1965 | TILE_OPC_SWINT2, TILE_OPC_NONE, | 2063 | TILEPRO_OPC_SWINT2, TILEPRO_OPC_NONE, |
1966 | BITFIELD(53, 1) /* index 1314 */, | 2064 | BITFIELD(53, 1) /* index 1314 */, |
1967 | TILE_OPC_SWINT3, TILE_OPC_NONE, | 2065 | TILEPRO_OPC_SWINT3, TILEPRO_OPC_NONE, |
1968 | BITFIELD(53, 1) /* index 1317 */, | 2066 | BITFIELD(53, 1) /* index 1317 */, |
1969 | TILE_OPC_TNS, TILE_OPC_NONE, | 2067 | TILEPRO_OPC_TNS, TILEPRO_OPC_NONE, |
1970 | BITFIELD(53, 1) /* index 1320 */, | 2068 | BITFIELD(53, 1) /* index 1320 */, |
1971 | TILE_OPC_WH64, TILE_OPC_NONE, | 2069 | TILEPRO_OPC_WH64, TILEPRO_OPC_NONE, |
1972 | BITFIELD(43, 2) /* index 1323 */, | 2070 | BITFIELD(43, 2) /* index 1323 */, |
1973 | CHILD(1328), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2071 | CHILD(1328), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1974 | BITFIELD(45, 1) /* index 1328 */, | 2072 | BITFIELD(45, 1) /* index 1328 */, |
1975 | CHILD(1331), TILE_OPC_NONE, | 2073 | CHILD(1331), TILEPRO_OPC_NONE, |
1976 | BITFIELD(53, 1) /* index 1331 */, | 2074 | BITFIELD(53, 1) /* index 1331 */, |
1977 | TILE_OPC_LW_NA, TILE_OPC_NONE, | 2075 | TILEPRO_OPC_LW_NA, TILEPRO_OPC_NONE, |
1978 | BITFIELD(46, 7) /* index 1334 */, | 2076 | BITFIELD(46, 7) /* index 1334 */, |
1979 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, CHILD(1463), | 2077 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1980 | CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1466), CHILD(1466), | 2078 | CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1463), CHILD(1466), |
1981 | CHILD(1466), CHILD(1466), CHILD(1469), CHILD(1469), CHILD(1469), | 2079 | CHILD(1466), CHILD(1466), CHILD(1466), CHILD(1469), CHILD(1469), |
1982 | CHILD(1469), CHILD(1472), CHILD(1472), CHILD(1472), CHILD(1472), | 2080 | CHILD(1469), CHILD(1469), CHILD(1472), CHILD(1472), CHILD(1472), |
1983 | CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1478), | 2081 | CHILD(1472), CHILD(1475), CHILD(1475), CHILD(1475), CHILD(1475), |
1984 | CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1481), CHILD(1481), | 2082 | CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1478), CHILD(1481), |
1985 | CHILD(1481), CHILD(1481), CHILD(1484), CHILD(1484), CHILD(1484), | 2083 | CHILD(1481), CHILD(1481), CHILD(1481), CHILD(1484), CHILD(1484), |
1986 | CHILD(1484), CHILD(1487), CHILD(1487), CHILD(1487), CHILD(1487), | 2084 | CHILD(1484), CHILD(1484), CHILD(1487), CHILD(1487), CHILD(1487), |
1987 | CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1151), | 2085 | CHILD(1487), CHILD(1490), CHILD(1490), CHILD(1490), CHILD(1490), |
1988 | CHILD(1493), CHILD(1517), CHILD(1529), TILE_OPC_NONE, TILE_OPC_NONE, | 2086 | CHILD(1151), CHILD(1493), CHILD(1517), CHILD(1529), TILEPRO_OPC_NONE, |
1989 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2087 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1990 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2088 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1991 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2089 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1992 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2090 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1993 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2091 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1994 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2092 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1995 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2093 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1996 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2094 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1997 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2095 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1998 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2096 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
1999 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2097 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2000 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2098 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2001 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2099 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2002 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2100 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2003 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2101 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2004 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2102 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2103 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
2104 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
2105 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
2106 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
2005 | BITFIELD(53, 1) /* index 1463 */, | 2107 | BITFIELD(53, 1) /* index 1463 */, |
2006 | TILE_OPC_RLI_SN, TILE_OPC_NONE, | 2108 | TILEPRO_OPC_RLI_SN, TILEPRO_OPC_NONE, |
2007 | BITFIELD(53, 1) /* index 1466 */, | 2109 | BITFIELD(53, 1) /* index 1466 */, |
2008 | TILE_OPC_SHLIB_SN, TILE_OPC_NONE, | 2110 | TILEPRO_OPC_SHLIB_SN, TILEPRO_OPC_NONE, |
2009 | BITFIELD(53, 1) /* index 1469 */, | 2111 | BITFIELD(53, 1) /* index 1469 */, |
2010 | TILE_OPC_SHLIH_SN, TILE_OPC_NONE, | 2112 | TILEPRO_OPC_SHLIH_SN, TILEPRO_OPC_NONE, |
2011 | BITFIELD(53, 1) /* index 1472 */, | 2113 | BITFIELD(53, 1) /* index 1472 */, |
2012 | TILE_OPC_SHLI_SN, TILE_OPC_NONE, | 2114 | TILEPRO_OPC_SHLI_SN, TILEPRO_OPC_NONE, |
2013 | BITFIELD(53, 1) /* index 1475 */, | 2115 | BITFIELD(53, 1) /* index 1475 */, |
2014 | TILE_OPC_SHRIB_SN, TILE_OPC_NONE, | 2116 | TILEPRO_OPC_SHRIB_SN, TILEPRO_OPC_NONE, |
2015 | BITFIELD(53, 1) /* index 1478 */, | 2117 | BITFIELD(53, 1) /* index 1478 */, |
2016 | TILE_OPC_SHRIH_SN, TILE_OPC_NONE, | 2118 | TILEPRO_OPC_SHRIH_SN, TILEPRO_OPC_NONE, |
2017 | BITFIELD(53, 1) /* index 1481 */, | 2119 | BITFIELD(53, 1) /* index 1481 */, |
2018 | TILE_OPC_SHRI_SN, TILE_OPC_NONE, | 2120 | TILEPRO_OPC_SHRI_SN, TILEPRO_OPC_NONE, |
2019 | BITFIELD(53, 1) /* index 1484 */, | 2121 | BITFIELD(53, 1) /* index 1484 */, |
2020 | TILE_OPC_SRAIB_SN, TILE_OPC_NONE, | 2122 | TILEPRO_OPC_SRAIB_SN, TILEPRO_OPC_NONE, |
2021 | BITFIELD(53, 1) /* index 1487 */, | 2123 | BITFIELD(53, 1) /* index 1487 */, |
2022 | TILE_OPC_SRAIH_SN, TILE_OPC_NONE, | 2124 | TILEPRO_OPC_SRAIH_SN, TILEPRO_OPC_NONE, |
2023 | BITFIELD(53, 1) /* index 1490 */, | 2125 | BITFIELD(53, 1) /* index 1490 */, |
2024 | TILE_OPC_SRAI_SN, TILE_OPC_NONE, | 2126 | TILEPRO_OPC_SRAI_SN, TILEPRO_OPC_NONE, |
2025 | BITFIELD(43, 3) /* index 1493 */, | 2127 | BITFIELD(43, 3) /* index 1493 */, |
2026 | CHILD(1251), CHILD(1254), CHILD(1502), CHILD(1505), CHILD(1508), | 2128 | CHILD(1251), CHILD(1254), CHILD(1502), CHILD(1505), CHILD(1508), |
2027 | CHILD(1511), CHILD(1514), CHILD(1287), | 2129 | CHILD(1511), CHILD(1514), CHILD(1287), |
2028 | BITFIELD(53, 1) /* index 1502 */, | 2130 | BITFIELD(53, 1) /* index 1502 */, |
2029 | TILE_OPC_LB_SN, TILE_OPC_NONE, | 2131 | TILEPRO_OPC_LB_SN, TILEPRO_OPC_NONE, |
2030 | BITFIELD(53, 1) /* index 1505 */, | 2132 | BITFIELD(53, 1) /* index 1505 */, |
2031 | TILE_OPC_LB_U_SN, TILE_OPC_NONE, | 2133 | TILEPRO_OPC_LB_U_SN, TILEPRO_OPC_NONE, |
2032 | BITFIELD(53, 1) /* index 1508 */, | 2134 | BITFIELD(53, 1) /* index 1508 */, |
2033 | TILE_OPC_LH_SN, TILE_OPC_NONE, | 2135 | TILEPRO_OPC_LH_SN, TILEPRO_OPC_NONE, |
2034 | BITFIELD(53, 1) /* index 1511 */, | 2136 | BITFIELD(53, 1) /* index 1511 */, |
2035 | TILE_OPC_LH_U_SN, TILE_OPC_NONE, | 2137 | TILEPRO_OPC_LH_U_SN, TILEPRO_OPC_NONE, |
2036 | BITFIELD(53, 1) /* index 1514 */, | 2138 | BITFIELD(53, 1) /* index 1514 */, |
2037 | TILE_OPC_LW_SN, TILE_OPC_NONE, | 2139 | TILEPRO_OPC_LW_SN, TILEPRO_OPC_NONE, |
2038 | BITFIELD(43, 3) /* index 1517 */, | 2140 | BITFIELD(43, 3) /* index 1517 */, |
2039 | CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311), | 2141 | CHILD(1299), CHILD(1302), CHILD(1305), CHILD(1308), CHILD(1311), |
2040 | CHILD(1314), CHILD(1526), CHILD(1320), | 2142 | CHILD(1314), CHILD(1526), CHILD(1320), |
2041 | BITFIELD(53, 1) /* index 1526 */, | 2143 | BITFIELD(53, 1) /* index 1526 */, |
2042 | TILE_OPC_TNS_SN, TILE_OPC_NONE, | 2144 | TILEPRO_OPC_TNS_SN, TILEPRO_OPC_NONE, |
2043 | BITFIELD(43, 2) /* index 1529 */, | 2145 | BITFIELD(43, 2) /* index 1529 */, |
2044 | CHILD(1534), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2146 | CHILD(1534), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2045 | BITFIELD(45, 1) /* index 1534 */, | 2147 | BITFIELD(45, 1) /* index 1534 */, |
2046 | CHILD(1537), TILE_OPC_NONE, | 2148 | CHILD(1537), TILEPRO_OPC_NONE, |
2047 | BITFIELD(53, 1) /* index 1537 */, | 2149 | BITFIELD(53, 1) /* index 1537 */, |
2048 | TILE_OPC_LW_NA_SN, TILE_OPC_NONE, | 2150 | TILEPRO_OPC_LW_NA_SN, TILEPRO_OPC_NONE, |
2049 | }; | 2151 | }; |
2050 | 2152 | ||
2051 | static const unsigned short decode_Y0_fsm[168] = | 2153 | static const unsigned short decode_Y0_fsm[168] = |
2052 | { | 2154 | { |
2053 | BITFIELD(27, 4) /* index 0 */, | 2155 | BITFIELD(27, 4) /* index 0 */, |
2054 | TILE_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), | 2156 | TILEPRO_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), |
2055 | CHILD(57), CHILD(62), CHILD(67), TILE_OPC_ADDI, CHILD(72), CHILD(102), | 2157 | CHILD(57), CHILD(62), CHILD(67), TILEPRO_OPC_ADDI, CHILD(72), CHILD(102), |
2056 | TILE_OPC_SEQI, CHILD(117), TILE_OPC_SLTI, TILE_OPC_SLTI_U, | 2158 | TILEPRO_OPC_SEQI, CHILD(117), TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, |
2057 | BITFIELD(18, 2) /* index 17 */, | 2159 | BITFIELD(18, 2) /* index 17 */, |
2058 | TILE_OPC_ADD, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_SUB, | 2160 | TILEPRO_OPC_ADD, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_SUB, |
2059 | BITFIELD(18, 2) /* index 22 */, | 2161 | BITFIELD(18, 2) /* index 22 */, |
2060 | TILE_OPC_MNZ, TILE_OPC_MVNZ, TILE_OPC_MVZ, TILE_OPC_MZ, | 2162 | TILEPRO_OPC_MNZ, TILEPRO_OPC_MVNZ, TILEPRO_OPC_MVZ, TILEPRO_OPC_MZ, |
2061 | BITFIELD(18, 2) /* index 27 */, | 2163 | BITFIELD(18, 2) /* index 27 */, |
2062 | TILE_OPC_AND, TILE_OPC_NOR, CHILD(32), TILE_OPC_XOR, | 2164 | TILEPRO_OPC_AND, TILEPRO_OPC_NOR, CHILD(32), TILEPRO_OPC_XOR, |
2063 | BITFIELD(12, 2) /* index 32 */, | 2165 | BITFIELD(12, 2) /* index 32 */, |
2064 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(37), | 2166 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(37), |
2065 | BITFIELD(14, 2) /* index 37 */, | 2167 | BITFIELD(14, 2) /* index 37 */, |
2066 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(42), | 2168 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(42), |
2067 | BITFIELD(16, 2) /* index 42 */, | 2169 | BITFIELD(16, 2) /* index 42 */, |
2068 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, | 2170 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, |
2069 | BITFIELD(18, 2) /* index 47 */, | 2171 | BITFIELD(18, 2) /* index 47 */, |
2070 | TILE_OPC_RL, TILE_OPC_SHL, TILE_OPC_SHR, TILE_OPC_SRA, | 2172 | TILEPRO_OPC_RL, TILEPRO_OPC_SHL, TILEPRO_OPC_SHR, TILEPRO_OPC_SRA, |
2071 | BITFIELD(18, 2) /* index 52 */, | 2173 | BITFIELD(18, 2) /* index 52 */, |
2072 | TILE_OPC_SLTE, TILE_OPC_SLTE_U, TILE_OPC_SLT, TILE_OPC_SLT_U, | 2174 | TILEPRO_OPC_SLTE, TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLT, TILEPRO_OPC_SLT_U, |
2073 | BITFIELD(18, 2) /* index 57 */, | 2175 | BITFIELD(18, 2) /* index 57 */, |
2074 | TILE_OPC_MULHLSA_UU, TILE_OPC_S3A, TILE_OPC_SEQ, TILE_OPC_SNE, | 2176 | TILEPRO_OPC_MULHLSA_UU, TILEPRO_OPC_S3A, TILEPRO_OPC_SEQ, TILEPRO_OPC_SNE, |
2075 | BITFIELD(18, 2) /* index 62 */, | 2177 | BITFIELD(18, 2) /* index 62 */, |
2076 | TILE_OPC_MULHH_SS, TILE_OPC_MULHH_UU, TILE_OPC_MULLL_SS, TILE_OPC_MULLL_UU, | 2178 | TILEPRO_OPC_MULHH_SS, TILEPRO_OPC_MULHH_UU, TILEPRO_OPC_MULLL_SS, |
2179 | TILEPRO_OPC_MULLL_UU, | ||
2077 | BITFIELD(18, 2) /* index 67 */, | 2180 | BITFIELD(18, 2) /* index 67 */, |
2078 | TILE_OPC_MULHHA_SS, TILE_OPC_MULHHA_UU, TILE_OPC_MULLLA_SS, | 2181 | TILEPRO_OPC_MULHHA_SS, TILEPRO_OPC_MULHHA_UU, TILEPRO_OPC_MULLLA_SS, |
2079 | TILE_OPC_MULLLA_UU, | 2182 | TILEPRO_OPC_MULLLA_UU, |
2080 | BITFIELD(0, 2) /* index 72 */, | 2183 | BITFIELD(0, 2) /* index 72 */, |
2081 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(77), | 2184 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(77), |
2082 | BITFIELD(2, 2) /* index 77 */, | 2185 | BITFIELD(2, 2) /* index 77 */, |
2083 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(82), | 2186 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(82), |
2084 | BITFIELD(4, 2) /* index 82 */, | 2187 | BITFIELD(4, 2) /* index 82 */, |
2085 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(87), | 2188 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(87), |
2086 | BITFIELD(6, 2) /* index 87 */, | 2189 | BITFIELD(6, 2) /* index 87 */, |
2087 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(92), | 2190 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(92), |
2088 | BITFIELD(8, 2) /* index 92 */, | 2191 | BITFIELD(8, 2) /* index 92 */, |
2089 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(97), | 2192 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(97), |
2090 | BITFIELD(10, 2) /* index 97 */, | 2193 | BITFIELD(10, 2) /* index 97 */, |
2091 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, | 2194 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, |
2092 | BITFIELD(6, 2) /* index 102 */, | 2195 | BITFIELD(6, 2) /* index 102 */, |
2093 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(107), | 2196 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(107), |
2094 | BITFIELD(8, 2) /* index 107 */, | 2197 | BITFIELD(8, 2) /* index 107 */, |
2095 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(112), | 2198 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(112), |
2096 | BITFIELD(10, 2) /* index 112 */, | 2199 | BITFIELD(10, 2) /* index 112 */, |
2097 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, | 2200 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, |
2098 | BITFIELD(15, 5) /* index 117 */, | 2201 | BITFIELD(15, 5) /* index 117 */, |
2099 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_RLI, | 2202 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2100 | TILE_OPC_RLI, TILE_OPC_RLI, TILE_OPC_RLI, TILE_OPC_SHLI, TILE_OPC_SHLI, | 2203 | TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, TILEPRO_OPC_RLI, |
2101 | TILE_OPC_SHLI, TILE_OPC_SHLI, TILE_OPC_SHRI, TILE_OPC_SHRI, TILE_OPC_SHRI, | 2204 | TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHLI, |
2102 | TILE_OPC_SHRI, TILE_OPC_SRAI, TILE_OPC_SRAI, TILE_OPC_SRAI, TILE_OPC_SRAI, | 2205 | TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, TILEPRO_OPC_SHRI, |
2103 | CHILD(150), CHILD(159), TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2206 | TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, TILEPRO_OPC_SRAI, |
2104 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2207 | CHILD(150), CHILD(159), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2105 | TILE_OPC_NONE, TILE_OPC_NONE, | 2208 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2209 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, | ||
2106 | BITFIELD(12, 3) /* index 150 */, | 2210 | BITFIELD(12, 3) /* index 150 */, |
2107 | TILE_OPC_NONE, TILE_OPC_BITX, TILE_OPC_BYTEX, TILE_OPC_CLZ, TILE_OPC_CTZ, | 2211 | TILEPRO_OPC_NONE, TILEPRO_OPC_BITX, TILEPRO_OPC_BYTEX, TILEPRO_OPC_CLZ, |
2108 | TILE_OPC_FNOP, TILE_OPC_NOP, TILE_OPC_PCNT, | 2212 | TILEPRO_OPC_CTZ, TILEPRO_OPC_FNOP, TILEPRO_OPC_NOP, TILEPRO_OPC_PCNT, |
2109 | BITFIELD(12, 3) /* index 159 */, | 2213 | BITFIELD(12, 3) /* index 159 */, |
2110 | TILE_OPC_TBLIDXB0, TILE_OPC_TBLIDXB1, TILE_OPC_TBLIDXB2, TILE_OPC_TBLIDXB3, | 2214 | TILEPRO_OPC_TBLIDXB0, TILEPRO_OPC_TBLIDXB1, TILEPRO_OPC_TBLIDXB2, |
2111 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2215 | TILEPRO_OPC_TBLIDXB3, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2216 | TILEPRO_OPC_NONE, | ||
2112 | }; | 2217 | }; |
2113 | 2218 | ||
2114 | static const unsigned short decode_Y1_fsm[140] = | 2219 | static const unsigned short decode_Y1_fsm[140] = |
2115 | { | 2220 | { |
2116 | BITFIELD(59, 4) /* index 0 */, | 2221 | BITFIELD(59, 4) /* index 0 */, |
2117 | TILE_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), | 2222 | TILEPRO_OPC_NONE, CHILD(17), CHILD(22), CHILD(27), CHILD(47), CHILD(52), |
2118 | CHILD(57), TILE_OPC_ADDI, CHILD(62), CHILD(92), TILE_OPC_SEQI, CHILD(107), | 2223 | CHILD(57), TILEPRO_OPC_ADDI, CHILD(62), CHILD(92), TILEPRO_OPC_SEQI, |
2119 | TILE_OPC_SLTI, TILE_OPC_SLTI_U, TILE_OPC_NONE, TILE_OPC_NONE, | 2224 | CHILD(107), TILEPRO_OPC_SLTI, TILEPRO_OPC_SLTI_U, TILEPRO_OPC_NONE, |
2225 | TILEPRO_OPC_NONE, | ||
2120 | BITFIELD(49, 2) /* index 17 */, | 2226 | BITFIELD(49, 2) /* index 17 */, |
2121 | TILE_OPC_ADD, TILE_OPC_S1A, TILE_OPC_S2A, TILE_OPC_SUB, | 2227 | TILEPRO_OPC_ADD, TILEPRO_OPC_S1A, TILEPRO_OPC_S2A, TILEPRO_OPC_SUB, |
2122 | BITFIELD(49, 2) /* index 22 */, | 2228 | BITFIELD(49, 2) /* index 22 */, |
2123 | TILE_OPC_NONE, TILE_OPC_MNZ, TILE_OPC_MZ, TILE_OPC_NONE, | 2229 | TILEPRO_OPC_NONE, TILEPRO_OPC_MNZ, TILEPRO_OPC_MZ, TILEPRO_OPC_NONE, |
2124 | BITFIELD(49, 2) /* index 27 */, | 2230 | BITFIELD(49, 2) /* index 27 */, |
2125 | TILE_OPC_AND, TILE_OPC_NOR, CHILD(32), TILE_OPC_XOR, | 2231 | TILEPRO_OPC_AND, TILEPRO_OPC_NOR, CHILD(32), TILEPRO_OPC_XOR, |
2126 | BITFIELD(43, 2) /* index 32 */, | 2232 | BITFIELD(43, 2) /* index 32 */, |
2127 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(37), | 2233 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(37), |
2128 | BITFIELD(45, 2) /* index 37 */, | 2234 | BITFIELD(45, 2) /* index 37 */, |
2129 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, CHILD(42), | 2235 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, CHILD(42), |
2130 | BITFIELD(47, 2) /* index 42 */, | 2236 | BITFIELD(47, 2) /* index 42 */, |
2131 | TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_OR, TILE_OPC_MOVE, | 2237 | TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_OR, TILEPRO_OPC_MOVE, |
2132 | BITFIELD(49, 2) /* index 47 */, | 2238 | BITFIELD(49, 2) /* index 47 */, |
2133 | TILE_OPC_RL, TILE_OPC_SHL, TILE_OPC_SHR, TILE_OPC_SRA, | 2239 | TILEPRO_OPC_RL, TILEPRO_OPC_SHL, TILEPRO_OPC_SHR, TILEPRO_OPC_SRA, |
2134 | BITFIELD(49, 2) /* index 52 */, | 2240 | BITFIELD(49, 2) /* index 52 */, |
2135 | TILE_OPC_SLTE, TILE_OPC_SLTE_U, TILE_OPC_SLT, TILE_OPC_SLT_U, | 2241 | TILEPRO_OPC_SLTE, TILEPRO_OPC_SLTE_U, TILEPRO_OPC_SLT, TILEPRO_OPC_SLT_U, |
2136 | BITFIELD(49, 2) /* index 57 */, | 2242 | BITFIELD(49, 2) /* index 57 */, |
2137 | TILE_OPC_NONE, TILE_OPC_S3A, TILE_OPC_SEQ, TILE_OPC_SNE, | 2243 | TILEPRO_OPC_NONE, TILEPRO_OPC_S3A, TILEPRO_OPC_SEQ, TILEPRO_OPC_SNE, |
2138 | BITFIELD(31, 2) /* index 62 */, | 2244 | BITFIELD(31, 2) /* index 62 */, |
2139 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(67), | 2245 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(67), |
2140 | BITFIELD(33, 2) /* index 67 */, | 2246 | BITFIELD(33, 2) /* index 67 */, |
2141 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(72), | 2247 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(72), |
2142 | BITFIELD(35, 2) /* index 72 */, | 2248 | BITFIELD(35, 2) /* index 72 */, |
2143 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(77), | 2249 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(77), |
2144 | BITFIELD(37, 2) /* index 77 */, | 2250 | BITFIELD(37, 2) /* index 77 */, |
2145 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(82), | 2251 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(82), |
2146 | BITFIELD(39, 2) /* index 82 */, | 2252 | BITFIELD(39, 2) /* index 82 */, |
2147 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, CHILD(87), | 2253 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, CHILD(87), |
2148 | BITFIELD(41, 2) /* index 87 */, | 2254 | BITFIELD(41, 2) /* index 87 */, |
2149 | TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_ANDI, TILE_OPC_INFO, | 2255 | TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_ANDI, TILEPRO_OPC_INFO, |
2150 | BITFIELD(37, 2) /* index 92 */, | 2256 | BITFIELD(37, 2) /* index 92 */, |
2151 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(97), | 2257 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(97), |
2152 | BITFIELD(39, 2) /* index 97 */, | 2258 | BITFIELD(39, 2) /* index 97 */, |
2153 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, CHILD(102), | 2259 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, CHILD(102), |
2154 | BITFIELD(41, 2) /* index 102 */, | 2260 | BITFIELD(41, 2) /* index 102 */, |
2155 | TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_ORI, TILE_OPC_MOVEI, | 2261 | TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_ORI, TILEPRO_OPC_MOVEI, |
2156 | BITFIELD(48, 3) /* index 107 */, | 2262 | BITFIELD(48, 3) /* index 107 */, |
2157 | TILE_OPC_NONE, TILE_OPC_RLI, TILE_OPC_SHLI, TILE_OPC_SHRI, TILE_OPC_SRAI, | 2263 | TILEPRO_OPC_NONE, TILEPRO_OPC_RLI, TILEPRO_OPC_SHLI, TILEPRO_OPC_SHRI, |
2158 | CHILD(116), TILE_OPC_NONE, TILE_OPC_NONE, | 2264 | TILEPRO_OPC_SRAI, CHILD(116), TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2159 | BITFIELD(43, 3) /* index 116 */, | 2265 | BITFIELD(43, 3) /* index 116 */, |
2160 | TILE_OPC_NONE, CHILD(125), CHILD(130), CHILD(135), TILE_OPC_NONE, | 2266 | TILEPRO_OPC_NONE, CHILD(125), CHILD(130), CHILD(135), TILEPRO_OPC_NONE, |
2161 | TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2267 | TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2162 | BITFIELD(46, 2) /* index 125 */, | 2268 | BITFIELD(46, 2) /* index 125 */, |
2163 | TILE_OPC_FNOP, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2269 | TILEPRO_OPC_FNOP, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2164 | BITFIELD(46, 2) /* index 130 */, | 2270 | BITFIELD(46, 2) /* index 130 */, |
2165 | TILE_OPC_ILL, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2271 | TILEPRO_OPC_ILL, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2166 | BITFIELD(46, 2) /* index 135 */, | 2272 | BITFIELD(46, 2) /* index 135 */, |
2167 | TILE_OPC_NOP, TILE_OPC_NONE, TILE_OPC_NONE, TILE_OPC_NONE, | 2273 | TILEPRO_OPC_NOP, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, TILEPRO_OPC_NONE, |
2168 | }; | 2274 | }; |
2169 | 2275 | ||
2170 | static const unsigned short decode_Y2_fsm[24] = | 2276 | static const unsigned short decode_Y2_fsm[24] = |
2171 | { | 2277 | { |
2172 | BITFIELD(56, 3) /* index 0 */, | 2278 | BITFIELD(56, 3) /* index 0 */, |
2173 | CHILD(9), TILE_OPC_LB_U, TILE_OPC_LH, TILE_OPC_LH_U, TILE_OPC_LW, | 2279 | CHILD(9), TILEPRO_OPC_LB_U, TILEPRO_OPC_LH, TILEPRO_OPC_LH_U, |
2174 | TILE_OPC_SB, TILE_OPC_SH, TILE_OPC_SW, | 2280 | TILEPRO_OPC_LW, TILEPRO_OPC_SB, TILEPRO_OPC_SH, TILEPRO_OPC_SW, |
2175 | BITFIELD(20, 2) /* index 9 */, | 2281 | BITFIELD(20, 2) /* index 9 */, |
2176 | TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(14), | 2282 | TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(14), |
2177 | BITFIELD(22, 2) /* index 14 */, | 2283 | BITFIELD(22, 2) /* index 14 */, |
2178 | TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, CHILD(19), | 2284 | TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, CHILD(19), |
2179 | BITFIELD(24, 2) /* index 19 */, | 2285 | BITFIELD(24, 2) /* index 19 */, |
2180 | TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_LB, TILE_OPC_PREFETCH, | 2286 | TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_LB, TILEPRO_OPC_PREFETCH, |
2181 | }; | 2287 | }; |
2182 | 2288 | ||
2183 | #undef BITFIELD | 2289 | #undef BITFIELD |
2184 | #undef CHILD | 2290 | #undef CHILD |
2185 | const unsigned short * const | 2291 | const unsigned short * const |
2186 | tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS] = | 2292 | tilepro_bundle_decoder_fsms[TILEPRO_NUM_PIPELINE_ENCODINGS] = |
2187 | { | 2293 | { |
2188 | decode_X0_fsm, | 2294 | decode_X0_fsm, |
2189 | decode_X1_fsm, | 2295 | decode_X1_fsm, |
@@ -2191,220 +2297,220 @@ tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS] = | |||
2191 | decode_Y1_fsm, | 2297 | decode_Y1_fsm, |
2192 | decode_Y2_fsm | 2298 | decode_Y2_fsm |
2193 | }; | 2299 | }; |
2194 | const struct tile_operand tile_operands[43] = | 2300 | const struct tilepro_operand tilepro_operands[43] = |
2195 | { | 2301 | { |
2196 | { | 2302 | { |
2197 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_X0), | 2303 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_X0), |
2198 | 8, 1, 0, 0, 0, 0, | 2304 | 8, 1, 0, 0, 0, 0, |
2199 | create_Imm8_X0, get_Imm8_X0 | 2305 | create_Imm8_X0, get_Imm8_X0 |
2200 | }, | 2306 | }, |
2201 | { | 2307 | { |
2202 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_X1), | 2308 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_X1), |
2203 | 8, 1, 0, 0, 0, 0, | 2309 | 8, 1, 0, 0, 0, 0, |
2204 | create_Imm8_X1, get_Imm8_X1 | 2310 | create_Imm8_X1, get_Imm8_X1 |
2205 | }, | 2311 | }, |
2206 | { | 2312 | { |
2207 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_Y0), | 2313 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_Y0), |
2208 | 8, 1, 0, 0, 0, 0, | 2314 | 8, 1, 0, 0, 0, 0, |
2209 | create_Imm8_Y0, get_Imm8_Y0 | 2315 | create_Imm8_Y0, get_Imm8_Y0 |
2210 | }, | 2316 | }, |
2211 | { | 2317 | { |
2212 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM8_Y1), | 2318 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM8_Y1), |
2213 | 8, 1, 0, 0, 0, 0, | 2319 | 8, 1, 0, 0, 0, 0, |
2214 | create_Imm8_Y1, get_Imm8_Y1 | 2320 | create_Imm8_Y1, get_Imm8_Y1 |
2215 | }, | 2321 | }, |
2216 | { | 2322 | { |
2217 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM16_X0), | 2323 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM16_X0), |
2218 | 16, 1, 0, 0, 0, 0, | 2324 | 16, 1, 0, 0, 0, 0, |
2219 | create_Imm16_X0, get_Imm16_X0 | 2325 | create_Imm16_X0, get_Imm16_X0 |
2220 | }, | 2326 | }, |
2221 | { | 2327 | { |
2222 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_IMM16_X1), | 2328 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_IMM16_X1), |
2223 | 16, 1, 0, 0, 0, 0, | 2329 | 16, 1, 0, 0, 0, 0, |
2224 | create_Imm16_X1, get_Imm16_X1 | 2330 | create_Imm16_X1, get_Imm16_X1 |
2225 | }, | 2331 | }, |
2226 | { | 2332 | { |
2227 | TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_JOFFLONG_X1), | 2333 | TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(TILEPRO_JOFFLONG_X1), |
2228 | 29, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, | 2334 | 29, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, |
2229 | create_JOffLong_X1, get_JOffLong_X1 | 2335 | create_JOffLong_X1, get_JOffLong_X1 |
2230 | }, | 2336 | }, |
2231 | { | 2337 | { |
2232 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2338 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2233 | 6, 0, 0, 1, 0, 0, | 2339 | 6, 0, 0, 1, 0, 0, |
2234 | create_Dest_X0, get_Dest_X0 | 2340 | create_Dest_X0, get_Dest_X0 |
2235 | }, | 2341 | }, |
2236 | { | 2342 | { |
2237 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2343 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2238 | 6, 0, 1, 0, 0, 0, | 2344 | 6, 0, 1, 0, 0, 0, |
2239 | create_SrcA_X0, get_SrcA_X0 | 2345 | create_SrcA_X0, get_SrcA_X0 |
2240 | }, | 2346 | }, |
2241 | { | 2347 | { |
2242 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2348 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2243 | 6, 0, 0, 1, 0, 0, | 2349 | 6, 0, 0, 1, 0, 0, |
2244 | create_Dest_X1, get_Dest_X1 | 2350 | create_Dest_X1, get_Dest_X1 |
2245 | }, | 2351 | }, |
2246 | { | 2352 | { |
2247 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2353 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2248 | 6, 0, 1, 0, 0, 0, | 2354 | 6, 0, 1, 0, 0, 0, |
2249 | create_SrcA_X1, get_SrcA_X1 | 2355 | create_SrcA_X1, get_SrcA_X1 |
2250 | }, | 2356 | }, |
2251 | { | 2357 | { |
2252 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2358 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2253 | 6, 0, 0, 1, 0, 0, | 2359 | 6, 0, 0, 1, 0, 0, |
2254 | create_Dest_Y0, get_Dest_Y0 | 2360 | create_Dest_Y0, get_Dest_Y0 |
2255 | }, | 2361 | }, |
2256 | { | 2362 | { |
2257 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2363 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2258 | 6, 0, 1, 0, 0, 0, | 2364 | 6, 0, 1, 0, 0, 0, |
2259 | create_SrcA_Y0, get_SrcA_Y0 | 2365 | create_SrcA_Y0, get_SrcA_Y0 |
2260 | }, | 2366 | }, |
2261 | { | 2367 | { |
2262 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2368 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2263 | 6, 0, 0, 1, 0, 0, | 2369 | 6, 0, 0, 1, 0, 0, |
2264 | create_Dest_Y1, get_Dest_Y1 | 2370 | create_Dest_Y1, get_Dest_Y1 |
2265 | }, | 2371 | }, |
2266 | { | 2372 | { |
2267 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2373 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2268 | 6, 0, 1, 0, 0, 0, | 2374 | 6, 0, 1, 0, 0, 0, |
2269 | create_SrcA_Y1, get_SrcA_Y1 | 2375 | create_SrcA_Y1, get_SrcA_Y1 |
2270 | }, | 2376 | }, |
2271 | { | 2377 | { |
2272 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2378 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2273 | 6, 0, 1, 0, 0, 0, | 2379 | 6, 0, 1, 0, 0, 0, |
2274 | create_SrcA_Y2, get_SrcA_Y2 | 2380 | create_SrcA_Y2, get_SrcA_Y2 |
2275 | }, | 2381 | }, |
2276 | { | 2382 | { |
2277 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2383 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2278 | 6, 0, 1, 0, 0, 0, | 2384 | 6, 0, 1, 0, 0, 0, |
2279 | create_SrcB_X0, get_SrcB_X0 | 2385 | create_SrcB_X0, get_SrcB_X0 |
2280 | }, | 2386 | }, |
2281 | { | 2387 | { |
2282 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2388 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2283 | 6, 0, 1, 0, 0, 0, | 2389 | 6, 0, 1, 0, 0, 0, |
2284 | create_SrcB_X1, get_SrcB_X1 | 2390 | create_SrcB_X1, get_SrcB_X1 |
2285 | }, | 2391 | }, |
2286 | { | 2392 | { |
2287 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2393 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2288 | 6, 0, 1, 0, 0, 0, | 2394 | 6, 0, 1, 0, 0, 0, |
2289 | create_SrcB_Y0, get_SrcB_Y0 | 2395 | create_SrcB_Y0, get_SrcB_Y0 |
2290 | }, | 2396 | }, |
2291 | { | 2397 | { |
2292 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2398 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2293 | 6, 0, 1, 0, 0, 0, | 2399 | 6, 0, 1, 0, 0, 0, |
2294 | create_SrcB_Y1, get_SrcB_Y1 | 2400 | create_SrcB_Y1, get_SrcB_Y1 |
2295 | }, | 2401 | }, |
2296 | { | 2402 | { |
2297 | TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_BROFF_X1), | 2403 | TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(TILEPRO_BROFF_X1), |
2298 | 17, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, | 2404 | 17, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, |
2299 | create_BrOff_X1, get_BrOff_X1 | 2405 | create_BrOff_X1, get_BrOff_X1 |
2300 | }, | 2406 | }, |
2301 | { | 2407 | { |
2302 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2408 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2303 | 6, 0, 1, 1, 0, 0, | 2409 | 6, 0, 1, 1, 0, 0, |
2304 | create_Dest_X0, get_Dest_X0 | 2410 | create_Dest_X0, get_Dest_X0 |
2305 | }, | 2411 | }, |
2306 | { | 2412 | { |
2307 | TILE_OP_TYPE_ADDRESS, BFD_RELOC(NONE), | 2413 | TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(NONE), |
2308 | 28, 1, 0, 0, 1, TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, | 2414 | 28, 1, 0, 0, 1, TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES, |
2309 | create_JOff_X1, get_JOff_X1 | 2415 | create_JOff_X1, get_JOff_X1 |
2310 | }, | 2416 | }, |
2311 | { | 2417 | { |
2312 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2418 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2313 | 6, 0, 0, 1, 0, 0, | 2419 | 6, 0, 0, 1, 0, 0, |
2314 | create_SrcBDest_Y2, get_SrcBDest_Y2 | 2420 | create_SrcBDest_Y2, get_SrcBDest_Y2 |
2315 | }, | 2421 | }, |
2316 | { | 2422 | { |
2317 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2423 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2318 | 6, 0, 1, 1, 0, 0, | 2424 | 6, 0, 1, 1, 0, 0, |
2319 | create_SrcA_X1, get_SrcA_X1 | 2425 | create_SrcA_X1, get_SrcA_X1 |
2320 | }, | 2426 | }, |
2321 | { | 2427 | { |
2322 | TILE_OP_TYPE_SPR, BFD_RELOC(TILE_MF_IMM15_X1), | 2428 | TILEPRO_OP_TYPE_SPR, BFD_RELOC(TILEPRO_MF_IMM15_X1), |
2323 | 15, 0, 0, 0, 0, 0, | 2429 | 15, 0, 0, 0, 0, 0, |
2324 | create_MF_Imm15_X1, get_MF_Imm15_X1 | 2430 | create_MF_Imm15_X1, get_MF_Imm15_X1 |
2325 | }, | 2431 | }, |
2326 | { | 2432 | { |
2327 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMSTART_X0), | 2433 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMSTART_X0), |
2328 | 5, 0, 0, 0, 0, 0, | 2434 | 5, 0, 0, 0, 0, 0, |
2329 | create_MMStart_X0, get_MMStart_X0 | 2435 | create_MMStart_X0, get_MMStart_X0 |
2330 | }, | 2436 | }, |
2331 | { | 2437 | { |
2332 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMEND_X0), | 2438 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMEND_X0), |
2333 | 5, 0, 0, 0, 0, 0, | 2439 | 5, 0, 0, 0, 0, 0, |
2334 | create_MMEnd_X0, get_MMEnd_X0 | 2440 | create_MMEnd_X0, get_MMEnd_X0 |
2335 | }, | 2441 | }, |
2336 | { | 2442 | { |
2337 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMSTART_X1), | 2443 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMSTART_X1), |
2338 | 5, 0, 0, 0, 0, 0, | 2444 | 5, 0, 0, 0, 0, 0, |
2339 | create_MMStart_X1, get_MMStart_X1 | 2445 | create_MMStart_X1, get_MMStart_X1 |
2340 | }, | 2446 | }, |
2341 | { | 2447 | { |
2342 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_MMEND_X1), | 2448 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_MMEND_X1), |
2343 | 5, 0, 0, 0, 0, 0, | 2449 | 5, 0, 0, 0, 0, 0, |
2344 | create_MMEnd_X1, get_MMEnd_X1 | 2450 | create_MMEnd_X1, get_MMEnd_X1 |
2345 | }, | 2451 | }, |
2346 | { | 2452 | { |
2347 | TILE_OP_TYPE_SPR, BFD_RELOC(TILE_MT_IMM15_X1), | 2453 | TILEPRO_OP_TYPE_SPR, BFD_RELOC(TILEPRO_MT_IMM15_X1), |
2348 | 15, 0, 0, 0, 0, 0, | 2454 | 15, 0, 0, 0, 0, 0, |
2349 | create_MT_Imm15_X1, get_MT_Imm15_X1 | 2455 | create_MT_Imm15_X1, get_MT_Imm15_X1 |
2350 | }, | 2456 | }, |
2351 | { | 2457 | { |
2352 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2458 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2353 | 6, 0, 1, 1, 0, 0, | 2459 | 6, 0, 1, 1, 0, 0, |
2354 | create_Dest_Y0, get_Dest_Y0 | 2460 | create_Dest_Y0, get_Dest_Y0 |
2355 | }, | 2461 | }, |
2356 | { | 2462 | { |
2357 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_X0), | 2463 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_X0), |
2358 | 5, 0, 0, 0, 0, 0, | 2464 | 5, 0, 0, 0, 0, 0, |
2359 | create_ShAmt_X0, get_ShAmt_X0 | 2465 | create_ShAmt_X0, get_ShAmt_X0 |
2360 | }, | 2466 | }, |
2361 | { | 2467 | { |
2362 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_X1), | 2468 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_X1), |
2363 | 5, 0, 0, 0, 0, 0, | 2469 | 5, 0, 0, 0, 0, 0, |
2364 | create_ShAmt_X1, get_ShAmt_X1 | 2470 | create_ShAmt_X1, get_ShAmt_X1 |
2365 | }, | 2471 | }, |
2366 | { | 2472 | { |
2367 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_Y0), | 2473 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_Y0), |
2368 | 5, 0, 0, 0, 0, 0, | 2474 | 5, 0, 0, 0, 0, 0, |
2369 | create_ShAmt_Y0, get_ShAmt_Y0 | 2475 | create_ShAmt_Y0, get_ShAmt_Y0 |
2370 | }, | 2476 | }, |
2371 | { | 2477 | { |
2372 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SHAMT_Y1), | 2478 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_SHAMT_Y1), |
2373 | 5, 0, 0, 0, 0, 0, | 2479 | 5, 0, 0, 0, 0, 0, |
2374 | create_ShAmt_Y1, get_ShAmt_Y1 | 2480 | create_ShAmt_Y1, get_ShAmt_Y1 |
2375 | }, | 2481 | }, |
2376 | { | 2482 | { |
2377 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2483 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2378 | 6, 0, 1, 0, 0, 0, | 2484 | 6, 0, 1, 0, 0, 0, |
2379 | create_SrcBDest_Y2, get_SrcBDest_Y2 | 2485 | create_SrcBDest_Y2, get_SrcBDest_Y2 |
2380 | }, | 2486 | }, |
2381 | { | 2487 | { |
2382 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), | 2488 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEPRO_DEST_IMM8_X1), |
2383 | 8, 1, 0, 0, 0, 0, | 2489 | 8, 1, 0, 0, 0, 0, |
2384 | create_Dest_Imm8_X1, get_Dest_Imm8_X1 | 2490 | create_Dest_Imm8_X1, get_Dest_Imm8_X1 |
2385 | }, | 2491 | }, |
2386 | { | 2492 | { |
2387 | TILE_OP_TYPE_ADDRESS, BFD_RELOC(TILE_SN_BROFF), | 2493 | TILEPRO_OP_TYPE_ADDRESS, BFD_RELOC(NONE), |
2388 | 10, 1, 0, 0, 1, TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES, | 2494 | 10, 1, 0, 0, 1, TILEPRO_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES, |
2389 | create_BrOff_SN, get_BrOff_SN | 2495 | create_BrOff_SN, get_BrOff_SN |
2390 | }, | 2496 | }, |
2391 | { | 2497 | { |
2392 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SN_UIMM8), | 2498 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), |
2393 | 8, 0, 0, 0, 0, 0, | 2499 | 8, 0, 0, 0, 0, 0, |
2394 | create_Imm8_SN, get_Imm8_SN | 2500 | create_Imm8_SN, get_Imm8_SN |
2395 | }, | 2501 | }, |
2396 | { | 2502 | { |
2397 | TILE_OP_TYPE_IMMEDIATE, BFD_RELOC(TILE_SN_IMM8), | 2503 | TILEPRO_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), |
2398 | 8, 1, 0, 0, 0, 0, | 2504 | 8, 1, 0, 0, 0, 0, |
2399 | create_Imm8_SN, get_Imm8_SN | 2505 | create_Imm8_SN, get_Imm8_SN |
2400 | }, | 2506 | }, |
2401 | { | 2507 | { |
2402 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2508 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2403 | 2, 0, 0, 1, 0, 0, | 2509 | 2, 0, 0, 1, 0, 0, |
2404 | create_Dest_SN, get_Dest_SN | 2510 | create_Dest_SN, get_Dest_SN |
2405 | }, | 2511 | }, |
2406 | { | 2512 | { |
2407 | TILE_OP_TYPE_REGISTER, BFD_RELOC(NONE), | 2513 | TILEPRO_OP_TYPE_REGISTER, BFD_RELOC(NONE), |
2408 | 2, 0, 1, 0, 0, 0, | 2514 | 2, 0, 1, 0, 0, 0, |
2409 | create_Src_SN, get_Src_SN | 2515 | create_Src_SN, get_Src_SN |
2410 | } | 2516 | } |
@@ -2416,10 +2522,10 @@ const struct tile_operand tile_operands[43] = | |||
2416 | /* Given a set of bundle bits and a specific pipe, returns which | 2522 | /* Given a set of bundle bits and a specific pipe, returns which |
2417 | * instruction the bundle contains in that pipe. | 2523 | * instruction the bundle contains in that pipe. |
2418 | */ | 2524 | */ |
2419 | const struct tile_opcode * | 2525 | const struct tilepro_opcode * |
2420 | find_opcode(tile_bundle_bits bits, tile_pipeline pipe) | 2526 | find_opcode(tilepro_bundle_bits bits, tilepro_pipeline pipe) |
2421 | { | 2527 | { |
2422 | const unsigned short *table = tile_bundle_decoder_fsms[pipe]; | 2528 | const unsigned short *table = tilepro_bundle_decoder_fsms[pipe]; |
2423 | int index = 0; | 2529 | int index = 0; |
2424 | 2530 | ||
2425 | while (1) | 2531 | while (1) |
@@ -2429,51 +2535,51 @@ find_opcode(tile_bundle_bits bits, tile_pipeline pipe) | |||
2429 | ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6); | 2535 | ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6); |
2430 | 2536 | ||
2431 | unsigned short next = table[index + 1 + bitfield]; | 2537 | unsigned short next = table[index + 1 + bitfield]; |
2432 | if (next <= TILE_OPC_NONE) | 2538 | if (next <= TILEPRO_OPC_NONE) |
2433 | return &tile_opcodes[next]; | 2539 | return &tilepro_opcodes[next]; |
2434 | 2540 | ||
2435 | index = next - TILE_OPC_NONE; | 2541 | index = next - TILEPRO_OPC_NONE; |
2436 | } | 2542 | } |
2437 | } | 2543 | } |
2438 | 2544 | ||
2439 | 2545 | ||
2440 | int | 2546 | int |
2441 | parse_insn_tile(tile_bundle_bits bits, | 2547 | parse_insn_tilepro(tilepro_bundle_bits bits, |
2442 | unsigned int pc, | 2548 | unsigned int pc, |
2443 | struct tile_decoded_instruction | 2549 | struct tilepro_decoded_instruction |
2444 | decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]) | 2550 | decoded[TILEPRO_MAX_INSTRUCTIONS_PER_BUNDLE]) |
2445 | { | 2551 | { |
2446 | int num_instructions = 0; | 2552 | int num_instructions = 0; |
2447 | int pipe; | 2553 | int pipe; |
2448 | 2554 | ||
2449 | int min_pipe, max_pipe; | 2555 | int min_pipe, max_pipe; |
2450 | if ((bits & TILE_BUNDLE_Y_ENCODING_MASK) == 0) | 2556 | if ((bits & TILEPRO_BUNDLE_Y_ENCODING_MASK) == 0) |
2451 | { | 2557 | { |
2452 | min_pipe = TILE_PIPELINE_X0; | 2558 | min_pipe = TILEPRO_PIPELINE_X0; |
2453 | max_pipe = TILE_PIPELINE_X1; | 2559 | max_pipe = TILEPRO_PIPELINE_X1; |
2454 | } | 2560 | } |
2455 | else | 2561 | else |
2456 | { | 2562 | { |
2457 | min_pipe = TILE_PIPELINE_Y0; | 2563 | min_pipe = TILEPRO_PIPELINE_Y0; |
2458 | max_pipe = TILE_PIPELINE_Y2; | 2564 | max_pipe = TILEPRO_PIPELINE_Y2; |
2459 | } | 2565 | } |
2460 | 2566 | ||
2461 | /* For each pipe, find an instruction that fits. */ | 2567 | /* For each pipe, find an instruction that fits. */ |
2462 | for (pipe = min_pipe; pipe <= max_pipe; pipe++) | 2568 | for (pipe = min_pipe; pipe <= max_pipe; pipe++) |
2463 | { | 2569 | { |
2464 | const struct tile_opcode *opc; | 2570 | const struct tilepro_opcode *opc; |
2465 | struct tile_decoded_instruction *d; | 2571 | struct tilepro_decoded_instruction *d; |
2466 | int i; | 2572 | int i; |
2467 | 2573 | ||
2468 | d = &decoded[num_instructions++]; | 2574 | d = &decoded[num_instructions++]; |
2469 | opc = find_opcode (bits, (tile_pipeline)pipe); | 2575 | opc = find_opcode (bits, (tilepro_pipeline)pipe); |
2470 | d->opcode = opc; | 2576 | d->opcode = opc; |
2471 | 2577 | ||
2472 | /* Decode each operand, sign extending, etc. as appropriate. */ | 2578 | /* Decode each operand, sign extending, etc. as appropriate. */ |
2473 | for (i = 0; i < opc->num_operands; i++) | 2579 | for (i = 0; i < opc->num_operands; i++) |
2474 | { | 2580 | { |
2475 | const struct tile_operand *op = | 2581 | const struct tilepro_operand *op = |
2476 | &tile_operands[opc->operands[pipe][i]]; | 2582 | &tilepro_operands[opc->operands[pipe][i]]; |
2477 | int opval = op->extract (bits); | 2583 | int opval = op->extract (bits); |
2478 | if (op->is_signed) | 2584 | if (op->is_signed) |
2479 | { | 2585 | { |
@@ -2483,9 +2589,9 @@ parse_insn_tile(tile_bundle_bits bits, | |||
2483 | } | 2589 | } |
2484 | 2590 | ||
2485 | /* Adjust PC-relative scaled branch offsets. */ | 2591 | /* Adjust PC-relative scaled branch offsets. */ |
2486 | if (op->type == TILE_OP_TYPE_ADDRESS) | 2592 | if (op->type == TILEPRO_OP_TYPE_ADDRESS) |
2487 | { | 2593 | { |
2488 | opval *= TILE_BUNDLE_SIZE_IN_BYTES; | 2594 | opval *= TILEPRO_BUNDLE_SIZE_IN_BYTES; |
2489 | opval += (int)pc; | 2595 | opval += (int)pc; |
2490 | } | 2596 | } |
2491 | 2597 | ||
diff --git a/arch/tile/kernel/tile-desc_64.c b/arch/tile/kernel/tile-desc_64.c index d57007bed77f..65b5f8aca706 100644 --- a/arch/tile/kernel/tile-desc_64.c +++ b/arch/tile/kernel/tile-desc_64.c | |||
@@ -1,3 +1,23 @@ | |||
1 | /* TILE-Gx opcode information. | ||
2 | * | ||
3 | * Copyright 2011 Tilera Corporation. All Rights Reserved. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or | ||
6 | * modify it under the terms of the GNU General Public License | ||
7 | * as published by the Free Software Foundation, version 2. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but | ||
10 | * WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | ||
12 | * NON INFRINGEMENT. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * | ||
16 | * | ||
17 | * | ||
18 | * | ||
19 | */ | ||
20 | |||
1 | /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ | 21 | /* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */ |
2 | #define BFD_RELOC(x) -1 | 22 | #define BFD_RELOC(x) -1 |
3 | 23 | ||
@@ -6,10 +26,8 @@ | |||
6 | #define TREG_SN 56 | 26 | #define TREG_SN 56 |
7 | #define TREG_ZERO 63 | 27 | #define TREG_ZERO 63 |
8 | 28 | ||
9 | /* FIXME: Rename this. */ | ||
10 | #include <asm/opcode-tile_64.h> | ||
11 | |||
12 | #include <linux/stddef.h> | 29 | #include <linux/stddef.h> |
30 | #include <asm/tile-desc.h> | ||
13 | 31 | ||
14 | const struct tilegx_opcode tilegx_opcodes[334] = | 32 | const struct tilegx_opcode tilegx_opcodes[334] = |
15 | { | 33 | { |
@@ -2040,12 +2058,12 @@ const struct tilegx_operand tilegx_operands[35] = | |||
2040 | create_BrOff_X1, get_BrOff_X1 | 2058 | create_BrOff_X1, get_BrOff_X1 |
2041 | }, | 2059 | }, |
2042 | { | 2060 | { |
2043 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), | 2061 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMSTART_X0), |
2044 | 6, 0, 0, 0, 0, 0, | 2062 | 6, 0, 0, 0, 0, 0, |
2045 | create_BFStart_X0, get_BFStart_X0 | 2063 | create_BFStart_X0, get_BFStart_X0 |
2046 | }, | 2064 | }, |
2047 | { | 2065 | { |
2048 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE), | 2066 | TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_MMEND_X0), |
2049 | 6, 0, 0, 0, 0, 0, | 2067 | 6, 0, 0, 0, 0, 0, |
2050 | create_BFEnd_X0, get_BFEnd_X0 | 2068 | create_BFEnd_X0, get_BFEnd_X0 |
2051 | }, | 2069 | }, |
diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c index f9803dfa7357..4f47b8a356df 100644 --- a/arch/tile/kernel/traps.c +++ b/arch/tile/kernel/traps.c | |||
@@ -19,13 +19,12 @@ | |||
19 | #include <linux/reboot.h> | 19 | #include <linux/reboot.h> |
20 | #include <linux/uaccess.h> | 20 | #include <linux/uaccess.h> |
21 | #include <linux/ptrace.h> | 21 | #include <linux/ptrace.h> |
22 | #include <asm/opcode-tile.h> | ||
23 | #include <asm/opcode_constants.h> | ||
24 | #include <asm/stack.h> | 22 | #include <asm/stack.h> |
25 | #include <asm/traps.h> | 23 | #include <asm/traps.h> |
26 | 24 | ||
27 | #include <arch/interrupts.h> | 25 | #include <arch/interrupts.h> |
28 | #include <arch/spr_def.h> | 26 | #include <arch/spr_def.h> |
27 | #include <arch/opcode.h> | ||
29 | 28 | ||
30 | void __init trap_init(void) | 29 | void __init trap_init(void) |
31 | { | 30 | { |
@@ -135,7 +134,7 @@ static int special_ill(bundle_bits bundle, int *sigp, int *codep) | |||
135 | if (get_UnaryOpcodeExtension_X1(bundle) != ILL_UNARY_OPCODE_X1) | 134 | if (get_UnaryOpcodeExtension_X1(bundle) != ILL_UNARY_OPCODE_X1) |
136 | return 0; | 135 | return 0; |
137 | #else | 136 | #else |
138 | if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) | 137 | if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) |
139 | return 0; | 138 | return 0; |
140 | if (get_Opcode_X1(bundle) != SHUN_0_OPCODE_X1) | 139 | if (get_Opcode_X1(bundle) != SHUN_0_OPCODE_X1) |
141 | return 0; | 140 | return 0; |