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authorSimon Horman <horms+renesas@verge.net.au>2013-04-02 21:49:18 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-04-02 21:49:18 -0400
commiteb0ae7280939fda741ad6ae9b108725517652f56 (patch)
treeaf0a7387d7f9424a3b7bd2c1a065d4433a76270b
parentac22dde76c80a3ffa3c3c24cf16bb8076b20b767 (diff)
parent202ac6a21a79500ef5aab4cd8665be2597e9345c (diff)
Merge tag 'renesas-pinmux2-for-v3.10' into boards-base
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10 Highlights: * Compilation fixes for sh7269 and for when CONFIG_BUG is not set * sh-pfc Support for r8a73a4 SoC * Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10 This merge is made to supply run-time dependencies for the following patches that will bea added on top: ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support
Diffstat
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi94
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi35
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi63
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi81
-rw-r--r--arch/arm/mach-shmobile/Kconfig28
-rw-r--r--arch/arm/mach-shmobile/Makefile3
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c35
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g.c14
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c32
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c115
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c114
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c104
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c196
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c93
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c50
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c115
-rw-r--r--arch/arm/mach-shmobile/clock.c13
-rw-r--r--arch/arm/mach-shmobile/include/mach/clock.h39
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h53
-rw-r--r--arch/arm/mach-shmobile/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a73a4.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h9
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h28
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h330
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7790.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h12
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h15
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c641
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c53
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c117
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c202
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c192
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c193
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c58
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c137
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c126
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c2
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-rcar.c396
-rw-r--r--drivers/irqchip/Kconfig8
-rw-r--r--drivers/irqchip/Makefile2
-rw-r--r--drivers/irqchip/irq-renesas-intc-irqpin.c547
-rw-r--r--drivers/irqchip/irq-renesas-irqc.c307
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c41
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c45
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c2587
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c64
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c479
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c6
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c11
-rw-r--r--include/linux/platform_data/gpio-rcar.h26
-rw-r--r--include/linux/platform_data/irq-renesas-intc-irqpin.h29
-rw-r--r--include/linux/platform_data/irq-renesas-irqc.h27
58 files changed, 6120 insertions, 1883 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5b714695b01b..b63902e7cacd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -725,7 +725,7 @@ config ARCH_SHMOBILE
725 select MULTI_IRQ_HANDLER 725 select MULTI_IRQ_HANDLER
726 select NEED_MACH_MEMORY_H 726 select NEED_MACH_MEMORY_H
727 select NO_IOPORT 727 select NO_IOPORT
728 select PINCTRL 728 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
729 select PM_GENERIC_DOMAINS if PM 729 select PM_GENERIC_DOMAINS if PM
730 select SPARSE_IRQ 730 select SPARSE_IRQ
731 help 731 help
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
new file mode 100644
index 000000000000..fde2a337d1ff
--- /dev/null
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -0,0 +1,94 @@
1/*
2 * Device Tree Source for the r8a73a4 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/ {
13 compatible = "renesas,r8a73a4";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a15";
25 reg = <0>;
26 clock-frequency = <1500000000>;
27 };
28 };
29
30 gic: interrupt-controller@f1001000 {
31 compatible = "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
33 #address-cells = <0>;
34 interrupt-controller;
35 reg = <0 0xf1001000 0 0x1000>,
36 <0 0xf1002000 0 0x1000>,
37 <0 0xf1004000 0 0x2000>,
38 <0 0xf1006000 0 0x2000>;
39 interrupts = <1 9 0xf04>;
40
41 gic-cpuif@4 {
42 compatible = "arm,gic-cpuif";
43 cpuif-id = <4>;
44 cpu = <&cpu0>;
45 };
46 };
47
48 timer {
49 compatible = "arm,armv7-timer";
50 interrupts = <1 13 0xf08>,
51 <1 14 0xf08>,
52 <1 11 0xf08>,
53 <1 10 0xf08>;
54 };
55
56 irqc0: interrupt-controller@e61c0000 {
57 compatible = "renesas,irqc";
58 #interrupt-cells = <2>;
59 interrupt-controller;
60 reg = <0 0xe61c0000 0 0x200>;
61 interrupt-parent = <&gic>;
62 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
63 <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
64 <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
65 <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
66 <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
67 <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
68 <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
69 <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
70 };
71
72 irqc1: interrupt-controller@e61c0200 {
73 compatible = "renesas,irqc";
74 #interrupt-cells = <2>;
75 interrupt-controller;
76 reg = <0 0xe61c0200 0 0x200>;
77 interrupt-parent = <&gic>;
78 interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
79 <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
80 <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
81 <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
82 <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
83 <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
84 <0 56 4>, <0 57 4>;
85 };
86
87 thermal@e61f0000 {
88 compatible = "renesas,rcar-thermal";
89 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
90 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
91 interrupt-parent = <&gic>;
92 interrupts = <0 69 4>;
93 };
94};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
new file mode 100644
index 000000000000..474373559bdc
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -0,0 +1,35 @@
1/*
2 * Device Tree Source for Renesas r8a7778
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2013 Renesas Solutions Corp.
10 * Copyright (C) 2013 Simon Horman
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17/include/ "skeleton.dtsi"
18
19/ {
20 compatible = "renesas,r8a7778";
21
22 cpus {
23 cpu@0 {
24 compatible = "arm,cortex-a9";
25 };
26 };
27
28 gic: interrupt-controller@fe438000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 interrupt-controller;
32 reg = <0xfe438000 0x1000>,
33 <0xfe430000 0x100>;
34 };
35};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
new file mode 100644
index 000000000000..7a1711027e41
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -0,0 +1,63 @@
1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/ {
12 compatible = "renesas,r8a7790";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a15";
24 reg = <0>;
25 clock-frequency = <1300000000>;
26 };
27 };
28
29 gic: interrupt-controller@f1001000 {
30 compatible = "arm,cortex-a15-gic";
31 #interrupt-cells = <3>;
32 #address-cells = <0>;
33 interrupt-controller;
34 reg = <0 0xf1001000 0 0x1000>,
35 <0 0xf1002000 0 0x1000>,
36 <0 0xf1004000 0 0x2000>,
37 <0 0xf1006000 0 0x2000>;
38 interrupts = <1 9 0xf04>;
39
40 gic-cpuif@4 {
41 compatible = "arm,gic-cpuif";
42 cpuif-id = <4>;
43 cpu = <&cpu0>;
44 };
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <1 13 0xf08>,
50 <1 14 0xf08>,
51 <1 11 0xf08>,
52 <1 10 0xf08>;
53 };
54
55 irqc0: interrupt-controller@e61c0000 {
56 compatible = "renesas,irqc";
57 #interrupt-cells = <2>;
58 interrupt-controller;
59 reg = <0 0xe61c0000 0 0x200>;
60 interrupt-parent = <&gic>;
61 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
62 };
63};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 3e4d383ac6d9..ec40bf78289e 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -38,6 +38,87 @@
38 <0xf0000100 0x100>; 38 <0xf0000100 0x100>;
39 }; 39 };
40 40
41 irqpin0: irqpin@e6900000 {
42 compatible = "renesas,intc-irqpin";
43 #interrupt-cells = <2>;
44 interrupt-controller;
45 reg = <0xe6900000 4>,
46 <0xe6900010 4>,
47 <0xe6900020 1>,
48 <0xe6900040 1>,
49 <0xe6900060 1>;
50 interrupt-parent = <&gic>;
51 interrupts = <0 1 0x4
52 0 2 0x4
53 0 3 0x4
54 0 4 0x4
55 0 5 0x4
56 0 6 0x4
57 0 7 0x4
58 0 8 0x4>;
59 };
60
61 irqpin1: irqpin@e6900004 {
62 compatible = "renesas,intc-irqpin";
63 #interrupt-cells = <2>;
64 interrupt-controller;
65 reg = <0xe6900004 4>,
66 <0xe6900014 4>,
67 <0xe6900024 1>,
68 <0xe6900044 1>,
69 <0xe6900064 1>;
70 interrupt-parent = <&gic>;
71 interrupts = <0 9 0x4
72 0 10 0x4
73 0 11 0x4
74 0 12 0x4
75 0 13 0x4
76 0 14 0x4
77 0 15 0x4
78 0 16 0x4>;
79 control-parent;
80 };
81
82 irqpin2: irqpin@e6900008 {
83 compatible = "renesas,intc-irqpin";
84 #interrupt-cells = <2>;
85 interrupt-controller;
86 reg = <0xe6900008 4>,
87 <0xe6900018 4>,
88 <0xe6900028 1>,
89 <0xe6900048 1>,
90 <0xe6900068 1>;
91 interrupt-parent = <&gic>;
92 interrupts = <0 17 0x4
93 0 18 0x4
94 0 19 0x4
95 0 20 0x4
96 0 21 0x4
97 0 22 0x4
98 0 23 0x4
99 0 24 0x4>;
100 };
101
102 irqpin3: irqpin@e690000c {
103 compatible = "renesas,intc-irqpin";
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 reg = <0xe690000c 4>,
107 <0xe690001c 4>,
108 <0xe690002c 1>,
109 <0xe690004c 1>,
110 <0xe690006c 1>;
111 interrupt-parent = <&gic>;
112 interrupts = <0 25 0x4
113 0 26 0x4
114 0 27 0x4
115 0 28 0x4
116 0 29 0x4
117 0 30 0x4
118 0 31 0x4
119 0 32 0x4>;
120 };
121
41 i2c0: i2c@0xe6820000 { 122 i2c0: i2c@0xe6820000 {
42 #address-cells = <1>; 123 #address-cells = <1>;
43 #size-cells = <0>; 124 #size-cells = <0>;
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index ab2bb71db9b2..3933a315adf2 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -16,12 +16,30 @@ config ARCH_SH73A0
16 select CPU_V7 16 select CPU_V7
17 select I2C 17 select I2C
18 select SH_CLK_CPG 18 select SH_CLK_CPG
19 select RENESAS_INTC_IRQPIN
20
21config ARCH_R8A73A4
22 bool "R-Mobile APE6 (R8A73A40)"
23 select ARCH_WANT_OPTIONAL_GPIOLIB
24 select ARM_GIC
25 select CPU_V7
26 select ARM_ARCH_TIMER
27 select SH_CLK_CPG
28 select RENESAS_IRQC
19 29
20config ARCH_R8A7740 30config ARCH_R8A7740
21 bool "R-Mobile A1 (R8A77400)" 31 bool "R-Mobile A1 (R8A77400)"
22 select ARCH_WANT_OPTIONAL_GPIOLIB 32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select ARM_GIC
23 select CPU_V7 34 select CPU_V7
24 select SH_CLK_CPG 35 select SH_CLK_CPG
36 select RENESAS_INTC_IRQPIN
37
38config ARCH_R8A7778
39 bool "R-Car M1 (R8A77780)"
40 select CPU_V7
41 select SH_CLK_CPG
42 select ARM_GIC
25 43
26config ARCH_R8A7779 44config ARCH_R8A7779
27 bool "R-Car H1 (R8A77790)" 45 bool "R-Car H1 (R8A77790)"
@@ -31,6 +49,16 @@ config ARCH_R8A7779
31 select SH_CLK_CPG 49 select SH_CLK_CPG
32 select USB_ARCH_HAS_EHCI 50 select USB_ARCH_HAS_EHCI
33 select USB_ARCH_HAS_OHCI 51 select USB_ARCH_HAS_OHCI
52 select RENESAS_INTC_IRQPIN
53
54config ARCH_R8A7790
55 bool "R-Car H2 (R8A77900)"
56 select ARCH_WANT_OPTIONAL_GPIOLIB
57 select ARM_GIC
58 select CPU_V7
59 select ARM_ARCH_TIMER
60 select SH_CLK_CPG
61 select RENESAS_IRQC
34 62
35config ARCH_EMEV2 63config ARCH_EMEV2
36 bool "Emma Mobile EV2" 64 bool "Emma Mobile EV2"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index c621edfa6ead..0c9a2901370e 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -8,8 +8,11 @@ obj-y := timer.o console.o clock.o
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o 12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
12obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o 14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o
13obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o 16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
14 17
15# SMP objects 18# SMP objects
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 7a78f9486684..81db74acaa44 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -148,7 +148,7 @@
148 * see 148 * see
149 * usbhsf_power_ctrl() 149 * usbhsf_power_ctrl()
150 */ 150 */
151#define IRQ7 evt2irq(0x02e0) 151#define IRQ7 irq_pin(7)
152#define USBCR1 IOMEM(0xe605810a) 152#define USBCR1 IOMEM(0xe605810a)
153#define USBH 0xC6700000 153#define USBH 0xC6700000
154#define USBH_USBCTR 0x10834 154#define USBH_USBCTR 0x10834
@@ -333,7 +333,7 @@ static struct resource usbhsf_resources[] = {
333 .flags = IORESOURCE_MEM, 333 .flags = IORESOURCE_MEM,
334 }, 334 },
335 { 335 {
336 .start = evt2irq(0x0A20), 336 .start = gic_spi(51),
337 .flags = IORESOURCE_IRQ, 337 .flags = IORESOURCE_IRQ,
338 }, 338 },
339}; 339};
@@ -366,7 +366,7 @@ static struct resource sh_eth_resources[] = {
366 .end = 0xe9a02000 - 1, 366 .end = 0xe9a02000 - 1,
367 .flags = IORESOURCE_MEM, 367 .flags = IORESOURCE_MEM,
368 }, { 368 }, {
369 .start = evt2irq(0x0500), 369 .start = gic_spi(110),
370 .flags = IORESOURCE_IRQ, 370 .flags = IORESOURCE_IRQ,
371 }, 371 },
372}; 372};
@@ -420,7 +420,7 @@ static struct resource lcdc0_resources[] = {
420 .flags = IORESOURCE_MEM, 420 .flags = IORESOURCE_MEM,
421 }, 421 },
422 [1] = { 422 [1] = {
423 .start = intcs_evt2irq(0x580), 423 .start = gic_spi(177),
424 .flags = IORESOURCE_IRQ, 424 .flags = IORESOURCE_IRQ,
425 }, 425 },
426}; 426};
@@ -455,7 +455,7 @@ static struct resource hdmi_resources[] = {
455 .flags = IORESOURCE_MEM, 455 .flags = IORESOURCE_MEM,
456 }, 456 },
457 [1] = { 457 [1] = {
458 .start = evt2irq(0x1700), 458 .start = gic_spi(131),
459 .flags = IORESOURCE_IRQ, 459 .flags = IORESOURCE_IRQ,
460 }, 460 },
461 [2] = { 461 [2] = {
@@ -517,7 +517,7 @@ static struct resource hdmi_lcdc_resources[] = {
517 .flags = IORESOURCE_MEM, 517 .flags = IORESOURCE_MEM,
518 }, 518 },
519 [1] = { 519 [1] = {
520 .start = intcs_evt2irq(0x1780), 520 .start = gic_spi(178),
521 .flags = IORESOURCE_IRQ, 521 .flags = IORESOURCE_IRQ,
522 }, 522 },
523}; 523};
@@ -681,7 +681,7 @@ static struct platform_device vcc_sdhi1 = {
681 * We can use IRQ31 as card detect irq, 681 * We can use IRQ31 as card detect irq,
682 * but it needs chattering removal operation 682 * but it needs chattering removal operation
683 */ 683 */
684#define IRQ31 evt2irq(0x33E0) 684#define IRQ31 irq_pin(31)
685static struct sh_mobile_sdhi_info sdhi0_info = { 685static struct sh_mobile_sdhi_info sdhi0_info = {
686 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 686 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
687 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 687 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -703,12 +703,12 @@ static struct resource sdhi0_resources[] = {
703 */ 703 */
704 { 704 {
705 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 705 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
706 .start = evt2irq(0x0E20), 706 .start = gic_spi(118),
707 .flags = IORESOURCE_IRQ, 707 .flags = IORESOURCE_IRQ,
708 }, 708 },
709 { 709 {
710 .name = SH_MOBILE_SDHI_IRQ_SDIO, 710 .name = SH_MOBILE_SDHI_IRQ_SDIO,
711 .start = evt2irq(0x0E40), 711 .start = gic_spi(119),
712 .flags = IORESOURCE_IRQ, 712 .flags = IORESOURCE_IRQ,
713 }, 713 },
714}; 714};
@@ -742,15 +742,15 @@ static struct resource sdhi1_resources[] = {
742 .flags = IORESOURCE_MEM, 742 .flags = IORESOURCE_MEM,
743 }, 743 },
744 [1] = { 744 [1] = {
745 .start = evt2irq(0x0E80), 745 .start = gic_spi(121),
746 .flags = IORESOURCE_IRQ, 746 .flags = IORESOURCE_IRQ,
747 }, 747 },
748 [2] = { 748 [2] = {
749 .start = evt2irq(0x0EA0), 749 .start = gic_spi(122),
750 .flags = IORESOURCE_IRQ, 750 .flags = IORESOURCE_IRQ,
751 }, 751 },
752 [3] = { 752 [3] = {
753 .start = evt2irq(0x0EC0), 753 .start = gic_spi(123),
754 .flags = IORESOURCE_IRQ, 754 .flags = IORESOURCE_IRQ,
755 }, 755 },
756}; 756};
@@ -793,12 +793,12 @@ static struct resource sh_mmcif_resources[] = {
793 }, 793 },
794 [1] = { 794 [1] = {
795 /* MMC ERR */ 795 /* MMC ERR */
796 .start = evt2irq(0x1AC0), 796 .start = gic_spi(56),
797 .flags = IORESOURCE_IRQ, 797 .flags = IORESOURCE_IRQ,
798 }, 798 },
799 [2] = { 799 [2] = {
800 /* MMC NOR */ 800 /* MMC NOR */
801 .start = evt2irq(0x1AE0), 801 .start = gic_spi(57),
802 .flags = IORESOURCE_IRQ, 802 .flags = IORESOURCE_IRQ,
803 }, 803 },
804}; 804};
@@ -875,7 +875,7 @@ static struct resource ceu0_resources[] = {
875 .flags = IORESOURCE_MEM, 875 .flags = IORESOURCE_MEM,
876 }, 876 },
877 [1] = { 877 [1] = {
878 .start = intcs_evt2irq(0x0500), 878 .start = gic_spi(160),
879 .flags = IORESOURCE_IRQ, 879 .flags = IORESOURCE_IRQ,
880 }, 880 },
881 [2] = { 881 [2] = {
@@ -917,7 +917,7 @@ static struct resource fsi_resources[] = {
917 .flags = IORESOURCE_MEM, 917 .flags = IORESOURCE_MEM,
918 }, 918 },
919 [1] = { 919 [1] = {
920 .start = evt2irq(0x1840), 920 .start = gic_spi(9),
921 .flags = IORESOURCE_IRQ, 921 .flags = IORESOURCE_IRQ,
922 }, 922 },
923}; 923};
@@ -1000,7 +1000,7 @@ static struct platform_device i2c_gpio_device = {
1000static struct i2c_board_info i2c0_devices[] = { 1000static struct i2c_board_info i2c0_devices[] = {
1001 { 1001 {
1002 I2C_BOARD_INFO("st1232-ts", 0x55), 1002 I2C_BOARD_INFO("st1232-ts", 0x55),
1003 .irq = evt2irq(0x0340), 1003 .irq = irq_pin(10),
1004 }, 1004 },
1005 { 1005 {
1006 I2C_BOARD_INFO("wm8978", 0x1a), 1006 I2C_BOARD_INFO("wm8978", 0x1a),
@@ -1283,7 +1283,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
1283 .map_io = r8a7740_map_io, 1283 .map_io = r8a7740_map_io,
1284 .init_early = eva_add_early_devices, 1284 .init_early = eva_add_early_devices,
1285 .init_irq = r8a7740_init_irq, 1285 .init_irq = r8a7740_init_irq,
1286 .handle_irq = shmobile_handle_irq_intc,
1287 .init_machine = eva_init, 1286 .init_machine = eva_init,
1288 .init_late = shmobile_init_late, 1287 .init_late = shmobile_init_late,
1289 .init_time = eva_earlytimer_init, 1288 .init_time = eva_earlytimer_init,
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 77a66ac12417..e2d33243ef52 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -83,7 +83,7 @@ static struct resource smsc9221_resources[] = {
83 .flags = IORESOURCE_MEM, 83 .flags = IORESOURCE_MEM,
84 }, 84 },
85 [1] = { 85 [1] = {
86 .start = intcs_evt2irq(0x260), /* IRQ3 */ 86 .start = irq_pin(3), /* IRQ3 */
87 .flags = IORESOURCE_IRQ, 87 .flags = IORESOURCE_IRQ,
88 }, 88 },
89}; 89};
@@ -117,7 +117,7 @@ static struct resource usb_resources[] = {
117 .flags = IORESOURCE_MEM, 117 .flags = IORESOURCE_MEM,
118 }, 118 },
119 [1] = { 119 [1] = {
120 .start = intcs_evt2irq(0x220), /* IRQ1 */ 120 .start = irq_pin(1), /* IRQ1 */
121 .flags = IORESOURCE_IRQ, 121 .flags = IORESOURCE_IRQ,
122 }, 122 },
123}; 123};
@@ -140,7 +140,7 @@ struct usbhs_private {
140 struct renesas_usbhs_platform_info info; 140 struct renesas_usbhs_platform_info info;
141}; 141};
142 142
143#define IRQ15 intcs_evt2irq(0x03e0) 143#define IRQ15 irq_pin(15)
144#define USB_PHY_MODE (1 << 4) 144#define USB_PHY_MODE (1 << 4)
145#define USB_PHY_INT_EN ((1 << 3) | (1 << 2)) 145#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
146#define USB_PHY_ON (1 << 1) 146#define USB_PHY_ON (1 << 1)
@@ -615,25 +615,25 @@ static struct i2c_board_info i2c0_devices[] = {
615 }, 615 },
616 { 616 {
617 I2C_BOARD_INFO("ak8975", 0x0c), 617 I2C_BOARD_INFO("ak8975", 0x0c),
618 .irq = intcs_evt2irq(0x3380), /* IRQ28 */ 618 .irq = irq_pin(28), /* IRQ28 */
619 }, 619 },
620 { 620 {
621 I2C_BOARD_INFO("adxl34x", 0x1d), 621 I2C_BOARD_INFO("adxl34x", 0x1d),
622 .irq = intcs_evt2irq(0x3340), /* IRQ26 */ 622 .irq = irq_pin(26), /* IRQ26 */
623 }, 623 },
624}; 624};
625 625
626static struct i2c_board_info i2c1_devices[] = { 626static struct i2c_board_info i2c1_devices[] = {
627 { 627 {
628 I2C_BOARD_INFO("st1232-ts", 0x55), 628 I2C_BOARD_INFO("st1232-ts", 0x55),
629 .irq = intcs_evt2irq(0x300), /* IRQ8 */ 629 .irq = irq_pin(8), /* IRQ8 */
630 }, 630 },
631}; 631};
632 632
633static struct i2c_board_info i2c3_devices[] = { 633static struct i2c_board_info i2c3_devices[] = {
634 { 634 {
635 I2C_BOARD_INFO("pcf8575", 0x20), 635 I2C_BOARD_INFO("pcf8575", 0x20),
636 .irq = intcs_evt2irq(0x3260), /* IRQ19 */ 636 .irq = irq_pin(19), /* IRQ19 */
637 .platform_data = &pcf8575_pdata, 637 .platform_data = &pcf8575_pdata,
638 }, 638 },
639}; 639};
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 2333a2d7c937..91052855cc12 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,6 +25,7 @@
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/leds.h>
28#include <linux/dma-mapping.h> 29#include <linux/dma-mapping.h>
29#include <linux/pinctrl/machine.h> 30#include <linux/pinctrl/machine.h>
30#include <linux/regulator/fixed.h> 31#include <linux/regulator/fixed.h>
@@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = {
168 .num_resources = ARRAY_SIZE(usb_phy_resources), 169 .num_resources = ARRAY_SIZE(usb_phy_resources),
169}; 170};
170 171
172/* LEDS */
173static struct gpio_led marzen_leds[] = {
174 {
175 .name = "led2",
176 .gpio = 157,
177 .default_state = LEDS_GPIO_DEFSTATE_ON,
178 }, {
179 .name = "led3",
180 .gpio = 158,
181 .default_state = LEDS_GPIO_DEFSTATE_ON,
182 }, {
183 .name = "led4",
184 .gpio = 159,
185 .default_state = LEDS_GPIO_DEFSTATE_ON,
186 },
187};
188
189static struct gpio_led_platform_data marzen_leds_pdata = {
190 .leds = marzen_leds,
191 .num_leds = ARRAY_SIZE(marzen_leds),
192};
193
194static struct platform_device leds_device = {
195 .name = "leds-gpio",
196 .id = 0,
197 .dev = {
198 .platform_data = &marzen_leds_pdata,
199 },
200};
201
171static struct platform_device *marzen_devices[] __initdata = { 202static struct platform_device *marzen_devices[] __initdata = {
172 &eth_device, 203 &eth_device,
173 &sdhi0_device, 204 &sdhi0_device,
174 &thermal_device, 205 &thermal_device,
175 &hspi_device, 206 &hspi_device,
176 &usb_phy_device, 207 &usb_phy_device,
208 &leds_device,
177}; 209};
178 210
179/* USB */ 211/* USB */
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
new file mode 100644
index 000000000000..e710c00c3822
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -0,0 +1,115 @@
1/*
2 * r8a73a4 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x270
29
30#define MPCKCR 0xe6150080
31#define SMSTPCR2 0xe6150138
32#define SMSTPCR5 0xe6150144
33
34static struct clk_mapping cpg_mapping = {
35 .phys = CPG_BASE,
36 .len = CPG_LEN,
37};
38
39static struct clk extalr_clk = {
40 .rate = 32768,
41 .mapping = &cpg_mapping,
42};
43
44static struct clk extal1_clk = {
45 .rate = 26000000,
46 .mapping = &cpg_mapping,
47};
48
49static struct clk extal2_clk = {
50 .rate = 48000000,
51 .mapping = &cpg_mapping,
52};
53
54static struct clk *main_clks[] = {
55 &extalr_clk,
56 &extal1_clk,
57 &extal2_clk,
58};
59
60enum {
61 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
62 MSTP522,
63 MSTP_NR
64};
65
66static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
68 [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
69 [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
70 [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
71 [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
72 [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
73 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
74};
75
76static struct clk_lookup lookups[] = {
77 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
78 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
79 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
80 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
81 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
82 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
83 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
84
85 /* for DT */
86 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
87};
88
89void __init r8a73a4_clock_init(void)
90{
91 void __iomem *cpg_base, *reg;
92 int k, ret = 0;
93
94 /* fix MPCLK to EXTAL2 for now.
95 * this is needed until more detailed clock topology is supported
96 */
97 cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
98 BUG_ON(!cpg_base);
99 reg = cpg_base + (MPCKCR - CPG_BASE);
100 iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
101 iounmap(cpg_base);
102
103 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
104 ret = clk_register(main_clks[k]);
105
106 if (!ret)
107 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
108
109 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
110
111 if (!ret)
112 shmobile_clk_init();
113 else
114 panic("failed to setup r8a73a4 clocks\n");
115}
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 1feb9a2286a8..c0d39aa6de50 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/sh_clk.h> 23#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h>
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/r8a7740.h> 27#include <mach/r8a7740.h>
27 28
@@ -97,42 +98,13 @@ static struct clk dv_clk = {
97 .rate = 27000000, 98 .rate = 27000000,
98}; 99};
99 100
100static unsigned long div_recalc(struct clk *clk) 101SH_CLK_RATIO(div2, 1, 2);
101{ 102SH_CLK_RATIO(div1k, 1, 1024);
102 return clk->parent->rate / (int)(clk->priv);
103}
104
105static struct sh_clk_ops div_clk_ops = {
106 .recalc = div_recalc,
107};
108
109/* extal1 / 2 */
110static struct clk extal1_div2_clk = {
111 .ops = &div_clk_ops,
112 .priv = (void *)2,
113 .parent = &extal1_clk,
114};
115
116/* extal1 / 1024 */
117static struct clk extal1_div1024_clk = {
118 .ops = &div_clk_ops,
119 .priv = (void *)1024,
120 .parent = &extal1_clk,
121};
122
123/* extal1 / 2 / 1024 */
124static struct clk extal1_div2048_clk = {
125 .ops = &div_clk_ops,
126 .priv = (void *)1024,
127 .parent = &extal1_div2_clk,
128};
129 103
130/* extal2 / 2 */ 104SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
131static struct clk extal2_div2_clk = { 105SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
132 .ops = &div_clk_ops, 106SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
133 .priv = (void *)2, 107SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
134 .parent = &extal2_clk,
135};
136 108
137static struct sh_clk_ops followparent_clk_ops = { 109static struct sh_clk_ops followparent_clk_ops = {
138 .recalc = followparent_recalc, 110 .recalc = followparent_recalc,
@@ -143,11 +115,7 @@ static struct clk system_clk = {
143 .ops = &followparent_clk_ops, 115 .ops = &followparent_clk_ops,
144}; 116};
145 117
146static struct clk system_div2_clk = { 118SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
147 .ops = &div_clk_ops,
148 .priv = (void *)2,
149 .parent = &system_clk,
150};
151 119
152/* r_clk */ 120/* r_clk */
153static struct clk r_clk = { 121static struct clk r_clk = {
@@ -184,11 +152,7 @@ static struct clk pllc1_clk = {
184}; 152};
185 153
186/* PLLC1 / 2 */ 154/* PLLC1 / 2 */
187static struct clk pllc1_div2_clk = { 155SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
188 .ops = &div_clk_ops,
189 .priv = (void *)2,
190 .parent = &pllc1_clk,
191};
192 156
193/* USB clock */ 157/* USB clock */
194/* 158/*
@@ -323,6 +287,7 @@ struct clk *main_clks[] = {
323 &fsibck_clk, 287 &fsibck_clk,
324}; 288};
325 289
290/* DIV4 clocks */
326static void div4_kick(struct clk *clk) 291static void div4_kick(struct clk *clk)
327{ 292{
328 unsigned long value; 293 unsigned long value;
@@ -346,6 +311,26 @@ static struct clk_div4_table div4_table = {
346 .kick = div4_kick, 311 .kick = div4_kick,
347}; 312};
348 313
314enum {
315 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
316 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
317 DIV4_NR
318};
319
320struct clk div4_clks[DIV4_NR] = {
321 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
326 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
327 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
328 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
329 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
330 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
331 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
332};
333
349/* DIV6 reparent */ 334/* DIV6 reparent */
350enum { 335enum {
351 DIV6_HDMI, 336 DIV6_HDMI,
@@ -391,6 +376,16 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
391 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), 376 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
392}; 377};
393 378
379/* DIV6 clocks */
380enum {
381 DIV6_SUB,
382 DIV6_NR
383};
384
385static struct clk div6_clks[DIV6_NR] = {
386 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
387};
388
394/* HDMI1/2 clock */ 389/* HDMI1/2 clock */
395static unsigned long hdmi12_recalc(struct clk *clk) 390static unsigned long hdmi12_recalc(struct clk *clk)
396{ 391{
@@ -456,35 +451,6 @@ static struct clk fsidivs[] = {
456 451
457/* MSTP */ 452/* MSTP */
458enum { 453enum {
459 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
460 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
461 DIV4_NR
462};
463
464struct clk div4_clks[DIV4_NR] = {
465 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
466 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
467 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
468 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
469 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
470 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
471 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
472 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
473 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
474 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
475 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
476};
477
478enum {
479 DIV6_SUB,
480 DIV6_NR
481};
482
483static struct clk div6_clks[DIV6_NR] = {
484 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
485};
486
487enum {
488 MSTP128, MSTP127, MSTP125, 454 MSTP128, MSTP127, MSTP125,
489 MSTP116, MSTP111, MSTP100, MSTP117, 455 MSTP116, MSTP111, MSTP100, MSTP117,
490 456
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
new file mode 100644
index 000000000000..f1277f45381e
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -0,0 +1,104 @@
1/*
2 * r8a7778 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 * Copyright (C) 2011 Magnus Damm
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/io.h>
27#include <linux/sh_clk.h>
28#include <linux/clkdev.h>
29#include <mach/common.h>
30
31#define MSTPCR0 IOMEM(0xffc80030)
32#define MSTPCR1 IOMEM(0xffc80034)
33#define MSTPCR3 IOMEM(0xffc8003c)
34#define MSTPSR1 IOMEM(0xffc80044)
35#define MSTPSR4 IOMEM(0xffc80048)
36#define MSTPSR6 IOMEM(0xffc8004c)
37#define MSTPCR4 IOMEM(0xffc80050)
38#define MSTPCR5 IOMEM(0xffc80054)
39#define MSTPCR6 IOMEM(0xffc80058)
40
41/* ioremap() through clock mapping mandatory to avoid
42 * collision with ARM coherent DMA virtual memory range.
43 */
44
45static struct clk_mapping cpg_mapping = {
46 .phys = 0xffc80000,
47 .len = 0x80,
48};
49
50static struct clk clkp = {
51 .rate = 62500000, /* FIXME: shortcut */
52 .flags = CLK_ENABLE_ON_INIT,
53 .mapping = &cpg_mapping,
54};
55
56static struct clk *main_clks[] = {
57 &clkp,
58};
59
60enum {
61 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
62 MSTP016, MSTP015,
63 MSTP_NR };
64
65static struct clk mstp_clks[MSTP_NR] = {
66 [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
67 [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
68 [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
69 [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
70 [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
71 [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
72 [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
73 [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
74};
75
76static struct clk_lookup lookups[] = {
77 /* MSTP32 clocks */
78 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
79 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
80 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
81 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
82 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
83 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
84 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
85 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
86};
87
88void __init r8a7778_clock_init(void)
89{
90 int k, ret = 0;
91
92 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
93 ret = clk_register(main_clks[k]);
94
95 if (!ret)
96 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
97
98 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
99
100 if (!ret)
101 shmobile_clk_init();
102 else
103 panic("failed to setup r8a7778 clocks\n");
104}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index d9edeaf66007..7d86bfbb5b06 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -17,13 +17,17 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#include <linux/bitops.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <mach/clock.h>
25#include <mach/common.h> 27#include <mach/common.h>
26 28
29#define MD(nr) BIT(nr)
30
27#define FRQMR IOMEM(0xffc80014) 31#define FRQMR IOMEM(0xffc80014)
28#define MSTPCR0 IOMEM(0xffc80030) 32#define MSTPCR0 IOMEM(0xffc80030)
29#define MSTPCR1 IOMEM(0xffc80034) 33#define MSTPCR1 IOMEM(0xffc80034)
@@ -36,6 +40,9 @@
36#define MSTPCR6 IOMEM(0xffc80058) 40#define MSTPCR6 IOMEM(0xffc80058)
37#define MSTPCR7 IOMEM(0xffc80040) 41#define MSTPCR7 IOMEM(0xffc80040)
38 42
43#define MODEMR 0xffcc0020
44
45
39/* ioremap() through clock mapping mandatory to avoid 46/* ioremap() through clock mapping mandatory to avoid
40 * collision with ARM coherent DMA virtual memory range. 47 * collision with ARM coherent DMA virtual memory range.
41 */ 48 */
@@ -50,40 +57,39 @@ static struct clk_mapping cpg_mapping = {
50 * from the platform code. 57 * from the platform code.
51 */ 58 */
52static struct clk plla_clk = { 59static struct clk plla_clk = {
53 .rate = 1500000000, 60 /* .rate will be updated on r8a7779_clock_init() */
54 .mapping = &cpg_mapping, 61 .mapping = &cpg_mapping,
55}; 62};
56 63
64/*
65 * clock ratio of these clock will be updated
66 * on r8a7779_clock_init()
67 */
68SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
69SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
70SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
71SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
72SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
73SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
74SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
75SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
76SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
77SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
78SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
79
57static struct clk *main_clks[] = { 80static struct clk *main_clks[] = {
58 &plla_clk, 81 &plla_clk,
59}; 82 &clkz_clk,
60 83 &clkzs_clk,
61static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; 84 &clki_clk,
62 85 &clks_clk,
63static struct clk_div_mult_table div4_div_mult_table = { 86 &clks1_clk,
64 .divisors = divisors, 87 &clks3_clk,
65 .nr_divisors = ARRAY_SIZE(divisors), 88 &clks4_clk,
66}; 89 &clkb_clk,
67 90 &clkout_clk,
68static struct clk_div4_table div4_table = { 91 &clkp_clk,
69 .div_mult_table = &div4_div_mult_table, 92 &clkg_clk,
70};
71
72enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
73
74static struct clk div4_clks[DIV4_NR] = {
75 [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
76 0x0018, CLK_ENABLE_ON_INIT),
77 [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
78 0x0700, CLK_ENABLE_ON_INIT),
79 [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
80 0x0040, CLK_ENABLE_ON_INIT),
81 [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
82 0x0010, CLK_ENABLE_ON_INIT),
83 [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
84 0x0060, CLK_ENABLE_ON_INIT),
85 [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
86 0x0300, CLK_ENABLE_ON_INIT),
87}; 93};
88 94
89enum { MSTP323, MSTP322, MSTP321, MSTP320, 95enum { MSTP323, MSTP322, MSTP321, MSTP320,
@@ -96,52 +102,28 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320,
96 MSTP_NR }; 102 MSTP_NR };
97 103
98static struct clk mstp_clks[MSTP_NR] = { 104static struct clk mstp_clks[MSTP_NR] = {
99 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ 105 [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
100 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ 106 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
101 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ 107 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
102 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ 108 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
103 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ 109 [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
104 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ 110 [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
105 [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ 111 [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */
106 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ 112 [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */
107 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ 113 [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
108 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */ 114 [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
109 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */ 115 [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
110 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */ 116 [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
111 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ 117 [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
112 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ 118 [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
113 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ 119 [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
114 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ 120 [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
115 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ 121 [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
116 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ 122 [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
117 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ 123 [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
118 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ 124 [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
119 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ 125 [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
120 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */ 126 [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
121};
122
123static unsigned long mul4_recalc(struct clk *clk)
124{
125 return clk->parent->rate * 4;
126}
127
128static struct sh_clk_ops mul4_clk_ops = {
129 .recalc = mul4_recalc,
130};
131
132struct clk clkz_clk = {
133 .ops = &mul4_clk_ops,
134 .parent = &div4_clks[DIV4_S],
135};
136
137struct clk clkzs_clk = {
138 /* clks x 4 / 4 = clks */
139 .parent = &div4_clks[DIV4_S],
140};
141
142static struct clk *late_main_clks[] = {
143 &clkz_clk,
144 &clkzs_clk,
145}; 127};
146 128
147static struct clk_lookup lookups[] = { 129static struct clk_lookup lookups[] = {
@@ -151,12 +133,12 @@ static struct clk_lookup lookups[] = {
151 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), 133 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
152 134
153 /* DIV4 clocks */ 135 /* DIV4 clocks */
154 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), 136 CLKDEV_CON_ID("shyway_clk", &clks_clk),
155 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), 137 CLKDEV_CON_ID("bus_clk", &clkout_clk),
156 CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), 138 CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
157 CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), 139 CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
158 CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), 140 CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
159 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 141 CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
160 142
161 /* MSTP32 clocks */ 143 /* MSTP32 clocks */
162 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ 144 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
@@ -190,20 +172,60 @@ static struct clk_lookup lookups[] = {
190 172
191void __init r8a7779_clock_init(void) 173void __init r8a7779_clock_init(void)
192{ 174{
175 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
176 u32 mode;
193 int k, ret = 0; 177 int k, ret = 0;
194 178
179 BUG_ON(!modemr);
180 mode = ioread32(modemr);
181 iounmap(modemr);
182
183 if (mode & MD(1)) {
184 plla_clk.rate = 1500000000;
185
186 SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
187 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
188 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
189 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
190 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
191 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
192 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
193 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
194 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
195 if (mode & MD(2)) {
196 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
197 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
198 } else {
199 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
200 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
201 }
202 } else {
203 plla_clk.rate = 1600000000;
204
205 SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
206 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
207 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
208 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
209 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
210 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
211 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
212 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
213 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
214 if (mode & MD(2)) {
215 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
216 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
217 } else {
218 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
219 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
220 }
221 }
222
195 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 223 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
196 ret = clk_register(main_clks[k]); 224 ret = clk_register(main_clks[k]);
197 225
198 if (!ret) 226 if (!ret)
199 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
200
201 if (!ret)
202 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 227 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
203 228
204 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
205 ret = clk_register(late_main_clks[k]);
206
207 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 229 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
208 230
209 if (!ret) 231 if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
new file mode 100644
index 000000000000..bad9bf2e34d6
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -0,0 +1,93 @@
1/*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x1000
29
30#define SMSTPCR2 0xe6150138
31#define SMSTPCR7 0xe615014c
32
33static struct clk_mapping cpg_mapping = {
34 .phys = CPG_BASE,
35 .len = CPG_LEN,
36};
37
38static struct clk p_clk = {
39 .rate = 65000000, /* shortcut for now */
40 .mapping = &cpg_mapping,
41};
42
43static struct clk mp_clk = {
44 .rate = 52000000, /* shortcut for now */
45 .mapping = &cpg_mapping,
46};
47
48static struct clk *main_clks[] = {
49 &p_clk,
50 &mp_clk,
51};
52
53enum { MSTP721, MSTP720,
54 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
55static struct clk mstp_clks[MSTP_NR] = {
56 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
57 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
58 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
59 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
60 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
61 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
62 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
63 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
64};
65
66static struct clk_lookup lookups[] = {
67 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
68 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
69 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
70 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
71 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
72 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
73 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
74 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
75};
76
77void __init r8a7790_clock_init(void)
78{
79 int k, ret = 0;
80
81 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
82 ret = clk_register(main_clks[k]);
83
84 if (!ret)
85 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
86
87 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
88
89 if (!ret)
90 shmobile_clk_init();
91 else
92 panic("failed to setup r8a7790 clocks\n");
93}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 45d21fe317f4..7e105932c09d 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <mach/clock.h>
24#include <mach/common.h> 25#include <mach/common.h>
25 26
26/* SH7372 registers */ 27/* SH7372 registers */
@@ -83,39 +84,12 @@ struct clk sh7372_extal2_clk = {
83 .rate = 48000000, 84 .rate = 48000000,
84}; 85};
85 86
86/* A fixed divide-by-2 block */ 87SH_CLK_RATIO(div2, 1, 2);
87static unsigned long div2_recalc(struct clk *clk)
88{
89 return clk->parent->rate / 2;
90}
91
92static struct sh_clk_ops div2_clk_ops = {
93 .recalc = div2_recalc,
94};
95 88
96/* Divide dv_clki by two */ 89SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
97struct clk sh7372_dv_clki_div2_clk = { 90SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
98 .ops = &div2_clk_ops, 91SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
99 .parent = &sh7372_dv_clki_clk, 92SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
100};
101
102/* Divide extal1 by two */
103static struct clk extal1_div2_clk = {
104 .ops = &div2_clk_ops,
105 .parent = &sh7372_extal1_clk,
106};
107
108/* Divide extal2 by two */
109static struct clk extal2_div2_clk = {
110 .ops = &div2_clk_ops,
111 .parent = &sh7372_extal2_clk,
112};
113
114/* Divide extal2 by four */
115static struct clk extal2_div4_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &extal2_div2_clk,
118};
119 93
120/* PLLC0 and PLLC1 */ 94/* PLLC0 and PLLC1 */
121static unsigned long pllc01_recalc(struct clk *clk) 95static unsigned long pllc01_recalc(struct clk *clk)
@@ -147,10 +121,7 @@ static struct clk pllc1_clk = {
147}; 121};
148 122
149/* Divide PLLC1 by two */ 123/* Divide PLLC1 by two */
150static struct clk pllc1_div2_clk = { 124SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
151 .ops = &div2_clk_ops,
152 .parent = &pllc1_clk,
153};
154 125
155/* PLLC2 */ 126/* PLLC2 */
156 127
@@ -342,7 +313,7 @@ static struct clk_div4_table div4_table = {
342}; 313};
343 314
344enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, 315enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
345 DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, 316 DIV4_ZX, DIV4_HP,
346 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, 317 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
347 DIV4_DDRP, DIV4_NR }; 318 DIV4_DDRP, DIV4_NR };
348 319
@@ -355,8 +326,6 @@ static struct clk div4_clks[DIV4_NR] = {
355 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 326 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
356 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), 327 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
357 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), 328 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
358 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
359 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
360 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), 329 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
361 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), 330 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
362 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), 331 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
@@ -516,8 +485,6 @@ static struct clk_lookup lookups[] = {
516 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), 485 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
517 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), 486 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
518 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), 487 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
519 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
520 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
521 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), 488 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
522 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), 489 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
523 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), 490 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
@@ -654,5 +621,4 @@ void __init sh7372_clock_init(void)
654 shmobile_clk_init(); 621 shmobile_clk_init();
655 else 622 else
656 panic("failed to setup sh7372 clocks\n"); 623 panic("failed to setup sh7372 clocks\n");
657
658} 624}
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 71843dd39e16..784fbaa4cc55 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <asm/processor.h>
25#include <mach/clock.h>
24#include <mach/common.h> 26#include <mach/common.h>
25 27
26#define FRQCRA IOMEM(0xe6150000) 28#define FRQCRA IOMEM(0xe6150000)
@@ -82,61 +84,16 @@ struct clk sh73a0_extal2_clk = {
82 .rate = 48000000, 84 .rate = 48000000,
83}; 85};
84 86
85/* A fixed divide-by-2 block */
86static unsigned long div2_recalc(struct clk *clk)
87{
88 return clk->parent->rate / 2;
89}
90
91static struct sh_clk_ops div2_clk_ops = {
92 .recalc = div2_recalc,
93};
94
95static unsigned long div7_recalc(struct clk *clk)
96{
97 return clk->parent->rate / 7;
98}
99
100static struct sh_clk_ops div7_clk_ops = {
101 .recalc = div7_recalc,
102};
103
104static unsigned long div13_recalc(struct clk *clk)
105{
106 return clk->parent->rate / 13;
107}
108
109static struct sh_clk_ops div13_clk_ops = {
110 .recalc = div13_recalc,
111};
112
113/* Divide extal1 by two */
114static struct clk extal1_div2_clk = {
115 .ops = &div2_clk_ops,
116 .parent = &sh73a0_extal1_clk,
117};
118
119/* Divide extal2 by two */
120static struct clk extal2_div2_clk = {
121 .ops = &div2_clk_ops,
122 .parent = &sh73a0_extal2_clk,
123};
124
125static struct sh_clk_ops main_clk_ops = { 87static struct sh_clk_ops main_clk_ops = {
126 .recalc = followparent_recalc, 88 .recalc = followparent_recalc,
127}; 89};
128 90
129/* Main clock */ 91/* Main clock */
130static struct clk main_clk = { 92static struct clk main_clk = {
93 /* .parent wll be set on sh73a0_clock_init() */
131 .ops = &main_clk_ops, 94 .ops = &main_clk_ops,
132}; 95};
133 96
134/* Divide Main clock by two */
135static struct clk main_div2_clk = {
136 .ops = &div2_clk_ops,
137 .parent = &main_clk,
138};
139
140/* PLL0, PLL1, PLL2, PLL3 */ 97/* PLL0, PLL1, PLL2, PLL3 */
141static unsigned long pll_recalc(struct clk *clk) 98static unsigned long pll_recalc(struct clk *clk)
142{ 99{
@@ -192,21 +149,17 @@ static struct clk pll3_clk = {
192 .enable_bit = 3, 149 .enable_bit = 3,
193}; 150};
194 151
195/* Divide PLL */ 152/* A fixed divide block */
196static struct clk pll1_div2_clk = { 153SH_CLK_RATIO(div2, 1, 2);
197 .ops = &div2_clk_ops, 154SH_CLK_RATIO(div7, 1, 7);
198 .parent = &pll1_clk, 155SH_CLK_RATIO(div13, 1, 13);
199};
200
201static struct clk pll1_div7_clk = {
202 .ops = &div7_clk_ops,
203 .parent = &pll1_clk,
204};
205 156
206static struct clk pll1_div13_clk = { 157SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2);
207 .ops = &div13_clk_ops, 158SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2);
208 .parent = &pll1_clk, 159SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
209}; 160SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
161SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7);
162SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13);
210 163
211/* External input clock */ 164/* External input clock */
212struct clk sh73a0_extcki_clk = { 165struct clk sh73a0_extcki_clk = {
@@ -234,14 +187,24 @@ static struct clk *main_clks[] = {
234 &sh73a0_extalr_clk, 187 &sh73a0_extalr_clk,
235}; 188};
236 189
237static void div4_kick(struct clk *clk) 190static int frqcr_kick(void)
238{ 191{
239 unsigned long value; 192 int i;
193
194 /* set KICK bit in FRQCRB to update hardware setting, check success */
195 __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB);
196 for (i = 1000; i; i--)
197 if (__raw_readl(FRQCRB) & (1 << 31))
198 cpu_relax();
199 else
200 return i;
240 201
241 /* set KICK bit in FRQCRB to update hardware setting */ 202 return -ETIMEDOUT;
242 value = __raw_readl(FRQCRB); 203}
243 value |= (1 << 31); 204
244 __raw_writel(value, FRQCRB); 205static void div4_kick(struct clk *clk)
206{
207 frqcr_kick();
245} 208}
246 209
247static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 210static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
@@ -258,7 +221,7 @@ static struct clk_div4_table div4_table = {
258}; 221};
259 222
260enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, 223enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
261 DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; 224 DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR };
262 225
263#define DIV4(_reg, _bit, _mask, _flags) \ 226#define DIV4(_reg, _bit, _mask, _flags) \
264 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) 227 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
@@ -271,12 +234,24 @@ static struct clk div4_clks[DIV4_NR] = {
271 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), 234 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
272 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), 235 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
273 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), 236 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
274 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
275 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
276 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), 237 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
277 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), 238 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
278}; 239};
279 240
241static unsigned long twd_recalc(struct clk *clk)
242{
243 return clk_get_rate(clk->parent) / 4;
244}
245
246static struct sh_clk_ops twd_clk_ops = {
247 .recalc = twd_recalc,
248};
249
250static struct clk twd_clk = {
251 .parent = &div4_clks[DIV4_Z],
252 .ops = &twd_clk_ops,
253};
254
280enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, 255enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
281 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, 256 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
282 DIV6_FSIA, DIV6_FSIB, DIV6_SUB, 257 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -471,6 +446,7 @@ static struct clk dsi1phy_clk = {
471static struct clk *late_main_clks[] = { 446static struct clk *late_main_clks[] = {
472 &dsi0phy_clk, 447 &dsi0phy_clk,
473 &dsi1phy_clk, 448 &dsi1phy_clk,
449 &twd_clk,
474}; 450};
475 451
476enum { MSTP001, 452enum { MSTP001,
@@ -535,6 +511,7 @@ static struct clk mstp_clks[MSTP_NR] = {
535static struct clk_lookup lookups[] = { 511static struct clk_lookup lookups[] = {
536 /* main clocks */ 512 /* main clocks */
537 CLKDEV_CON_ID("r_clk", &r_clk), 513 CLKDEV_CON_ID("r_clk", &r_clk),
514 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
538 515
539 /* DIV6 clocks */ 516 /* DIV6 clocks */
540 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), 517 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index e816ca9bd213..ad7df629d995 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -23,6 +23,19 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
25#include <linux/export.h> 25#include <linux/export.h>
26#include <mach/clock.h>
27#include <mach/common.h>
28
29unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
30{
31 struct clk_ratio *p = clk->priv;
32
33 return clk->parent->rate / p->div * p->mul;
34};
35
36struct sh_clk_ops shmobile_fixed_ratio_clk_ops = {
37 .recalc = shmobile_fixed_ratio_clk_recalc,
38};
26 39
27int __init shmobile_clk_init(void) 40int __init shmobile_clk_init(void)
28{ 41{
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
new file mode 100644
index 000000000000..76ac61292e48
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -0,0 +1,39 @@
1#ifndef CLOCK_H
2#define CLOCK_H
3
4unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
5extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
6
7/* clock ratio */
8struct clk_ratio {
9 int mul;
10 int div;
11};
12
13#define SH_CLK_RATIO(name, m, d) \
14static struct clk_ratio name ##_ratio = { \
15 .mul = m, \
16 .div = d, \
17}
18
19#define SH_FIXED_RATIO_CLKg(name, p, r) \
20struct clk name = { \
21 .parent = &p, \
22 .ops = &shmobile_fixed_ratio_clk_ops,\
23 .priv = &r ## _ratio, \
24}
25
26#define SH_FIXED_RATIO_CLK(name, p, r) \
27static SH_FIXED_RATIO_CLKg(name, p, r);
28
29#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
30 SH_CLK_RATIO(name, m, d); \
31 SH_FIXED_RATIO_CLK(name, p, name);
32
33#define SH_CLK_SET_RATIO(p, m, d) \
34{ \
35 (p)->mul = m; \
36 (p)->div = d; \
37}
38
39#endif
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 86fcdf9fde1b..e002cfd9d2df 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -19,59 +19,6 @@ extern int shmobile_enter_wfi(struct cpuidle_device *dev,
19 struct cpuidle_driver *drv, int index); 19 struct cpuidle_driver *drv, int index);
20extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 20extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
21 21
22extern void sh7372_init_irq(void);
23extern void sh7372_map_io(void);
24extern void sh7372_earlytimer_init(void);
25extern void sh7372_add_early_devices(void);
26extern void sh7372_add_standard_devices(void);
27extern void sh7372_add_early_devices_dt(void);
28extern void sh7372_add_standard_devices_dt(void);
29extern void sh7372_clock_init(void);
30extern void sh7372_pinmux_init(void);
31extern void sh7372_pm_init(void);
32extern void sh7372_resume_core_standby_sysc(void);
33extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
34extern struct clk sh7372_extal1_clk;
35extern struct clk sh7372_extal2_clk;
36
37extern void sh73a0_init_delay(void);
38extern void sh73a0_init_irq(void);
39extern void sh73a0_init_irq_dt(void);
40extern void sh73a0_map_io(void);
41extern void sh73a0_earlytimer_init(void);
42extern void sh73a0_add_early_devices(void);
43extern void sh73a0_add_standard_devices(void);
44extern void sh73a0_add_standard_devices_dt(void);
45extern void sh73a0_clock_init(void);
46extern void sh73a0_pinmux_init(void);
47extern void sh73a0_pm_init(void);
48extern struct clk sh73a0_extal1_clk;
49extern struct clk sh73a0_extal2_clk;
50extern struct clk sh73a0_extcki_clk;
51extern struct clk sh73a0_extalr_clk;
52
53extern void r8a7740_meram_workaround(void);
54extern void r8a7740_init_irq(void);
55extern void r8a7740_map_io(void);
56extern void r8a7740_add_early_devices(void);
57extern void r8a7740_add_standard_devices(void);
58extern void r8a7740_clock_init(u8 md_ck);
59extern void r8a7740_pinmux_init(void);
60extern void r8a7740_pm_init(void);
61
62extern void r8a7779_init_delay(void);
63extern void r8a7779_init_irq(void);
64extern void r8a7779_init_irq_dt(void);
65extern void r8a7779_map_io(void);
66extern void r8a7779_earlytimer_init(void);
67extern void r8a7779_add_early_devices(void);
68extern void r8a7779_add_standard_devices(void);
69extern void r8a7779_add_standard_devices_dt(void);
70extern void r8a7779_clock_init(void);
71extern void r8a7779_pinmux_init(void);
72extern void r8a7779_pm_init(void);
73extern void r8a7779_register_twd(void);
74
75#ifdef CONFIG_SUSPEND 22#ifdef CONFIG_SUSPEND
76int shmobile_suspend_init(void); 23int shmobile_suspend_init(void);
77#else 24#else
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index 992ed213cec1..b2074e2acb15 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -12,4 +12,8 @@
12#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) 12#define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect))
13#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) 13#define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt))
14 14
15/* External IRQ pins */
16#define IRQPIN_BASE 2000
17#define irq_pin(nr) ((nr) + IRQPIN_BASE)
18
15#endif /* __ASM_MACH_IRQS_H */ 19#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
new file mode 100644
index 000000000000..f043103e32c9
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_R8A73A4_H__
2#define __ASM_R8A73A4_H__
3
4void r8a73a4_add_standard_devices(void);
5void r8a73a4_clock_init(void);
6void r8a73a4_pinmux_init(void);
7
8#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index c2583610ad36..abdc4d4efa28 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -532,6 +532,15 @@ enum {
532 SHDMA_SLAVE_USBHS_RX, 532 SHDMA_SLAVE_USBHS_RX,
533}; 533};
534 534
535extern void r8a7740_meram_workaround(void);
536extern void r8a7740_init_irq(void);
537extern void r8a7740_map_io(void);
538extern void r8a7740_add_early_devices(void);
539extern void r8a7740_add_standard_devices(void);
540extern void r8a7740_clock_init(u8 md_ck);
541extern void r8a7740_pinmux_init(void);
542extern void r8a7740_pm_init(void);
543
535#ifdef CONFIG_PM 544#ifdef CONFIG_PM
536extern void __init r8a7740_init_pm_domains(void); 545extern void __init r8a7740_init_pm_domains(void);
537#else 546#else
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
new file mode 100644
index 000000000000..a755dcafef4d
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -0,0 +1,28 @@
1/*
2 * Copyright (C) 2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ASM_R8A7778_H__
19#define __ASM_R8A7778_H__
20
21extern void r8a7778_add_standard_devices(void);
22extern void r8a7778_add_standard_devices_dt(void);
23extern void r8a7778_init_delay(void);
24extern void r8a7778_init_irq(void);
25extern void r8a7778_init_irq_dt(void);
26extern void r8a7778_clock_init(void);
27
28#endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 8ea0ad18cdff..945299ed1638 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,323 +4,6 @@
4#include <linux/sh_clk.h> 4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h> 5#include <linux/pm_domain.h>
6 6
7/* Pin Function Controller:
8 * GPIO_FN_xx - GPIO used to select pin function
9 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
10 */
11enum {
12 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
13 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
14 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
15 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
16 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
17 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
18 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
19 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
20
21 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
22 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
23 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
24 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
25 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
26 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
27 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
28 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
29
30 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
31 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
32 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
33 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
34 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
35 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
36 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
37 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
38
39 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
40 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
41 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
42 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
43 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
44 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
45 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
46 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
47
48 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
49 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
50 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
51 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
52 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
53 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
54 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
55 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
56
57 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
58 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
59 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
60 GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
61 GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
62 GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
63 GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
64 GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
65
66 GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
67 GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
68 GPIO_GP_6_8,
69
70 GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
71 GPIO_FN_A19,
72
73 /* IPSR0 */
74 GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
76 GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
77 GPIO_FN_HCTS1, GPIO_FN_A0,
78 GPIO_FN_FD3, GPIO_FN_A20,
79 GPIO_FN_A21,
80 GPIO_FN_A22, GPIO_FN_VI1_R0,
81 GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
82 GPIO_FN_A24, GPIO_FN_FD4,
83 GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
84 GPIO_FN_FD5,
85 GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
86 GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
87 GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
88 GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
89
90 /* IPSR1 */
91 GPIO_FN_FD6, GPIO_FN_FD7,
92 GPIO_FN_FALE,
93 GPIO_FN_ATACS00,
94 GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
95 GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
96 GPIO_FN_SSI_SDATA9,
97 GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
98 GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
99 GPIO_FN_FD1,
100 GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
101 GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
102 GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
103 GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
104 GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
105 GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
106 GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
107
108 /* IPSR2 */
109 GPIO_FN_HRX0, GPIO_FN_SCKZ,
110 GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
111 GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
112 GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
113 GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
114 GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
115 GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
116 GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
117 GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
118 GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
119 GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
120 GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
121 GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
122 GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
123 GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
124 GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
125 GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
126 GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
127 GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
128 GPIO_FN_AUDATA2,
129
130 /* IPSR3 */
131 GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
132 GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
133 GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
134 GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
135 GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
136 GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
137 GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
138 GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
139 GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
140 GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
141 GPIO_FN_LCDOUT23,
142 GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
143 GPIO_FN_QCLK,
144 GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
145 GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
146 GPIO_FN_QSTH_QHS,
147 GPIO_FN_QSTB_QHE,
148 GPIO_FN_QCPV_QDE,
149 GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
150
151 /* IPSR4 */
152 GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
153 GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
154 GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
155 GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
156 GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
157 GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
158 GPIO_FN_AUDSYNC,
159 GPIO_FN_VI2_G0,
160 GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
161 GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
162 GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
163 GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
164 GPIO_FN_VI2_DATA3_VI2_B3,
165 GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
166 GPIO_FN_VI2_G6,
167 GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
168 GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
169 GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
170 GPIO_FN_SCL2_B,
171
172 /* IPSR5 */
173 GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
174 GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
175 GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
176 GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
177 GPIO_FN_VI2_CLKENB,
178 GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
179 GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
180 GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
181 GPIO_FN_VI3_VSYNC,
182 GPIO_FN_VI2_CLK,
183 GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
184 GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
185 GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
186 GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
187 GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
188 GPIO_FN_VI2_DATA7_VI2_B7,
189 GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
190 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
191 GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
192 GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
193 GPIO_FN_MOUT0,
194
195 /* IPSR6 */
196 GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
197 GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
198 GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
199 GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
200 GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
201 GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
202 GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
203 GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
204 GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
205 GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
206 GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
207 GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
208 GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
209 GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
210 GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
211 GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
212
213 /* IPSR7 */
214 GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
215 GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
216 GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
217 GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
218 GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
219 GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
220 GPIO_FN_TCLK1_C,
221 GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
222 GPIO_FN_ATACS01,
223 GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
224 GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
225 GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
226 GPIO_FN_ATARD1, GPIO_FN_CC5_TCK,
227 GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI,
228 GPIO_FN_DREQ2, GPIO_FN_DACK2,
229
230 /* IPSR8 */
231 GPIO_FN_AD_CLK,
232 GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
233 GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
234 GPIO_FN_AD_DI,
235 GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
236 GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
237 GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
238 GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
239 GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
240 GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
241 GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
242 GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
243 GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
244 GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
245 GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
246 GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
247 GPIO_FN_HSCK1_B,
248 GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
249 GPIO_FN_PWMFSW0_C,
250
251 /* IPSR9 */
252 GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
253 GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
254 GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
255 GPIO_FN_VI0_DATA4_VI0_B4,
256 GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
257 GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
258 GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
259 GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
260 GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
261 GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
262 GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
263 GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
264 GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
265 GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
266 GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER,
267 GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
268 GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
269 GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
270
271 /* IPSR10 */
272 GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
273 GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
274 GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
275 GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
276 GPIO_FN_ARM_TRACEDATA_12,
277 GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
278 GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
279 GPIO_FN_ARM_TRACEDATA_14,
280 GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
281 GPIO_FN_ARM_TRACEDATA_15,
282 GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
283 GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
284 GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
285 GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
286 GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
287 GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
288 GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
289 GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
290 GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
291
292 /* IPSR11 */
293 GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
294 GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
295 GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
296 GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
297 GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
298 GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
299 GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
300 GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
301 GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
302 GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
303 GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
304 GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
305 GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
306 GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
307 GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
308 GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
309 GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
310 GPIO_FN_HRTS0_B,
311
312 /* IPSR12 */
313 GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
314 GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
315 GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
316 GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
317 GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
318 GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
319 GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
320 GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
321 GPIO_FN_GPS_MAG, GPIO_FN_FCE,
322};
323
324struct platform_device; 7struct platform_device;
325 8
326struct r8a7779_pm_ch { 9struct r8a7779_pm_ch {
@@ -339,6 +22,19 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
339 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; 22 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
340} 23}
341 24
25extern void r8a7779_init_delay(void);
26extern void r8a7779_init_irq(void);
27extern void r8a7779_init_irq_extpin(int irlm);
28extern void r8a7779_init_irq_dt(void);
29extern void r8a7779_map_io(void);
30extern void r8a7779_earlytimer_init(void);
31extern void r8a7779_add_early_devices(void);
32extern void r8a7779_add_standard_devices(void);
33extern void r8a7779_add_standard_devices_dt(void);
34extern void r8a7779_clock_init(void);
35extern void r8a7779_pinmux_init(void);
36extern void r8a7779_pm_init(void);
37extern void r8a7779_register_twd(void);
342extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); 38extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
343extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); 39extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
344 40
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
new file mode 100644
index 000000000000..9bd6f5c894bb
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_R8A7790_H__
2#define __ASM_R8A7790_H__
3
4void r8a7790_add_standard_devices(void);
5void r8a7790_clock_init(void);
6void r8a7790_pinmux_init(void);
7
8#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 7ded4ebaf5cc..fd7cba024c39 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -449,6 +449,18 @@ extern struct clk sh7372_dv_clki_clk;
449extern struct clk sh7372_dv_clki_div2_clk; 449extern struct clk sh7372_dv_clki_div2_clk;
450extern struct clk sh7372_pllc2_clk; 450extern struct clk sh7372_pllc2_clk;
451 451
452extern void sh7372_init_irq(void);
453extern void sh7372_map_io(void);
454extern void sh7372_earlytimer_init(void);
455extern void sh7372_add_early_devices(void);
456extern void sh7372_add_standard_devices(void);
457extern void sh7372_add_early_devices_dt(void);
458extern void sh7372_add_standard_devices_dt(void);
459extern void sh7372_clock_init(void);
460extern void sh7372_pinmux_init(void);
461extern void sh7372_pm_init(void);
462extern void sh7372_resume_core_standby_sysc(void);
463extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
452extern void sh7372_intcs_suspend(void); 464extern void sh7372_intcs_suspend(void);
453extern void sh7372_intcs_resume(void); 465extern void sh7372_intcs_resume(void);
454extern void sh7372_intca_suspend(void); 466extern void sh7372_intca_suspend(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index fbc1584d6712..eb7a4320d487 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -444,6 +444,21 @@ enum {
444#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) 444#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
445#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) 445#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
446 446
447extern void sh73a0_init_delay(void);
448extern void sh73a0_init_irq(void);
449extern void sh73a0_init_irq_dt(void);
450extern void sh73a0_map_io(void);
451extern void sh73a0_earlytimer_init(void);
452extern void sh73a0_add_early_devices(void);
453extern void sh73a0_add_standard_devices(void);
454extern void sh73a0_add_standard_devices_dt(void);
455extern void sh73a0_clock_init(void);
456extern void sh73a0_pinmux_init(void);
457extern void sh73a0_pm_init(void);
458extern struct clk sh73a0_extal1_clk;
459extern struct clk sh73a0_extal2_clk;
460extern struct clk sh73a0_extcki_clk;
461extern struct clk sh73a0_extalr_clk;
447extern struct smp_operations sh73a0_smp_ops; 462extern struct smp_operations sh73a0_smp_ops;
448 463
449#endif /* __ASM_SH73A0_H__ */ 464#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index 9a69a31918ba..b741c8409a5a 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -18,620 +18,39 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/kernel.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h> 22#include <linux/io.h>
26#include <linux/sh_intc.h> 23#include <linux/irqchip/arm-gic.h>
27#include <mach/intc.h>
28#include <mach/irqs.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/*
33 * INTCA
34 */
35enum {
36 UNUSED_INTCA = 0,
37
38 /* interrupt sources INTCA */
39 DIRC,
40 ATAPI,
41 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
42 AP_ARM_COMMTX, AP_ARM_COMMRX,
43 MFI, MFIS,
44 BBIF1, BBIF2,
45 USBHSDMAC,
46 USBF_OUL_SOF, USBF_IXL_INT,
47 SGX540,
48 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
49 CMT2,
50 CMT3,
51 KEYSC,
52 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
53 MSIOF2, MSIOF1,
54 SCIFA4, SCIFA5, SCIFB,
55 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
56 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
57 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
58 AP_ARM_L2CINT,
59 IRDA,
60 TPU0,
61 SCIFA6, SCIFA7,
62 GbEther,
63 ICBS0,
64 DDM,
65 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
66 RWDT0,
67 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
68 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
74 HDMI,
75 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
76 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
77 SPU2_0, SPU2_1,
78 FSI, FMSI,
79 HDMI_SSS, HDMI_KEY,
80 IPMMU,
81 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
82 MFIS2,
83 CPORTR2S,
84 CMT14, CMT15,
85 MMCIF_0, MMCIF_1, MMCIF_2,
86 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
87 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
88
89 /* interrupt groups INTCA */
90 DMAC1_1, DMAC1_2,
91 DMAC2_1, DMAC2_2,
92 DMAC3_1, DMAC3_2,
93 AP_ARM1, AP_ARM2,
94 SDHI0, SDHI1, SDHI2,
95 SHWYSTAT,
96 USBF, USBH1, USBH2,
97 RSPI, SPU2, FLCTL, IIC1,
98};
99
100static struct intc_vect intca_vectors[] __initdata = {
101 INTC_VECT(DIRC, 0x0560),
102 INTC_VECT(ATAPI, 0x05E0),
103 INTC_VECT(IIC1_ALI, 0x0780),
104 INTC_VECT(IIC1_TACKI, 0x07A0),
105 INTC_VECT(IIC1_WAITI, 0x07C0),
106 INTC_VECT(IIC1_DTEI, 0x07E0),
107 INTC_VECT(AP_ARM_COMMTX, 0x0840),
108 INTC_VECT(AP_ARM_COMMRX, 0x0860),
109 INTC_VECT(MFI, 0x0900),
110 INTC_VECT(MFIS, 0x0920),
111 INTC_VECT(BBIF1, 0x0940),
112 INTC_VECT(BBIF2, 0x0960),
113 INTC_VECT(USBHSDMAC, 0x0A00),
114 INTC_VECT(USBF_OUL_SOF, 0x0A20),
115 INTC_VECT(USBF_IXL_INT, 0x0A40),
116 INTC_VECT(SGX540, 0x0A60),
117 INTC_VECT(CMT1_0, 0x0B00),
118 INTC_VECT(CMT1_1, 0x0B20),
119 INTC_VECT(CMT1_2, 0x0B40),
120 INTC_VECT(CMT1_3, 0x0B60),
121 INTC_VECT(CMT2, 0x0B80),
122 INTC_VECT(CMT3, 0x0BA0),
123 INTC_VECT(KEYSC, 0x0BE0),
124 INTC_VECT(SCIFA0, 0x0C00),
125 INTC_VECT(SCIFA1, 0x0C20),
126 INTC_VECT(SCIFA2, 0x0C40),
127 INTC_VECT(SCIFA3, 0x0C60),
128 INTC_VECT(MSIOF2, 0x0C80),
129 INTC_VECT(MSIOF1, 0x0D00),
130 INTC_VECT(SCIFA4, 0x0D20),
131 INTC_VECT(SCIFA5, 0x0D40),
132 INTC_VECT(SCIFB, 0x0D60),
133 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
134 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
135 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
136 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
137 INTC_VECT(SDHI0_0, 0x0E00),
138 INTC_VECT(SDHI0_1, 0x0E20),
139 INTC_VECT(SDHI0_2, 0x0E40),
140 INTC_VECT(SDHI0_3, 0x0E60),
141 INTC_VECT(SDHI1_0, 0x0E80),
142 INTC_VECT(SDHI1_1, 0x0EA0),
143 INTC_VECT(SDHI1_2, 0x0EC0),
144 INTC_VECT(SDHI1_3, 0x0EE0),
145 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
146 INTC_VECT(IRDA, 0x0480),
147 INTC_VECT(TPU0, 0x04A0),
148 INTC_VECT(SCIFA6, 0x04C0),
149 INTC_VECT(SCIFA7, 0x04E0),
150 INTC_VECT(GbEther, 0x0500),
151 INTC_VECT(ICBS0, 0x0540),
152 INTC_VECT(DDM, 0x1140),
153 INTC_VECT(SDHI2_0, 0x1200),
154 INTC_VECT(SDHI2_1, 0x1220),
155 INTC_VECT(SDHI2_2, 0x1240),
156 INTC_VECT(SDHI2_3, 0x1260),
157 INTC_VECT(RWDT0, 0x1280),
158 INTC_VECT(DMAC1_1_DEI0, 0x2000),
159 INTC_VECT(DMAC1_1_DEI1, 0x2020),
160 INTC_VECT(DMAC1_1_DEI2, 0x2040),
161 INTC_VECT(DMAC1_1_DEI3, 0x2060),
162 INTC_VECT(DMAC1_2_DEI4, 0x2080),
163 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
164 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
165 INTC_VECT(DMAC2_1_DEI0, 0x2100),
166 INTC_VECT(DMAC2_1_DEI1, 0x2120),
167 INTC_VECT(DMAC2_1_DEI2, 0x2140),
168 INTC_VECT(DMAC2_1_DEI3, 0x2160),
169 INTC_VECT(DMAC2_2_DEI4, 0x2180),
170 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
171 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
172 INTC_VECT(DMAC3_1_DEI0, 0x2200),
173 INTC_VECT(DMAC3_1_DEI1, 0x2220),
174 INTC_VECT(DMAC3_1_DEI2, 0x2240),
175 INTC_VECT(DMAC3_1_DEI3, 0x2260),
176 INTC_VECT(DMAC3_2_DEI4, 0x2280),
177 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
178 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
179 INTC_VECT(SHWYSTAT_RT, 0x1300),
180 INTC_VECT(SHWYSTAT_HS, 0x1320),
181 INTC_VECT(SHWYSTAT_COM, 0x1340),
182 INTC_VECT(USBH_INT, 0x1540),
183 INTC_VECT(USBH_OHCI, 0x1560),
184 INTC_VECT(USBH_EHCI, 0x1580),
185 INTC_VECT(USBH_PME, 0x15A0),
186 INTC_VECT(USBH_BIND, 0x15C0),
187 INTC_VECT(HDMI, 0x1700),
188 INTC_VECT(RSPI_OVRF, 0x1780),
189 INTC_VECT(RSPI_SPTEF, 0x17A0),
190 INTC_VECT(RSPI_SPRF, 0x17C0),
191 INTC_VECT(SPU2_0, 0x1800),
192 INTC_VECT(SPU2_1, 0x1820),
193 INTC_VECT(FSI, 0x1840),
194 INTC_VECT(FMSI, 0x1860),
195 INTC_VECT(HDMI_SSS, 0x18A0),
196 INTC_VECT(HDMI_KEY, 0x18C0),
197 INTC_VECT(IPMMU, 0x1920),
198 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
199 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
200 INTC_VECT(MFIS2, 0x1A00),
201 INTC_VECT(CPORTR2S, 0x1A20),
202 INTC_VECT(CMT14, 0x1A40),
203 INTC_VECT(CMT15, 0x1A60),
204 INTC_VECT(MMCIF_0, 0x1AA0),
205 INTC_VECT(MMCIF_1, 0x1AC0),
206 INTC_VECT(MMCIF_2, 0x1AE0),
207 INTC_VECT(SIM_ERI, 0x1C00),
208 INTC_VECT(SIM_RXI, 0x1C20),
209 INTC_VECT(SIM_TXI, 0x1C40),
210 INTC_VECT(SIM_TEI, 0x1C60),
211 INTC_VECT(STPRO_0, 0x1C80),
212 INTC_VECT(STPRO_1, 0x1CA0),
213 INTC_VECT(STPRO_2, 0x1CC0),
214 INTC_VECT(STPRO_3, 0x1CE0),
215 INTC_VECT(STPRO_4, 0x1D00),
216};
217
218static struct intc_group intca_groups[] __initdata = {
219 INTC_GROUP(DMAC1_1,
220 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
221 INTC_GROUP(DMAC1_2,
222 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
223 INTC_GROUP(DMAC2_1,
224 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
225 INTC_GROUP(DMAC2_2,
226 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
227 INTC_GROUP(DMAC3_1,
228 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
229 INTC_GROUP(DMAC3_2,
230 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
231 INTC_GROUP(AP_ARM1,
232 AP_ARM_COMMTX, AP_ARM_COMMRX),
233 INTC_GROUP(AP_ARM2,
234 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
235 INTC_GROUP(USBF,
236 USBF_OUL_SOF, USBF_IXL_INT),
237 INTC_GROUP(SDHI0,
238 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
239 INTC_GROUP(SDHI1,
240 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
241 INTC_GROUP(SDHI2,
242 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
243 INTC_GROUP(SHWYSTAT,
244 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
245 INTC_GROUP(USBH1, /* FIXME */
246 USBH_INT, USBH_OHCI),
247 INTC_GROUP(USBH2, /* FIXME */
248 USBH_EHCI,
249 USBH_PME, USBH_BIND),
250 INTC_GROUP(RSPI,
251 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
252 INTC_GROUP(SPU2,
253 SPU2_0, SPU2_1),
254 INTC_GROUP(FLCTL,
255 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
256 INTC_GROUP(IIC1,
257 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
258};
259
260static struct intc_mask_reg intca_mask_registers[] __initdata = {
261 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
262 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
263 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
264 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
265 { ATAPI, 0, DIRC, 0,
266 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
267 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
268 { 0, 0, 0, 0,
269 BBIF1, BBIF2, MFIS, MFI } },
270 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
271 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
272 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
273 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
274 { DDM, 0, 0, 0,
275 0, 0, 0, 0 } },
276 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
277 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
278 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
279 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
280 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
281 0, 0, MSIOF2, 0 } },
282 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
283 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
284 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
285 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
286 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
287 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
288 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
289 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
290 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
291 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
292 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
293 0, 0, 0, 0 } },
294 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
295 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
296 ICBS0, 0, 0, 0 } },
297 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
298 { 0, 0, TPU0, SCIFA6,
299 SCIFA7, GbEther, 0, 0 } },
300 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
301 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
302 0, CMT3, 0, RWDT0 } },
303 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
304 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
305 0, 0, 0, 0 } },
306 /* IMR1A3 / IMCR1A3 */
307 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
308 { 0, 0, USBH_INT, USBH_OHCI,
309 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
310 /* IMR3A3 / IMCR3A3 */
311 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
312 { HDMI, 0, 0, 0,
313 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
314 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
315 { SPU2_0, SPU2_1, FSI, FMSI,
316 0, HDMI_SSS, HDMI_KEY, 0 } },
317 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
318 { 0, IPMMU, 0, 0,
319 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
320 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
321 { MFIS2, CPORTR2S, CMT14, CMT15,
322 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
323 /* IMR8A3 / IMCR8A3 */
324 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
325 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
326 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
327 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
328 { STPRO_4, 0, 0, 0,
329 0, 0, 0, 0 } },
330};
331
332static struct intc_prio_reg intca_prio_registers[] __initdata = {
333 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
334 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
335 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
336 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
337 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
338 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
339 SGX540, CMT1_0 } },
340 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
341 SCIFA2, SCIFA3 } },
342 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
343 FLCTL, SDHI0 } },
344 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
345 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
346 AP_ARM_L2CINT, 0 } },
347 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
348 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
349 SCIFA7, GbEther } },
350 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
351 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
352 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
353 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
354 /* IPRBA3 */
355 /* IPRCA3 */
356 /* IPRDA3 */
357 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
358 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
359 /* IPRGA3 */
360 /* IPRHA3 */
361 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
362 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
363 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
364 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
365 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
366 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
367 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
368 CMT14, CMT15 } },
369 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
370 /* IPRQA3 */
371 /* IPRRA3 */
372 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
373 SIM_TXI, SIM_TEI } },
374 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
375 STPRO_2, STPRO_3 } },
376 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
377};
378
379static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
380 intca_vectors, intca_groups,
381 intca_mask_registers, intca_prio_registers,
382 NULL);
383
384INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
385 INTC_VECT, "r8a7740-intca-irq-pins");
386
387
388/*
389 * INTCS
390 */
391enum {
392 UNUSED_INTCS = 0,
393
394 INTCS,
395
396 /* interrupt sources INTCS */
397
398 /* HUDI */
399 /* STPRO */
400 /* RTDMAC(1) */
401 VPU5HA2,
402 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
403 /* MFI */
404 /* BBIF2 */
405 VPU5F,
406 _2DG_BRK_INT,
407 /* SGX540 */
408 /* 2DDMAC */
409 /* IPMMU */
410 /* RTDMAC 2 */
411 /* KEYSC */
412 /* MSIOF */
413 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
414 TMU0_0, TMU0_1, TMU0_2,
415 CMT0,
416 /* CMT2 */
417 LMB,
418 CTI,
419 VOU,
420 /* RWDT0 */
421 ICB,
422 VIO6C,
423 CEU20, CEU21,
424 JPU,
425 LCDC0,
426 LCRC,
427 /* RTDMAC2(1) */
428 /* RTDMAC2(2) */
429 LCDC1,
430 /* SPU2 */
431 /* FSI */
432 /* FMSI */
433 TMU1_0, TMU1_1, TMU1_2,
434 CMT4,
435 DISP,
436 DSRV,
437 /* MFIS2 */
438 CPORTS2R,
439
440 /* interrupt groups INTCS */
441 _2DG1,
442 IIC0, TMU1,
443};
444
445static struct intc_vect intcs_vectors[] = {
446 /* HUDI */
447 /* STPRO */
448 /* RTDMAC(1) */
449 INTCS_VECT(VPU5HA2, 0x0880),
450 INTCS_VECT(_2DG_TRAP, 0x08A0),
451 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
452 INTCS_VECT(_2DG_CER_INT, 0x08E0),
453 /* MFI */
454 /* BBIF2 */
455 INTCS_VECT(VPU5F, 0x0980),
456 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
457 /* SGX540 */
458 /* 2DDMAC */
459 /* IPMMU */
460 /* RTDMAC(2) */
461 /* KEYSC */
462 /* MSIOF */
463 INTCS_VECT(IIC0_ALI, 0x0E00),
464 INTCS_VECT(IIC0_TACKI, 0x0E20),
465 INTCS_VECT(IIC0_WAITI, 0x0E40),
466 INTCS_VECT(IIC0_DTEI, 0x0E60),
467 INTCS_VECT(TMU0_0, 0x0E80),
468 INTCS_VECT(TMU0_1, 0x0EA0),
469 INTCS_VECT(TMU0_2, 0x0EC0),
470 INTCS_VECT(CMT0, 0x0F00),
471 /* CMT2 */
472 INTCS_VECT(LMB, 0x0F60),
473 INTCS_VECT(CTI, 0x0400),
474 INTCS_VECT(VOU, 0x0420),
475 /* RWDT0 */
476 INTCS_VECT(ICB, 0x0480),
477 INTCS_VECT(VIO6C, 0x04E0),
478 INTCS_VECT(CEU20, 0x0500),
479 INTCS_VECT(CEU21, 0x0520),
480 INTCS_VECT(JPU, 0x0560),
481 INTCS_VECT(LCDC0, 0x0580),
482 INTCS_VECT(LCRC, 0x05A0),
483 /* RTDMAC2(1) */
484 /* RTDMAC2(2) */
485 INTCS_VECT(LCDC1, 0x1780),
486 /* SPU2 */
487 /* FSI */
488 /* FMSI */
489 INTCS_VECT(TMU1_0, 0x1900),
490 INTCS_VECT(TMU1_1, 0x1920),
491 INTCS_VECT(TMU1_2, 0x1940),
492 INTCS_VECT(CMT4, 0x1980),
493 INTCS_VECT(DISP, 0x19A0),
494 INTCS_VECT(DSRV, 0x19C0),
495 /* MFIS2 */
496 INTCS_VECT(CPORTS2R, 0x1A20),
497
498 INTC_VECT(INTCS, 0xf80),
499};
500
501static struct intc_group intcs_groups[] __initdata = {
502 INTC_GROUP(_2DG1, /*FIXME*/
503 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
504 INTC_GROUP(IIC0,
505 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
506 INTC_GROUP(TMU1,
507 TMU1_0, TMU1_1, TMU1_2),
508};
509
510static struct intc_mask_reg intcs_mask_registers[] = {
511 /* IMR0SA / IMCR0SA */ /* all 0 */
512 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
513 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
514 0, 0, 0, 0 /*STPRO*/ } },
515 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
516 { 0/*STPRO*/, 0, CEU21, VPU5F,
517 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
518 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
519 { 0, 0, 0, 0, /*2DDMAC*/
520 VIO6C, 0, 0, ICB } },
521 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
522 { 0, 0, VOU, CTI,
523 JPU, 0, LCRC, LCDC0 } },
524 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
525 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
526 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
527 { 0, TMU0_2, TMU0_1, TMU0_0,
528 0, 0, 0, 0 } },
529 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
530 { 0, 0, 0, 0,
531 CEU20, 0, 0, 0 } },
532 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
533 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
534 0, 0, 0, 0 } },
535 /* IMR10SA / IMCR10SA */ /*IPMMU*/
536 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
537 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
538 0, _2DG_BRK_INT, LMB, 0 } },
539 /* IMR12SA / IMCR12SA */
540 /* IMR13SA / IMCR13SA */
541 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
542 /* IMR1SA3 / IMCR1SA3 */
543 /* IMR2SA3 / IMCR2SA3 */
544 /* IMR3SA3 / IMCR3SA3 */
545 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
546 { 0, 0, 0, 0,
547 LCDC1, 0, 0, 0 } },
548 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
549 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
550 { TMU1_0, TMU1_1, TMU1_2, 0,
551 CMT4, DISP, DSRV, 0 } },
552 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
553 { 0/*MFIS2*/, CPORTS2R, 0, 0,
554 0, 0, 0, 0 } },
555 { /* INTAMASK */ 0xffd20104, 0, 16,
556 { 0, 0, 0, 0, 0, 0, 0, 0,
557 0, 0, 0, 0, 0, 0, 0, INTCS } },
558};
559
560/* Priority is needed for INTCA to receive the INTCS interrupt */
561static struct intc_prio_reg intcs_prio_registers[] = {
562 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
563 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
564 /* IPRCS */ /*BBIF2*/
565 /* IPRDS */
566 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
567 0/*MFI*/, VPU5F } },
568 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
569 0/*CMT2*/, CMT0 } },
570 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
571 TMU0_2, _2DG1 } },
572 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
573 _2DG_BRK_INT/*FIXME*/ } },
574 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
575 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
576 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
577 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
578 /* IPRMS */ /*RWDT0*/
579 /* IPRAS3 */ /*RTDMAC2(1)*/
580 /* IPRBS3 */ /*RTDMAC2(2)*/
581 /* IPRCS3 */
582 /* IPRDS3 */
583 /* IPRES3 */
584 /* IPRFS3 */
585 /* IPRGS3 */
586 /* IPRHS3 */
587 /* IPRIS3 */
588 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
589 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
590 /* IPRLS3 */
591 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
592 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
593 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
594 /* IPRPS3 */
595};
596
597static struct resource intcs_resources[] __initdata = {
598 [0] = {
599 .start = 0xffd20000,
600 .end = 0xffd201ff,
601 .flags = IORESOURCE_MEM,
602 },
603 [1] = {
604 .start = 0xffd50000,
605 .end = 0xffd501ff,
606 .flags = IORESOURCE_MEM,
607 }
608};
609
610static struct intc_desc intcs_desc __initdata = {
611 .name = "r8a7740-intcs",
612 .resource = intcs_resources,
613 .num_resources = ARRAY_SIZE(intcs_resources),
614 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
615 intcs_prio_registers, NULL, NULL),
616};
617
618static void intcs_demux(unsigned int irq, struct irq_desc *desc)
619{
620 void __iomem *reg = (void *)irq_get_handler_data(irq);
621 unsigned int evtcodeas = ioread32(reg);
622
623 generic_handle_irq(intcs_evt2irq(evtcodeas));
624}
625 24
626void __init r8a7740_init_irq(void) 25void __init r8a7740_init_irq(void)
627{ 26{
628 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 27 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
629 28 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
630 register_intc_controller(&intca_desc); 29 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
631 register_intc_controller(&intca_irq_pins_desc); 30 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
632 register_intc_controller(&intcs_desc); 31 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
633 32
634 /* demux using INTEVTSA */ 33 /* initialize the Generic Interrupt Controller PL390 r0p0 */
635 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); 34 gic_init(0, 29, gic_dist_base, gic_cpu_base);
636 irq_set_chained_handler(evt2irq(0xf80), intcs_demux); 35
36 /* route signals to GIC */
37 iowrite32(0x0, pfc_inta_ctrl);
38
39 /*
40 * To mask the shared interrupt to SPI 149 we must ensure to set
41 * PRIO *and* MASK. Else we run into IRQ floods when registering
42 * the intc_irqpin devices
43 */
44 iowrite32(0x0, intc_prio_base + 0x0);
45 iowrite32(0x0, intc_prio_base + 0x4);
46 iowrite32(0x0, intc_prio_base + 0x8);
47 iowrite32(0x0, intc_prio_base + 0xc);
48 iowrite8(0xff, intc_msk_base + 0x0);
49 iowrite8(0xff, intc_msk_base + 0x4);
50 iowrite8(0xff, intc_msk_base + 0x8);
51 iowrite8(0xff, intc_msk_base + 0xc);
52
53 iounmap(intc_prio_base);
54 iounmap(intc_msk_base);
55 iounmap(pfc_inta_ctrl);
637} 56}
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index f9cc4bc9c798..b86dc8908724 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -19,13 +19,16 @@
19 */ 19 */
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/platform_device.h>
22#include <linux/interrupt.h> 23#include <linux/interrupt.h>
23#include <linux/irq.h> 24#include <linux/irq.h>
24#include <linux/io.h> 25#include <linux/io.h>
25#include <linux/irqchip/arm-gic.h> 26#include <linux/irqchip/arm-gic.h>
26#include <mach/common.h> 27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
27#include <linux/irqchip.h> 28#include <linux/irqchip.h>
29#include <mach/common.h>
28#include <mach/intc.h> 30#include <mach/intc.h>
31#include <mach/irqs.h>
29#include <mach/r8a7779.h> 32#include <mach/r8a7779.h>
30#include <asm/mach-types.h> 33#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
@@ -39,6 +42,54 @@
39#define INT2NTSR0 IOMEM(0xfe700060) 42#define INT2NTSR0 IOMEM(0xfe700060)
40#define INT2NTSR1 IOMEM(0xfe700064) 43#define INT2NTSR1 IOMEM(0xfe700064)
41 44
45static struct renesas_intc_irqpin_config irqpin0_platform_data = {
46 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
47 .sense_bitfield_width = 2,
48};
49
50static struct resource irqpin0_resources[] = {
51 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
52 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
53 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
54 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
55 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
56 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
57 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
58 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
59 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
60};
61
62static struct platform_device irqpin0_device = {
63 .name = "renesas_intc_irqpin",
64 .id = 0,
65 .resource = irqpin0_resources,
66 .num_resources = ARRAY_SIZE(irqpin0_resources),
67 .dev = {
68 .platform_data = &irqpin0_platform_data,
69 },
70};
71
72void __init r8a7779_init_irq_extpin(int irlm)
73{
74 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
75 unsigned long tmp;
76
77 if (icr0) {
78 tmp = ioread32(icr0);
79 if (irlm)
80 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
81 else
82 tmp &= ~(1 << 23); /* IRL mode - not supported */
83 tmp |= (1 << 21); /* LVLMODE = 1 */
84 iowrite32(tmp, icr0);
85 iounmap(icr0);
86
87 if (irlm)
88 platform_device_register(&irqpin0_device);
89 } else
90 pr_warn("r8a7779: unable to setup external irq pin mode\n");
91}
92
42static int r8a7779_set_wake(struct irq_data *data, unsigned int on) 93static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
43{ 94{
44 return 0; /* always allow wakeup */ 95 return 0; /* always allow wakeup */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index a81a1d804e2e..19a26f4579b3 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -260,108 +260,6 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
260 return 0; /* always allow wakeup */ 260 return 0; /* always allow wakeup */
261} 261}
262 262
263#define RELOC_BASE 0x1200
264
265/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
266#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
267
268INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
269 INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
270
271static int to_gic_irq(struct irq_data *data)
272{
273 unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
274
275 if (vect >= 0x3200)
276 vect -= 0x3000;
277 else
278 vect -= 0x0200;
279
280 return gic_spi((vect >> 5) + 1);
281}
282
283static int to_intca_reloc_irq(struct irq_data *data)
284{
285 return data->irq + (RELOC_BASE >> 5);
286}
287
288#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
289#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
290
291static void intca_gic_enable(struct irq_data *data)
292{
293 irq_cb(irq_unmask, to_intca_reloc_irq(data));
294 irq_cb(irq_unmask, to_gic_irq(data));
295}
296
297static void intca_gic_disable(struct irq_data *data)
298{
299 irq_cb(irq_mask, to_gic_irq(data));
300 irq_cb(irq_mask, to_intca_reloc_irq(data));
301}
302
303static void intca_gic_mask_ack(struct irq_data *data)
304{
305 irq_cb(irq_mask, to_gic_irq(data));
306 irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
307}
308
309static void intca_gic_eoi(struct irq_data *data)
310{
311 irq_cb(irq_eoi, to_gic_irq(data));
312}
313
314static int intca_gic_set_type(struct irq_data *data, unsigned int type)
315{
316 return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
317}
318
319#ifdef CONFIG_SMP
320static int intca_gic_set_affinity(struct irq_data *data,
321 const struct cpumask *cpumask,
322 bool force)
323{
324 return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
325}
326#endif
327
328struct irq_chip intca_gic_irq_chip = {
329 .name = "INTCA-GIC",
330 .irq_mask = intca_gic_disable,
331 .irq_unmask = intca_gic_enable,
332 .irq_mask_ack = intca_gic_mask_ack,
333 .irq_eoi = intca_gic_eoi,
334 .irq_enable = intca_gic_enable,
335 .irq_disable = intca_gic_disable,
336 .irq_shutdown = intca_gic_disable,
337 .irq_set_type = intca_gic_set_type,
338 .irq_set_wake = sh73a0_set_wake,
339#ifdef CONFIG_SMP
340 .irq_set_affinity = intca_gic_set_affinity,
341#endif
342};
343
344static int to_intc_vect(int irq)
345{
346 unsigned int irq_pin = irq - gic_spi(1);
347 unsigned int offs;
348
349 if (irq_pin < 16)
350 offs = 0x0200;
351 else
352 offs = 0x3000;
353
354 return offs + (irq_pin << 5);
355}
356
357static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
358{
359 generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
360 return IRQ_HANDLED;
361}
362
363static struct irqaction sh73a0_irq_pin_cascade[32];
364
365#define PINTER0_PHYS 0xe69000a0 263#define PINTER0_PHYS 0xe69000a0
366#define PINTER1_PHYS 0xe69000a4 264#define PINTER1_PHYS 0xe69000a4
367#define PINTER0_VIRT IOMEM(0xe69000a0) 265#define PINTER0_VIRT IOMEM(0xe69000a0)
@@ -422,13 +320,11 @@ void __init sh73a0_init_irq(void)
422 void __iomem *gic_dist_base = IOMEM(0xf0001000); 320 void __iomem *gic_dist_base = IOMEM(0xf0001000);
423 void __iomem *gic_cpu_base = IOMEM(0xf0000100); 321 void __iomem *gic_cpu_base = IOMEM(0xf0000100);
424 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 322 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
425 int k, n;
426 323
427 gic_init(0, 29, gic_dist_base, gic_cpu_base); 324 gic_init(0, 29, gic_dist_base, gic_cpu_base);
428 gic_arch_extn.irq_set_wake = sh73a0_set_wake; 325 gic_arch_extn.irq_set_wake = sh73a0_set_wake;
429 326
430 register_intc_controller(&intcs_desc); 327 register_intc_controller(&intcs_desc);
431 register_intc_controller(&intca_irq_pins_desc);
432 register_intc_controller(&intc_pint0_desc); 328 register_intc_controller(&intc_pint0_desc);
433 register_intc_controller(&intc_pint1_desc); 329 register_intc_controller(&intc_pint1_desc);
434 330
@@ -438,19 +334,6 @@ void __init sh73a0_init_irq(void)
438 sh73a0_intcs_cascade.dev_id = intevtsa; 334 sh73a0_intcs_cascade.dev_id = intevtsa;
439 setup_irq(gic_spi(50), &sh73a0_intcs_cascade); 335 setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
440 336
441 /* IRQ pins require special handling through INTCA and GIC */
442 for (k = 0; k < 32; k++) {
443 sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
444 sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
445 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
446
447 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
448 WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
449 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
450 handle_level_irq, "level");
451 set_irq_flags(n, IRQF_VALID); /* yuck */
452 }
453
454 /* PINT pins are sanely tied to the GIC as SPI */ 337 /* PINT pins are sanely tied to the GIC as SPI */
455 sh73a0_pint0_cascade.name = "PINT0 cascade"; 338 sh73a0_pint0_cascade.name = "PINT0 cascade";
456 sh73a0_pint0_cascade.handler = sh73a0_pint0_demux; 339 sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
new file mode 100644
index 000000000000..c5a75a7a508f
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -0,0 +1,202 @@
1/*
2 * r8a73a4 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/irq.h>
21#include <linux/irqchip.h>
22#include <linux/kernel.h>
23#include <linux/of_platform.h>
24#include <linux/platform_data/irq-renesas-irqc.h>
25#include <linux/serial_sci.h>
26#include <mach/common.h>
27#include <mach/irqs.h>
28#include <mach/r8a73a4.h>
29#include <asm/mach/arch.h>
30
31static const struct resource pfc_resources[] = {
32 DEFINE_RES_MEM(0xe6050000, 0x9000),
33};
34
35void __init r8a73a4_pinmux_init(void)
36{
37 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
38 ARRAY_SIZE(pfc_resources));
39}
40
41#define SCIF_COMMON(scif_type, baseaddr, irq) \
42 .type = scif_type, \
43 .mapbase = baseaddr, \
44 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
45 .scbrr_algo_id = SCBRR_ALGO_4, \
46 .irqs = SCIx_IRQ_MUXED(irq)
47
48#define SCIFA_DATA(index, baseaddr, irq) \
49[index] = { \
50 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
52}
53
54#define SCIFB_DATA(index, baseaddr, irq) \
55[index] = { \
56 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
57 .scscr = SCSCR_RE | SCSCR_TE, \
58}
59
60enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
61
62static const struct plat_sci_port scif[] = {
63 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
64 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
65 SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
66 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
67 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
68 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
69};
70
71static inline void r8a73a4_register_scif(int idx)
72{
73 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
74 sizeof(struct plat_sci_port));
75}
76
77static const struct renesas_irqc_config irqc0_data = {
78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
79};
80
81static const struct resource irqc0_resources[] = {
82 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
83 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
84 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
85 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
86 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
87 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
88 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
89 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
90 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
91 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
92 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
93 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
94 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
95 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
96 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
97 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
98 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
99 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
100 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
101 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
102 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
103 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
104 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
105 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
106 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
107 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
108 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
109 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
110 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
111 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
112 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
113 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
114 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
115};
116
117static const struct renesas_irqc_config irqc1_data = {
118 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
119};
120
121static const struct resource irqc1_resources[] = {
122 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
123 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
124 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
125 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
126 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
127 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
128 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
129 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
130 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
131 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
132 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
133 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
134 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
135 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
136 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
137 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
138 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
139 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
140 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
141 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
142 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
143 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
144 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
145 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
146 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
147 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
148 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
149};
150
151#define r8a73a4_register_irqc(idx) \
152 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
153 idx, irqc##idx##_resources, \
154 ARRAY_SIZE(irqc##idx##_resources), \
155 &irqc##idx##_data, \
156 sizeof(struct renesas_irqc_config))
157
158/* Thermal0 -> Thermal2 */
159static const struct resource thermal0_resources[] = {
160 DEFINE_RES_MEM(0xe61f0000, 0x14),
161 DEFINE_RES_MEM(0xe61f0100, 0x38),
162 DEFINE_RES_MEM(0xe61f0200, 0x38),
163 DEFINE_RES_MEM(0xe61f0300, 0x38),
164 DEFINE_RES_IRQ(gic_spi(69)),
165};
166
167#define r8a73a4_register_thermal() \
168 platform_device_register_simple("rcar_thermal", -1, \
169 thermal0_resources, \
170 ARRAY_SIZE(thermal0_resources))
171
172void __init r8a73a4_add_standard_devices(void)
173{
174 r8a73a4_register_scif(SCIFA0);
175 r8a73a4_register_scif(SCIFA1);
176 r8a73a4_register_scif(SCIFB0);
177 r8a73a4_register_scif(SCIFB1);
178 r8a73a4_register_scif(SCIFB2);
179 r8a73a4_register_scif(SCIFB3);
180 r8a73a4_register_irqc(0);
181 r8a73a4_register_irqc(1);
182 r8a73a4_register_thermal();
183}
184
185#ifdef CONFIG_USE_OF
186void __init r8a73a4_add_standard_devices_dt(void)
187{
188 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
189}
190
191static const char *r8a73a4_boards_compat_dt[] __initdata = {
192 "renesas,r8a73a4",
193 NULL,
194};
195
196DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
197 .init_irq = irqchip_init,
198 .init_machine = r8a73a4_add_standard_devices_dt,
199 .init_time = shmobile_timer_init,
200 .dt_compat = r8a73a4_boards_compat_dt,
201MACHINE_END
202#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8b85d4d8fab6..228d7aba4a7c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_data/irq-renesas-intc-irqpin.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/of_platform.h> 27#include <linux/of_platform.h>
27#include <linux/serial_sci.h> 28#include <linux/serial_sci.h>
@@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void)
94 platform_device_register(&r8a7740_pfc_device); 95 platform_device_register(&r8a7740_pfc_device);
95} 96}
96 97
98static struct renesas_intc_irqpin_config irqpin0_platform_data = {
99 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
100};
101
102static struct resource irqpin0_resources[] = {
103 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
104 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
105 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
106 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
107 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
108 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
109 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
110 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
111 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
112 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
113 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
114 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
115 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
116};
117
118static struct platform_device irqpin0_device = {
119 .name = "renesas_intc_irqpin",
120 .id = 0,
121 .resource = irqpin0_resources,
122 .num_resources = ARRAY_SIZE(irqpin0_resources),
123 .dev = {
124 .platform_data = &irqpin0_platform_data,
125 },
126};
127
128static struct renesas_intc_irqpin_config irqpin1_platform_data = {
129 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
130};
131
132static struct resource irqpin1_resources[] = {
133 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
134 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
135 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
136 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
137 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
138 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
139 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
140 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
141 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
142 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
143 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
144 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
145 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
146};
147
148static struct platform_device irqpin1_device = {
149 .name = "renesas_intc_irqpin",
150 .id = 1,
151 .resource = irqpin1_resources,
152 .num_resources = ARRAY_SIZE(irqpin1_resources),
153 .dev = {
154 .platform_data = &irqpin1_platform_data,
155 },
156};
157
158static struct renesas_intc_irqpin_config irqpin2_platform_data = {
159 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
160};
161
162static struct resource irqpin2_resources[] = {
163 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
164 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
165 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
166 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
167 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
168 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
169 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
170 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
171 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
172 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
173 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
174 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
175 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
176};
177
178static struct platform_device irqpin2_device = {
179 .name = "renesas_intc_irqpin",
180 .id = 2,
181 .resource = irqpin2_resources,
182 .num_resources = ARRAY_SIZE(irqpin2_resources),
183 .dev = {
184 .platform_data = &irqpin2_platform_data,
185 },
186};
187
188static struct renesas_intc_irqpin_config irqpin3_platform_data = {
189 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
190};
191
192static struct resource irqpin3_resources[] = {
193 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
194 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
195 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
196 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
197 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
198 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
199 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
200 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
201 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
202 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
203 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
204 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
205 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
206};
207
208static struct platform_device irqpin3_device = {
209 .name = "renesas_intc_irqpin",
210 .id = 3,
211 .resource = irqpin3_resources,
212 .num_resources = ARRAY_SIZE(irqpin3_resources),
213 .dev = {
214 .platform_data = &irqpin3_platform_data,
215 },
216};
217
97/* SCIFA0 */ 218/* SCIFA0 */
98static struct plat_sci_port scif0_platform_data = { 219static struct plat_sci_port scif0_platform_data = {
99 .mapbase = 0xe6c40000, 220 .mapbase = 0xe6c40000,
@@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = {
101 .scscr = SCSCR_RE | SCSCR_TE, 222 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4, 223 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA, 224 .type = PORT_SCIFA,
104 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), 225 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
105}; 226};
106 227
107static struct platform_device scif0_device = { 228static struct platform_device scif0_device = {
@@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = {
119 .scscr = SCSCR_RE | SCSCR_TE, 240 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4, 241 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA, 242 .type = PORT_SCIFA,
122 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), 243 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
123}; 244};
124 245
125static struct platform_device scif1_device = { 246static struct platform_device scif1_device = {
@@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = {
137 .scscr = SCSCR_RE | SCSCR_TE, 258 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4, 259 .scbrr_algo_id = SCBRR_ALGO_4,
139 .type = PORT_SCIFA, 260 .type = PORT_SCIFA,
140 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), 261 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
141}; 262};
142 263
143static struct platform_device scif2_device = { 264static struct platform_device scif2_device = {
@@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = {
155 .scscr = SCSCR_RE | SCSCR_TE, 276 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4, 277 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA, 278 .type = PORT_SCIFA,
158 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), 279 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
159}; 280};
160 281
161static struct platform_device scif3_device = { 282static struct platform_device scif3_device = {
@@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE, 294 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4, 295 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFA, 296 .type = PORT_SCIFA,
176 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), 297 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
177}; 298};
178 299
179static struct platform_device scif4_device = { 300static struct platform_device scif4_device = {
@@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = {
191 .scscr = SCSCR_RE | SCSCR_TE, 312 .scscr = SCSCR_RE | SCSCR_TE,
192 .scbrr_algo_id = SCBRR_ALGO_4, 313 .scbrr_algo_id = SCBRR_ALGO_4,
193 .type = PORT_SCIFA, 314 .type = PORT_SCIFA,
194 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), 315 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
195}; 316};
196 317
197static struct platform_device scif5_device = { 318static struct platform_device scif5_device = {
@@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = {
209 .scscr = SCSCR_RE | SCSCR_TE, 330 .scscr = SCSCR_RE | SCSCR_TE,
210 .scbrr_algo_id = SCBRR_ALGO_4, 331 .scbrr_algo_id = SCBRR_ALGO_4,
211 .type = PORT_SCIFA, 332 .type = PORT_SCIFA,
212 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), 333 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
213}; 334};
214 335
215static struct platform_device scif6_device = { 336static struct platform_device scif6_device = {
@@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = {
227 .scscr = SCSCR_RE | SCSCR_TE, 348 .scscr = SCSCR_RE | SCSCR_TE,
228 .scbrr_algo_id = SCBRR_ALGO_4, 349 .scbrr_algo_id = SCBRR_ALGO_4,
229 .type = PORT_SCIFA, 350 .type = PORT_SCIFA,
230 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), 351 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
231}; 352};
232 353
233static struct platform_device scif7_device = { 354static struct platform_device scif7_device = {
@@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = {
245 .scscr = SCSCR_RE | SCSCR_TE, 366 .scscr = SCSCR_RE | SCSCR_TE,
246 .scbrr_algo_id = SCBRR_ALGO_4, 367 .scbrr_algo_id = SCBRR_ALGO_4,
247 .type = PORT_SCIFB, 368 .type = PORT_SCIFB,
248 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), 369 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
249}; 370};
250 371
251static struct platform_device scifb_device = { 372static struct platform_device scifb_device = {
@@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = {
273 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
274 }, 395 },
275 [1] = { 396 [1] = {
276 .start = evt2irq(0x0b00), 397 .start = gic_spi(58),
277 .flags = IORESOURCE_IRQ, 398 .flags = IORESOURCE_IRQ,
278 }, 399 },
279}; 400};
@@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = {
304 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
305 }, 426 },
306 [1] = { 427 [1] = {
307 .start = intcs_evt2irq(0xe80), 428 .start = gic_spi(198),
308 .flags = IORESOURCE_IRQ, 429 .flags = IORESOURCE_IRQ,
309 }, 430 },
310}; 431};
@@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = {
334 .flags = IORESOURCE_MEM, 455 .flags = IORESOURCE_MEM,
335 }, 456 },
336 [1] = { 457 [1] = {
337 .start = intcs_evt2irq(0xea0), 458 .start = gic_spi(199),
338 .flags = IORESOURCE_IRQ, 459 .flags = IORESOURCE_IRQ,
339 }, 460 },
340}; 461};
@@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = {
364 .flags = IORESOURCE_MEM, 485 .flags = IORESOURCE_MEM,
365 }, 486 },
366 [1] = { 487 [1] = {
367 .start = intcs_evt2irq(0xec0), 488 .start = gic_spi(200),
368 .flags = IORESOURCE_IRQ, 489 .flags = IORESOURCE_IRQ,
369 }, 490 },
370}; 491};
@@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = {
411}; 532};
412 533
413static struct platform_device *r8a7740_early_devices[] __initdata = { 534static struct platform_device *r8a7740_early_devices[] __initdata = {
535 &irqpin0_device,
536 &irqpin1_device,
537 &irqpin2_device,
538 &irqpin3_device,
414 &scif0_device, 539 &scif0_device,
415 &scif1_device, 540 &scif1_device,
416 &scif2_device, 541 &scif2_device,
@@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = {
525 }, 650 },
526 { 651 {
527 .name = "error_irq", 652 .name = "error_irq",
528 .start = evt2irq(0x20c0), 653 .start = gic_spi(34),
529 .end = evt2irq(0x20c0), 654 .end = gic_spi(34),
530 .flags = IORESOURCE_IRQ, 655 .flags = IORESOURCE_IRQ,
531 }, 656 },
532 { 657 {
533 /* IRQ for channels 0-5 */ 658 /* IRQ for channels 0-5 */
534 .start = evt2irq(0x2000), 659 .start = gic_spi(28),
535 .end = evt2irq(0x20a0), 660 .end = gic_spi(33),
536 .flags = IORESOURCE_IRQ, 661 .flags = IORESOURCE_IRQ,
537 }, 662 },
538}; 663};
@@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = {
553 }, 678 },
554 { 679 {
555 .name = "error_irq", 680 .name = "error_irq",
556 .start = evt2irq(0x21c0), 681 .start = gic_spi(41),
557 .end = evt2irq(0x21c0), 682 .end = gic_spi(41),
558 .flags = IORESOURCE_IRQ, 683 .flags = IORESOURCE_IRQ,
559 }, 684 },
560 { 685 {
561 /* IRQ for channels 0-5 */ 686 /* IRQ for channels 0-5 */
562 .start = evt2irq(0x2100), 687 .start = gic_spi(35),
563 .end = evt2irq(0x21a0), 688 .end = gic_spi(40),
564 .flags = IORESOURCE_IRQ, 689 .flags = IORESOURCE_IRQ,
565 }, 690 },
566}; 691};
@@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = {
581 }, 706 },
582 { 707 {
583 .name = "error_irq", 708 .name = "error_irq",
584 .start = evt2irq(0x22c0), 709 .start = gic_spi(48),
585 .end = evt2irq(0x22c0), 710 .end = gic_spi(48),
586 .flags = IORESOURCE_IRQ, 711 .flags = IORESOURCE_IRQ,
587 }, 712 },
588 { 713 {
589 /* IRQ for channels 0-5 */ 714 /* IRQ for channels 0-5 */
590 .start = evt2irq(0x2200), 715 .start = gic_spi(42),
591 .end = evt2irq(0x22a0), 716 .end = gic_spi(47),
592 .flags = IORESOURCE_IRQ, 717 .flags = IORESOURCE_IRQ,
593 }, 718 },
594}; 719};
@@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = {
677 }, 802 },
678 { 803 {
679 /* IRQ for channels */ 804 /* IRQ for channels */
680 .start = evt2irq(0x0a00), 805 .start = gic_spi(49),
681 .end = evt2irq(0x0a00), 806 .end = gic_spi(49),
682 .flags = IORESOURCE_IRQ, 807 .flags = IORESOURCE_IRQ,
683 }, 808 },
684}; 809};
@@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = {
702 .flags = IORESOURCE_MEM, 827 .flags = IORESOURCE_MEM,
703 }, 828 },
704 [1] = { 829 [1] = {
705 .start = intcs_evt2irq(0xe00), 830 .start = gic_spi(201),
706 .end = intcs_evt2irq(0xe60), 831 .end = gic_spi(204),
707 .flags = IORESOURCE_IRQ, 832 .flags = IORESOURCE_IRQ,
708 }, 833 },
709}; 834};
@@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = {
716 .flags = IORESOURCE_MEM, 841 .flags = IORESOURCE_MEM,
717 }, 842 },
718 [1] = { 843 [1] = {
719 .start = evt2irq(0x780), /* IIC1_ALI1 */ 844 .start = gic_spi(70), /* IIC1_ALI1 */
720 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ 845 .end = gic_spi(73), /* IIC1_DTEI1 */
721 .flags = IORESOURCE_IRQ, 846 .flags = IORESOURCE_IRQ,
722 }, 847 },
723}; 848};
@@ -738,8 +863,8 @@ static struct platform_device i2c1_device = {
738 863
739static struct resource pmu_resources[] = { 864static struct resource pmu_resources[] = {
740 [0] = { 865 [0] = {
741 .start = evt2irq(0x19a0), 866 .start = gic_spi(83),
742 .end = evt2irq(0x19a0), 867 .end = gic_spi(83),
743 .flags = IORESOURCE_IRQ, 868 .flags = IORESOURCE_IRQ,
744 }, 869 },
745}; 870};
@@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
904 .map_io = r8a7740_map_io, 1029 .map_io = r8a7740_map_io,
905 .init_early = r8a7740_add_early_devices_dt, 1030 .init_early = r8a7740_add_early_devices_dt,
906 .init_irq = r8a7740_init_irq, 1031 .init_irq = r8a7740_init_irq,
907 .handle_irq = shmobile_handle_irq_intc,
908 .init_machine = r8a7740_add_standard_devices_dt, 1032 .init_machine = r8a7740_add_standard_devices_dt,
909 .init_time = shmobile_timer_init, 1033 .init_time = shmobile_timer_init,
910 .dt_compat = r8a7740_boards_compat_dt, 1034 .dt_compat = r8a7740_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
new file mode 100644
index 000000000000..01c62bedf9cf
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -0,0 +1,193 @@
1/*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/irqchip/arm-gic.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/platform_device.h>
27#include <linux/irqchip.h>
28#include <linux/serial_sci.h>
29#include <linux/sh_timer.h>
30#include <mach/irqs.h>
31#include <mach/r8a7778.h>
32#include <mach/common.h>
33#include <asm/mach/arch.h>
34#include <asm/hardware/cache-l2x0.h>
35
36/* SCIF */
37#define SCIF_INFO(baseaddr, irq) \
38{ \
39 .mapbase = baseaddr, \
40 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
41 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
42 .scbrr_algo_id = SCBRR_ALGO_2, \
43 .type = PORT_SCIF, \
44 .irqs = SCIx_IRQ_MUXED(irq), \
45}
46
47static struct plat_sci_port scif_platform_data[] = {
48 SCIF_INFO(0xffe40000, gic_iid(0x66)),
49 SCIF_INFO(0xffe41000, gic_iid(0x67)),
50 SCIF_INFO(0xffe42000, gic_iid(0x68)),
51 SCIF_INFO(0xffe43000, gic_iid(0x69)),
52 SCIF_INFO(0xffe44000, gic_iid(0x6a)),
53 SCIF_INFO(0xffe45000, gic_iid(0x6b)),
54};
55
56/* TMU */
57static struct resource sh_tmu0_resources[] = {
58 DEFINE_RES_MEM(0xffd80008, 12),
59 DEFINE_RES_IRQ(gic_iid(0x40)),
60};
61
62static struct sh_timer_config sh_tmu0_platform_data = {
63 .name = "TMU00",
64 .channel_offset = 0x4,
65 .timer_bit = 0,
66 .clockevent_rating = 200,
67};
68
69static struct resource sh_tmu1_resources[] = {
70 DEFINE_RES_MEM(0xffd80014, 12),
71 DEFINE_RES_IRQ(gic_iid(0x41)),
72};
73
74static struct sh_timer_config sh_tmu1_platform_data = {
75 .name = "TMU01",
76 .channel_offset = 0x10,
77 .timer_bit = 1,
78 .clocksource_rating = 200,
79};
80
81#define PLATFORM_INFO(n, i) \
82{ \
83 .parent = &platform_bus, \
84 .name = #n, \
85 .id = i, \
86 .res = n ## i ## _resources, \
87 .num_res = ARRAY_SIZE(n ## i ##_resources), \
88 .data = &n ## i ##_platform_data, \
89 .size_data = sizeof(n ## i ## _platform_data), \
90}
91
92struct platform_device_info platform_devinfo[] = {
93 PLATFORM_INFO(sh_tmu, 0),
94 PLATFORM_INFO(sh_tmu, 1),
95};
96
97void __init r8a7778_add_standard_devices(void)
98{
99 int i;
100
101#ifdef CONFIG_CACHE_L2X0
102 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
103 if (base) {
104 /*
105 * Early BRESP enable, Shared attribute override enable, 64K*16way
106 * don't call iounmap(base)
107 */
108 l2x0_init(base, 0x40470000, 0x82000fff);
109 }
110#endif
111
112 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
113 platform_device_register_data(&platform_bus, "sh-sci", i,
114 &scif_platform_data[i],
115 sizeof(struct plat_sci_port));
116
117 for (i = 0; i < ARRAY_SIZE(platform_devinfo); i++)
118 platform_device_register_full(&platform_devinfo[i]);
119}
120
121#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
122#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
123
124#define INT2NTSR0 0x00018 /* 0xfe700018 */
125#define INT2NTSR1 0x0002c /* 0xfe70002c */
126static void __init r8a7778_init_irq_common(void)
127{
128 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
129
130 BUG_ON(!base);
131
132 /* route all interrupts to ARM */
133 __raw_writel(0x73ffffff, base + INT2NTSR0);
134 __raw_writel(0xffffffff, base + INT2NTSR1);
135
136 /* unmask all known interrupts in INTCS2 */
137 __raw_writel(0x08330773, base + INT2SMSKCR0);
138 __raw_writel(0x00311110, base + INT2SMSKCR1);
139
140 iounmap(base);
141}
142
143void __init r8a7778_init_irq(void)
144{
145 void __iomem *gic_dist_base;
146 void __iomem *gic_cpu_base;
147
148 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
149 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
150 BUG_ON(!gic_dist_base || !gic_cpu_base);
151
152 /* use GIC to handle interrupts */
153 gic_init(0, 29, gic_dist_base, gic_cpu_base);
154
155 r8a7778_init_irq_common();
156}
157
158void __init r8a7778_init_delay(void)
159{
160 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
161}
162
163#ifdef CONFIG_USE_OF
164void __init r8a7778_init_irq_dt(void)
165{
166 irqchip_init();
167 r8a7778_init_irq_common();
168}
169
170static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
171 {},
172};
173
174void __init r8a7778_add_standard_devices_dt(void)
175{
176 of_platform_populate(NULL, of_default_bus_match_table,
177 r8a7778_auxdata_lookup, NULL);
178}
179
180static const char *r8a7778_compat_dt[] __initdata = {
181 "renesas,r8a7778",
182 NULL,
183};
184
185DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
186 .init_early = r8a7778_init_delay,
187 .init_irq = r8a7778_init_irq_dt,
188 .init_machine = r8a7778_add_standard_devices_dt,
189 .init_time = shmobile_timer_init,
190 .dt_compat = r8a7778_compat_dt,
191MACHINE_END
192
193#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 042df35e71a0..a460ba3dedcb 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/delay.h> 27#include <linux/delay.h>
27#include <linux/input.h> 28#include <linux/input.h>
@@ -68,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = {
68 .end = 0xfffc023b, 69 .end = 0xfffc023b,
69 .flags = IORESOURCE_MEM, 70 .flags = IORESOURCE_MEM,
70 }, 71 },
71 [1] = {
72 .start = 0xffc40000,
73 .end = 0xffc46fff,
74 .flags = IORESOURCE_MEM,
75 }
76}; 72};
77 73
78static struct platform_device r8a7779_pfc_device = { 74static struct platform_device r8a7779_pfc_device = {
@@ -82,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = {
82 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 78 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
83}; 79};
84 80
81#define R8A7779_GPIO(idx, npins) \
82static struct resource r8a7779_gpio##idx##_resources[] = { \
83 [0] = { \
84 .start = 0xffc40000 + 0x1000 * (idx), \
85 .end = 0xffc4002b + 0x1000 * (idx), \
86 .flags = IORESOURCE_MEM, \
87 }, \
88 [1] = { \
89 .start = gic_iid(0xad + (idx)), \
90 .flags = IORESOURCE_IRQ, \
91 } \
92}; \
93 \
94static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
95 .gpio_base = 32 * (idx), \
96 .irq_base = 0, \
97 .number_of_pins = npins, \
98 .pctl_name = "pfc-r8a7779", \
99}; \
100 \
101static struct platform_device r8a7779_gpio##idx##_device = { \
102 .name = "gpio_rcar", \
103 .id = idx, \
104 .resource = r8a7779_gpio##idx##_resources, \
105 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
106 .dev = { \
107 .platform_data = &r8a7779_gpio##idx##_platform_data, \
108 }, \
109}
110
111R8A7779_GPIO(0, 32);
112R8A7779_GPIO(1, 32);
113R8A7779_GPIO(2, 32);
114R8A7779_GPIO(3, 32);
115R8A7779_GPIO(4, 32);
116R8A7779_GPIO(5, 32);
117R8A7779_GPIO(6, 9);
118
119static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
120 &r8a7779_pfc_device,
121 &r8a7779_gpio0_device,
122 &r8a7779_gpio1_device,
123 &r8a7779_gpio2_device,
124 &r8a7779_gpio3_device,
125 &r8a7779_gpio4_device,
126 &r8a7779_gpio5_device,
127 &r8a7779_gpio6_device,
128};
129
85void __init r8a7779_pinmux_init(void) 130void __init r8a7779_pinmux_init(void)
86{ 131{
87 platform_device_register(&r8a7779_pfc_device); 132 platform_add_devices(r8a7779_pinctrl_devices,
133 ARRAY_SIZE(r8a7779_pinctrl_devices));
88} 134}
89 135
90static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
new file mode 100644
index 000000000000..481201a4f3f5
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -0,0 +1,137 @@
1/*
2 * r8a7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/irq.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h>
24#include <linux/of_platform.h>
25#include <linux/serial_sci.h>
26#include <linux/platform_data/irq-renesas-irqc.h>
27#include <mach/common.h>
28#include <mach/irqs.h>
29#include <mach/r8a7790.h>
30#include <asm/mach/arch.h>
31
32static const struct resource pfc_resources[] = {
33 DEFINE_RES_MEM(0xe6060000, 0x250),
34};
35
36void __init r8a7790_pinmux_init(void)
37{
38 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
39 ARRAY_SIZE(pfc_resources));
40}
41
42#define SCIF_COMMON(scif_type, baseaddr, irq) \
43 .type = scif_type, \
44 .mapbase = baseaddr, \
45 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
46 .irqs = SCIx_IRQ_MUXED(irq)
47
48#define SCIFA_DATA(index, baseaddr, irq) \
49[index] = { \
50 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
51 .scbrr_algo_id = SCBRR_ALGO_4, \
52 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
53}
54
55#define SCIFB_DATA(index, baseaddr, irq) \
56[index] = { \
57 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
58 .scbrr_algo_id = SCBRR_ALGO_4, \
59 .scscr = SCSCR_RE | SCSCR_TE, \
60}
61
62#define SCIF_DATA(index, baseaddr, irq) \
63[index] = { \
64 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
65 .scbrr_algo_id = SCBRR_ALGO_2, \
66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
67}
68
69enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
70
71static const struct plat_sci_port scif[] = {
72 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
73 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
74 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
75 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
76 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
77 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
78 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
79 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
80};
81
82static inline void r8a7790_register_scif(int idx)
83{
84 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
85 sizeof(struct plat_sci_port));
86}
87
88static struct renesas_irqc_config irqc0_data = {
89 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
90};
91
92static struct resource irqc0_resources[] = {
93 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
94 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
95 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
96 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
97 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
98};
99
100#define r8a7790_register_irqc(idx) \
101 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
102 idx, irqc##idx##_resources, \
103 ARRAY_SIZE(irqc##idx##_resources), \
104 &irqc##idx##_data, \
105 sizeof(struct renesas_irqc_config))
106
107void __init r8a7790_add_standard_devices(void)
108{
109 r8a7790_register_scif(SCIFA0);
110 r8a7790_register_scif(SCIFA1);
111 r8a7790_register_scif(SCIFB0);
112 r8a7790_register_scif(SCIFB1);
113 r8a7790_register_scif(SCIFB2);
114 r8a7790_register_scif(SCIFA2);
115 r8a7790_register_scif(SCIF0);
116 r8a7790_register_scif(SCIF1);
117 r8a7790_register_irqc(0);
118}
119
120#ifdef CONFIG_USE_OF
121void __init r8a7790_add_standard_devices_dt(void)
122{
123 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
124}
125
126static const char *r8a7790_boards_compat_dt[] __initdata = {
127 "renesas,r8a7790",
128 NULL,
129};
130
131DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
132 .init_irq = irqchip_init,
133 .init_machine = r8a7790_add_standard_devices_dt,
134 .init_time = shmobile_timer_init,
135 .dt_compat = r8a7790_boards_compat_dt,
136MACHINE_END
137#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 2257a915746d..e8cd93a5c550 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -33,6 +33,7 @@
33#include <linux/sh_intc.h> 33#include <linux/sh_intc.h>
34#include <linux/sh_timer.h> 34#include <linux/sh_timer.h>
35#include <linux/platform_data/sh_ipmmu.h> 35#include <linux/platform_data/sh_ipmmu.h>
36#include <linux/platform_data/irq-renesas-intc-irqpin.h>
36#include <mach/dma-register.h> 37#include <mach/dma-register.h>
37#include <mach/hardware.h> 38#include <mach/hardware.h>
38#include <mach/irqs.h> 39#include <mach/irqs.h>
@@ -811,6 +812,127 @@ static struct platform_device ipmmu_device = {
811 .num_resources = ARRAY_SIZE(ipmmu_resources), 812 .num_resources = ARRAY_SIZE(ipmmu_resources),
812}; 813};
813 814
815static struct renesas_intc_irqpin_config irqpin0_platform_data = {
816 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
817};
818
819static struct resource irqpin0_resources[] = {
820 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
821 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
822 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
823 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
824 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
825 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
826 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
827 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
828 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
829 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
830 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
831 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
832 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
833};
834
835static struct platform_device irqpin0_device = {
836 .name = "renesas_intc_irqpin",
837 .id = 0,
838 .resource = irqpin0_resources,
839 .num_resources = ARRAY_SIZE(irqpin0_resources),
840 .dev = {
841 .platform_data = &irqpin0_platform_data,
842 },
843};
844
845static struct renesas_intc_irqpin_config irqpin1_platform_data = {
846 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
847 .control_parent = true, /* Disable spurious IRQ10 */
848};
849
850static struct resource irqpin1_resources[] = {
851 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
852 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
853 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
854 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
855 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
856 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
857 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
858 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
859 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
860 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
861 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
862 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
863 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
864};
865
866static struct platform_device irqpin1_device = {
867 .name = "renesas_intc_irqpin",
868 .id = 1,
869 .resource = irqpin1_resources,
870 .num_resources = ARRAY_SIZE(irqpin1_resources),
871 .dev = {
872 .platform_data = &irqpin1_platform_data,
873 },
874};
875
876static struct renesas_intc_irqpin_config irqpin2_platform_data = {
877 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
878};
879
880static struct resource irqpin2_resources[] = {
881 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
882 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
883 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
884 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
885 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
886 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
887 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
888 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
889 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
890 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
891 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
892 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
893 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
894};
895
896static struct platform_device irqpin2_device = {
897 .name = "renesas_intc_irqpin",
898 .id = 2,
899 .resource = irqpin2_resources,
900 .num_resources = ARRAY_SIZE(irqpin2_resources),
901 .dev = {
902 .platform_data = &irqpin2_platform_data,
903 },
904};
905
906static struct renesas_intc_irqpin_config irqpin3_platform_data = {
907 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
908};
909
910static struct resource irqpin3_resources[] = {
911 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
912 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
913 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
914 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
915 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
916 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
917 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
918 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
919 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
920 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
921 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
922 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
923 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
924};
925
926static struct platform_device irqpin3_device = {
927 .name = "renesas_intc_irqpin",
928 .id = 3,
929 .resource = irqpin3_resources,
930 .num_resources = ARRAY_SIZE(irqpin3_resources),
931 .dev = {
932 .platform_data = &irqpin3_platform_data,
933 },
934};
935
814static struct platform_device *sh73a0_devices_dt[] __initdata = { 936static struct platform_device *sh73a0_devices_dt[] __initdata = {
815 &scif0_device, 937 &scif0_device,
816 &scif1_device, 938 &scif1_device,
@@ -839,6 +961,10 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
839 &dma0_device, 961 &dma0_device,
840 &mpdma0_device, 962 &mpdma0_device,
841 &pmu_device, 963 &pmu_device,
964 &irqpin0_device,
965 &irqpin1_device,
966 &irqpin2_device,
967 &irqpin3_device,
842}; 968};
843 969
844#define SRCR2 IOMEM(0xe61580b0) 970#define SRCR2 IOMEM(0xe61580b0)
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index 1825b0bd523d..4c17fb6970b1 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -9,7 +9,9 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11 11
12#include <linux/bug.h>
12#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h>
13#include <linux/kernel.h> 15#include <linux/kernel.h>
14#include <cpu/pfc.h> 16#include <cpu/pfc.h>
15 17
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93aaadf99f28..d766e3cbef18 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -204,6 +204,12 @@ config GPIO_PXA
204 help 204 help
205 Say yes here to support the PXA GPIO device 205 Say yes here to support the PXA GPIO device
206 206
207config GPIO_RCAR
208 tristate "Renesas R-Car GPIO"
209 depends on ARM
210 help
211 Say yes here to support GPIO on Renesas R-Car SoCs.
212
207config GPIO_SPEAR_SPICS 213config GPIO_SPEAR_SPICS
208 bool "ST SPEAr13xx SPI Chip Select as GPIO support" 214 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
209 depends on PLAT_SPEAR 215 depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 22e07bc9fcb5..b41c74d45287 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
57obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o 57obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
58obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o 58obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
59obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o 59obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
60obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
60obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o 61obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
61obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o 62obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
62obj-$(CONFIG_GPIO_SCH) += gpio-sch.o 63obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
new file mode 100644
index 000000000000..b4ca450947b8
--- /dev/null
+++ b/drivers/gpio/gpio-rcar.c
@@ -0,0 +1,396 @@
1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
24#include <linux/module.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/platform_data/gpio-rcar.h>
27#include <linux/platform_device.h>
28#include <linux/spinlock.h>
29#include <linux/slab.h>
30
31struct gpio_rcar_priv {
32 void __iomem *base;
33 spinlock_t lock;
34 struct gpio_rcar_config config;
35 struct platform_device *pdev;
36 struct gpio_chip gpio_chip;
37 struct irq_chip irq_chip;
38 struct irq_domain *irq_domain;
39};
40
41#define IOINTSEL 0x00
42#define INOUTSEL 0x04
43#define OUTDT 0x08
44#define INDT 0x0c
45#define INTDT 0x10
46#define INTCLR 0x14
47#define INTMSK 0x18
48#define MSKCLR 0x1c
49#define POSNEG 0x20
50#define EDGLEVEL 0x24
51#define FILONOFF 0x28
52
53static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
54{
55 return ioread32(p->base + offs);
56}
57
58static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
59 u32 value)
60{
61 iowrite32(value, p->base + offs);
62}
63
64static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
65 int bit, bool value)
66{
67 u32 tmp = gpio_rcar_read(p, offs);
68
69 if (value)
70 tmp |= BIT(bit);
71 else
72 tmp &= ~BIT(bit);
73
74 gpio_rcar_write(p, offs, tmp);
75}
76
77static void gpio_rcar_irq_disable(struct irq_data *d)
78{
79 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
80
81 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
82}
83
84static void gpio_rcar_irq_enable(struct irq_data *d)
85{
86 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
87
88 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
89}
90
91static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
92 unsigned int hwirq,
93 bool active_high_rising_edge,
94 bool level_trigger)
95{
96 unsigned long flags;
97
98 /* follow steps in the GPIO documentation for
99 * "Setting Edge-Sensitive Interrupt Input Mode" and
100 * "Setting Level-Sensitive Interrupt Input Mode"
101 */
102
103 spin_lock_irqsave(&p->lock, flags);
104
105 /* Configure postive or negative logic in POSNEG */
106 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
107
108 /* Configure edge or level trigger in EDGLEVEL */
109 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
110
111 /* Select "Interrupt Input Mode" in IOINTSEL */
112 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
113
114 /* Write INTCLR in case of edge trigger */
115 if (!level_trigger)
116 gpio_rcar_write(p, INTCLR, BIT(hwirq));
117
118 spin_unlock_irqrestore(&p->lock, flags);
119}
120
121static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
122{
123 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
124 unsigned int hwirq = irqd_to_hwirq(d);
125
126 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
127
128 switch (type & IRQ_TYPE_SENSE_MASK) {
129 case IRQ_TYPE_LEVEL_HIGH:
130 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
131 break;
132 case IRQ_TYPE_LEVEL_LOW:
133 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
134 break;
135 case IRQ_TYPE_EDGE_RISING:
136 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
137 break;
138 case IRQ_TYPE_EDGE_FALLING:
139 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
140 break;
141 default:
142 return -EINVAL;
143 }
144 return 0;
145}
146
147static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
148{
149 struct gpio_rcar_priv *p = dev_id;
150 u32 pending;
151 unsigned int offset, irqs_handled = 0;
152
153 while ((pending = gpio_rcar_read(p, INTDT))) {
154 offset = __ffs(pending);
155 gpio_rcar_write(p, INTCLR, BIT(offset));
156 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
157 irqs_handled++;
158 }
159
160 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
161}
162
163static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
164{
165 return container_of(chip, struct gpio_rcar_priv, gpio_chip);
166}
167
168static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
169 unsigned int gpio,
170 bool output)
171{
172 struct gpio_rcar_priv *p = gpio_to_priv(chip);
173 unsigned long flags;
174
175 /* follow steps in the GPIO documentation for
176 * "Setting General Output Mode" and
177 * "Setting General Input Mode"
178 */
179
180 spin_lock_irqsave(&p->lock, flags);
181
182 /* Configure postive logic in POSNEG */
183 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
184
185 /* Select "General Input/Output Mode" in IOINTSEL */
186 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
187
188 /* Select Input Mode or Output Mode in INOUTSEL */
189 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
190
191 spin_unlock_irqrestore(&p->lock, flags);
192}
193
194static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
195{
196 return pinctrl_request_gpio(chip->base + offset);
197}
198
199static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
200{
201 pinctrl_free_gpio(chip->base + offset);
202
203 /* Set the GPIO as an input to ensure that the next GPIO request won't
204 * drive the GPIO pin as an output.
205 */
206 gpio_rcar_config_general_input_output_mode(chip, offset, false);
207}
208
209static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
210{
211 gpio_rcar_config_general_input_output_mode(chip, offset, false);
212 return 0;
213}
214
215static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
216{
217 return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
218}
219
220static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
221{
222 struct gpio_rcar_priv *p = gpio_to_priv(chip);
223 unsigned long flags;
224
225 spin_lock_irqsave(&p->lock, flags);
226 gpio_rcar_modify_bit(p, OUTDT, offset, value);
227 spin_unlock_irqrestore(&p->lock, flags);
228}
229
230static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
231 int value)
232{
233 /* write GPIO value to output before selecting output mode of pin */
234 gpio_rcar_set(chip, offset, value);
235 gpio_rcar_config_general_input_output_mode(chip, offset, true);
236 return 0;
237}
238
239static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
240{
241 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
242}
243
244static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
245 irq_hw_number_t hw)
246{
247 struct gpio_rcar_priv *p = h->host_data;
248
249 dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
250
251 irq_set_chip_data(virq, h->host_data);
252 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
253 set_irq_flags(virq, IRQF_VALID); /* kill me now */
254 return 0;
255}
256
257static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
258 .map = gpio_rcar_irq_domain_map,
259};
260
261static int gpio_rcar_probe(struct platform_device *pdev)
262{
263 struct gpio_rcar_config *pdata = pdev->dev.platform_data;
264 struct gpio_rcar_priv *p;
265 struct resource *io, *irq;
266 struct gpio_chip *gpio_chip;
267 struct irq_chip *irq_chip;
268 const char *name = dev_name(&pdev->dev);
269 int ret;
270
271 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
272 if (!p) {
273 dev_err(&pdev->dev, "failed to allocate driver data\n");
274 ret = -ENOMEM;
275 goto err0;
276 }
277
278 /* deal with driver instance configuration */
279 if (pdata)
280 p->config = *pdata;
281
282 p->pdev = pdev;
283 platform_set_drvdata(pdev, p);
284 spin_lock_init(&p->lock);
285
286 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
287 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
288
289 if (!io || !irq) {
290 dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
291 ret = -EINVAL;
292 goto err0;
293 }
294
295 p->base = devm_ioremap_nocache(&pdev->dev, io->start,
296 resource_size(io));
297 if (!p->base) {
298 dev_err(&pdev->dev, "failed to remap I/O memory\n");
299 ret = -ENXIO;
300 goto err0;
301 }
302
303 gpio_chip = &p->gpio_chip;
304 gpio_chip->request = gpio_rcar_request;
305 gpio_chip->free = gpio_rcar_free;
306 gpio_chip->direction_input = gpio_rcar_direction_input;
307 gpio_chip->get = gpio_rcar_get;
308 gpio_chip->direction_output = gpio_rcar_direction_output;
309 gpio_chip->set = gpio_rcar_set;
310 gpio_chip->to_irq = gpio_rcar_to_irq;
311 gpio_chip->label = name;
312 gpio_chip->owner = THIS_MODULE;
313 gpio_chip->base = p->config.gpio_base;
314 gpio_chip->ngpio = p->config.number_of_pins;
315
316 irq_chip = &p->irq_chip;
317 irq_chip->name = name;
318 irq_chip->irq_mask = gpio_rcar_irq_disable;
319 irq_chip->irq_unmask = gpio_rcar_irq_enable;
320 irq_chip->irq_enable = gpio_rcar_irq_enable;
321 irq_chip->irq_disable = gpio_rcar_irq_disable;
322 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
323 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
324
325 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
326 p->config.number_of_pins,
327 p->config.irq_base,
328 &gpio_rcar_irq_domain_ops, p);
329 if (!p->irq_domain) {
330 ret = -ENXIO;
331 dev_err(&pdev->dev, "cannot initialize irq domain\n");
332 goto err1;
333 }
334
335 if (devm_request_irq(&pdev->dev, irq->start,
336 gpio_rcar_irq_handler, 0, name, p)) {
337 dev_err(&pdev->dev, "failed to request IRQ\n");
338 ret = -ENOENT;
339 goto err1;
340 }
341
342 ret = gpiochip_add(gpio_chip);
343 if (ret) {
344 dev_err(&pdev->dev, "failed to add GPIO controller\n");
345 goto err1;
346 }
347
348 dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
349
350 /* warn in case of mismatch if irq base is specified */
351 if (p->config.irq_base) {
352 ret = irq_find_mapping(p->irq_domain, 0);
353 if (p->config.irq_base != ret)
354 dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
355 p->config.irq_base, ret);
356 }
357
358 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
359 gpio_chip->base, gpio_chip->ngpio);
360 if (ret < 0)
361 dev_warn(&pdev->dev, "failed to add pin range\n");
362
363 return 0;
364
365err1:
366 irq_domain_remove(p->irq_domain);
367err0:
368 return ret;
369}
370
371static int gpio_rcar_remove(struct platform_device *pdev)
372{
373 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
374 int ret;
375
376 ret = gpiochip_remove(&p->gpio_chip);
377 if (ret)
378 return ret;
379
380 irq_domain_remove(p->irq_domain);
381 return 0;
382}
383
384static struct platform_driver gpio_rcar_device_driver = {
385 .probe = gpio_rcar_probe,
386 .remove = gpio_rcar_remove,
387 .driver = {
388 .name = "gpio_rcar",
389 }
390};
391
392module_platform_driver(gpio_rcar_device_driver);
393
394MODULE_AUTHOR("Magnus Damm");
395MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
396MODULE_LICENSE("GPL v2");
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a350969e5efe..4a33351c25dc 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -25,6 +25,14 @@ config ARM_VIC_NR
25 The maximum number of VICs available in the system, for 25 The maximum number of VICs available in the system, for
26 power management. 26 power management.
27 27
28config RENESAS_INTC_IRQPIN
29 bool
30 select IRQ_DOMAIN
31
32config RENESAS_IRQC
33 bool
34 select IRQ_DOMAIN
35
28config VERSATILE_FPGA_IRQ 36config VERSATILE_FPGA_IRQ
29 bool 37 bool
30 select IRQ_DOMAIN 38 select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 98e3b87bdf1b..e41ceb9bec22 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -8,4 +8,6 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o
8obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o 8obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
9obj-$(CONFIG_ARM_GIC) += irq-gic.o 9obj-$(CONFIG_ARM_GIC) += irq-gic.o
10obj-$(CONFIG_ARM_VIC) += irq-vic.o 10obj-$(CONFIG_ARM_VIC) += irq-vic.o
11obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
12obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
11obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o 13obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
new file mode 100644
index 000000000000..5a68e5accec1
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -0,0 +1,547 @@
1/*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/err.h>
29#include <linux/slab.h>
30#include <linux/module.h>
31#include <linux/platform_data/irq-renesas-intc-irqpin.h>
32
33#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
34
35#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
36#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
37#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
38#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
39#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
40#define INTC_IRQPIN_REG_NR 5
41
42/* INTC external IRQ PIN hardware register access:
43 *
44 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
45 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
46 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
47 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
48 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
49 *
50 * (*) May be accessed by more than one driver instance - lock needed
51 * (**) Read-modify-write access by one driver instance - lock needed
52 * (***) Accessed by one driver instance only - no locking needed
53 */
54
55struct intc_irqpin_iomem {
56 void __iomem *iomem;
57 unsigned long (*read)(void __iomem *iomem);
58 void (*write)(void __iomem *iomem, unsigned long data);
59 int width;
60};
61
62struct intc_irqpin_irq {
63 int hw_irq;
64 int requested_irq;
65 int domain_irq;
66 struct intc_irqpin_priv *p;
67};
68
69struct intc_irqpin_priv {
70 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
71 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
72 struct renesas_intc_irqpin_config config;
73 unsigned int number_of_irqs;
74 struct platform_device *pdev;
75 struct irq_chip irq_chip;
76 struct irq_domain *irq_domain;
77 bool shared_irqs;
78 u8 shared_irq_mask;
79};
80
81static unsigned long intc_irqpin_read32(void __iomem *iomem)
82{
83 return ioread32(iomem);
84}
85
86static unsigned long intc_irqpin_read8(void __iomem *iomem)
87{
88 return ioread8(iomem);
89}
90
91static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
92{
93 iowrite32(data, iomem);
94}
95
96static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
97{
98 iowrite8(data, iomem);
99}
100
101static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
102 int reg)
103{
104 struct intc_irqpin_iomem *i = &p->iomem[reg];
105
106 return i->read(i->iomem);
107}
108
109static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
110 int reg, unsigned long data)
111{
112 struct intc_irqpin_iomem *i = &p->iomem[reg];
113
114 i->write(i->iomem, data);
115}
116
117static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
118 int reg, int hw_irq)
119{
120 return BIT((p->iomem[reg].width - 1) - hw_irq);
121}
122
123static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
124 int reg, int hw_irq)
125{
126 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
127}
128
129static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
130
131static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
132 int reg, int shift,
133 int width, int value)
134{
135 unsigned long flags;
136 unsigned long tmp;
137
138 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
139
140 tmp = intc_irqpin_read(p, reg);
141 tmp &= ~(((1 << width) - 1) << shift);
142 tmp |= value << shift;
143 intc_irqpin_write(p, reg, tmp);
144
145 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
146}
147
148static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
149 int irq, int do_mask)
150{
151 int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
152 int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
153
154 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
155 shift, bitfield_width,
156 do_mask ? 0 : (1 << bitfield_width) - 1);
157}
158
159static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
160{
161 int bitfield_width = p->config.sense_bitfield_width;
162 int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
163
164 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
165
166 if (value >= (1 << bitfield_width))
167 return -EINVAL;
168
169 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
170 bitfield_width, value);
171 return 0;
172}
173
174static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
175{
176 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
177 str, i->requested_irq, i->hw_irq, i->domain_irq);
178}
179
180static void intc_irqpin_irq_enable(struct irq_data *d)
181{
182 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
183 int hw_irq = irqd_to_hwirq(d);
184
185 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
186 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
187}
188
189static void intc_irqpin_irq_disable(struct irq_data *d)
190{
191 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
192 int hw_irq = irqd_to_hwirq(d);
193
194 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
195 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
196}
197
198static void intc_irqpin_shared_irq_enable(struct irq_data *d)
199{
200 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
201 int hw_irq = irqd_to_hwirq(d);
202
203 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
204 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
205
206 p->shared_irq_mask &= ~BIT(hw_irq);
207}
208
209static void intc_irqpin_shared_irq_disable(struct irq_data *d)
210{
211 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
212 int hw_irq = irqd_to_hwirq(d);
213
214 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
215 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
216
217 p->shared_irq_mask |= BIT(hw_irq);
218}
219
220static void intc_irqpin_irq_enable_force(struct irq_data *d)
221{
222 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
223 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
224
225 intc_irqpin_irq_enable(d);
226
227 /* enable interrupt through parent interrupt controller,
228 * assumes non-shared interrupt with 1:1 mapping
229 * needed for busted IRQs on some SoCs like sh73a0
230 */
231 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
232}
233
234static void intc_irqpin_irq_disable_force(struct irq_data *d)
235{
236 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
237 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
238
239 /* disable interrupt through parent interrupt controller,
240 * assumes non-shared interrupt with 1:1 mapping
241 * needed for busted IRQs on some SoCs like sh73a0
242 */
243 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
244 intc_irqpin_irq_disable(d);
245}
246
247#define INTC_IRQ_SENSE_VALID 0x10
248#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
249
250static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
251 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
252 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
253 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
254 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
255 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
256};
257
258static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
259{
260 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
261 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
262
263 if (!(value & INTC_IRQ_SENSE_VALID))
264 return -EINVAL;
265
266 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
267 value ^ INTC_IRQ_SENSE_VALID);
268}
269
270static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
271{
272 struct intc_irqpin_irq *i = dev_id;
273 struct intc_irqpin_priv *p = i->p;
274 unsigned long bit;
275
276 intc_irqpin_dbg(i, "demux1");
277 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
278
279 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
280 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
281 intc_irqpin_dbg(i, "demux2");
282 generic_handle_irq(i->domain_irq);
283 return IRQ_HANDLED;
284 }
285 return IRQ_NONE;
286}
287
288static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
289{
290 struct intc_irqpin_priv *p = dev_id;
291 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
292 irqreturn_t status = IRQ_NONE;
293 int k;
294
295 for (k = 0; k < 8; k++) {
296 if (reg_source & BIT(7 - k)) {
297 if (BIT(k) & p->shared_irq_mask)
298 continue;
299
300 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
301 }
302 }
303
304 return status;
305}
306
307static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
308 irq_hw_number_t hw)
309{
310 struct intc_irqpin_priv *p = h->host_data;
311
312 p->irq[hw].domain_irq = virq;
313 p->irq[hw].hw_irq = hw;
314
315 intc_irqpin_dbg(&p->irq[hw], "map");
316 irq_set_chip_data(virq, h->host_data);
317 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
318 set_irq_flags(virq, IRQF_VALID); /* kill me now */
319 return 0;
320}
321
322static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
323 .map = intc_irqpin_irq_domain_map,
324 .xlate = irq_domain_xlate_twocell,
325};
326
327static int intc_irqpin_probe(struct platform_device *pdev)
328{
329 struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data;
330 struct intc_irqpin_priv *p;
331 struct intc_irqpin_iomem *i;
332 struct resource *io[INTC_IRQPIN_REG_NR];
333 struct resource *irq;
334 struct irq_chip *irq_chip;
335 void (*enable_fn)(struct irq_data *d);
336 void (*disable_fn)(struct irq_data *d);
337 const char *name = dev_name(&pdev->dev);
338 int ref_irq;
339 int ret;
340 int k;
341
342 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
343 if (!p) {
344 dev_err(&pdev->dev, "failed to allocate driver data\n");
345 ret = -ENOMEM;
346 goto err0;
347 }
348
349 /* deal with driver instance configuration */
350 if (pdata)
351 memcpy(&p->config, pdata, sizeof(*pdata));
352 if (!p->config.sense_bitfield_width)
353 p->config.sense_bitfield_width = 4; /* default to 4 bits */
354
355 p->pdev = pdev;
356 platform_set_drvdata(pdev, p);
357
358 /* get hold of manadatory IOMEM */
359 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
360 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
361 if (!io[k]) {
362 dev_err(&pdev->dev, "not enough IOMEM resources\n");
363 ret = -EINVAL;
364 goto err0;
365 }
366 }
367
368 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
369 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
370 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
371 if (!irq)
372 break;
373
374 p->irq[k].p = p;
375 p->irq[k].requested_irq = irq->start;
376 }
377
378 p->number_of_irqs = k;
379 if (p->number_of_irqs < 1) {
380 dev_err(&pdev->dev, "not enough IRQ resources\n");
381 ret = -EINVAL;
382 goto err0;
383 }
384
385 /* ioremap IOMEM and setup read/write callbacks */
386 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
387 i = &p->iomem[k];
388
389 switch (resource_size(io[k])) {
390 case 1:
391 i->width = 8;
392 i->read = intc_irqpin_read8;
393 i->write = intc_irqpin_write8;
394 break;
395 case 4:
396 i->width = 32;
397 i->read = intc_irqpin_read32;
398 i->write = intc_irqpin_write32;
399 break;
400 default:
401 dev_err(&pdev->dev, "IOMEM size mismatch\n");
402 ret = -EINVAL;
403 goto err0;
404 }
405
406 i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start,
407 resource_size(io[k]));
408 if (!i->iomem) {
409 dev_err(&pdev->dev, "failed to remap IOMEM\n");
410 ret = -ENXIO;
411 goto err0;
412 }
413 }
414
415 /* mask all interrupts using priority */
416 for (k = 0; k < p->number_of_irqs; k++)
417 intc_irqpin_mask_unmask_prio(p, k, 1);
418
419 /* clear all pending interrupts */
420 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
421
422 /* scan for shared interrupt lines */
423 ref_irq = p->irq[0].requested_irq;
424 p->shared_irqs = true;
425 for (k = 1; k < p->number_of_irqs; k++) {
426 if (ref_irq != p->irq[k].requested_irq) {
427 p->shared_irqs = false;
428 break;
429 }
430 }
431
432 /* use more severe masking method if requested */
433 if (p->config.control_parent) {
434 enable_fn = intc_irqpin_irq_enable_force;
435 disable_fn = intc_irqpin_irq_disable_force;
436 } else if (!p->shared_irqs) {
437 enable_fn = intc_irqpin_irq_enable;
438 disable_fn = intc_irqpin_irq_disable;
439 } else {
440 enable_fn = intc_irqpin_shared_irq_enable;
441 disable_fn = intc_irqpin_shared_irq_disable;
442 }
443
444 irq_chip = &p->irq_chip;
445 irq_chip->name = name;
446 irq_chip->irq_mask = disable_fn;
447 irq_chip->irq_unmask = enable_fn;
448 irq_chip->irq_enable = enable_fn;
449 irq_chip->irq_disable = disable_fn;
450 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
451 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
452
453 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
454 p->number_of_irqs,
455 p->config.irq_base,
456 &intc_irqpin_irq_domain_ops, p);
457 if (!p->irq_domain) {
458 ret = -ENXIO;
459 dev_err(&pdev->dev, "cannot initialize irq domain\n");
460 goto err0;
461 }
462
463 if (p->shared_irqs) {
464 /* request one shared interrupt */
465 if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq,
466 intc_irqpin_shared_irq_handler,
467 IRQF_SHARED, name, p)) {
468 dev_err(&pdev->dev, "failed to request low IRQ\n");
469 ret = -ENOENT;
470 goto err1;
471 }
472 } else {
473 /* request interrupts one by one */
474 for (k = 0; k < p->number_of_irqs; k++) {
475 if (devm_request_irq(&pdev->dev,
476 p->irq[k].requested_irq,
477 intc_irqpin_irq_handler,
478 0, name, &p->irq[k])) {
479 dev_err(&pdev->dev,
480 "failed to request low IRQ\n");
481 ret = -ENOENT;
482 goto err1;
483 }
484 }
485 }
486
487 /* unmask all interrupts on prio level */
488 for (k = 0; k < p->number_of_irqs; k++)
489 intc_irqpin_mask_unmask_prio(p, k, 0);
490
491 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
492
493 /* warn in case of mismatch if irq base is specified */
494 if (p->config.irq_base) {
495 if (p->config.irq_base != p->irq[0].domain_irq)
496 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
497 p->config.irq_base, p->irq[0].domain_irq);
498 }
499
500 return 0;
501
502err1:
503 irq_domain_remove(p->irq_domain);
504err0:
505 return ret;
506}
507
508static int intc_irqpin_remove(struct platform_device *pdev)
509{
510 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
511
512 irq_domain_remove(p->irq_domain);
513
514 return 0;
515}
516
517static const struct of_device_id intc_irqpin_dt_ids[] = {
518 { .compatible = "renesas,intc-irqpin", },
519 {},
520};
521MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
522
523static struct platform_driver intc_irqpin_device_driver = {
524 .probe = intc_irqpin_probe,
525 .remove = intc_irqpin_remove,
526 .driver = {
527 .name = "renesas_intc_irqpin",
528 .of_match_table = intc_irqpin_dt_ids,
529 .owner = THIS_MODULE,
530 }
531};
532
533static int __init intc_irqpin_init(void)
534{
535 return platform_driver_register(&intc_irqpin_device_driver);
536}
537postcore_initcall(intc_irqpin_init);
538
539static void __exit intc_irqpin_exit(void)
540{
541 platform_driver_unregister(&intc_irqpin_device_driver);
542}
543module_exit(intc_irqpin_exit);
544
545MODULE_AUTHOR("Magnus Damm");
546MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
547MODULE_LICENSE("GPL v2");
diff --git a/drivers/irqchip/irq-renesas-irqc.c b/drivers/irqchip/irq-renesas-irqc.c
new file mode 100644
index 000000000000..927bff373aac
--- /dev/null
+++ b/drivers/irqchip/irq-renesas-irqc.c
@@ -0,0 +1,307 @@
1/*
2 * Renesas IRQC Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/err.h>
29#include <linux/slab.h>
30#include <linux/module.h>
31#include <linux/platform_data/irq-renesas-irqc.h>
32
33#define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */
34
35#define IRQC_REQ_STS 0x00
36#define IRQC_EN_STS 0x04
37#define IRQC_EN_SET 0x08
38#define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10))
39#define DETECT_STATUS 0x100
40#define IRQC_CONFIG(n) (0x180 + ((n) * 0x04))
41
42struct irqc_irq {
43 int hw_irq;
44 int requested_irq;
45 int domain_irq;
46 struct irqc_priv *p;
47};
48
49struct irqc_priv {
50 void __iomem *iomem;
51 void __iomem *cpu_int_base;
52 struct irqc_irq irq[IRQC_IRQ_MAX];
53 struct renesas_irqc_config config;
54 unsigned int number_of_irqs;
55 struct platform_device *pdev;
56 struct irq_chip irq_chip;
57 struct irq_domain *irq_domain;
58};
59
60static void irqc_dbg(struct irqc_irq *i, char *str)
61{
62 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
63 str, i->requested_irq, i->hw_irq, i->domain_irq);
64}
65
66static void irqc_irq_enable(struct irq_data *d)
67{
68 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
69 int hw_irq = irqd_to_hwirq(d);
70
71 irqc_dbg(&p->irq[hw_irq], "enable");
72 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET);
73}
74
75static void irqc_irq_disable(struct irq_data *d)
76{
77 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
78 int hw_irq = irqd_to_hwirq(d);
79
80 irqc_dbg(&p->irq[hw_irq], "disable");
81 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS);
82}
83
84#define INTC_IRQ_SENSE_VALID 0x10
85#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
86
87static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = {
88 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01),
89 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02),
90 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */
91 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */
92 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */
93};
94
95static int irqc_irq_set_type(struct irq_data *d, unsigned int type)
96{
97 struct irqc_priv *p = irq_data_get_irq_chip_data(d);
98 int hw_irq = irqd_to_hwirq(d);
99 unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK];
100 unsigned long tmp;
101
102 irqc_dbg(&p->irq[hw_irq], "sense");
103
104 if (!(value & INTC_IRQ_SENSE_VALID))
105 return -EINVAL;
106
107 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq));
108 tmp &= ~0x3f;
109 tmp |= value ^ INTC_IRQ_SENSE_VALID;
110 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq));
111 return 0;
112}
113
114static irqreturn_t irqc_irq_handler(int irq, void *dev_id)
115{
116 struct irqc_irq *i = dev_id;
117 struct irqc_priv *p = i->p;
118 unsigned long bit = BIT(i->hw_irq);
119
120 irqc_dbg(i, "demux1");
121
122 if (ioread32(p->iomem + DETECT_STATUS) & bit) {
123 iowrite32(bit, p->iomem + DETECT_STATUS);
124 irqc_dbg(i, "demux2");
125 generic_handle_irq(i->domain_irq);
126 return IRQ_HANDLED;
127 }
128 return IRQ_NONE;
129}
130
131static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
132 irq_hw_number_t hw)
133{
134 struct irqc_priv *p = h->host_data;
135
136 p->irq[hw].domain_irq = virq;
137 p->irq[hw].hw_irq = hw;
138
139 irqc_dbg(&p->irq[hw], "map");
140 irq_set_chip_data(virq, h->host_data);
141 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
142 set_irq_flags(virq, IRQF_VALID); /* kill me now */
143 return 0;
144}
145
146static struct irq_domain_ops irqc_irq_domain_ops = {
147 .map = irqc_irq_domain_map,
148 .xlate = irq_domain_xlate_twocell,
149};
150
151static int irqc_probe(struct platform_device *pdev)
152{
153 struct renesas_irqc_config *pdata = pdev->dev.platform_data;
154 struct irqc_priv *p;
155 struct resource *io;
156 struct resource *irq;
157 struct irq_chip *irq_chip;
158 const char *name = dev_name(&pdev->dev);
159 int ret;
160 int k;
161
162 p = kzalloc(sizeof(*p), GFP_KERNEL);
163 if (!p) {
164 dev_err(&pdev->dev, "failed to allocate driver data\n");
165 ret = -ENOMEM;
166 goto err0;
167 }
168
169 /* deal with driver instance configuration */
170 if (pdata)
171 memcpy(&p->config, pdata, sizeof(*pdata));
172
173 p->pdev = pdev;
174 platform_set_drvdata(pdev, p);
175
176 /* get hold of manadatory IOMEM */
177 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
178 if (!io) {
179 dev_err(&pdev->dev, "not enough IOMEM resources\n");
180 ret = -EINVAL;
181 goto err1;
182 }
183
184 /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */
185 for (k = 0; k < IRQC_IRQ_MAX; k++) {
186 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
187 if (!irq)
188 break;
189
190 p->irq[k].p = p;
191 p->irq[k].requested_irq = irq->start;
192 }
193
194 p->number_of_irqs = k;
195 if (p->number_of_irqs < 1) {
196 dev_err(&pdev->dev, "not enough IRQ resources\n");
197 ret = -EINVAL;
198 goto err1;
199 }
200
201 /* ioremap IOMEM and setup read/write callbacks */
202 p->iomem = ioremap_nocache(io->start, resource_size(io));
203 if (!p->iomem) {
204 dev_err(&pdev->dev, "failed to remap IOMEM\n");
205 ret = -ENXIO;
206 goto err2;
207 }
208
209 p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */
210
211 irq_chip = &p->irq_chip;
212 irq_chip->name = name;
213 irq_chip->irq_mask = irqc_irq_disable;
214 irq_chip->irq_unmask = irqc_irq_enable;
215 irq_chip->irq_enable = irqc_irq_enable;
216 irq_chip->irq_disable = irqc_irq_disable;
217 irq_chip->irq_set_type = irqc_irq_set_type;
218 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE;
219
220 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
221 p->number_of_irqs,
222 p->config.irq_base,
223 &irqc_irq_domain_ops, p);
224 if (!p->irq_domain) {
225 ret = -ENXIO;
226 dev_err(&pdev->dev, "cannot initialize irq domain\n");
227 goto err2;
228 }
229
230 /* request interrupts one by one */
231 for (k = 0; k < p->number_of_irqs; k++) {
232 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler,
233 0, name, &p->irq[k])) {
234 dev_err(&pdev->dev, "failed to request IRQ\n");
235 ret = -ENOENT;
236 goto err3;
237 }
238 }
239
240 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs);
241
242 /* warn in case of mismatch if irq base is specified */
243 if (p->config.irq_base) {
244 if (p->config.irq_base != p->irq[0].domain_irq)
245 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n",
246 p->config.irq_base, p->irq[0].domain_irq);
247 }
248
249 return 0;
250err3:
251 for (; k >= 0; k--)
252 free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]);
253
254 irq_domain_remove(p->irq_domain);
255err2:
256 iounmap(p->iomem);
257err1:
258 kfree(p);
259err0:
260 return ret;
261}
262
263static int irqc_remove(struct platform_device *pdev)
264{
265 struct irqc_priv *p = platform_get_drvdata(pdev);
266 int k;
267
268 for (k = 0; k < p->number_of_irqs; k++)
269 free_irq(p->irq[k].requested_irq, &p->irq[k]);
270
271 irq_domain_remove(p->irq_domain);
272 iounmap(p->iomem);
273 kfree(p);
274 return 0;
275}
276
277static const struct of_device_id irqc_dt_ids[] = {
278 { .compatible = "renesas,irqc", },
279 {},
280};
281MODULE_DEVICE_TABLE(of, irqc_dt_ids);
282
283static struct platform_driver irqc_device_driver = {
284 .probe = irqc_probe,
285 .remove = irqc_remove,
286 .driver = {
287 .name = "renesas_irqc",
288 .of_match_table = irqc_dt_ids,
289 .owner = THIS_MODULE,
290 }
291};
292
293static int __init irqc_init(void)
294{
295 return platform_driver_register(&irqc_device_driver);
296}
297postcore_initcall(irqc_init);
298
299static void __exit irqc_exit(void)
300{
301 platform_driver_unregister(&irqc_device_driver);
302}
303module_exit(irqc_exit);
304
305MODULE_AUTHOR("Magnus Damm");
306MODULE_DESCRIPTION("Renesas IRQC Driver");
307MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index af16f8f6ab6c..0e1f99c33d47 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -22,6 +22,11 @@ config GPIO_SH_PFC
22 This enables support for GPIOs within the SoC's pin function 22 This enables support for GPIOs within the SoC's pin function
23 controller. 23 controller.
24 24
25config PINCTRL_PFC_R8A73A4
26 def_bool y
27 depends on ARCH_R8A73A4
28 select PINCTRL_SH_PFC
29
25config PINCTRL_PFC_R8A7740 30config PINCTRL_PFC_R8A7740
26 def_bool y 31 def_bool y
27 depends on ARCH_R8A7740 32 depends on ARCH_R8A7740
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index e8b9562c47e1..211cd8e98a8a 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
3sh-pfc-objs += gpio.o 3sh-pfc-objs += gpio.o
4endif 4endif
5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o 5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
6obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o 7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
7obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o 8obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
8obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 9obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index feef89792568..b551336924a5 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -72,6 +72,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
72 } 72 }
73 73
74 BUG(); 74 BUG();
75 return NULL;
75} 76}
76 77
77int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) 78int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
@@ -267,7 +268,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
267 int ret; 268 int ret;
268 269
269 switch (pinmux_type) { 270 switch (pinmux_type) {
270 271 case PINMUX_TYPE_GPIO:
271 case PINMUX_TYPE_FUNCTION: 272 case PINMUX_TYPE_FUNCTION:
272 range = NULL; 273 range = NULL;
273 break; 274 break;
@@ -296,6 +297,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
296 enum_id = 0; 297 enum_id = 0;
297 field = 0; 298 field = 0;
298 value = 0; 299 value = 0;
300
301 /* Iterate over all the configuration fields we need to update. */
299 while (1) { 302 while (1) {
300 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 303 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
301 if (pos < 0) 304 if (pos < 0)
@@ -304,18 +307,20 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
304 if (!enum_id) 307 if (!enum_id)
305 break; 308 break;
306 309
307 /* first check if this is a function enum */ 310 /* Check if the configuration field selects a function. If it
311 * doesn't, skip the field if it's not applicable to the
312 * requested pinmux type.
313 */
308 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 314 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
309 if (!in_range) { 315 if (!in_range) {
310 /* not a function enum */ 316 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
311 if (range) { 317 /* Functions are allowed to modify all
312 /* 318 * fields.
313 * other range exists, so this pin is 319 */
314 * a regular GPIO pin that now is being 320 in_range = 1;
315 * bound to a specific direction. 321 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
316 * 322 /* Input/output types can only modify fields
317 * for this case we only allow function enums 323 * that correspond to their respective ranges.
318 * and the enums that match the other range.
319 */ 324 */
320 in_range = sh_pfc_enum_in_range(enum_id, range); 325 in_range = sh_pfc_enum_in_range(enum_id, range);
321 326
@@ -326,17 +331,8 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
326 */ 331 */
327 if (in_range && enum_id == range->force) 332 if (in_range && enum_id == range->force)
328 continue; 333 continue;
329 } else {
330 /*
331 * no other range exists, so this pin
332 * must then be of the function type.
333 *
334 * allow function type pins to select
335 * any combination of function/in/out
336 * in their MARK lists.
337 */
338 in_range = 1;
339 } 334 }
335 /* GPIOs are only allowed to modify function fields. */
340 } 336 }
341 337
342 if (!in_range) 338 if (!in_range)
@@ -422,6 +418,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
422} 418}
423 419
424static const struct platform_device_id sh_pfc_id_table[] = { 420static const struct platform_device_id sh_pfc_id_table[] = {
421#ifdef CONFIG_PINCTRL_PFC_R8A73A4
422 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
423#endif
425#ifdef CONFIG_PINCTRL_PFC_R8A7740 424#ifdef CONFIG_PINCTRL_PFC_R8A7740
426 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, 425 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
427#endif 426#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 763d717ca979..89cb4289d761 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -54,6 +54,7 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
54int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); 54int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
55int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); 55int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
56 56
57extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
57extern const struct sh_pfc_soc_info r8a7740_pinmux_info; 58extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
58extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 59extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
59extern const struct sh_pfc_soc_info sh7203_pinmux_info; 60extern const struct sh_pfc_soc_info sh7203_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index d7acb06d888c..d37efa7dcf90 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -101,24 +101,9 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
101static int gpio_setup_data_regs(struct sh_pfc_chip *chip) 101static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
102{ 102{
103 struct sh_pfc *pfc = chip->pfc; 103 struct sh_pfc *pfc = chip->pfc;
104 unsigned long addr = pfc->info->data_regs[0].reg;
105 const struct pinmux_data_reg *dreg; 104 const struct pinmux_data_reg *dreg;
106 unsigned int i; 105 unsigned int i;
107 106
108 /* Find the window that contain the GPIO registers. */
109 for (i = 0; i < pfc->num_windows; ++i) {
110 struct sh_pfc_window *window = &pfc->window[i];
111
112 if (addr >= window->phys && addr < window->phys + window->size)
113 break;
114 }
115
116 if (i == pfc->num_windows)
117 return -EINVAL;
118
119 /* GPIO data registers must be in the first memory resource. */
120 chip->mem = &pfc->window[i];
121
122 /* Count the number of data registers, allocate memory and initialize 107 /* Count the number of data registers, allocate memory and initialize
123 * them. 108 * them.
124 */ 109 */
@@ -319,7 +304,8 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
319 */ 304 */
320 305
321static struct sh_pfc_chip * 306static struct sh_pfc_chip *
322sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *)) 307sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
308 struct sh_pfc_window *mem)
323{ 309{
324 struct sh_pfc_chip *chip; 310 struct sh_pfc_chip *chip;
325 int ret; 311 int ret;
@@ -328,6 +314,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
328 if (unlikely(!chip)) 314 if (unlikely(!chip))
329 return ERR_PTR(-ENOMEM); 315 return ERR_PTR(-ENOMEM);
330 316
317 chip->mem = mem;
331 chip->pfc = pfc; 318 chip->pfc = pfc;
332 319
333 ret = setup(chip); 320 ret = setup(chip);
@@ -354,8 +341,27 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
354 unsigned int i; 341 unsigned int i;
355 int ret; 342 int ret;
356 343
344 if (pfc->info->data_regs == NULL)
345 return 0;
346
347 /* Find the memory window that contain the GPIO registers. Boards that
348 * register a separate GPIO device will not supply a memory resource
349 * that covers the data registers. In that case don't try to handle
350 * GPIOs.
351 */
352 for (i = 0; i < pfc->num_windows; ++i) {
353 struct sh_pfc_window *window = &pfc->window[i];
354
355 if (pfc->info->data_regs[0].reg >= window->phys &&
356 pfc->info->data_regs[0].reg < window->phys + window->size)
357 break;
358 }
359
360 if (i == pfc->num_windows)
361 return 0;
362
357 /* Register the real GPIOs chip. */ 363 /* Register the real GPIOs chip. */
358 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); 364 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]);
359 if (IS_ERR(chip)) 365 if (IS_ERR(chip))
360 return PTR_ERR(chip); 366 return PTR_ERR(chip);
361 367
@@ -384,7 +390,10 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
384 } 390 }
385 391
386 /* Register the function GPIOs chip. */ 392 /* Register the function GPIOs chip. */
387 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); 393 if (pfc->info->nr_func_gpios == 0)
394 return 0;
395
396 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
388 if (IS_ERR(chip)) 397 if (IS_ERR(chip))
389 return PTR_ERR(chip); 398 return PTR_ERR(chip);
390 399
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
new file mode 100644
index 000000000000..bbff5596e922
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -0,0 +1,2587 @@
1/*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/pinctrl/pinconf-generic.h>
23#include <mach/irqs.h>
24#include <mach/r8a73a4.h>
25
26#include "core.h"
27#include "sh_pfc.h"
28
29#define CPU_ALL_PORT(fn, pfx, sfx) \
30 /* Port0 - Port30 */ \
31 PORT_10(fn, pfx, sfx), \
32 PORT_10(fn, pfx##1, sfx), \
33 PORT_10(fn, pfx##2, sfx), \
34 PORT_1(fn, pfx##30, sfx), \
35 /* Port32 - Port40 */ \
36 PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
37 PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
38 PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
39 PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
40 PORT_1(fn, pfx##40, sfx), \
41 /* Port64 - Port85 */ \
42 PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
43 PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
44 PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
45 PORT_10(fn, pfx##7, sfx), \
46 PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
47 PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
48 PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
49 /* Port96 - Port126 */ \
50 PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
51 PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
52 PORT_10(fn, pfx##10, sfx), \
53 PORT_10(fn, pfx##11, sfx), \
54 PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
55 PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
56 PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
57 PORT_1(fn, pfx##126, sfx), \
58 /* Port128 - Port134 */ \
59 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
60 PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
61 PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
62 PORT_1(fn, pfx##134, sfx), \
63 /* Port160 - Port178 */ \
64 PORT_10(fn, pfx##16, sfx), \
65 PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
66 PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
67 PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
68 PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
69 PORT_1(fn, pfx##178, sfx), \
70 /* Port192 - Port222 */ \
71 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
72 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
73 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
74 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
75 PORT_10(fn, pfx##20, sfx), \
76 PORT_10(fn, pfx##21, sfx), \
77 PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
78 PORT_1(fn, pfx##222, sfx), \
79 /* Port224 - Port250 */ \
80 PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
81 PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
82 PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
83 PORT_10(fn, pfx##23, sfx), \
84 PORT_10(fn, pfx##24, sfx), \
85 PORT_1(fn, pfx##250, sfx), \
86 /* Port256 - Port283 */ \
87 PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
88 PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
89 PORT_10(fn, pfx##26, sfx), \
90 PORT_10(fn, pfx##27, sfx), \
91 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
92 PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
93 /* Port288 - Port308 */ \
94 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
95 PORT_10(fn, pfx##29, sfx), \
96 PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
97 PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
98 PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
99 PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
100 PORT_1(fn, pfx##308, sfx), \
101 /* Port320 - Port329 */ \
102 PORT_10(fn, pfx##32, sfx)
103
104
105enum {
106 PINMUX_RESERVED = 0,
107
108 /* PORT0_DATA -> PORT329_DATA */
109 PINMUX_DATA_BEGIN,
110 PORT_ALL(DATA),
111 PINMUX_DATA_END,
112
113 /* PORT0_IN -> PORT329_IN */
114 PINMUX_INPUT_BEGIN,
115 PORT_ALL(IN),
116 PINMUX_INPUT_END,
117
118 /* PORT0_OUT -> PORT329_OUT */
119 PINMUX_OUTPUT_BEGIN,
120 PORT_ALL(OUT),
121 PINMUX_OUTPUT_END,
122
123 PINMUX_FUNCTION_BEGIN,
124 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
125 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
126 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
127 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
128 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
129 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
130 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
131 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
132 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
133 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
134
135 MSEL1CR_31_0, MSEL1CR_31_1,
136 MSEL1CR_27_0, MSEL1CR_27_1,
137 MSEL1CR_25_0, MSEL1CR_25_1,
138 MSEL1CR_24_0, MSEL1CR_24_1,
139 MSEL1CR_22_0, MSEL1CR_22_1,
140 MSEL1CR_21_0, MSEL1CR_21_1,
141 MSEL1CR_20_0, MSEL1CR_20_1,
142 MSEL1CR_19_0, MSEL1CR_19_1,
143 MSEL1CR_18_0, MSEL1CR_18_1,
144 MSEL1CR_17_0, MSEL1CR_17_1,
145 MSEL1CR_16_0, MSEL1CR_16_1,
146 MSEL1CR_15_0, MSEL1CR_15_1,
147 MSEL1CR_14_0, MSEL1CR_14_1,
148 MSEL1CR_13_0, MSEL1CR_13_1,
149 MSEL1CR_12_0, MSEL1CR_12_1,
150 MSEL1CR_11_0, MSEL1CR_11_1,
151 MSEL1CR_10_0, MSEL1CR_10_1,
152 MSEL1CR_09_0, MSEL1CR_09_1,
153 MSEL1CR_08_0, MSEL1CR_08_1,
154 MSEL1CR_07_0, MSEL1CR_07_1,
155 MSEL1CR_06_0, MSEL1CR_06_1,
156 MSEL1CR_05_0, MSEL1CR_05_1,
157 MSEL1CR_04_0, MSEL1CR_04_1,
158 MSEL1CR_03_0, MSEL1CR_03_1,
159 MSEL1CR_02_0, MSEL1CR_02_1,
160 MSEL1CR_01_0, MSEL1CR_01_1,
161 MSEL1CR_00_0, MSEL1CR_00_1,
162
163 MSEL3CR_31_0, MSEL3CR_31_1,
164 MSEL3CR_28_0, MSEL3CR_28_1,
165 MSEL3CR_27_0, MSEL3CR_27_1,
166 MSEL3CR_26_0, MSEL3CR_26_1,
167 MSEL3CR_23_0, MSEL3CR_23_1,
168 MSEL3CR_22_0, MSEL3CR_22_1,
169 MSEL3CR_21_0, MSEL3CR_21_1,
170 MSEL3CR_20_0, MSEL3CR_20_1,
171 MSEL3CR_19_0, MSEL3CR_19_1,
172 MSEL3CR_18_0, MSEL3CR_18_1,
173 MSEL3CR_17_0, MSEL3CR_17_1,
174 MSEL3CR_16_0, MSEL3CR_16_1,
175 MSEL3CR_15_0, MSEL3CR_15_1,
176 MSEL3CR_12_0, MSEL3CR_12_1,
177 MSEL3CR_11_0, MSEL3CR_11_1,
178 MSEL3CR_10_0, MSEL3CR_10_1,
179 MSEL3CR_09_0, MSEL3CR_09_1,
180 MSEL3CR_06_0, MSEL3CR_06_1,
181 MSEL3CR_03_0, MSEL3CR_03_1,
182 MSEL3CR_01_0, MSEL3CR_01_1,
183 MSEL3CR_00_0, MSEL3CR_00_1,
184
185 MSEL4CR_30_0, MSEL4CR_30_1,
186 MSEL4CR_29_0, MSEL4CR_29_1,
187 MSEL4CR_28_0, MSEL4CR_28_1,
188 MSEL4CR_27_0, MSEL4CR_27_1,
189 MSEL4CR_26_0, MSEL4CR_26_1,
190 MSEL4CR_25_0, MSEL4CR_25_1,
191 MSEL4CR_24_0, MSEL4CR_24_1,
192 MSEL4CR_23_0, MSEL4CR_23_1,
193 MSEL4CR_22_0, MSEL4CR_22_1,
194 MSEL4CR_21_0, MSEL4CR_21_1,
195 MSEL4CR_20_0, MSEL4CR_20_1,
196 MSEL4CR_19_0, MSEL4CR_19_1,
197 MSEL4CR_18_0, MSEL4CR_18_1,
198 MSEL4CR_17_0, MSEL4CR_17_1,
199 MSEL4CR_16_0, MSEL4CR_16_1,
200 MSEL4CR_15_0, MSEL4CR_15_1,
201 MSEL4CR_14_0, MSEL4CR_14_1,
202 MSEL4CR_13_0, MSEL4CR_13_1,
203 MSEL4CR_12_0, MSEL4CR_12_1,
204 MSEL4CR_11_0, MSEL4CR_11_1,
205 MSEL4CR_10_0, MSEL4CR_10_1,
206 MSEL4CR_09_0, MSEL4CR_09_1,
207 MSEL4CR_07_0, MSEL4CR_07_1,
208 MSEL4CR_04_0, MSEL4CR_04_1,
209 MSEL4CR_01_0, MSEL4CR_01_1,
210
211 MSEL5CR_31_0, MSEL5CR_31_1,
212 MSEL5CR_30_0, MSEL5CR_30_1,
213 MSEL5CR_29_0, MSEL5CR_29_1,
214 MSEL5CR_28_0, MSEL5CR_28_1,
215 MSEL5CR_27_0, MSEL5CR_27_1,
216 MSEL5CR_26_0, MSEL5CR_26_1,
217 MSEL5CR_25_0, MSEL5CR_25_1,
218 MSEL5CR_24_0, MSEL5CR_24_1,
219 MSEL5CR_23_0, MSEL5CR_23_1,
220 MSEL5CR_22_0, MSEL5CR_22_1,
221 MSEL5CR_21_0, MSEL5CR_21_1,
222 MSEL5CR_20_0, MSEL5CR_20_1,
223 MSEL5CR_19_0, MSEL5CR_19_1,
224 MSEL5CR_18_0, MSEL5CR_18_1,
225 MSEL5CR_17_0, MSEL5CR_17_1,
226 MSEL5CR_16_0, MSEL5CR_16_1,
227 MSEL5CR_15_0, MSEL5CR_15_1,
228 MSEL5CR_14_0, MSEL5CR_14_1,
229 MSEL5CR_13_0, MSEL5CR_13_1,
230 MSEL5CR_12_0, MSEL5CR_12_1,
231 MSEL5CR_11_0, MSEL5CR_11_1,
232 MSEL5CR_10_0, MSEL5CR_10_1,
233 MSEL5CR_09_0, MSEL5CR_09_1,
234 MSEL5CR_08_0, MSEL5CR_08_1,
235 MSEL5CR_07_0, MSEL5CR_07_1,
236 MSEL5CR_06_0, MSEL5CR_06_1,
237
238 MSEL8CR_16_0, MSEL8CR_16_1,
239 MSEL8CR_01_0, MSEL8CR_01_1,
240 MSEL8CR_00_0, MSEL8CR_00_1,
241
242 PINMUX_FUNCTION_END,
243
244 PINMUX_MARK_BEGIN,
245
246
247#define F1(a) a##_MARK
248#define F2(a) a##_MARK
249#define F3(a) a##_MARK
250#define F4(a) a##_MARK
251#define F5(a) a##_MARK
252#define F6(a) a##_MARK
253#define F7(a) a##_MARK
254#define IRQ(a) IRQ##a##_MARK
255
256 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
257 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
258 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
259 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
260 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
261 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
262 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
263 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
264 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
265 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
266 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
267 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
268 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
269 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
270 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
271 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
272 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
273 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
274 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
275 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
276 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
277 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
278 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
279 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
280 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
281 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
282 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
283 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
284 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
285 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
286 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
287 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
288
289 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
290 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
291 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
292 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
293 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
294 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
295 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
296 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
297 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
298 F7(CHSCIF0_HSCK), /* Port40 */
299
300 F1(PDM0_DATA), /* Port64 */
301 F1(PDM1_DATA),
302 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
303 IRQ(40),
304 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
305 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
306 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
307 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
308 F7(CHSCIF1_HRTS), /* Port70 */
309 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
310 F7(CHSCIF1_HCTS),
311 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
312 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
313 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
314 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
315 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
316
317 F1(KEYIN0), /* Port96 */
318 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
319 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
320 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
321 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
322 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
323 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
324 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
325 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
326 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
327 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
328 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
329 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
330 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
331 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
332 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
333 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
334 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
335 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
336 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
337 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
338 F5(SIM0_VOLTSEL1), /* Port130 */
339 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
340 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
341 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
342 IRQ(20), /* Port160 */
343 IRQ(21), IRQ(22), IRQ(23),
344 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
345 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
346 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
347 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
348 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
349 F1(A9), F2(MMCD1_6), IRQ(32),
350 F1(A8), F2(MMCD1_5), IRQ(33),
351 F1(A7), F2(MMCD1_4), IRQ(34),
352 F1(A6), F2(MMCD1_3), IRQ(35),
353 F1(A5), F2(MMCD1_2), IRQ(36),
354 F1(A4), F2(MMCD1_1), IRQ(37),
355 F1(A3), F2(MMCD1_0), IRQ(38),
356 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
357 F1(A1),
358 F1(A0), F2(BS),
359 F1(CKO), F2(MMCCLK1),
360 F1(CS0_N), F5(SIM0_GPO1),
361 F1(CS2_N), F5(SIM0_GPO2),
362 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
363 F1(D15), F5(GIO_OUT15),
364 F1(D14), F5(GIO_OUT14),
365 F1(D13), F5(GIO_OUT13),
366 F1(D12), F5(GIO_OUT12), /* Port210 */
367 F1(D11), F5(WGM_TXP2),
368 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
369 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
370 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
371 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
372 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
373 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
374 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
375 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
376 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
377 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
378 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
379 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
380 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
381 F1(WE0_N), F2(RDWR_227),
382 F1(WE1_N), F5(SIM0_GPO0),
383 F1(PWMO), F2(VIO_CKO1_229),
384 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
385 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
386 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
387 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
388 F1(FSIAISLD), F2(PDM3_DATA_235),
389 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
390 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
391 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
392 F1(FSIBISLD), /* Port240 */
393 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
394 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
395 F1(FSIBCK), F3(ISP_SHUTTER0_245),
396 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
397 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
398 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
399 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
400 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
401 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
402 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
403 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
404 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
405 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
406 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
407 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
408 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
409 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
410 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
411 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
412 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
413 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
414 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
415 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
416 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
417 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
418 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
419 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
420 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
421 F4(MSIOF6_SS1), /* Port300 */
422 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
423 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
424 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
425 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
426 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
427 IRQ(55), IRQ(56), IRQ(57),
428 PINMUX_MARK_END,
429};
430
431#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
432#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
433
434static const pinmux_enum_t pinmux_data[] = {
435 /* specify valid pin states for each pin in GPIO mode */
436 PINMUX_DATA_ALL(),
437
438 /* Port0 */
439 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
440 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
441 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
442 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
443
444 /* Port1 */
445 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
446 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
447 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
448 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
449
450 /* Port2 */
451 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
452 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
453 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
454 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
455
456 /* Port3 */
457 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
458 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
459 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
460 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
461
462 /* Port4 */
463 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
464 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
465 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
466 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
467
468 /* Port5 */
469 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
470 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
471 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
472 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
473
474 /* Port6 */
475 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
476 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
477 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
478 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
479
480 /* Port7 */
481 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
482 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
483 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
484 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
485
486 /* Port8 */
487 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
488 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
489 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
490 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
491
492 /* Port9 */
493 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
494 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
495 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
496 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
497
498 /* Port10 */
499 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
500 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
501 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
502 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
503
504 /* Port11 */
505 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
506 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
507 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
508 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
509
510 /* Port12 */
511 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
512 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
513 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
514 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
515
516 /* Port13 */
517 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
518 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
519 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
520 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
521 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
522
523 /* Port14 */
524 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
525 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
526 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
527 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
528 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
529
530 /* Port15 */
531 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
532 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
533 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
534 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
535
536 /* Port16 */
537 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
538 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
539 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
540
541 /* Port17 */
542 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
543 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
544 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
545
546 /* Port18 */
547 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
548 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
549 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
550
551 /* Port19 */
552 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
553 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
554 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
555
556 /* Port20 */
557 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
558 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
559 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
560
561 /* Port21 */
562 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
563 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
564 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
565
566 /* Port22 */
567 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
568 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
569 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
570
571 /* Port23 */
572 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
573 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
574 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
575
576 /* Port24 */
577 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
578 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
579 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
580 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
581
582 /* Port25 */
583 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
584 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
585 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
586
587 /* Port26 */
588 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
589 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
590 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
591 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
592
593 /* Port27 */
594 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
595 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
596 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
597 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
598
599 /* Port28 */
600 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
601 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
602 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
603
604 /* Port29 */
605 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
606 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
607 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
608
609 /* Port30 */
610 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
611 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
612 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
613
614 /* Port32 */
615 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
616 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
617 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
618
619 /* Port33 */
620 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
621 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
622 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
623
624 /* Port34 */
625 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
626 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
627 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
628
629 /* Port35 */
630 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
631 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
632
633 /* Port36 */
634 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
635 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
636
637 /* Port37 */
638 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
639 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
640
641 /* Port38 */
642 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
643 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
644 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
645 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
646
647 /* Port39 */
648 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
649 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
650 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
651 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
652
653 /* Port40 */
654 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
655 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
656 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
657 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
658
659 /* Port64 */
660 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
661
662 /* Port65 */
663 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
664
665 /* Port66 */
666 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
667 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
668 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
669 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
670 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
671
672 /* Port67 */
673 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
674 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
675 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
676 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
677
678 /* Port68 */
679 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
680 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
681 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
682 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
683
684 /* Port69 */
685 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
686 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
687 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
688 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
689
690 /* Port70 */
691 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
692 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
693 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
694 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
695 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
696
697 /* Port71 */
698 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
699 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
700 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
701 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
702 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
703
704 /* Port72 */
705 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
706 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
707 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
708 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
709
710 /* Port73 */
711 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
712 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
713 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
714 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
715
716 /* Port74 - Port85 */
717 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
718 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
719 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
720 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
721 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
722 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
723 PINMUX_DATA(TXP_MARK, PORT80_FN1),
724 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
725 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
726 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
727 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
728 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
729
730 /* Port96 - Port101 */
731 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
732 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
733 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
734 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
735 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
736 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
737
738 /* Port102 */
739 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
740 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
741
742 /* Port103 */
743 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
744 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
745
746 /* Port104 - Port108 */
747 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
748 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
749 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
750 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
751 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
752
753 /* Port109 */
754 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
755 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
756
757 /* Port110 */
758 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
759 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
760
761 /* Port111 */
762 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
763 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
764 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
765
766 /* Port112 */
767 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
768 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
769 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
770 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
771
772 /* Port113 */
773 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
774 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
775 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
776 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
777
778 /* Port114 */
779 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
780 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
781 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
782 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
783
784 /* Port115 */
785 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
786 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
787 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
788 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
789
790 /* Port116 */
791 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
792 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
793
794 /* Port117 */
795 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
796 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
797
798 /* Port118 */
799 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
800 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
801
802 /* Port119 */
803 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
804 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
805
806 /* Port120 */
807 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
808 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
809 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
810
811 /* Port121 */
812 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
813 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
814
815 /* Port122 */
816 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
817 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
818
819 /* Port123 */
820 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
821 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
822
823 /* Port124 */
824 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
825
826 /* Port125 */
827 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
828 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
829 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
830 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
831
832 /* Port126 */
833 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
834 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
835 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
836
837 /* Port128 */
838 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
839 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
840 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
841 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
842
843 /* Port129 */
844 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
845 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
846 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
847
848 /* Port130 */
849 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
850 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
851 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
852 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
853
854 /* Port131 */
855 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
856 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
857
858 /* Port132 */
859 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
860 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
861 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
862
863 /* Port133 */
864 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
865 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
866 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
867 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
868
869 /* Port134 */
870 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
871 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
872 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
873
874 /* Port160 - Port178 */
875 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
876 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
877 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
878 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
879 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
880 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
881 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
882 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
883 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
884 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
885 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
886 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
887 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
888 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
889 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
890 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
891 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
892 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
893 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
894
895 /* Port192 - Port200 FN1 */
896 PINMUX_DATA(A10_MARK, PORT192_FN1),
897 PINMUX_DATA(A9_MARK, PORT193_FN1),
898 PINMUX_DATA(A8_MARK, PORT194_FN1),
899 PINMUX_DATA(A7_MARK, PORT195_FN1),
900 PINMUX_DATA(A6_MARK, PORT196_FN1),
901 PINMUX_DATA(A5_MARK, PORT197_FN1),
902 PINMUX_DATA(A4_MARK, PORT198_FN1),
903 PINMUX_DATA(A3_MARK, PORT199_FN1),
904 PINMUX_DATA(A2_MARK, PORT200_FN1),
905
906 /* Port192 - Port200 FN2 */
907 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
908 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
909 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
910 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
911 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
912 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
913 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
914 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
915 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
916
917 /* Port192 - Port200 IRQ */
918 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
919 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
920 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
921 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
922 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
923 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
924 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
925 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
926 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
927
928 /* Port201 */
929 PINMUX_DATA(A1_MARK, PORT201_FN1),
930
931 /* Port202 */
932 PINMUX_DATA(A0_MARK, PORT202_FN1),
933 PINMUX_DATA(BS_MARK, PORT202_FN2),
934
935 /* Port203 */
936 PINMUX_DATA(CKO_MARK, PORT203_FN1),
937 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
938
939 /* Port204 */
940 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
941 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
942
943 /* Port205 */
944 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
945 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
946
947 /* Port206 */
948 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
949 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
950 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
951
952 /* Port207 - Port212 FN1 */
953 PINMUX_DATA(D15_MARK, PORT207_FN1),
954 PINMUX_DATA(D14_MARK, PORT208_FN1),
955 PINMUX_DATA(D13_MARK, PORT209_FN1),
956 PINMUX_DATA(D12_MARK, PORT210_FN1),
957 PINMUX_DATA(D11_MARK, PORT211_FN1),
958 PINMUX_DATA(D10_MARK, PORT212_FN1),
959
960 /* Port207 - Port212 FN5 */
961 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
962 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
963 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
964 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
965 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
966 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
967
968 /* Port213 - Port222 FN1 */
969 PINMUX_DATA(D9_MARK, PORT213_FN1),
970 PINMUX_DATA(D8_MARK, PORT214_FN1),
971 PINMUX_DATA(D7_MARK, PORT215_FN1),
972 PINMUX_DATA(D6_MARK, PORT216_FN1),
973 PINMUX_DATA(D5_MARK, PORT217_FN1),
974 PINMUX_DATA(D4_MARK, PORT218_FN1),
975 PINMUX_DATA(D3_MARK, PORT219_FN1),
976 PINMUX_DATA(D2_MARK, PORT220_FN1),
977 PINMUX_DATA(D1_MARK, PORT221_FN1),
978 PINMUX_DATA(D0_MARK, PORT222_FN1),
979
980 /* Port213 - Port222 FN2 */
981 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
982 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
983 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
984 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
985 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
986 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
987 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
988 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
989 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
990 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
991
992 /* Port213 - Port222 FN5 */
993 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
994 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
995 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
996 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
997 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
998 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
999 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
1000 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
1001 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
1002 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
1003
1004 /* Port224 */
1005 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1006 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1007 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1008
1009 /* Port225 */
1010 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1011
1012 /* Port226 */
1013 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1014 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1015 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1016
1017 /* Port227 */
1018 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1019 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1020
1021 /* Port228 */
1022 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1023 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1024
1025 /* Port229 */
1026 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1027 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1028
1029 /* Port230 */
1030 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1031 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1032
1033 /* Port231 */
1034 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1035 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1036
1037 /* Port232 */
1038 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1039 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1040
1041 /* Port233 */
1042 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1043 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1044
1045 /* Port234 */
1046 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1047 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1048 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1049
1050 /* Port235 */
1051 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1052 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1053
1054 /* Port236 */
1055 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1056 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1057 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1058
1059 /* Port237 */
1060 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1061 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1062
1063 /* Port238 */
1064 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1065 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1066
1067 /* Port239 */
1068 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1069 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1070
1071 /* Port240 */
1072 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1073
1074 /* Port241 */
1075 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1076 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1077
1078 /* Port242 */
1079 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1080 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1081
1082 /* Port243 */
1083 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1084 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1085
1086 /* Port244 */
1087 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1088 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1089
1090 /* Port245 */
1091 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1092 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1093
1094 /* Port246 - Port250 FN1 */
1095 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1096 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1097 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1098 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1099 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1100
1101 /* Port256 - Port258 */
1102 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1103 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1104 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1105
1106 /* Port259 */
1107 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1108 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1109
1110 /* Port260 */
1111 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1112
1113 /* Port261 */
1114 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1115 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1116
1117 /* Port262 */
1118 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1119
1120 /* Port263 - Port266 FN1 */
1121 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1122 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1123 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1124 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1125
1126 /* Port263 - Port266 FN4 */
1127 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1128 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1129 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1130 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1131
1132 /* Port267 */
1133 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1134
1135 /* Port268 */
1136 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1137 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1138
1139 /* Port269 */
1140 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1141 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1142
1143 /* Port270 - Port273 FN1 */
1144 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1145 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1146 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1147 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1148
1149 /* Port270 - Port273 FN3 */
1150 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1151 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1152 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1153 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1154
1155 /* Port274 */
1156 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1157 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1158
1159 /* Port275 - Port280 */
1160 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1161 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1162 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1163 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1164 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1165 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1166
1167 /* Port281 */
1168 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1169 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1170
1171 /* Port282 */
1172 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1173 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1174
1175 /* Port283 */
1176 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1177
1178 /* Port289 */
1179 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1180 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1181
1182 /* Port290 */
1183 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1184 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1185 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1186
1187 /* Port291 - Port294 FN1 */
1188 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1189 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1190 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1191 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1192
1193 /* Port291 - Port294 FN3 */
1194 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1195 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1196 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1197 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1198
1199 /* Port295 */
1200 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1201 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1202 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1203 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1204
1205 /* Port296 */
1206 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1207 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1208 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1209
1210 /* Port297 - Port300 FN1 */
1211 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1212 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1213 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1214 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1215
1216 /* Port297 - Port300 FN2 */
1217 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1218 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1219 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1220 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1221
1222 /* Port297 - Port300 FN3 */
1223 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1224 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1225 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1226 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1227
1228 /* Port297 - Port300 FN4 */
1229 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1230 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1231 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1232 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1233
1234 /* Port301 */
1235 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1236 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1237
1238 /* Port302 - Port306 FN1 */
1239 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1240 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1241 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1242 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1243 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1244
1245 /* Port302 - Port306 FN3 */
1246 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1247 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1248 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1249 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1250 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1251
1252 /* Port307 */
1253 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1254
1255 /* Port308 */
1256 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1257 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1258
1259 /* Port320 - Port329 */
1260 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1261 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1262 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1263 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1264 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1265 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1266 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1267 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1268 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1269 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1270};
1271
1272#define R8A73A4_PIN(pin, cfgs) \
1273 { \
1274 .name = __stringify(PORT##pin), \
1275 .enum_id = PORT##pin##_DATA, \
1276 .configs = cfgs, \
1277 }
1278
1279#define __O (SH_PFC_PIN_CFG_OUTPUT)
1280#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1281#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1282
1283#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
1284#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
1285
1286static struct sh_pfc_pin pinmux_pins[] = {
1287 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1288 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1289 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1290 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1291 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1292 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1293 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1294 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1295 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1296 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1297 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1298 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1299 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1300 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1301 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1302 R8A73A4_PIN_IO_PU_PD(30),
1303 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1304 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1305 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1306 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1307 R8A73A4_PIN_IO_PU_PD(40),
1308 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1309 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1310 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1311 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1312 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1313 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1314 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1315 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1316 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1317 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1318 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1319 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1320 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1321 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1322 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1323 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1324 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1325 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1326 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1327 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1328 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1329 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1330 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1331 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1332 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1333 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1334 R8A73A4_PIN_IO_PU_PD(126),
1335 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1336 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1337 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1338 R8A73A4_PIN_IO_PU_PD(134),
1339 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1340 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1341 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1342 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1343 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1344 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1345 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1346 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1347 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1348 R8A73A4_PIN_IO_PU_PD(178),
1349 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1350 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1351 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1352 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1353 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1354 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1355 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1356 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1357 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1358 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1359 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1360 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1361 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1362 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1363 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1364 R8A73A4_PIN_IO_PU_PD(222),
1365 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1366 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1367 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1368 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1369 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1370 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1371 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1372 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1373 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1374 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1375 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1376 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1377 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1378 R8A73A4_PIN_IO_PU_PD(250),
1379 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1380 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1381 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1382 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1383 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1384 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1385 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1386 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1387 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1388 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1389 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1390 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1391 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1392 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1393 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1394 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1395 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1396 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1397 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1398 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1399 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1400 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1401 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1402 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1403 R8A73A4_PIN_IO_PU_PD(308),
1404 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1405 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1406 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1407 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1408 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1409};
1410
1411static const struct pinmux_range pinmux_ranges[] = {
1412 {.begin = 0, .end = 30,},
1413 {.begin = 32, .end = 40,},
1414 {.begin = 64, .end = 85,},
1415 {.begin = 96, .end = 126,},
1416 {.begin = 128, .end = 134,},
1417 {.begin = 160, .end = 178,},
1418 {.begin = 192, .end = 222,},
1419 {.begin = 224, .end = 250,},
1420 {.begin = 256, .end = 283,},
1421 {.begin = 288, .end = 308,},
1422 {.begin = 320, .end = 329,},
1423};
1424
1425/* - IRQC ------------------------------------------------------------------- */
1426#define IRQC_PINS_MUX(pin, irq_mark) \
1427static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1428 pin, \
1429}; \
1430static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1431 IRQ##irq_mark##_MARK, \
1432}
1433IRQC_PINS_MUX(0, 0);
1434IRQC_PINS_MUX(1, 1);
1435IRQC_PINS_MUX(2, 2);
1436IRQC_PINS_MUX(3, 3);
1437IRQC_PINS_MUX(4, 4);
1438IRQC_PINS_MUX(5, 5);
1439IRQC_PINS_MUX(6, 6);
1440IRQC_PINS_MUX(7, 7);
1441IRQC_PINS_MUX(8, 8);
1442IRQC_PINS_MUX(9, 9);
1443IRQC_PINS_MUX(10, 10);
1444IRQC_PINS_MUX(11, 11);
1445IRQC_PINS_MUX(12, 12);
1446IRQC_PINS_MUX(13, 13);
1447IRQC_PINS_MUX(14, 14);
1448IRQC_PINS_MUX(15, 15);
1449IRQC_PINS_MUX(66, 40);
1450IRQC_PINS_MUX(84, 19);
1451IRQC_PINS_MUX(85, 18);
1452IRQC_PINS_MUX(102, 41);
1453IRQC_PINS_MUX(103, 42);
1454IRQC_PINS_MUX(109, 43);
1455IRQC_PINS_MUX(110, 44);
1456IRQC_PINS_MUX(111, 45);
1457IRQC_PINS_MUX(112, 46);
1458IRQC_PINS_MUX(113, 47);
1459IRQC_PINS_MUX(114, 48);
1460IRQC_PINS_MUX(115, 49);
1461IRQC_PINS_MUX(160, 20);
1462IRQC_PINS_MUX(161, 21);
1463IRQC_PINS_MUX(162, 22);
1464IRQC_PINS_MUX(163, 23);
1465IRQC_PINS_MUX(175, 24);
1466IRQC_PINS_MUX(176, 25);
1467IRQC_PINS_MUX(177, 26);
1468IRQC_PINS_MUX(178, 27);
1469IRQC_PINS_MUX(192, 31);
1470IRQC_PINS_MUX(193, 32);
1471IRQC_PINS_MUX(194, 33);
1472IRQC_PINS_MUX(195, 34);
1473IRQC_PINS_MUX(196, 35);
1474IRQC_PINS_MUX(197, 36);
1475IRQC_PINS_MUX(198, 37);
1476IRQC_PINS_MUX(199, 38);
1477IRQC_PINS_MUX(200, 39);
1478IRQC_PINS_MUX(290, 51);
1479IRQC_PINS_MUX(296, 52);
1480IRQC_PINS_MUX(301, 50);
1481IRQC_PINS_MUX(320, 16);
1482IRQC_PINS_MUX(321, 17);
1483IRQC_PINS_MUX(322, 28);
1484IRQC_PINS_MUX(323, 29);
1485IRQC_PINS_MUX(324, 30);
1486IRQC_PINS_MUX(325, 53);
1487IRQC_PINS_MUX(326, 54);
1488IRQC_PINS_MUX(327, 55);
1489IRQC_PINS_MUX(328, 56);
1490IRQC_PINS_MUX(329, 57);
1491/* - SCIFA0 ----------------------------------------------------------------- */
1492static const unsigned int scifa0_data_pins[] = {
1493 /* SCIFA0_RXD, SCIFA0_TXD */
1494 117, 116,
1495};
1496static const unsigned int scifa0_data_mux[] = {
1497 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1498};
1499static const unsigned int scifa0_clk_pins[] = {
1500 /* SCIFA0_SCK */
1501 34,
1502};
1503static const unsigned int scifa0_clk_mux[] = {
1504 SCIFA0_SCK_MARK,
1505};
1506static const unsigned int scifa0_ctrl_pins[] = {
1507 /* SCIFA0_RTS, SCIFA0_CTS */
1508 32, 33,
1509};
1510static const unsigned int scifa0_ctrl_mux[] = {
1511 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1512};
1513/* - SCIFA1 ----------------------------------------------------------------- */
1514static const unsigned int scifa1_data_pins[] = {
1515 /* SCIFA1_RXD, SCIFA1_TXD */
1516 119, 118,
1517};
1518static const unsigned int scifa1_data_mux[] = {
1519 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1520};
1521static const unsigned int scifa1_clk_pins[] = {
1522 /* SCIFA1_SCK */
1523 37,
1524};
1525static const unsigned int scifa1_clk_mux[] = {
1526 SCIFA1_SCK_MARK,
1527};
1528static const unsigned int scifa1_ctrl_pins[] = {
1529 /* SCIFA1_RTS, SCIFA1_CTS */
1530 35, 36,
1531};
1532static const unsigned int scifa1_ctrl_mux[] = {
1533 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1534};
1535/* - SCIFB0 ----------------------------------------------------------------- */
1536static const unsigned int scifb0_data_pins[] = {
1537 /* SCIFB0_RXD, SCIFB0_TXD */
1538 123, 122,
1539};
1540static const unsigned int scifb0_data_mux[] = {
1541 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1542};
1543static const unsigned int scifb0_clk_pins[] = {
1544 /* SCIFB0_SCK */
1545 40,
1546};
1547static const unsigned int scifb0_clk_mux[] = {
1548 SCIFB0_SCK_MARK,
1549};
1550static const unsigned int scifb0_ctrl_pins[] = {
1551 /* SCIFB0_RTS, SCIFB0_CTS */
1552 38, 39,
1553};
1554static const unsigned int scifb0_ctrl_mux[] = {
1555 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1556};
1557/* - SCIFB1 ----------------------------------------------------------------- */
1558static const unsigned int scifb1_data_pins[] = {
1559 /* SCIFB1_RXD, SCIFB1_TXD */
1560 27, 26,
1561};
1562static const unsigned int scifb1_data_mux[] = {
1563 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1564};
1565static const unsigned int scifb1_clk_pins[] = {
1566 /* SCIFB1_SCK */
1567 28,
1568};
1569static const unsigned int scifb1_clk_mux[] = {
1570 SCIFB1_SCK_28_MARK,
1571};
1572static const unsigned int scifb1_ctrl_pins[] = {
1573 /* SCIFB1_RTS, SCIFB1_CTS */
1574 24, 25,
1575};
1576static const unsigned int scifb1_ctrl_mux[] = {
1577 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1578};
1579static const unsigned int scifb1_data_b_pins[] = {
1580 /* SCIFB1_RXD, SCIFB1_TXD */
1581 72, 67,
1582};
1583static const unsigned int scifb1_data_b_mux[] = {
1584 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1585};
1586static const unsigned int scifb1_clk_b_pins[] = {
1587 /* SCIFB1_SCK */
1588 261,
1589};
1590static const unsigned int scifb1_clk_b_mux[] = {
1591 SCIFB1_SCK_261_MARK,
1592};
1593static const unsigned int scifb1_ctrl_b_pins[] = {
1594 /* SCIFB1_RTS, SCIFB1_CTS */
1595 70, 71,
1596};
1597static const unsigned int scifb1_ctrl_b_mux[] = {
1598 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1599};
1600/* - SCIFB2 ----------------------------------------------------------------- */
1601static const unsigned int scifb2_data_pins[] = {
1602 /* SCIFB2_RXD, SCIFB2_TXD */
1603 69, 68,
1604};
1605static const unsigned int scifb2_data_mux[] = {
1606 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1607};
1608static const unsigned int scifb2_clk_pins[] = {
1609 /* SCIFB2_SCK */
1610 262,
1611};
1612static const unsigned int scifb2_clk_mux[] = {
1613 SCIFB2_SCK_262_MARK,
1614};
1615static const unsigned int scifb2_ctrl_pins[] = {
1616 /* SCIFB2_RTS, SCIFB2_CTS */
1617 73, 66,
1618};
1619static const unsigned int scifb2_ctrl_mux[] = {
1620 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1621};
1622static const unsigned int scifb2_data_b_pins[] = {
1623 /* SCIFB2_RXD, SCIFB2_TXD */
1624 297, 295,
1625};
1626static const unsigned int scifb2_data_b_mux[] = {
1627 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1628};
1629static const unsigned int scifb2_clk_b_pins[] = {
1630 /* SCIFB2_SCK */
1631 299,
1632};
1633static const unsigned int scifb2_clk_b_mux[] = {
1634 SCIFB2_SCK_299_MARK,
1635};
1636static const unsigned int scifb2_ctrl_b_pins[] = {
1637 /* SCIFB2_RTS, SCIFB2_CTS */
1638 300, 298,
1639};
1640static const unsigned int scifb2_ctrl_b_mux[] = {
1641 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1642};
1643/* - SCIFB3 ----------------------------------------------------------------- */
1644static const unsigned int scifb3_data_pins[] = {
1645 /* SCIFB3_RXD, SCIFB3_TXD */
1646 22, 21,
1647};
1648static const unsigned int scifb3_data_mux[] = {
1649 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1650};
1651static const unsigned int scifb3_clk_pins[] = {
1652 /* SCIFB3_SCK */
1653 23,
1654};
1655static const unsigned int scifb3_clk_mux[] = {
1656 SCIFB3_SCK_23_MARK,
1657};
1658static const unsigned int scifb3_ctrl_pins[] = {
1659 /* SCIFB3_RTS, SCIFB3_CTS */
1660 19, 20,
1661};
1662static const unsigned int scifb3_ctrl_mux[] = {
1663 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1664};
1665static const unsigned int scifb3_data_b_pins[] = {
1666 /* SCIFB3_RXD, SCIFB3_TXD */
1667 120, 121,
1668};
1669static const unsigned int scifb3_data_b_mux[] = {
1670 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1671};
1672static const unsigned int scifb3_clk_b_pins[] = {
1673 /* SCIFB3_SCK */
1674 40,
1675};
1676static const unsigned int scifb3_clk_b_mux[] = {
1677 SCIFB3_SCK_40_MARK,
1678};
1679static const unsigned int scifb3_ctrl_b_pins[] = {
1680 /* SCIFB3_RTS, SCIFB3_CTS */
1681 38, 39,
1682};
1683static const unsigned int scifb3_ctrl_b_mux[] = {
1684 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1685};
1686
1687static const struct sh_pfc_pin_group pinmux_groups[] = {
1688 SH_PFC_PIN_GROUP(irqc_irq0),
1689 SH_PFC_PIN_GROUP(irqc_irq1),
1690 SH_PFC_PIN_GROUP(irqc_irq2),
1691 SH_PFC_PIN_GROUP(irqc_irq3),
1692 SH_PFC_PIN_GROUP(irqc_irq4),
1693 SH_PFC_PIN_GROUP(irqc_irq5),
1694 SH_PFC_PIN_GROUP(irqc_irq6),
1695 SH_PFC_PIN_GROUP(irqc_irq7),
1696 SH_PFC_PIN_GROUP(irqc_irq8),
1697 SH_PFC_PIN_GROUP(irqc_irq9),
1698 SH_PFC_PIN_GROUP(irqc_irq10),
1699 SH_PFC_PIN_GROUP(irqc_irq11),
1700 SH_PFC_PIN_GROUP(irqc_irq12),
1701 SH_PFC_PIN_GROUP(irqc_irq13),
1702 SH_PFC_PIN_GROUP(irqc_irq14),
1703 SH_PFC_PIN_GROUP(irqc_irq15),
1704 SH_PFC_PIN_GROUP(irqc_irq16),
1705 SH_PFC_PIN_GROUP(irqc_irq17),
1706 SH_PFC_PIN_GROUP(irqc_irq18),
1707 SH_PFC_PIN_GROUP(irqc_irq19),
1708 SH_PFC_PIN_GROUP(irqc_irq20),
1709 SH_PFC_PIN_GROUP(irqc_irq21),
1710 SH_PFC_PIN_GROUP(irqc_irq22),
1711 SH_PFC_PIN_GROUP(irqc_irq23),
1712 SH_PFC_PIN_GROUP(irqc_irq24),
1713 SH_PFC_PIN_GROUP(irqc_irq25),
1714 SH_PFC_PIN_GROUP(irqc_irq26),
1715 SH_PFC_PIN_GROUP(irqc_irq27),
1716 SH_PFC_PIN_GROUP(irqc_irq28),
1717 SH_PFC_PIN_GROUP(irqc_irq29),
1718 SH_PFC_PIN_GROUP(irqc_irq30),
1719 SH_PFC_PIN_GROUP(irqc_irq31),
1720 SH_PFC_PIN_GROUP(irqc_irq32),
1721 SH_PFC_PIN_GROUP(irqc_irq33),
1722 SH_PFC_PIN_GROUP(irqc_irq34),
1723 SH_PFC_PIN_GROUP(irqc_irq35),
1724 SH_PFC_PIN_GROUP(irqc_irq36),
1725 SH_PFC_PIN_GROUP(irqc_irq37),
1726 SH_PFC_PIN_GROUP(irqc_irq38),
1727 SH_PFC_PIN_GROUP(irqc_irq39),
1728 SH_PFC_PIN_GROUP(irqc_irq40),
1729 SH_PFC_PIN_GROUP(irqc_irq41),
1730 SH_PFC_PIN_GROUP(irqc_irq42),
1731 SH_PFC_PIN_GROUP(irqc_irq43),
1732 SH_PFC_PIN_GROUP(irqc_irq44),
1733 SH_PFC_PIN_GROUP(irqc_irq45),
1734 SH_PFC_PIN_GROUP(irqc_irq46),
1735 SH_PFC_PIN_GROUP(irqc_irq47),
1736 SH_PFC_PIN_GROUP(irqc_irq48),
1737 SH_PFC_PIN_GROUP(irqc_irq49),
1738 SH_PFC_PIN_GROUP(irqc_irq50),
1739 SH_PFC_PIN_GROUP(irqc_irq51),
1740 SH_PFC_PIN_GROUP(irqc_irq52),
1741 SH_PFC_PIN_GROUP(irqc_irq53),
1742 SH_PFC_PIN_GROUP(irqc_irq54),
1743 SH_PFC_PIN_GROUP(irqc_irq55),
1744 SH_PFC_PIN_GROUP(irqc_irq56),
1745 SH_PFC_PIN_GROUP(irqc_irq57),
1746 SH_PFC_PIN_GROUP(scifa0_data),
1747 SH_PFC_PIN_GROUP(scifa0_clk),
1748 SH_PFC_PIN_GROUP(scifa0_ctrl),
1749 SH_PFC_PIN_GROUP(scifa1_data),
1750 SH_PFC_PIN_GROUP(scifa1_clk),
1751 SH_PFC_PIN_GROUP(scifa1_ctrl),
1752 SH_PFC_PIN_GROUP(scifb0_data),
1753 SH_PFC_PIN_GROUP(scifb0_clk),
1754 SH_PFC_PIN_GROUP(scifb0_ctrl),
1755 SH_PFC_PIN_GROUP(scifb1_data),
1756 SH_PFC_PIN_GROUP(scifb1_clk),
1757 SH_PFC_PIN_GROUP(scifb1_ctrl),
1758 SH_PFC_PIN_GROUP(scifb1_data_b),
1759 SH_PFC_PIN_GROUP(scifb1_clk_b),
1760 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1761 SH_PFC_PIN_GROUP(scifb2_data),
1762 SH_PFC_PIN_GROUP(scifb2_clk),
1763 SH_PFC_PIN_GROUP(scifb2_ctrl),
1764 SH_PFC_PIN_GROUP(scifb2_data_b),
1765 SH_PFC_PIN_GROUP(scifb2_clk_b),
1766 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1767 SH_PFC_PIN_GROUP(scifb3_data),
1768 SH_PFC_PIN_GROUP(scifb3_clk),
1769 SH_PFC_PIN_GROUP(scifb3_ctrl),
1770 SH_PFC_PIN_GROUP(scifb3_data_b),
1771 SH_PFC_PIN_GROUP(scifb3_clk_b),
1772 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1773};
1774
1775static const char * const irqc_groups[] = {
1776 "irqc_irq0",
1777 "irqc_irq1",
1778 "irqc_irq2",
1779 "irqc_irq3",
1780 "irqc_irq4",
1781 "irqc_irq5",
1782 "irqc_irq6",
1783 "irqc_irq7",
1784 "irqc_irq8",
1785 "irqc_irq9",
1786 "irqc_irq10",
1787 "irqc_irq11",
1788 "irqc_irq12",
1789 "irqc_irq13",
1790 "irqc_irq14",
1791 "irqc_irq15",
1792 "irqc_irq16",
1793 "irqc_irq17",
1794 "irqc_irq18",
1795 "irqc_irq19",
1796 "irqc_irq20",
1797 "irqc_irq21",
1798 "irqc_irq22",
1799 "irqc_irq23",
1800 "irqc_irq24",
1801 "irqc_irq25",
1802 "irqc_irq26",
1803 "irqc_irq27",
1804 "irqc_irq28",
1805 "irqc_irq29",
1806 "irqc_irq30",
1807 "irqc_irq31",
1808 "irqc_irq32",
1809 "irqc_irq33",
1810 "irqc_irq34",
1811 "irqc_irq35",
1812 "irqc_irq36",
1813 "irqc_irq37",
1814 "irqc_irq38",
1815 "irqc_irq39",
1816 "irqc_irq40",
1817 "irqc_irq41",
1818 "irqc_irq42",
1819 "irqc_irq43",
1820 "irqc_irq44",
1821 "irqc_irq45",
1822 "irqc_irq46",
1823 "irqc_irq47",
1824 "irqc_irq48",
1825 "irqc_irq49",
1826 "irqc_irq50",
1827 "irqc_irq51",
1828 "irqc_irq52",
1829 "irqc_irq53",
1830 "irqc_irq54",
1831 "irqc_irq55",
1832 "irqc_irq56",
1833 "irqc_irq57",
1834};
1835
1836static const char * const scifa0_groups[] = {
1837 "scifa0_data",
1838 "scifa0_clk",
1839 "scifa0_ctrl",
1840};
1841
1842static const char * const scifa1_groups[] = {
1843 "scifa1_data",
1844 "scifa1_clk",
1845 "scifa1_ctrl",
1846};
1847
1848static const char * const scifb0_groups[] = {
1849 "scifb0_data",
1850 "scifb0_clk",
1851 "scifb0_ctrl",
1852};
1853
1854static const char * const scifb1_groups[] = {
1855 "scifb1_data",
1856 "scifb1_clk",
1857 "scifb1_ctrl",
1858 "scifb1_data_b",
1859 "scifb1_clk_b",
1860 "scifb1_ctrl_b",
1861};
1862
1863static const char * const scifb2_groups[] = {
1864 "scifb2_data",
1865 "scifb2_clk",
1866 "scifb2_ctrl",
1867 "scifb2_data_b",
1868 "scifb2_clk_b",
1869 "scifb2_ctrl_b",
1870};
1871
1872static const char * const scifb3_groups[] = {
1873 "scifb3_data",
1874 "scifb3_clk",
1875 "scifb3_ctrl",
1876 "scifb3_data_b",
1877 "scifb3_clk_b",
1878 "scifb3_ctrl_b",
1879};
1880
1881static const struct sh_pfc_function pinmux_functions[] = {
1882 SH_PFC_FUNCTION(irqc),
1883 SH_PFC_FUNCTION(scifa0),
1884 SH_PFC_FUNCTION(scifa1),
1885 SH_PFC_FUNCTION(scifb0),
1886 SH_PFC_FUNCTION(scifb1),
1887 SH_PFC_FUNCTION(scifb2),
1888 SH_PFC_FUNCTION(scifb3),
1889};
1890
1891#undef PORTCR
1892#define PORTCR(nr, reg) \
1893 { \
1894 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1895 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
1896 PORT##nr##_FN0, PORT##nr##_FN1, \
1897 PORT##nr##_FN2, PORT##nr##_FN3, \
1898 PORT##nr##_FN4, PORT##nr##_FN5, \
1899 PORT##nr##_FN6, PORT##nr##_FN7 } \
1900 }
1901
1902static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1903 PORTCR(0, 0xe6050000),
1904 PORTCR(1, 0xe6050001),
1905 PORTCR(2, 0xe6050002),
1906 PORTCR(3, 0xe6050003),
1907 PORTCR(4, 0xe6050004),
1908 PORTCR(5, 0xe6050005),
1909 PORTCR(6, 0xe6050006),
1910 PORTCR(7, 0xe6050007),
1911 PORTCR(8, 0xe6050008),
1912 PORTCR(9, 0xe6050009),
1913 PORTCR(10, 0xe605000A),
1914 PORTCR(11, 0xe605000B),
1915 PORTCR(12, 0xe605000C),
1916 PORTCR(13, 0xe605000D),
1917 PORTCR(14, 0xe605000E),
1918 PORTCR(15, 0xe605000F),
1919 PORTCR(16, 0xe6050010),
1920 PORTCR(17, 0xe6050011),
1921 PORTCR(18, 0xe6050012),
1922 PORTCR(19, 0xe6050013),
1923 PORTCR(20, 0xe6050014),
1924 PORTCR(21, 0xe6050015),
1925 PORTCR(22, 0xe6050016),
1926 PORTCR(23, 0xe6050017),
1927 PORTCR(24, 0xe6050018),
1928 PORTCR(25, 0xe6050019),
1929 PORTCR(26, 0xe605001A),
1930 PORTCR(27, 0xe605001B),
1931 PORTCR(28, 0xe605001C),
1932 PORTCR(29, 0xe605001D),
1933 PORTCR(30, 0xe605001E),
1934 PORTCR(32, 0xe6051020),
1935 PORTCR(33, 0xe6051021),
1936 PORTCR(34, 0xe6051022),
1937 PORTCR(35, 0xe6051023),
1938 PORTCR(36, 0xe6051024),
1939 PORTCR(37, 0xe6051025),
1940 PORTCR(38, 0xe6051026),
1941 PORTCR(39, 0xe6051027),
1942 PORTCR(40, 0xe6051028),
1943 PORTCR(64, 0xe6050040),
1944 PORTCR(65, 0xe6050041),
1945 PORTCR(66, 0xe6050042),
1946 PORTCR(67, 0xe6050043),
1947 PORTCR(68, 0xe6050044),
1948 PORTCR(69, 0xe6050045),
1949 PORTCR(70, 0xe6050046),
1950 PORTCR(71, 0xe6050047),
1951 PORTCR(72, 0xe6050048),
1952 PORTCR(73, 0xe6050049),
1953 PORTCR(74, 0xe605004A),
1954 PORTCR(75, 0xe605004B),
1955 PORTCR(76, 0xe605004C),
1956 PORTCR(77, 0xe605004D),
1957 PORTCR(78, 0xe605004E),
1958 PORTCR(79, 0xe605004F),
1959 PORTCR(80, 0xe6050050),
1960 PORTCR(81, 0xe6050051),
1961 PORTCR(82, 0xe6050052),
1962 PORTCR(83, 0xe6050053),
1963 PORTCR(84, 0xe6050054),
1964 PORTCR(85, 0xe6050055),
1965 PORTCR(96, 0xe6051060),
1966 PORTCR(97, 0xe6051061),
1967 PORTCR(98, 0xe6051062),
1968 PORTCR(99, 0xe6051063),
1969 PORTCR(100, 0xe6051064),
1970 PORTCR(101, 0xe6051065),
1971 PORTCR(102, 0xe6051066),
1972 PORTCR(103, 0xe6051067),
1973 PORTCR(104, 0xe6051068),
1974 PORTCR(105, 0xe6051069),
1975 PORTCR(106, 0xe605106A),
1976 PORTCR(107, 0xe605106B),
1977 PORTCR(108, 0xe605106C),
1978 PORTCR(109, 0xe605106D),
1979 PORTCR(110, 0xe605106E),
1980 PORTCR(111, 0xe605106F),
1981 PORTCR(112, 0xe6051070),
1982 PORTCR(113, 0xe6051071),
1983 PORTCR(114, 0xe6051072),
1984 PORTCR(115, 0xe6051073),
1985 PORTCR(116, 0xe6051074),
1986 PORTCR(117, 0xe6051075),
1987 PORTCR(118, 0xe6051076),
1988 PORTCR(119, 0xe6051077),
1989 PORTCR(120, 0xe6051078),
1990 PORTCR(121, 0xe6051079),
1991 PORTCR(122, 0xe605107A),
1992 PORTCR(123, 0xe605107B),
1993 PORTCR(124, 0xe605107C),
1994 PORTCR(125, 0xe605107D),
1995 PORTCR(126, 0xe605107E),
1996 PORTCR(128, 0xe6051080),
1997 PORTCR(129, 0xe6051081),
1998 PORTCR(130, 0xe6051082),
1999 PORTCR(131, 0xe6051083),
2000 PORTCR(132, 0xe6051084),
2001 PORTCR(133, 0xe6051085),
2002 PORTCR(134, 0xe6051086),
2003 PORTCR(160, 0xe60520A0),
2004 PORTCR(161, 0xe60520A1),
2005 PORTCR(162, 0xe60520A2),
2006 PORTCR(163, 0xe60520A3),
2007 PORTCR(164, 0xe60520A4),
2008 PORTCR(165, 0xe60520A5),
2009 PORTCR(166, 0xe60520A6),
2010 PORTCR(167, 0xe60520A7),
2011 PORTCR(168, 0xe60520A8),
2012 PORTCR(169, 0xe60520A9),
2013 PORTCR(170, 0xe60520AA),
2014 PORTCR(171, 0xe60520AB),
2015 PORTCR(172, 0xe60520AC),
2016 PORTCR(173, 0xe60520AD),
2017 PORTCR(174, 0xe60520AE),
2018 PORTCR(175, 0xe60520AF),
2019 PORTCR(176, 0xe60520B0),
2020 PORTCR(177, 0xe60520B1),
2021 PORTCR(178, 0xe60520B2),
2022 PORTCR(192, 0xe60520C0),
2023 PORTCR(193, 0xe60520C1),
2024 PORTCR(194, 0xe60520C2),
2025 PORTCR(195, 0xe60520C3),
2026 PORTCR(196, 0xe60520C4),
2027 PORTCR(197, 0xe60520C5),
2028 PORTCR(198, 0xe60520C6),
2029 PORTCR(199, 0xe60520C7),
2030 PORTCR(200, 0xe60520C8),
2031 PORTCR(201, 0xe60520C9),
2032 PORTCR(202, 0xe60520CA),
2033 PORTCR(203, 0xe60520CB),
2034 PORTCR(204, 0xe60520CC),
2035 PORTCR(205, 0xe60520CD),
2036 PORTCR(206, 0xe60520CE),
2037 PORTCR(207, 0xe60520CF),
2038 PORTCR(208, 0xe60520D0),
2039 PORTCR(209, 0xe60520D1),
2040 PORTCR(210, 0xe60520D2),
2041 PORTCR(211, 0xe60520D3),
2042 PORTCR(212, 0xe60520D4),
2043 PORTCR(213, 0xe60520D5),
2044 PORTCR(214, 0xe60520D6),
2045 PORTCR(215, 0xe60520D7),
2046 PORTCR(216, 0xe60520D8),
2047 PORTCR(217, 0xe60520D9),
2048 PORTCR(218, 0xe60520DA),
2049 PORTCR(219, 0xe60520DB),
2050 PORTCR(220, 0xe60520DC),
2051 PORTCR(221, 0xe60520DD),
2052 PORTCR(222, 0xe60520DE),
2053 PORTCR(224, 0xe60520E0),
2054 PORTCR(225, 0xe60520E1),
2055 PORTCR(226, 0xe60520E2),
2056 PORTCR(227, 0xe60520E3),
2057 PORTCR(228, 0xe60520E4),
2058 PORTCR(229, 0xe60520E5),
2059 PORTCR(230, 0xe60520e6),
2060 PORTCR(231, 0xe60520E7),
2061 PORTCR(232, 0xe60520E8),
2062 PORTCR(233, 0xe60520E9),
2063 PORTCR(234, 0xe60520EA),
2064 PORTCR(235, 0xe60520EB),
2065 PORTCR(236, 0xe60520EC),
2066 PORTCR(237, 0xe60520ED),
2067 PORTCR(238, 0xe60520EE),
2068 PORTCR(239, 0xe60520EF),
2069 PORTCR(240, 0xe60520F0),
2070 PORTCR(241, 0xe60520F1),
2071 PORTCR(242, 0xe60520F2),
2072 PORTCR(243, 0xe60520F3),
2073 PORTCR(244, 0xe60520F4),
2074 PORTCR(245, 0xe60520F5),
2075 PORTCR(246, 0xe60520F6),
2076 PORTCR(247, 0xe60520F7),
2077 PORTCR(248, 0xe60520F8),
2078 PORTCR(249, 0xe60520F9),
2079 PORTCR(250, 0xe60520FA),
2080 PORTCR(256, 0xe6052100),
2081 PORTCR(257, 0xe6052101),
2082 PORTCR(258, 0xe6052102),
2083 PORTCR(259, 0xe6052103),
2084 PORTCR(260, 0xe6052104),
2085 PORTCR(261, 0xe6052105),
2086 PORTCR(262, 0xe6052106),
2087 PORTCR(263, 0xe6052107),
2088 PORTCR(264, 0xe6052108),
2089 PORTCR(265, 0xe6052109),
2090 PORTCR(266, 0xe605210A),
2091 PORTCR(267, 0xe605210B),
2092 PORTCR(268, 0xe605210C),
2093 PORTCR(269, 0xe605210D),
2094 PORTCR(270, 0xe605210E),
2095 PORTCR(271, 0xe605210F),
2096 PORTCR(272, 0xe6052110),
2097 PORTCR(273, 0xe6052111),
2098 PORTCR(274, 0xe6052112),
2099 PORTCR(275, 0xe6052113),
2100 PORTCR(276, 0xe6052114),
2101 PORTCR(277, 0xe6052115),
2102 PORTCR(278, 0xe6052116),
2103 PORTCR(279, 0xe6052117),
2104 PORTCR(280, 0xe6052118),
2105 PORTCR(281, 0xe6052119),
2106 PORTCR(282, 0xe605211A),
2107 PORTCR(283, 0xe605211B),
2108 PORTCR(288, 0xe6053120),
2109 PORTCR(289, 0xe6053121),
2110 PORTCR(290, 0xe6053122),
2111 PORTCR(291, 0xe6053123),
2112 PORTCR(292, 0xe6053124),
2113 PORTCR(293, 0xe6053125),
2114 PORTCR(294, 0xe6053126),
2115 PORTCR(295, 0xe6053127),
2116 PORTCR(296, 0xe6053128),
2117 PORTCR(297, 0xe6053129),
2118 PORTCR(298, 0xe605312A),
2119 PORTCR(299, 0xe605312B),
2120 PORTCR(300, 0xe605312C),
2121 PORTCR(301, 0xe605312D),
2122 PORTCR(302, 0xe605312E),
2123 PORTCR(303, 0xe605312F),
2124 PORTCR(304, 0xe6053130),
2125 PORTCR(305, 0xe6053131),
2126 PORTCR(306, 0xe6053132),
2127 PORTCR(307, 0xe6053133),
2128 PORTCR(308, 0xe6053134),
2129 PORTCR(320, 0xe6053140),
2130 PORTCR(321, 0xe6053141),
2131 PORTCR(322, 0xe6053142),
2132 PORTCR(323, 0xe6053143),
2133 PORTCR(324, 0xe6053144),
2134 PORTCR(325, 0xe6053145),
2135 PORTCR(326, 0xe6053146),
2136 PORTCR(327, 0xe6053147),
2137 PORTCR(328, 0xe6053148),
2138 PORTCR(329, 0xe6053149),
2139
2140 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2141 MSEL1CR_31_0, MSEL1CR_31_1,
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 MSEL1CR_27_0, MSEL1CR_27_1,
2146 0, 0,
2147 MSEL1CR_25_0, MSEL1CR_25_1,
2148 MSEL1CR_24_0, MSEL1CR_24_1,
2149 0, 0,
2150 MSEL1CR_22_0, MSEL1CR_22_1,
2151 MSEL1CR_21_0, MSEL1CR_21_1,
2152 MSEL1CR_20_0, MSEL1CR_20_1,
2153 MSEL1CR_19_0, MSEL1CR_19_1,
2154 MSEL1CR_18_0, MSEL1CR_18_1,
2155 MSEL1CR_17_0, MSEL1CR_17_1,
2156 MSEL1CR_16_0, MSEL1CR_16_1,
2157 MSEL1CR_15_0, MSEL1CR_15_1,
2158 MSEL1CR_14_0, MSEL1CR_14_1,
2159 MSEL1CR_13_0, MSEL1CR_13_1,
2160 MSEL1CR_12_0, MSEL1CR_12_1,
2161 MSEL1CR_11_0, MSEL1CR_11_1,
2162 MSEL1CR_10_0, MSEL1CR_10_1,
2163 MSEL1CR_09_0, MSEL1CR_09_1,
2164 MSEL1CR_08_0, MSEL1CR_08_1,
2165 MSEL1CR_07_0, MSEL1CR_07_1,
2166 MSEL1CR_06_0, MSEL1CR_06_1,
2167 MSEL1CR_05_0, MSEL1CR_05_1,
2168 MSEL1CR_04_0, MSEL1CR_04_1,
2169 MSEL1CR_03_0, MSEL1CR_03_1,
2170 MSEL1CR_02_0, MSEL1CR_02_1,
2171 MSEL1CR_01_0, MSEL1CR_01_1,
2172 MSEL1CR_00_0, MSEL1CR_00_1,
2173 }
2174 },
2175 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2176 MSEL3CR_31_0, MSEL3CR_31_1,
2177 0, 0,
2178 0, 0,
2179 MSEL3CR_28_0, MSEL3CR_28_1,
2180 MSEL3CR_27_0, MSEL3CR_27_1,
2181 MSEL3CR_26_0, MSEL3CR_26_1,
2182 0, 0,
2183 0, 0,
2184 MSEL3CR_23_0, MSEL3CR_23_1,
2185 MSEL3CR_22_0, MSEL3CR_22_1,
2186 MSEL3CR_21_0, MSEL3CR_21_1,
2187 MSEL3CR_20_0, MSEL3CR_20_1,
2188 MSEL3CR_19_0, MSEL3CR_19_1,
2189 MSEL3CR_18_0, MSEL3CR_18_1,
2190 MSEL3CR_17_0, MSEL3CR_17_1,
2191 MSEL3CR_16_0, MSEL3CR_16_1,
2192 MSEL3CR_15_0, MSEL3CR_15_1,
2193 0, 0,
2194 0, 0,
2195 MSEL3CR_12_0, MSEL3CR_12_1,
2196 MSEL3CR_11_0, MSEL3CR_11_1,
2197 MSEL3CR_10_0, MSEL3CR_10_1,
2198 MSEL3CR_09_0, MSEL3CR_09_1,
2199 0, 0,
2200 0, 0,
2201 MSEL3CR_06_0, MSEL3CR_06_1,
2202 0, 0,
2203 0, 0,
2204 MSEL3CR_03_0, MSEL3CR_03_1,
2205 0, 0,
2206 MSEL3CR_01_0, MSEL3CR_01_1,
2207 MSEL3CR_00_0, MSEL3CR_00_1,
2208 }
2209 },
2210 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2211 0, 0,
2212 MSEL4CR_30_0, MSEL4CR_30_1,
2213 MSEL4CR_29_0, MSEL4CR_29_1,
2214 MSEL4CR_28_0, MSEL4CR_28_1,
2215 MSEL4CR_27_0, MSEL4CR_27_1,
2216 MSEL4CR_26_0, MSEL4CR_26_1,
2217 MSEL4CR_25_0, MSEL4CR_25_1,
2218 MSEL4CR_24_0, MSEL4CR_24_1,
2219 MSEL4CR_23_0, MSEL4CR_23_1,
2220 MSEL4CR_22_0, MSEL4CR_22_1,
2221 MSEL4CR_21_0, MSEL4CR_21_1,
2222 MSEL4CR_20_0, MSEL4CR_20_1,
2223 MSEL4CR_19_0, MSEL4CR_19_1,
2224 MSEL4CR_18_0, MSEL4CR_18_1,
2225 MSEL4CR_17_0, MSEL4CR_17_1,
2226 MSEL4CR_16_0, MSEL4CR_16_1,
2227 MSEL4CR_15_0, MSEL4CR_15_1,
2228 MSEL4CR_14_0, MSEL4CR_14_1,
2229 MSEL4CR_13_0, MSEL4CR_13_1,
2230 MSEL4CR_12_0, MSEL4CR_12_1,
2231 MSEL4CR_11_0, MSEL4CR_11_1,
2232 MSEL4CR_10_0, MSEL4CR_10_1,
2233 MSEL4CR_09_0, MSEL4CR_09_1,
2234 0, 0,
2235 MSEL4CR_07_0, MSEL4CR_07_1,
2236 0, 0,
2237 0, 0,
2238 MSEL4CR_04_0, MSEL4CR_04_1,
2239 0, 0,
2240 0, 0,
2241 MSEL4CR_01_0, MSEL4CR_01_1,
2242 0, 0,
2243 }
2244 },
2245 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2246 MSEL5CR_31_0, MSEL5CR_31_1,
2247 MSEL5CR_30_0, MSEL5CR_30_1,
2248 MSEL5CR_29_0, MSEL5CR_29_1,
2249 MSEL5CR_28_0, MSEL5CR_28_1,
2250 MSEL5CR_27_0, MSEL5CR_27_1,
2251 MSEL5CR_26_0, MSEL5CR_26_1,
2252 MSEL5CR_25_0, MSEL5CR_25_1,
2253 MSEL5CR_24_0, MSEL5CR_24_1,
2254 MSEL5CR_23_0, MSEL5CR_23_1,
2255 MSEL5CR_22_0, MSEL5CR_22_1,
2256 MSEL5CR_21_0, MSEL5CR_21_1,
2257 MSEL5CR_20_0, MSEL5CR_20_1,
2258 MSEL5CR_19_0, MSEL5CR_19_1,
2259 MSEL5CR_18_0, MSEL5CR_18_1,
2260 MSEL5CR_17_0, MSEL5CR_17_1,
2261 MSEL5CR_16_0, MSEL5CR_16_1,
2262 MSEL5CR_15_0, MSEL5CR_15_1,
2263 MSEL5CR_14_0, MSEL5CR_14_1,
2264 MSEL5CR_13_0, MSEL5CR_13_1,
2265 MSEL5CR_12_0, MSEL5CR_12_1,
2266 MSEL5CR_11_0, MSEL5CR_11_1,
2267 MSEL5CR_10_0, MSEL5CR_10_1,
2268 MSEL5CR_09_0, MSEL5CR_09_1,
2269 MSEL5CR_08_0, MSEL5CR_08_1,
2270 MSEL5CR_07_0, MSEL5CR_07_1,
2271 MSEL5CR_06_0, MSEL5CR_06_1,
2272 0, 0,
2273 0, 0,
2274 0, 0,
2275 0, 0,
2276 0, 0,
2277 0, 0,
2278 }
2279 },
2280 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2281 0, 0,
2282 0, 0,
2283 0, 0,
2284 0, 0,
2285 0, 0,
2286 0, 0,
2287 0, 0,
2288 0, 0,
2289 0, 0,
2290 0, 0,
2291 0, 0,
2292 0, 0,
2293 0, 0,
2294 0, 0,
2295 0, 0,
2296 MSEL8CR_16_0, MSEL8CR_16_1,
2297 0, 0,
2298 0, 0,
2299 0, 0,
2300 0, 0,
2301 0, 0,
2302 0, 0,
2303 0, 0,
2304 0, 0,
2305 0, 0,
2306 0, 0,
2307 0, 0,
2308 0, 0,
2309 0, 0,
2310 0, 0,
2311 MSEL8CR_01_0, MSEL8CR_01_1,
2312 MSEL8CR_00_0, MSEL8CR_00_1,
2313 }
2314 },
2315 { },
2316};
2317
2318static const struct pinmux_data_reg pinmux_data_regs[] = {
2319
2320 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2321 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2322 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2323 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2324 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2325 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2326 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2327 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2328 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2329 }
2330 },
2331 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2332 0, 0, 0, 0,
2333 0, 0, 0, 0,
2334 0, 0, 0, 0,
2335 0, 0, 0, 0,
2336 0, 0, 0, 0,
2337 0, 0, 0, PORT40_DATA,
2338 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2339 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2340 }
2341 },
2342 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2343 0, 0, 0, 0,
2344 0, 0, 0, 0,
2345 0, 0, PORT85_DATA, PORT84_DATA,
2346 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2347 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2348 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2349 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2350 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2351 }
2352 },
2353 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2354 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2355 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2356 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2357 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2358 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2359 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2360 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2361 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2362 }
2363 },
2364 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2365 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 0, 0, 0, 0,
2368 0, 0, 0, 0,
2369 0, 0, 0, 0,
2370 0, 0, 0, 0,
2371 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2372 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2373 }
2374 },
2375 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2376 0, 0, 0, 0,
2377 0, 0, 0, 0,
2378 0, 0, 0, 0,
2379 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2380 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2381 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2382 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2383 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2384 }
2385 },
2386 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2387 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2388 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2389 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2390 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2391 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2392 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2393 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2394 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2395 }
2396 },
2397 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2398 0, 0, 0, 0,
2399 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2400 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2401 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2402 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2403 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2404 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2405 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2406 }
2407 },
2408 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2409 0, 0, 0, 0,
2410 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2411 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2412 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2413 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2414 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2415 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2416 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2417 }
2418 },
2419 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2420 0, 0, 0, 0,
2421 0, 0, 0, 0,
2422 0, 0, 0, PORT308_DATA,
2423 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2424 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2425 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2426 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2427 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2428 }
2429 },
2430 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2431 0, 0, 0, 0,
2432 0, 0, 0, 0,
2433 0, 0, 0, 0,
2434 0, 0, 0, 0,
2435 0, 0, 0, 0,
2436 0, 0, PORT329_DATA, PORT328_DATA,
2437 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2438 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2439 }
2440 },
2441 { },
2442};
2443
2444static const struct pinmux_irq pinmux_irqs[] = {
2445 PINMUX_IRQ(irq_pin(0), 0),
2446 PINMUX_IRQ(irq_pin(1), 1),
2447 PINMUX_IRQ(irq_pin(2), 2),
2448 PINMUX_IRQ(irq_pin(3), 3),
2449 PINMUX_IRQ(irq_pin(4), 4),
2450 PINMUX_IRQ(irq_pin(5), 5),
2451 PINMUX_IRQ(irq_pin(6), 6),
2452 PINMUX_IRQ(irq_pin(7), 7),
2453 PINMUX_IRQ(irq_pin(8), 8),
2454 PINMUX_IRQ(irq_pin(9), 9),
2455 PINMUX_IRQ(irq_pin(10), 10),
2456 PINMUX_IRQ(irq_pin(11), 11),
2457 PINMUX_IRQ(irq_pin(12), 12),
2458 PINMUX_IRQ(irq_pin(13), 13),
2459 PINMUX_IRQ(irq_pin(14), 14),
2460 PINMUX_IRQ(irq_pin(15), 15),
2461 PINMUX_IRQ(irq_pin(16), 320),
2462 PINMUX_IRQ(irq_pin(17), 321),
2463 PINMUX_IRQ(irq_pin(18), 85),
2464 PINMUX_IRQ(irq_pin(19), 84),
2465 PINMUX_IRQ(irq_pin(20), 160),
2466 PINMUX_IRQ(irq_pin(21), 161),
2467 PINMUX_IRQ(irq_pin(22), 162),
2468 PINMUX_IRQ(irq_pin(23), 163),
2469 PINMUX_IRQ(irq_pin(24), 175),
2470 PINMUX_IRQ(irq_pin(25), 176),
2471 PINMUX_IRQ(irq_pin(26), 177),
2472 PINMUX_IRQ(irq_pin(27), 178),
2473 PINMUX_IRQ(irq_pin(28), 322),
2474 PINMUX_IRQ(irq_pin(29), 323),
2475 PINMUX_IRQ(irq_pin(30), 324),
2476 PINMUX_IRQ(irq_pin(31), 192),
2477 PINMUX_IRQ(irq_pin(32), 193),
2478 PINMUX_IRQ(irq_pin(33), 194),
2479 PINMUX_IRQ(irq_pin(34), 195),
2480 PINMUX_IRQ(irq_pin(35), 196),
2481 PINMUX_IRQ(irq_pin(36), 197),
2482 PINMUX_IRQ(irq_pin(37), 198),
2483 PINMUX_IRQ(irq_pin(38), 199),
2484 PINMUX_IRQ(irq_pin(39), 200),
2485 PINMUX_IRQ(irq_pin(40), 66),
2486 PINMUX_IRQ(irq_pin(41), 102),
2487 PINMUX_IRQ(irq_pin(42), 103),
2488 PINMUX_IRQ(irq_pin(43), 109),
2489 PINMUX_IRQ(irq_pin(44), 110),
2490 PINMUX_IRQ(irq_pin(45), 111),
2491 PINMUX_IRQ(irq_pin(46), 112),
2492 PINMUX_IRQ(irq_pin(47), 113),
2493 PINMUX_IRQ(irq_pin(48), 114),
2494 PINMUX_IRQ(irq_pin(49), 115),
2495 PINMUX_IRQ(irq_pin(50), 301),
2496 PINMUX_IRQ(irq_pin(51), 290),
2497 PINMUX_IRQ(irq_pin(52), 296),
2498 PINMUX_IRQ(irq_pin(53), 325),
2499 PINMUX_IRQ(irq_pin(54), 326),
2500 PINMUX_IRQ(irq_pin(55), 327),
2501 PINMUX_IRQ(irq_pin(56), 328),
2502 PINMUX_IRQ(irq_pin(57), 329),
2503};
2504
2505#define PORTCR_PULMD_OFF (0 << 6)
2506#define PORTCR_PULMD_DOWN (2 << 6)
2507#define PORTCR_PULMD_UP (3 << 6)
2508#define PORTCR_PULMD_MASK (3 << 6)
2509
2510static const unsigned int r8a73a4_portcr_offsets[] = {
2511 0x00000000, 0x00001000, 0x00000000, 0x00001000,
2512 0x00001000, 0x00002000, 0x00002000, 0x00002000,
2513 0x00002000, 0x00003000, 0x00003000,
2514};
2515
2516static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2517 unsigned int pin)
2518{
2519 void __iomem *addr;
2520
2521 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2522
2523 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2524 case PORTCR_PULMD_UP:
2525 return PIN_CONFIG_BIAS_PULL_UP;
2526 case PORTCR_PULMD_DOWN:
2527 return PIN_CONFIG_BIAS_PULL_DOWN;
2528 case PORTCR_PULMD_OFF:
2529 default:
2530 return PIN_CONFIG_BIAS_DISABLE;
2531 }
2532}
2533
2534static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2535 unsigned int bias)
2536{
2537 void __iomem *addr;
2538 u32 value;
2539
2540 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2541 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2542
2543 switch (bias) {
2544 case PIN_CONFIG_BIAS_PULL_UP:
2545 value |= PORTCR_PULMD_UP;
2546 break;
2547 case PIN_CONFIG_BIAS_PULL_DOWN:
2548 value |= PORTCR_PULMD_DOWN;
2549 break;
2550 }
2551
2552 iowrite8(value, addr);
2553}
2554
2555static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
2556 .get_bias = r8a73a4_pinmux_get_bias,
2557 .set_bias = r8a73a4_pinmux_set_bias,
2558};
2559
2560const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2561 .name = "r8a73a4_pfc",
2562 .ops = &r8a73a4_pinmux_ops,
2563
2564 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2565 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2566 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2567
2568 .pins = pinmux_pins,
2569 .nr_pins = ARRAY_SIZE(pinmux_pins),
2570
2571 .ranges = pinmux_ranges,
2572 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
2573
2574 .groups = pinmux_groups,
2575 .nr_groups = ARRAY_SIZE(pinmux_groups),
2576 .functions = pinmux_functions,
2577 .nr_functions = ARRAY_SIZE(pinmux_functions),
2578
2579 .cfg_regs = pinmux_config_regs,
2580 .data_regs = pinmux_data_regs,
2581
2582 .gpio_data = pinmux_data,
2583 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2584
2585 .gpio_irq = pinmux_irqs,
2586 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2587};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 3621d3e81fc3..bbd87d29bfd0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2994,38 +2994,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
2994}; 2994};
2995 2995
2996static const struct pinmux_irq pinmux_irqs[] = { 2996static const struct pinmux_irq pinmux_irqs[] = {
2997 PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ 2997 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
2998 PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20), /* IRQ1A */ 2998 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */
2999 PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ 2999 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
3000 PINMUX_IRQ(evt2irq(0x0260), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ 3000 PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */
3001 PINMUX_IRQ(evt2irq(0x0280), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ 3001 PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */
3002 PINMUX_IRQ(evt2irq(0x02A0), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ 3002 PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */
3003 PINMUX_IRQ(evt2irq(0x02C0), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ 3003 PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
3004 PINMUX_IRQ(evt2irq(0x02E0), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ 3004 PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
3005 PINMUX_IRQ(evt2irq(0x0300), GPIO_PORT119), /* IRQ8A */ 3005 PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */
3006 PINMUX_IRQ(evt2irq(0x0320), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ 3006 PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
3007 PINMUX_IRQ(evt2irq(0x0340), GPIO_PORT19), /* IRQ10A */ 3007 PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */
3008 PINMUX_IRQ(evt2irq(0x0360), GPIO_PORT104), /* IRQ11A */ 3008 PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */
3009 PINMUX_IRQ(evt2irq(0x0380), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ 3009 PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */
3010 PINMUX_IRQ(evt2irq(0x03A0), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ 3010 PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */
3011 PINMUX_IRQ(evt2irq(0x03C0), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ 3011 PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */
3012 PINMUX_IRQ(evt2irq(0x03E0), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ 3012 PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */
3013 PINMUX_IRQ(evt2irq(0x3200), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ 3013 PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */
3014 PINMUX_IRQ(evt2irq(0x3220), GPIO_PORT69), /* IRQ17A */ 3014 PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */
3015 PINMUX_IRQ(evt2irq(0x3240), GPIO_PORT70), /* IRQ18A */ 3015 PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */
3016 PINMUX_IRQ(evt2irq(0x3260), GPIO_PORT71), /* IRQ19A */ 3016 PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */
3017 PINMUX_IRQ(evt2irq(0x3280), GPIO_PORT67), /* IRQ20A */ 3017 PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */
3018 PINMUX_IRQ(evt2irq(0x32A0), GPIO_PORT202), /* IRQ21A */ 3018 PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */
3019 PINMUX_IRQ(evt2irq(0x32C0), GPIO_PORT95), /* IRQ22A */ 3019 PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */
3020 PINMUX_IRQ(evt2irq(0x32E0), GPIO_PORT96), /* IRQ23A */ 3020 PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */
3021 PINMUX_IRQ(evt2irq(0x3300), GPIO_PORT180), /* IRQ24A */ 3021 PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */
3022 PINMUX_IRQ(evt2irq(0x3320), GPIO_PORT38), /* IRQ25A */ 3022 PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */
3023 PINMUX_IRQ(evt2irq(0x3340), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ 3023 PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */
3024 PINMUX_IRQ(evt2irq(0x3360), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ 3024 PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */
3025 PINMUX_IRQ(evt2irq(0x3380), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ 3025 PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */
3026 PINMUX_IRQ(evt2irq(0x33A0), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ 3026 PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */
3027 PINMUX_IRQ(evt2irq(0x33C0), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ 3027 PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */
3028 PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ 3028 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
3029}; 3029};
3030 3030
3031const struct sh_pfc_soc_info r8a7740_pinmux_info = { 3031const struct sh_pfc_soc_info r8a7740_pinmux_info = {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 1d7b0dfbbb21..62dcdcdec940 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -19,39 +19,77 @@
19 */ 19 */
20 20
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <mach/r8a7779.h>
23 22
24#include "sh_pfc.h" 23#include "sh_pfc.h"
25 24
26#define CPU_32_PORT6(fn, pfx, sfx) \ 25#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
27 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ 26
28 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ 27#define PORT_GP_32(bank, fn, sfx) \
29 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ 28 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
30 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ 29 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
31 PORT_1(fn, pfx##8, sfx) 30 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
32 31 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
33#define CPU_ALL_PORT(fn, pfx, sfx) \ 32 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
34 PORT_32(fn, pfx##_0_, sfx), \ 33 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
35 PORT_32(fn, pfx##_1_, sfx), \ 34 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
36 PORT_32(fn, pfx##_2_, sfx), \ 35 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
37 PORT_32(fn, pfx##_3_, sfx), \ 36 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
38 PORT_32(fn, pfx##_4_, sfx), \ 37 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
39 PORT_32(fn, pfx##_5_, sfx), \ 38 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
40 CPU_32_PORT6(fn, pfx##_6_, sfx) 39 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
41 40 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
42#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) 41 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
43#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ 42 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
44 GP##pfx##_IN, GP##pfx##_OUT) 43 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
45 44
46#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT 45#define PORT_GP_32_9(bank, fn, sfx) \
47#define _GP_INDT(pfx, sfx) GP##pfx##_DATA 46 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
48 47 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
49#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) 48 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
50#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) 49 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
51#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) 50 PORT_GP_1(bank, 8, fn, sfx)
52 51
53#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused) 52#define PORT_GP_32_REV(bank, fn, sfx) \
54#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused) 53 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
54 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
55 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
56 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
57 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
58 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
59 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
60 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
61 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
62 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
63 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
64 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
65 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
66 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
67 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
68 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
69
70#define CPU_ALL_PORT(fn, sfx) \
71 PORT_GP_32(0, fn, sfx), \
72 PORT_GP_32(1, fn, sfx), \
73 PORT_GP_32(2, fn, sfx), \
74 PORT_GP_32(3, fn, sfx), \
75 PORT_GP_32(4, fn, sfx), \
76 PORT_GP_32(5, fn, sfx), \
77 PORT_GP_32_9(6, fn, sfx)
78
79#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
80
81#define _GP_GPIO(bank, pin, _name, sfx) \
82 [(bank * 32) + pin] = { \
83 .name = __stringify(_name), \
84 .enum_id = _name##_DATA, \
85 }
86
87#define _GP_DATA(bank, pin, name, sfx) \
88 PINMUX_DATA(name##_DATA, name##_FN)
89
90#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
91#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
92#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
55 93
56#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) 94#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
57#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ 95#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -64,14 +102,6 @@ enum {
64 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ 102 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
65 PINMUX_DATA_END, 103 PINMUX_DATA_END,
66 104
67 PINMUX_INPUT_BEGIN,
68 GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
69 PINMUX_INPUT_END,
70
71 PINMUX_OUTPUT_BEGIN,
72 GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
73 PINMUX_OUTPUT_END,
74
75 PINMUX_FUNCTION_BEGIN, 105 PINMUX_FUNCTION_BEGIN,
76 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ 106 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
77 107
@@ -1468,19 +1498,26 @@ static const unsigned int du0_rgb888_mux[] = {
1468 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK, 1498 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1469 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK, 1499 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1470}; 1500};
1471static const unsigned int du0_clk_0_pins[] = { 1501static const unsigned int du0_clk_in_pins[] = {
1472 /* CLKIN, CLKOUT */ 1502 /* CLKIN */
1473 29, 180, 1503 29,
1474}; 1504};
1475static const unsigned int du0_clk_0_mux[] = { 1505static const unsigned int du0_clk_in_mux[] = {
1476 DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK, 1506 DU0_DOTCLKIN_MARK,
1477}; 1507};
1478static const unsigned int du0_clk_1_pins[] = { 1508static const unsigned int du0_clk_out_0_pins[] = {
1479 /* CLKIN, CLKOUT */ 1509 /* CLKOUT */
1480 29, 30, 1510 180,
1481}; 1511};
1482static const unsigned int du0_clk_1_mux[] = { 1512static const unsigned int du0_clk_out_0_mux[] = {
1483 DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK, 1513 DU0_DOTCLKOUT0_MARK,
1514};
1515static const unsigned int du0_clk_out_1_pins[] = {
1516 /* CLKOUT */
1517 30,
1518};
1519static const unsigned int du0_clk_out_1_mux[] = {
1520 DU0_DOTCLKOUT1_MARK,
1484}; 1521};
1485static const unsigned int du0_sync_0_pins[] = { 1522static const unsigned int du0_sync_0_pins[] = {
1486 /* VSYNC, HSYNC, DISP */ 1523 /* VSYNC, HSYNC, DISP */
@@ -1541,12 +1578,19 @@ static const unsigned int du1_rgb888_mux[] = {
1541 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK, 1578 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1542 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK, 1579 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1543}; 1580};
1544static const unsigned int du1_clk_pins[] = { 1581static const unsigned int du1_clk_in_pins[] = {
1545 /* CLKIN, CLKOUT */ 1582 /* CLKIN */
1546 58, 59, 1583 58,
1584};
1585static const unsigned int du1_clk_in_mux[] = {
1586 DU1_DOTCLKIN_MARK,
1587};
1588static const unsigned int du1_clk_out_pins[] = {
1589 /* CLKOUT */
1590 59,
1547}; 1591};
1548static const unsigned int du1_clk_mux[] = { 1592static const unsigned int du1_clk_out_mux[] = {
1549 DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK, 1593 DU1_DOTCLKOUT_MARK,
1550}; 1594};
1551static const unsigned int du1_sync_0_pins[] = { 1595static const unsigned int du1_sync_0_pins[] = {
1552 /* VSYNC, HSYNC, DISP */ 1596 /* VSYNC, HSYNC, DISP */
@@ -2339,15 +2383,17 @@ static const unsigned int usb2_mux[] = {
2339static const struct sh_pfc_pin_group pinmux_groups[] = { 2383static const struct sh_pfc_pin_group pinmux_groups[] = {
2340 SH_PFC_PIN_GROUP(du0_rgb666), 2384 SH_PFC_PIN_GROUP(du0_rgb666),
2341 SH_PFC_PIN_GROUP(du0_rgb888), 2385 SH_PFC_PIN_GROUP(du0_rgb888),
2342 SH_PFC_PIN_GROUP(du0_clk_0), 2386 SH_PFC_PIN_GROUP(du0_clk_in),
2343 SH_PFC_PIN_GROUP(du0_clk_1), 2387 SH_PFC_PIN_GROUP(du0_clk_out_0),
2388 SH_PFC_PIN_GROUP(du0_clk_out_1),
2344 SH_PFC_PIN_GROUP(du0_sync_0), 2389 SH_PFC_PIN_GROUP(du0_sync_0),
2345 SH_PFC_PIN_GROUP(du0_sync_1), 2390 SH_PFC_PIN_GROUP(du0_sync_1),
2346 SH_PFC_PIN_GROUP(du0_oddf), 2391 SH_PFC_PIN_GROUP(du0_oddf),
2347 SH_PFC_PIN_GROUP(du0_cde), 2392 SH_PFC_PIN_GROUP(du0_cde),
2348 SH_PFC_PIN_GROUP(du1_rgb666), 2393 SH_PFC_PIN_GROUP(du1_rgb666),
2349 SH_PFC_PIN_GROUP(du1_rgb888), 2394 SH_PFC_PIN_GROUP(du1_rgb888),
2350 SH_PFC_PIN_GROUP(du1_clk), 2395 SH_PFC_PIN_GROUP(du1_clk_in),
2396 SH_PFC_PIN_GROUP(du1_clk_out),
2351 SH_PFC_PIN_GROUP(du1_sync_0), 2397 SH_PFC_PIN_GROUP(du1_sync_0),
2352 SH_PFC_PIN_GROUP(du1_sync_1), 2398 SH_PFC_PIN_GROUP(du1_sync_1),
2353 SH_PFC_PIN_GROUP(du1_oddf), 2399 SH_PFC_PIN_GROUP(du1_oddf),
@@ -2462,8 +2508,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2462static const char * const du0_groups[] = { 2508static const char * const du0_groups[] = {
2463 "du0_rgb666", 2509 "du0_rgb666",
2464 "du0_rgb888", 2510 "du0_rgb888",
2465 "du0_clk_0", 2511 "du0_clk_in",
2466 "du0_clk_1", 2512 "du0_clk_out_0",
2513 "du0_clk_out_1",
2467 "du0_sync_0", 2514 "du0_sync_0",
2468 "du0_sync_1", 2515 "du0_sync_1",
2469 "du0_oddf", 2516 "du0_oddf",
@@ -2473,7 +2520,8 @@ static const char * const du0_groups[] = {
2473static const char * const du1_groups[] = { 2520static const char * const du1_groups[] = {
2474 "du1_rgb666", 2521 "du1_rgb666",
2475 "du1_rgb888", 2522 "du1_rgb888",
2476 "du1_clk", 2523 "du1_clk_in",
2524 "du1_clk_out",
2477 "du1_sync_0", 2525 "du1_sync_0",
2478 "du1_sync_1", 2526 "du1_sync_1",
2479 "du1_oddf", 2527 "du1_oddf",
@@ -2670,274 +2718,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
2670 SH_PFC_FUNCTION(usb2), 2718 SH_PFC_FUNCTION(usb2),
2671}; 2719};
2672 2720
2673#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
2674
2675static const struct pinmux_func pinmux_func_gpios[] = {
2676 GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
2677 GPIO_FN(A19),
2678
2679 /* IPSR0 */
2680 GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
2681 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
2682 GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
2683 GPIO_FN(HCTS1), GPIO_FN(A0),
2684 GPIO_FN(FD3), GPIO_FN(A20),
2685 GPIO_FN(A21),
2686 GPIO_FN(A22),
2687 GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
2688 GPIO_FN(VI1_R1), GPIO_FN(A24),
2689 GPIO_FN(FD4), GPIO_FN(VI1_R2),
2690 GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
2691 GPIO_FN(FD5), GPIO_FN(VI1_R3),
2692 GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
2693 GPIO_FN(PWM0_B),
2694 GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
2695 GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
2696
2697 /* IPSR1 */
2698 GPIO_FN(FD6), GPIO_FN(FD7),
2699 GPIO_FN(FALE),
2700 GPIO_FN(ATACS00),
2701 GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4),
2702 GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B),
2703 GPIO_FN(SSI_SDATA9),
2704 GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
2705 GPIO_FN(HTX1),
2706 GPIO_FN(SSI_SCK9),
2707 GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
2708 GPIO_FN(HRX1), GPIO_FN(SSI_WS9),
2709 GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG),
2710 GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
2711 GPIO_FN(HTX0), GPIO_FN(SDATA),
2712 GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
2713 GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
2714 GPIO_FN(CC5_STATE34),
2715
2716 /* IPSR2 */
2717 GPIO_FN(HRX0), GPIO_FN(SCKZ),
2718 GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
2719 GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
2720 GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5),
2721 GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
2722 GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
2723 GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
2724 GPIO_FN(STM), GPIO_FN(PWM0_D),
2725 GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
2726 GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0),
2727 GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
2728 GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
2729 GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
2730 GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
2731 GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
2732 GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1),
2733 GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
2734 GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
2735 GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
2736 GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
2737 GPIO_FN(AUDATA2),
2738
2739 /* IPSR3 */
2740 GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
2741 GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10),
2742 GPIO_FN(LCDOUT11),
2743 GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13),
2744 GPIO_FN(LCDOUT14),
2745 GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
2746 GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
2747 GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
2748 GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5),
2749 GPIO_FN(LCDOUT18),
2750 GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
2751 GPIO_FN(LCDOUT21),
2752 GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
2753 GPIO_FN(QSTVA_QVS),
2754 GPIO_FN(SCL3_B), GPIO_FN(QCLK),
2755 GPIO_FN(QSTVB_QVE),
2756 GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
2757 GPIO_FN(QSTH_QHS),
2758 GPIO_FN(QSTB_QHE),
2759 GPIO_FN(QCPV_QDE),
2760 GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
2761
2762 /* IPSR4 */
2763 GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C),
2764 GPIO_FN(QPOLB), GPIO_FN(CAN1_RX),
2765 GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B),
2766 GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
2767 GPIO_FN(AUDCK),
2768 GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
2769 GPIO_FN(PWM0),
2770 GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0),
2771 GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
2772 GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
2773 GPIO_FN(VI2_G5),
2774 GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B),
2775 GPIO_FN(AUDATA6),
2776 GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B),
2777 GPIO_FN(AUDATA7),
2778 GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
2779 GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
2780 GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
2781 GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B),
2782
2783 /* IPSR5 */
2784 GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
2785 GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
2786 GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
2787 GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
2788 GPIO_FN(VI2_CLKENB),
2789 GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
2790 GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
2791 GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
2792 GPIO_FN(VI3_VSYNC),
2793 GPIO_FN(VI2_CLK),
2794 GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
2795 GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN),
2796 GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
2797 GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B),
2798 GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
2799 GPIO_FN(VI2_DATA7_VI2_B7),
2800 GPIO_FN(VI1_FIELD),
2801 GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
2802 GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
2803 GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB),
2804 GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
2805
2806 /* IPSR6 */
2807 GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
2808 GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
2809 GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
2810 GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
2811 GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
2812 GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
2813 GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
2814 GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
2815 GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
2816 GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
2817 GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
2818 GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
2819 GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D),
2820 GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
2821 GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
2822 GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6),
2823 GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
2824
2825 /* IPSR7 */
2826 GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
2827 GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
2828 GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
2829 GPIO_FN(SSI_SCK9_B),
2830 GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14),
2831 GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7),
2832 GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C),
2833 GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
2834 GPIO_FN(ATACS01), GPIO_FN(ATACS11),
2835 GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
2836 GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
2837 GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
2838 GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
2839 GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
2840 GPIO_FN(DACK2),
2841
2842 /* IPSR8 */
2843 GPIO_FN(AD_CLK),
2844 GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
2845 GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36),
2846 GPIO_FN(AD_DI),
2847 GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
2848 GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37),
2849 GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
2850 GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
2851 GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38),
2852 GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
2853 GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
2854 GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
2855 GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
2856 GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB),
2857 GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
2858 GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B),
2859 GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B),
2860 GPIO_FN(HSCK1_B),
2861 GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
2862 GPIO_FN(PWMFSW0_C),
2863
2864 /* IPSR9 */
2865 GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
2866 GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
2867 GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3),
2868 GPIO_FN(VI0_DATA4_VI0_B4),
2869 GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6),
2870 GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
2871 GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
2872 GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2),
2873 GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C),
2874 GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
2875 GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
2876 GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV),
2877 GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
2878 GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6),
2879 GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER),
2880 GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
2881 GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
2882 GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9),
2883
2884 /* IPSR10 */
2885 GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C),
2886 GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
2887 GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
2888 GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
2889 GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK),
2890 GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
2891 GPIO_FN(ARM_TRACEDATA_13),
2892 GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
2893 GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
2894 GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
2895 GPIO_FN(ARM_TRACEDATA_15),
2896 GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
2897 GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK),
2898 GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
2899 GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C),
2900 GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
2901 GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
2902 GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
2903 GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
2904 GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
2905 GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
2906
2907 /* IPSR11 */
2908 GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST),
2909 GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
2910 GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
2911 GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2),
2912 GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
2913 GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN),
2914 GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
2915 GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
2916 GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
2917 GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
2918 GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
2919 GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
2920 GPIO_FN(VI1_DATA7_VI1_B7),
2921 GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI),
2922 GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
2923 GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO),
2924 GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
2925 GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B),
2926 GPIO_FN(HRTS0_B),
2927
2928 /* IPSR12 */
2929 GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
2930 GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
2931 GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
2932 GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
2933 GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
2934 GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
2935 GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B),
2936 GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
2937 GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
2938 GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE),
2939};
2940
2941static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2721static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2942 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 2722 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2943 GP_0_31_FN, FN_IP3_31_29, 2723 GP_0_31_FN, FN_IP3_31_29,
@@ -3773,45 +3553,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3773 /* SEL_I2C1 [2] */ 3553 /* SEL_I2C1 [2] */
3774 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 } 3554 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
3775 }, 3555 },
3776 { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
3777 { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
3778 { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
3779 { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
3780 { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
3781 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
3782 { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
3783 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3784 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3785 0, 0, 0, 0, 0, 0, 0, 0,
3786 0, 0,
3787 0, 0,
3788 0, 0,
3789 GP_6_8_IN, GP_6_8_OUT,
3790 GP_6_7_IN, GP_6_7_OUT,
3791 GP_6_6_IN, GP_6_6_OUT,
3792 GP_6_5_IN, GP_6_5_OUT,
3793 GP_6_4_IN, GP_6_4_OUT,
3794 GP_6_3_IN, GP_6_3_OUT,
3795 GP_6_2_IN, GP_6_2_OUT,
3796 GP_6_1_IN, GP_6_1_OUT,
3797 GP_6_0_IN, GP_6_0_OUT, }
3798 },
3799 { },
3800};
3801
3802static const struct pinmux_data_reg pinmux_data_regs[] = {
3803 { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
3804 { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
3805 { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
3806 { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
3807 { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
3808 { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
3809 { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
3810 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3811 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
3812 GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
3813 GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
3814 },
3815 { }, 3556 { },
3816}; 3557};
3817 3558
@@ -3820,8 +3561,6 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3820 3561
3821 .unlock_reg = 0xfffc0000, /* PMMR */ 3562 .unlock_reg = 0xfffc0000, /* PMMR */
3822 3563
3823 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3824 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
3825 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 3564 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3826 3565
3827 .pins = pinmux_pins, 3566 .pins = pinmux_pins,
@@ -3831,11 +3570,7 @@ const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3831 .functions = pinmux_functions, 3570 .functions = pinmux_functions,
3832 .nr_functions = ARRAY_SIZE(pinmux_functions), 3571 .nr_functions = ARRAY_SIZE(pinmux_functions),
3833 3572
3834 .func_gpios = pinmux_func_gpios,
3835 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3836
3837 .cfg_regs = pinmux_config_regs, 3573 .cfg_regs = pinmux_config_regs,
3838 .data_regs = pinmux_data_regs,
3839 3574
3840 .gpio_data = pinmux_data, 3575 .gpio_data = pinmux_data,
3841 .gpio_data_size = ARRAY_SIZE(pinmux_data), 3576 .gpio_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index cde4387edce1..587f7772abf2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -3849,9 +3849,9 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3849 { }, 3849 { },
3850}; 3850};
3851 3851
3852/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */ 3852/* External IRQ pins mapped at IRQPIN_BASE */
3853#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5)) 3853#define EXT_IRQ16L(n) irq_pin(n)
3854#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5)) 3854#define EXT_IRQ16H(n) irq_pin(n)
3855 3855
3856static const struct pinmux_irq pinmux_irqs[] = { 3856static const struct pinmux_irq pinmux_irqs[] = {
3857 PINMUX_IRQ(EXT_IRQ16H(19), 9), 3857 PINMUX_IRQ(EXT_IRQ16H(19), 9),
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index aef268bc17ba..3492ec9a33b7 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -182,6 +182,17 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
182 goto done; 182 goto done;
183 } 183 }
184 184
185 if (!pfc->gpio) {
186 /* If GPIOs are handled externally the pin mux type need to be
187 * set to GPIO here.
188 */
189 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
190
191 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
192 if (ret < 0)
193 goto done;
194 }
195
185 cfg->type = PINMUX_TYPE_GPIO; 196 cfg->type = PINMUX_TYPE_GPIO;
186 197
187 ret = 0; 198 ret = 0;
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
new file mode 100644
index 000000000000..b253f77a7ddf
--- /dev/null
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -0,0 +1,26 @@
1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __GPIO_RCAR_H__
17#define __GPIO_RCAR_H__
18
19struct gpio_rcar_config {
20 unsigned int gpio_base;
21 unsigned int irq_base;
22 unsigned int number_of_pins;
23 const char *pctl_name;
24};
25
26#endif /* __GPIO_RCAR_H__ */
diff --git a/include/linux/platform_data/irq-renesas-intc-irqpin.h b/include/linux/platform_data/irq-renesas-intc-irqpin.h
new file mode 100644
index 000000000000..e4cb911066a6
--- /dev/null
+++ b/include/linux/platform_data/irq-renesas-intc-irqpin.h
@@ -0,0 +1,29 @@
1/*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __IRQ_RENESAS_INTC_IRQPIN_H__
21#define __IRQ_RENESAS_INTC_IRQPIN_H__
22
23struct renesas_intc_irqpin_config {
24 unsigned int sense_bitfield_width;
25 unsigned int irq_base;
26 bool control_parent;
27};
28
29#endif /* __IRQ_RENESAS_INTC_IRQPIN_H__ */
diff --git a/include/linux/platform_data/irq-renesas-irqc.h b/include/linux/platform_data/irq-renesas-irqc.h
new file mode 100644
index 000000000000..3ae17b3e00ed
--- /dev/null
+++ b/include/linux/platform_data/irq-renesas-irqc.h
@@ -0,0 +1,27 @@
1/*
2 * Renesas IRQC Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __IRQ_RENESAS_IRQC_H__
21#define __IRQ_RENESAS_IRQC_H__
22
23struct renesas_irqc_config {
24 unsigned int irq_base;
25};
26
27#endif /* __IRQ_RENESAS_IRQC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 12:04:22 -0400