diff options
| author | Paul Walmsley <paul@pwsan.com> | 2014-11-20 03:50:32 -0500 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2014-11-20 03:50:32 -0500 |
| commit | eb039a175163ebc2df4612c4a5393143017ce473 (patch) | |
| tree | 4d8f620a8d25c84ed0322680a72660237ce28ee9 | |
| parent | e01600e3125be3caf5635d90bb182864f3b2d9b3 (diff) | |
| parent | 33acc9fff9e0c48d3e1416a077cf9532b998ced0 (diff) | |
Merge branch 'dra7xx-uart-hwmod-v3.19' into omap-b-for-v3.19
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 5684f112654b..e2a70439bf35 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c | |||
| @@ -2075,6 +2075,70 @@ static struct omap_hwmod dra7xx_uart6_hwmod = { | |||
| 2075 | }, | 2075 | }, |
| 2076 | }; | 2076 | }; |
| 2077 | 2077 | ||
| 2078 | /* uart7 */ | ||
| 2079 | static struct omap_hwmod dra7xx_uart7_hwmod = { | ||
| 2080 | .name = "uart7", | ||
| 2081 | .class = &dra7xx_uart_hwmod_class, | ||
| 2082 | .clkdm_name = "l4per2_clkdm", | ||
| 2083 | .main_clk = "uart7_gfclk_mux", | ||
| 2084 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
| 2085 | .prcm = { | ||
| 2086 | .omap4 = { | ||
| 2087 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET, | ||
| 2088 | .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET, | ||
| 2089 | .modulemode = MODULEMODE_SWCTRL, | ||
| 2090 | }, | ||
| 2091 | }, | ||
| 2092 | }; | ||
| 2093 | |||
| 2094 | /* uart8 */ | ||
| 2095 | static struct omap_hwmod dra7xx_uart8_hwmod = { | ||
| 2096 | .name = "uart8", | ||
| 2097 | .class = &dra7xx_uart_hwmod_class, | ||
| 2098 | .clkdm_name = "l4per2_clkdm", | ||
| 2099 | .main_clk = "uart8_gfclk_mux", | ||
| 2100 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
| 2101 | .prcm = { | ||
| 2102 | .omap4 = { | ||
| 2103 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET, | ||
| 2104 | .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET, | ||
| 2105 | .modulemode = MODULEMODE_SWCTRL, | ||
| 2106 | }, | ||
| 2107 | }, | ||
| 2108 | }; | ||
| 2109 | |||
| 2110 | /* uart9 */ | ||
| 2111 | static struct omap_hwmod dra7xx_uart9_hwmod = { | ||
| 2112 | .name = "uart9", | ||
| 2113 | .class = &dra7xx_uart_hwmod_class, | ||
| 2114 | .clkdm_name = "l4per2_clkdm", | ||
| 2115 | .main_clk = "uart9_gfclk_mux", | ||
| 2116 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
| 2117 | .prcm = { | ||
| 2118 | .omap4 = { | ||
| 2119 | .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET, | ||
| 2120 | .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET, | ||
| 2121 | .modulemode = MODULEMODE_SWCTRL, | ||
| 2122 | }, | ||
| 2123 | }, | ||
| 2124 | }; | ||
| 2125 | |||
| 2126 | /* uart10 */ | ||
| 2127 | static struct omap_hwmod dra7xx_uart10_hwmod = { | ||
| 2128 | .name = "uart10", | ||
| 2129 | .class = &dra7xx_uart_hwmod_class, | ||
| 2130 | .clkdm_name = "wkupaon_clkdm", | ||
| 2131 | .main_clk = "uart10_gfclk_mux", | ||
| 2132 | .flags = HWMOD_SWSUP_SIDLE_ACT, | ||
| 2133 | .prcm = { | ||
| 2134 | .omap4 = { | ||
| 2135 | .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET, | ||
| 2136 | .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET, | ||
| 2137 | .modulemode = MODULEMODE_SWCTRL, | ||
| 2138 | }, | ||
| 2139 | }, | ||
| 2140 | }; | ||
| 2141 | |||
| 2078 | /* | 2142 | /* |
| 2079 | * 'usb_otg_ss' class | 2143 | * 'usb_otg_ss' class |
| 2080 | * | 2144 | * |
| @@ -3095,6 +3159,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = { | |||
| 3095 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3159 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3096 | }; | 3160 | }; |
| 3097 | 3161 | ||
| 3162 | /* l4_per2 -> uart7 */ | ||
| 3163 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = { | ||
| 3164 | .master = &dra7xx_l4_per2_hwmod, | ||
| 3165 | .slave = &dra7xx_uart7_hwmod, | ||
| 3166 | .clk = "l3_iclk_div", | ||
| 3167 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3168 | }; | ||
| 3169 | |||
| 3170 | /* l4_per2 -> uart8 */ | ||
| 3171 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = { | ||
| 3172 | .master = &dra7xx_l4_per2_hwmod, | ||
| 3173 | .slave = &dra7xx_uart8_hwmod, | ||
| 3174 | .clk = "l3_iclk_div", | ||
| 3175 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3176 | }; | ||
| 3177 | |||
| 3178 | /* l4_per2 -> uart9 */ | ||
| 3179 | static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = { | ||
| 3180 | .master = &dra7xx_l4_per2_hwmod, | ||
| 3181 | .slave = &dra7xx_uart9_hwmod, | ||
| 3182 | .clk = "l3_iclk_div", | ||
| 3183 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3184 | }; | ||
| 3185 | |||
| 3186 | /* l4_wkup -> uart10 */ | ||
| 3187 | static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = { | ||
| 3188 | .master = &dra7xx_l4_wkup_hwmod, | ||
| 3189 | .slave = &dra7xx_uart10_hwmod, | ||
| 3190 | .clk = "wkupaon_iclk_mux", | ||
| 3191 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
| 3192 | }; | ||
| 3193 | |||
| 3098 | /* l4_per3 -> usb_otg_ss1 */ | 3194 | /* l4_per3 -> usb_otg_ss1 */ |
| 3099 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { | 3195 | static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { |
| 3100 | .master = &dra7xx_l4_per3_hwmod, | 3196 | .master = &dra7xx_l4_per3_hwmod, |
| @@ -3259,6 +3355,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { | |||
| 3259 | &dra7xx_l4_per1__uart4, | 3355 | &dra7xx_l4_per1__uart4, |
| 3260 | &dra7xx_l4_per1__uart5, | 3356 | &dra7xx_l4_per1__uart5, |
| 3261 | &dra7xx_l4_per1__uart6, | 3357 | &dra7xx_l4_per1__uart6, |
| 3358 | &dra7xx_l4_per2__uart7, | ||
| 3359 | &dra7xx_l4_per2__uart8, | ||
| 3360 | &dra7xx_l4_per2__uart9, | ||
| 3361 | &dra7xx_l4_wkup__uart10, | ||
| 3262 | &dra7xx_l4_per3__usb_otg_ss1, | 3362 | &dra7xx_l4_per3__usb_otg_ss1, |
| 3263 | &dra7xx_l4_per3__usb_otg_ss2, | 3363 | &dra7xx_l4_per3__usb_otg_ss2, |
| 3264 | &dra7xx_l4_per3__usb_otg_ss3, | 3364 | &dra7xx_l4_per3__usb_otg_ss3, |
