pinctrl: Qualcomm SPMI PMIC GPIO pin controller driver

This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm GPIO sub-function blocks found in the PMIC chips.

Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

3 files changed, 947 insertions, 0 deletions

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 81275af9638b..3cd243c26b7d 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -47,4 +47,17 @@ config PINCTRL_MSM8X74
           This is the pinctrl, pinmux, pinconf and gpiolib driver for the
           Qualcomm TLMM block found in the Qualcomm 8974 platform.
 
+config PINCTRL_QCOM_SPMI_PMIC
+       tristate "Qualcomm SPMI PMIC pin controller driver"
+       depends on GPIOLIB && OF && SPMI
+       select REGMAP_SPMI
+       select PINMUX
+       select PINCONF
+       select GENERIC_PINCONF
+       help
+         This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+         Qualcomm GPIO and MPP blocks found in the Qualcomm PMIC's chips,
+         which are using SPMI for communication with SoC. Example PMIC's
+         devices are pm8841, pm8941 and pma8084.
+
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index ba8519fcd8d3..9b49c65a1cab 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_APQ8084)	+= pinctrl-apq8084.o
 obj-$(CONFIG_PINCTRL_IPQ8064)   += pinctrl-ipq8064.o
 obj-$(CONFIG_PINCTRL_MSM8960)   += pinctrl-msm8960.o
 obj-$(CONFIG_PINCTRL_MSM8X74)   += pinctrl-msm8x74.o
+obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
new file mode 100644
index 000000000000..b863b5080890
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -0,0 +1,933 @@
+/*
+ * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+#include "../core.h"
+#include "../pinctrl-utils.h"
+
+#define PMIC_GPIO_ADDRESS_RANGE                 0x100
+
+/* type and subtype registers base address offsets */
+#define PMIC_GPIO_REG_TYPE                      0x4
+#define PMIC_GPIO_REG_SUBTYPE                   0x5
+
+/* GPIO peripheral type and subtype out_values */
+#define PMIC_GPIO_TYPE                          0x10
+#define PMIC_GPIO_SUBTYPE_GPIO_4CH              0x1
+#define PMIC_GPIO_SUBTYPE_GPIOC_4CH             0x5
+#define PMIC_GPIO_SUBTYPE_GPIO_8CH              0x9
+#define PMIC_GPIO_SUBTYPE_GPIOC_8CH             0xd
+
+#define PMIC_MPP_REG_RT_STS                     0x10
+#define PMIC_MPP_REG_RT_STS_VAL_MASK            0x1
+
+/* control register base address offsets */
+#define PMIC_GPIO_REG_MODE_CTL                  0x40
+#define PMIC_GPIO_REG_DIG_VIN_CTL               0x41
+#define PMIC_GPIO_REG_DIG_PULL_CTL              0x42
+#define PMIC_GPIO_REG_DIG_OUT_CTL               0x45
+#define PMIC_GPIO_REG_EN_CTL                    0x46
+
+/* PMIC_GPIO_REG_MODE_CTL */
+#define PMIC_GPIO_REG_MODE_VALUE_SHIFT          0x1
+#define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT       1
+#define PMIC_GPIO_REG_MODE_FUNCTION_MASK        0x7
+#define PMIC_GPIO_REG_MODE_DIR_SHIFT            4
+#define PMIC_GPIO_REG_MODE_DIR_MASK             0x7
+
+/* PMIC_GPIO_REG_DIG_VIN_CTL */
+#define PMIC_GPIO_REG_VIN_SHIFT                 0
+#define PMIC_GPIO_REG_VIN_MASK                  0x7
+
+/* PMIC_GPIO_REG_DIG_PULL_CTL */
+#define PMIC_GPIO_REG_PULL_SHIFT                0
+#define PMIC_GPIO_REG_PULL_MASK                 0x7
+
+#define PMIC_GPIO_PULL_DOWN                     4
+#define PMIC_GPIO_PULL_DISABLE                  5
+
+/* PMIC_GPIO_REG_DIG_OUT_CTL */
+#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT        0
+#define PMIC_GPIO_REG_OUT_STRENGTH_MASK         0x3
+#define PMIC_GPIO_REG_OUT_TYPE_SHIFT            4
+#define PMIC_GPIO_REG_OUT_TYPE_MASK             0x3
+
+/*
+ * Output type - indicates pin should be configured as push-pull,
+ * open drain or open source.
+ */
+#define PMIC_GPIO_OUT_BUF_CMOS                  0
+#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS       1
+#define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS       2
+
+/* PMIC_GPIO_REG_EN_CTL */
+#define PMIC_GPIO_REG_MASTER_EN_SHIFT           7
+
+#define PMIC_GPIO_PHYSICAL_OFFSET               1
+
+/* Qualcomm specific pin configurations */
+#define PMIC_GPIO_CONF_PULL_UP                  (PIN_CONFIG_END + 1)
+#define PMIC_GPIO_CONF_STRENGTH                 (PIN_CONFIG_END + 2)
+
+/**
+ * struct pmic_gpio_pad - keep current GPIO settings
+ * @base: Address base in SPMI device.
+ * @irq: IRQ number which this GPIO generate.
+ * @is_enabled: Set to false when GPIO should be put in high Z state.
+ * @out_value: Cached pin output value
+ * @have_buffer: Set to true if GPIO output could be configured in push-pull,
+ *      open-drain or open-source mode.
+ * @output_enabled: Set to true if GPIO output logic is enabled.
+ * @input_enabled: Set to true if GPIO input buffer logic is enabled.
+ * @num_sources: Number of power-sources supported by this GPIO.
+ * @power_source: Current power-source used.
+ * @buffer_type: Push-pull, open-drain or open-source.
+ * @pullup: Constant current which flow trough GPIO output buffer.
+ * @strength: No, Low, Medium, High
+ * @function: See pmic_gpio_functions[]
+ */
+struct pmic_gpio_pad {
+        u16             base;
+        int             irq;
+        bool            is_enabled;
+        bool            out_value;
+        bool            have_buffer;
+        bool            output_enabled;
+        bool            input_enabled;
+        unsigned int    num_sources;
+        unsigned int    power_source;
+        unsigned int    buffer_type;
+        unsigned int    pullup;
+        unsigned int    strength;
+        unsigned int    function;
+};
+
+struct pmic_gpio_state {
+        struct device   *dev;
+        struct regmap   *map;
+        struct pinctrl_dev *ctrl;
+        struct gpio_chip chip;
+};
+
+struct pmic_gpio_bindings {
+        const char      *property;
+        unsigned        param;
+};
+
+static struct pmic_gpio_bindings pmic_gpio_bindings[] = {
+        {"qcom,pull-up-strength",       PMIC_GPIO_CONF_PULL_UP},
+        {"qcom,drive-strength",         PMIC_GPIO_CONF_STRENGTH},
+};
+
+static const char *const pmic_gpio_groups[] = {
+        "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
+        "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
+        "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
+        "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+        "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
+};
+
+static const char *const pmic_gpio_functions[] = {
+        PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,