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authorAlexander Shiyan <shc_work@mail.ru>2013-07-31 06:56:31 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-07-31 21:08:02 -0400
commitea4c39beace859139bc184a1aebdccdc12c04a2e (patch)
tree26793ec052bafb4045e3a304c99f8ebdb72bb0ba
parent90efa75f7ab0be5677f0cca155dbf0b39eacdd03 (diff)
serial: sccnxp: Using structure for each supported IC instead of switch in probe
This patch replaces switch in probe function to constant structure for each supported IC. This makes code a bit smaller and cleaner and helps adding DT support to the driver in the future. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/tty/serial/sccnxp.c272
1 files changed, 124 insertions, 148 deletions
diff --git a/drivers/tty/serial/sccnxp.c b/drivers/tty/serial/sccnxp.c
index 81e70477e6fd..49e9bbfe6cab 100644
--- a/drivers/tty/serial/sccnxp.c
+++ b/drivers/tty/serial/sccnxp.c
@@ -95,16 +95,17 @@
95#define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0) 95#define MCTRL_IBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_IP0)
96#define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0) 96#define MCTRL_OBIT(cfg, sig) ((((cfg) >> (sig)) & 0xf) - LINE_OP0)
97 97
98/* Supported chip types */ 98#define SCCNXP_HAVE_IO 0x00000001
99enum { 99#define SCCNXP_HAVE_MR0 0x00000002
100 SCCNXP_TYPE_SC2681 = 2681, 100
101 SCCNXP_TYPE_SC2691 = 2691, 101struct sccnxp_chip {
102 SCCNXP_TYPE_SC2692 = 2692, 102 const char *name;
103 SCCNXP_TYPE_SC2891 = 2891, 103 unsigned int nr;
104 SCCNXP_TYPE_SC2892 = 2892, 104 unsigned long freq_min;
105 SCCNXP_TYPE_SC28202 = 28202, 105 unsigned long freq_std;
106 SCCNXP_TYPE_SC68681 = 68681, 106 unsigned long freq_max;
107 SCCNXP_TYPE_SC68692 = 68692, 107 unsigned int flags;
108 unsigned int fifosize;
108}; 109};
109 110
110struct sccnxp_port { 111struct sccnxp_port {
@@ -112,16 +113,10 @@ struct sccnxp_port {
112 struct uart_port port[SCCNXP_MAX_UARTS]; 113 struct uart_port port[SCCNXP_MAX_UARTS];
113 bool opened[SCCNXP_MAX_UARTS]; 114 bool opened[SCCNXP_MAX_UARTS];
114 115
115 const char *name;
116 int irq; 116 int irq;
117
118 u8 imr; 117 u8 imr;
119 u8 addr_mask;
120 int freq_std;
121 118
122 int flags; 119 struct sccnxp_chip *chip;
123#define SCCNXP_HAVE_IO 0x00000001
124#define SCCNXP_HAVE_MR0 0x00000002
125 120
126#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 121#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
127 struct console console; 122 struct console console;
@@ -137,29 +132,94 @@ struct sccnxp_port {
137 struct regulator *regulator; 132 struct regulator *regulator;
138}; 133};
139 134
140static inline u8 sccnxp_raw_read(void __iomem *base, u8 reg, u8 shift) 135static const struct sccnxp_chip sc2681 = {
141{ 136 .name = "SC2681",
142 return readb(base + (reg << shift)); 137 .nr = 2,
143} 138 .freq_min = 1000000,
139 .freq_std = 3686400,
140 .freq_max = 4000000,
141 .flags = SCCNXP_HAVE_IO,
142 .fifosize = 3,
143};
144 144
145static inline void sccnxp_raw_write(void __iomem *base, u8 reg, u8 shift, u8 v) 145static const struct sccnxp_chip sc2691 = {
146{ 146 .name = "SC2691",
147 writeb(v, base + (reg << shift)); 147 .nr = 1,
148} 148 .freq_min = 1000000,
149 .freq_std = 3686400,
150 .freq_max = 4000000,
151 .flags = 0,
152 .fifosize = 3,
153};
154
155static const struct sccnxp_chip sc2692 = {
156 .name = "SC2692",
157 .nr = 2,
158 .freq_min = 1000000,
159 .freq_std = 3686400,
160 .freq_max = 4000000,
161 .flags = SCCNXP_HAVE_IO,
162 .fifosize = 3,
163};
164
165static const struct sccnxp_chip sc2891 = {
166 .name = "SC2891",
167 .nr = 1,
168 .freq_min = 100000,
169 .freq_std = 3686400,
170 .freq_max = 8000000,
171 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
172 .fifosize = 16,
173};
174
175static const struct sccnxp_chip sc2892 = {
176 .name = "SC2892",
177 .nr = 2,
178 .freq_min = 100000,
179 .freq_std = 3686400,
180 .freq_max = 8000000,
181 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
182 .fifosize = 16,
183};
184
185static const struct sccnxp_chip sc28202 = {
186 .name = "SC28202",
187 .nr = 2,
188 .freq_min = 1000000,
189 .freq_std = 14745600,
190 .freq_max = 50000000,
191 .flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
192 .fifosize = 256,
193};
194
195static const struct sccnxp_chip sc68681 = {
196 .name = "SC68681",
197 .nr = 2,
198 .freq_min = 1000000,
199 .freq_std = 3686400,
200 .freq_max = 4000000,
201 .flags = SCCNXP_HAVE_IO,
202 .fifosize = 3,
203};
204
205static const struct sccnxp_chip sc68692 = {
206 .name = "SC68692",
207 .nr = 2,
208 .freq_min = 1000000,
209 .freq_std = 3686400,
210 .freq_max = 4000000,
211 .flags = SCCNXP_HAVE_IO,
212 .fifosize = 3,
213};
149 214
150static inline u8 sccnxp_read(struct uart_port *port, u8 reg) 215static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
151{ 216{
152 struct sccnxp_port *s = dev_get_drvdata(port->dev); 217 return readb(port->membase + (reg << port->regshift));
153
154 return sccnxp_raw_read(port->membase, reg & s->addr_mask,
155 port->regshift);
156} 218}
157 219
158static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v) 220static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
159{ 221{
160 struct sccnxp_port *s = dev_get_drvdata(port->dev); 222 writeb(v, port->membase + (reg << port->regshift));
161
162 sccnxp_raw_write(port->membase, reg & s->addr_mask, port->regshift, v);
163} 223}
164 224
165static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg) 225static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
@@ -225,13 +285,14 @@ static int sccnxp_set_baud(struct uart_port *port, int baud)
225{ 285{
226 struct sccnxp_port *s = dev_get_drvdata(port->dev); 286 struct sccnxp_port *s = dev_get_drvdata(port->dev);
227 int div_std, tmp_baud, bestbaud = baud, besterr = -1; 287 int div_std, tmp_baud, bestbaud = baud, besterr = -1;
288 struct sccnxp_chip *chip = s->chip;
228 u8 i, acr = 0, csr = 0, mr0 = 0; 289 u8 i, acr = 0, csr = 0, mr0 = 0;
229 290
230 /* Find best baud from table */ 291 /* Find best baud from table */
231 for (i = 0; baud_std[i].baud && besterr; i++) { 292 for (i = 0; baud_std[i].baud && besterr; i++) {
232 if (baud_std[i].mr0 && !(s->flags & SCCNXP_HAVE_MR0)) 293 if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
233 continue; 294 continue;
234 div_std = DIV_ROUND_CLOSEST(s->freq_std, baud_std[i].baud); 295 div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
235 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std); 296 tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
236 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) { 297 if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
237 acr = baud_std[i].acr; 298 acr = baud_std[i].acr;
@@ -241,7 +302,7 @@ static int sccnxp_set_baud(struct uart_port *port, int baud)
241 } 302 }
242 } 303 }
243 304
244 if (s->flags & SCCNXP_HAVE_MR0) { 305 if (chip->flags & SCCNXP_HAVE_MR0) {
245 /* Enable FIFO, set half level for TX */ 306 /* Enable FIFO, set half level for TX */
246 mr0 |= MR0_FIFO | MR0_TXLVL; 307 mr0 |= MR0_FIFO | MR0_TXLVL;
247 /* Update MR0 */ 308 /* Update MR0 */
@@ -364,7 +425,7 @@ static void sccnxp_handle_tx(struct uart_port *port)
364 sccnxp_disable_irq(port, IMR_TXRDY); 425 sccnxp_disable_irq(port, IMR_TXRDY);
365 426
366 /* Set direction to input */ 427 /* Set direction to input */
367 if (s->flags & SCCNXP_HAVE_IO) 428 if (s->chip->flags & SCCNXP_HAVE_IO)
368 sccnxp_set_bit(port, DIR_OP, 0); 429 sccnxp_set_bit(port, DIR_OP, 0);
369 } 430 }
370 return; 431 return;
@@ -438,7 +499,7 @@ static void sccnxp_start_tx(struct uart_port *port)
438 spin_lock_irqsave(&s->lock, flags); 499 spin_lock_irqsave(&s->lock, flags);
439 500
440 /* Set direction to output */ 501 /* Set direction to output */
441 if (s->flags & SCCNXP_HAVE_IO) 502 if (s->chip->flags & SCCNXP_HAVE_IO)
442 sccnxp_set_bit(port, DIR_OP, 1); 503 sccnxp_set_bit(port, DIR_OP, 1);
443 504
444 sccnxp_enable_irq(port, IMR_TXRDY); 505 sccnxp_enable_irq(port, IMR_TXRDY);
@@ -484,7 +545,7 @@ static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
484 struct sccnxp_port *s = dev_get_drvdata(port->dev); 545 struct sccnxp_port *s = dev_get_drvdata(port->dev);
485 unsigned long flags; 546 unsigned long flags;
486 547
487 if (!(s->flags & SCCNXP_HAVE_IO)) 548 if (!(s->chip->flags & SCCNXP_HAVE_IO))
488 return; 549 return;
489 550
490 spin_lock_irqsave(&s->lock, flags); 551 spin_lock_irqsave(&s->lock, flags);
@@ -502,7 +563,7 @@ static unsigned int sccnxp_get_mctrl(struct uart_port *port)
502 struct sccnxp_port *s = dev_get_drvdata(port->dev); 563 struct sccnxp_port *s = dev_get_drvdata(port->dev);
503 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR; 564 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
504 565
505 if (!(s->flags & SCCNXP_HAVE_IO)) 566 if (!(s->chip->flags & SCCNXP_HAVE_IO))
506 return mctrl; 567 return mctrl;
507 568
508 spin_lock_irqsave(&s->lock, flags); 569 spin_lock_irqsave(&s->lock, flags);
@@ -618,7 +679,7 @@ static void sccnxp_set_termios(struct uart_port *port,
618 679
619 /* Setup baudrate */ 680 /* Setup baudrate */
620 baud = uart_get_baud_rate(port, termios, old, 50, 681 baud = uart_get_baud_rate(port, termios, old, 50,
621 (s->flags & SCCNXP_HAVE_MR0) ? 682 (s->chip->flags & SCCNXP_HAVE_MR0) ?
622 230400 : 38400); 683 230400 : 38400);
623 baud = sccnxp_set_baud(port, baud); 684 baud = sccnxp_set_baud(port, baud);
624 685
@@ -642,7 +703,7 @@ static int sccnxp_startup(struct uart_port *port)
642 703
643 spin_lock_irqsave(&s->lock, flags); 704 spin_lock_irqsave(&s->lock, flags);
644 705
645 if (s->flags & SCCNXP_HAVE_IO) { 706 if (s->chip->flags & SCCNXP_HAVE_IO) {
646 /* Outputs are controlled manually */ 707 /* Outputs are controlled manually */
647 sccnxp_write(port, SCCNXP_OPCR_REG, 0); 708 sccnxp_write(port, SCCNXP_OPCR_REG, 0);
648 } 709 }
@@ -682,7 +743,7 @@ static void sccnxp_shutdown(struct uart_port *port)
682 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE); 743 sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
683 744
684 /* Leave direction to input */ 745 /* Leave direction to input */
685 if (s->flags & SCCNXP_HAVE_IO) 746 if (s->chip->flags & SCCNXP_HAVE_IO)
686 sccnxp_set_bit(port, DIR_OP, 0); 747 sccnxp_set_bit(port, DIR_OP, 0);
687 748
688 spin_unlock_irqrestore(&s->lock, flags); 749 spin_unlock_irqrestore(&s->lock, flags);
@@ -692,7 +753,7 @@ static const char *sccnxp_type(struct uart_port *port)
692{ 753{
693 struct sccnxp_port *s = dev_get_drvdata(port->dev); 754 struct sccnxp_port *s = dev_get_drvdata(port->dev);
694 755
695 return (port->type == PORT_SC26XX) ? s->name : NULL; 756 return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
696} 757}
697 758
698static void sccnxp_release_port(struct uart_port *port) 759static void sccnxp_release_port(struct uart_port *port)
@@ -779,12 +840,24 @@ static int sccnxp_console_setup(struct console *co, char *options)
779} 840}
780#endif 841#endif
781 842
843static const struct platform_device_id sccnxp_id_table[] = {
844 { .name = "sc2681", .driver_data = (kernel_ulong_t)&sc2681, },
845 { .name = "sc2691", .driver_data = (kernel_ulong_t)&sc2691, },
846 { .name = "sc2692", .driver_data = (kernel_ulong_t)&sc2692, },
847 { .name = "sc2891", .driver_data = (kernel_ulong_t)&sc2891, },
848 { .name = "sc2892", .driver_data = (kernel_ulong_t)&sc2892, },
849 { .name = "sc28202", .driver_data = (kernel_ulong_t)&sc28202, },
850 { .name = "sc68681", .driver_data = (kernel_ulong_t)&sc68681, },
851 { .name = "sc68692", .driver_data = (kernel_ulong_t)&sc68692, },
852 { }
853};
854MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
855
782static int sccnxp_probe(struct platform_device *pdev) 856static int sccnxp_probe(struct platform_device *pdev)
783{ 857{
784 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 858 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
785 int chiptype = pdev->id_entry->driver_data;
786 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev); 859 struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
787 int i, ret, fifosize, freq_min, freq_max, uartclk; 860 int i, ret, uartclk;
788 struct sccnxp_port *s; 861 struct sccnxp_port *s;
789 void __iomem *membase; 862 void __iomem *membase;
790 struct clk *clk; 863 struct clk *clk;
@@ -802,92 +875,7 @@ static int sccnxp_probe(struct platform_device *pdev)
802 875
803 spin_lock_init(&s->lock); 876 spin_lock_init(&s->lock);
804 877
805 /* Individual chip settings */ 878 s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
806 switch (chiptype) {
807 case SCCNXP_TYPE_SC2681:
808 s->name = "SC2681";
809 s->uart.nr = 2;
810 s->freq_std = 3686400;
811 s->addr_mask = 0x0f;
812 s->flags = SCCNXP_HAVE_IO;
813 fifosize = 3;
814 freq_min = 1000000;
815 freq_max = 4000000;
816 break;
817 case SCCNXP_TYPE_SC2691:
818 s->name = "SC2691";
819 s->uart.nr = 1;
820 s->freq_std = 3686400;
821 s->addr_mask = 0x07;
822 s->flags = 0;
823 fifosize = 3;
824 freq_min = 1000000;
825 freq_max = 4000000;
826 break;
827 case SCCNXP_TYPE_SC2692:
828 s->name = "SC2692";
829 s->uart.nr = 2;
830 s->freq_std = 3686400;
831 s->addr_mask = 0x0f;
832 s->flags = SCCNXP_HAVE_IO;
833 fifosize = 3;
834 freq_min = 1000000;
835 freq_max = 4000000;
836 break;
837 case SCCNXP_TYPE_SC2891:
838 s->name = "SC2891";
839 s->uart.nr = 1;
840 s->freq_std = 3686400;
841 s->addr_mask = 0x0f;
842 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
843 fifosize = 16;
844 freq_min = 100000;
845 freq_max = 8000000;
846 break;
847 case SCCNXP_TYPE_SC2892:
848 s->name = "SC2892";
849 s->uart.nr = 2;
850 s->freq_std = 3686400;
851 s->addr_mask = 0x0f;
852 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
853 fifosize = 16;
854 freq_min = 100000;
855 freq_max = 8000000;
856 break;
857 case SCCNXP_TYPE_SC28202:
858 s->name = "SC28202";
859 s->uart.nr = 2;
860 s->freq_std = 14745600;
861 s->addr_mask = 0x7f;
862 s->flags = SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0;
863 fifosize = 256;
864 freq_min = 1000000;
865 freq_max = 50000000;
866 break;
867 case SCCNXP_TYPE_SC68681:
868 s->name = "SC68681";
869 s->uart.nr = 2;
870 s->freq_std = 3686400;
871 s->addr_mask = 0x0f;
872 s->flags = SCCNXP_HAVE_IO;
873 fifosize = 3;
874 freq_min = 1000000;
875 freq_max = 4000000;
876 break;
877 case SCCNXP_TYPE_SC68692:
878 s->name = "SC68692";
879 s->uart.nr = 2;
880 s->freq_std = 3686400;
881 s->addr_mask = 0x0f;
882 s->flags = SCCNXP_HAVE_IO;
883 fifosize = 3;
884 freq_min = 1000000;
885 freq_max = 4000000;
886 break;
887 default:
888 dev_err(&pdev->dev, "Unsupported chip type %i\n", chiptype);
889 return -ENOTSUPP;
890 }
891 879
892 s->regulator = devm_regulator_get(&pdev->dev, "vcc"); 880 s->regulator = devm_regulator_get(&pdev->dev, "vcc");
893 if (!IS_ERR(s->regulator)) { 881 if (!IS_ERR(s->regulator)) {
@@ -907,12 +895,12 @@ static int sccnxp_probe(struct platform_device *pdev)
907 goto err_out; 895 goto err_out;
908 } 896 }
909 dev_notice(&pdev->dev, "Using default clock frequency\n"); 897 dev_notice(&pdev->dev, "Using default clock frequency\n");
910 uartclk = s->freq_std; 898 uartclk = s->chip->freq_std;
911 } else 899 } else
912 uartclk = clk_get_rate(clk); 900 uartclk = clk_get_rate(clk);
913 901
914 /* Check input frequency */ 902 /* Check input frequency */
915 if ((uartclk < freq_min) || (uartclk > freq_max)) { 903 if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
916 dev_err(&pdev->dev, "Frequency out of bounds\n"); 904 dev_err(&pdev->dev, "Frequency out of bounds\n");
917 ret = -EINVAL; 905 ret = -EINVAL;
918 goto err_out; 906 goto err_out;
@@ -940,6 +928,7 @@ static int sccnxp_probe(struct platform_device *pdev)
940 s->uart.dev_name = "ttySC"; 928 s->uart.dev_name = "ttySC";
941 s->uart.major = SCCNXP_MAJOR; 929 s->uart.major = SCCNXP_MAJOR;
942 s->uart.minor = SCCNXP_MINOR; 930 s->uart.minor = SCCNXP_MINOR;
931 s->uart.nr = s->chip->nr;
943#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE 932#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
944 s->uart.cons = &s->console; 933 s->uart.cons = &s->console;
945 s->uart.cons->device = uart_console_device; 934 s->uart.cons->device = uart_console_device;
@@ -961,7 +950,7 @@ static int sccnxp_probe(struct platform_device *pdev)
961 s->port[i].dev = &pdev->dev; 950 s->port[i].dev = &pdev->dev;
962 s->port[i].irq = s->irq; 951 s->port[i].irq = s->irq;
963 s->port[i].type = PORT_SC26XX; 952 s->port[i].type = PORT_SC26XX;
964 s->port[i].fifosize = fifosize; 953 s->port[i].fifosize = s->chip->fifosize;
965 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE; 954 s->port[i].flags = UPF_SKIP_TEST | UPF_FIXED_TYPE;
966 s->port[i].iotype = UPIO_MEM; 955 s->port[i].iotype = UPIO_MEM;
967 s->port[i].mapbase = res->start; 956 s->port[i].mapbase = res->start;
@@ -971,7 +960,7 @@ static int sccnxp_probe(struct platform_device *pdev)
971 s->port[i].ops = &sccnxp_ops; 960 s->port[i].ops = &sccnxp_ops;
972 uart_add_one_port(&s->uart, &s->port[i]); 961 uart_add_one_port(&s->uart, &s->port[i]);
973 /* Set direction to input */ 962 /* Set direction to input */
974 if (s->flags & SCCNXP_HAVE_IO) 963 if (s->chip->flags & SCCNXP_HAVE_IO)
975 sccnxp_set_bit(&s->port[i], DIR_OP, 0); 964 sccnxp_set_bit(&s->port[i], DIR_OP, 0);
976 } 965 }
977 966
@@ -1025,19 +1014,6 @@ static int sccnxp_remove(struct platform_device *pdev)
1025 return 0; 1014 return 0;
1026} 1015}
1027 1016
1028static const struct platform_device_id sccnxp_id_table[] = {
1029 { "sc2681", SCCNXP_TYPE_SC2681 },
1030 { "sc2691", SCCNXP_TYPE_SC2691 },
1031 { "sc2692", SCCNXP_TYPE_SC2692 },
1032 { "sc2891", SCCNXP_TYPE_SC2891 },
1033 { "sc2892", SCCNXP_TYPE_SC2892 },
1034 { "sc28202", SCCNXP_TYPE_SC28202 },
1035 { "sc68681", SCCNXP_TYPE_SC68681 },
1036 { "sc68692", SCCNXP_TYPE_SC68692 },
1037 { },
1038};
1039MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
1040
1041static struct platform_driver sccnxp_uart_driver = { 1017static struct platform_driver sccnxp_uart_driver = {
1042 .driver = { 1018 .driver = {
1043 .name = SCCNXP_NAME, 1019 .name = SCCNXP_NAME,