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authorPhilippe De Muyter <phdm@macqel.be>2010-09-20 07:11:11 -0400
committerGreg Ungerer <gerg@uclinux.org>2010-10-20 20:17:30 -0400
commitea49f8ffae6262e8de9a0d3e9fcdd384156c7e05 (patch)
tree546e2ec64f98b5c39a14b61c9861edcbc70e6e35
parenta7c681f620e75cb0efbe7da092723a6ecd17bc01 (diff)
m68knommu: add basic mmu-less m548x support
Add a very basic mmu-less support for coldfire m548x family. This is perhaps also valid for m547x family. The port comprises the serial, tick timer and reboot support. The gpio part compiles but is empty. This gives a functional albeit limited linux for the m548x coldfire family. This has been tested on a Freescale M548xEVB Lite board with a M5484 processor and the default dbug monitor. Signed-off-by: Philippe De Muyter <phdm@macqel.be> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat
-rw-r--r--arch/m68k/include/asm/cacheflush_no.h2
-rw-r--r--arch/m68k/include/asm/coldfire.h4
-rw-r--r--arch/m68k/include/asm/gpio.h7
-rw-r--r--arch/m68k/include/asm/m548xgpt.h88
-rw-r--r--arch/m68k/include/asm/m548xsim.h55
-rw-r--r--arch/m68k/include/asm/mcfcache.h2
-rw-r--r--arch/m68k/include/asm/mcfsim.h2
-rw-r--r--arch/m68k/include/asm/mcfslt.h44
-rw-r--r--arch/m68k/include/asm/mcfuart.h5
-rw-r--r--arch/m68knommu/Kconfig7
-rw-r--r--arch/m68knommu/Makefile3
-rw-r--r--arch/m68knommu/platform/548x/Makefile18
-rw-r--r--arch/m68knommu/platform/548x/config.c115
-rw-r--r--arch/m68knommu/platform/coldfire/Makefile1
-rw-r--r--arch/m68knommu/platform/coldfire/sltimers.c145
15 files changed, 493 insertions, 5 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 89f195656be7..7085bd51668b 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -29,7 +29,7 @@
29 29
30static inline void __flush_cache_all(void) 30static inline void __flush_cache_all(void)
31{ 31{
32#ifdef CONFIG_M5407 32#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
33 /* 33 /*
34 * Use cpushl to push and invalidate all cache lines. 34 * Use cpushl to push and invalidate all cache lines.
35 * Gas doesn't seem to know how to generate the ColdFire 35 * Gas doesn't seem to know how to generate the ColdFire
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 83a9fa4e618a..3b0a34d0fe33 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -32,7 +32,9 @@
32 */ 32 */
33#define MCF_MBAR 0x10000000 33#define MCF_MBAR 0x10000000
34#define MCF_MBAR2 0x80000000 34#define MCF_MBAR2 0x80000000
35#if defined(CONFIG_M520x) 35#if defined(CONFIG_M548x)
36#define MCF_IPSBAR MCF_MBAR
37#elif defined(CONFIG_M520x)
36#define MCF_IPSBAR 0xFC000000 38#define MCF_IPSBAR 0xFC000000
37#else 39#else
38#define MCF_IPSBAR 0x40000000 40#define MCF_IPSBAR 0x40000000
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 283214dc65a7..1b57adbafad5 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -36,7 +36,8 @@
36 */ 36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) 39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M548x)
40 41
41/* These parts have GPIO organized by 8 bit ports */ 42/* These parts have GPIO organized by 8 bit ports */
42 43
@@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio)
136#endif 137#endif
137 else 138 else
138 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 139 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
140#else
141 return 0;
139#endif 142#endif
140} 143}
141 144
@@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
173#endif 176#endif
174 else 177 else
175 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 178 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
179#else
180 return 0;
176#endif 181#endif
177} 182}
178 183
diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h
new file mode 100644
index 000000000000..c8ef158a1c4e
--- /dev/null
+++ b/arch/m68k/include/asm/m548xgpt.h
@@ -0,0 +1,88 @@
1/*
2 * File: m548xgpt.h
3 * Purpose: Register and bit definitions for the MCF548X
4 *
5 * Notes:
6 *
7 */
8
9#ifndef m548xgpt_h
10#define m548xgpt_h
11
12/*********************************************************************
13*
14* General Purpose Timers (GPT)
15*
16*********************************************************************/
17
18/* Register read/write macros */
19#define MCF_GPT_GMS0 0x000800
20#define MCF_GPT_GCIR0 0x000804
21#define MCF_GPT_GPWM0 0x000808
22#define MCF_GPT_GSR0 0x00080C
23#define MCF_GPT_GMS1 0x000810
24#define MCF_GPT_GCIR1 0x000814
25#define MCF_GPT_GPWM1 0x000818
26#define MCF_GPT_GSR1 0x00081C
27#define MCF_GPT_GMS2 0x000820
28#define MCF_GPT_GCIR2 0x000824
29#define MCF_GPT_GPWM2 0x000828
30#define MCF_GPT_GSR2 0x00082C
31#define MCF_GPT_GMS3 0x000830
32#define MCF_GPT_GCIR3 0x000834
33#define MCF_GPT_GPWM3 0x000838
34#define MCF_GPT_GSR3 0x00083C
35#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
36#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
37#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
38#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
39
40/* Bit definitions and macros for MCF_GPT_GMS */
41#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
42#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
43#define MCF_GPT_GMS_IEN (0x00000100)
44#define MCF_GPT_GMS_OD (0x00000200)
45#define MCF_GPT_GMS_SC (0x00000400)
46#define MCF_GPT_GMS_CE (0x00001000)
47#define MCF_GPT_GMS_WDEN (0x00008000)
48#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
49#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
50#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
51#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
52#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
53#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
54#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
55#define MCF_GPT_GMS_ICT_ANY (0x00000000)
56#define MCF_GPT_GMS_ICT_RISE (0x00010000)
57#define MCF_GPT_GMS_ICT_FALL (0x00020000)
58#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
59#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
60#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
61#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
62#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
63#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
64#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
65#define MCF_GPT_GMS_TMS_PWM (0x00000003)
66#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
67
68/* Bit definitions and macros for MCF_GPT_GCIR */
69#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
70#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
71
72/* Bit definitions and macros for MCF_GPT_GPWM */
73#define MCF_GPT_GPWM_LOAD (0x00000001)
74#define MCF_GPT_GPWM_PWMOP (0x00000100)
75#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
76
77/* Bit definitions and macros for MCF_GPT_GSR */
78#define MCF_GPT_GSR_CAPT (0x00000001)
79#define MCF_GPT_GSR_COMP (0x00000002)
80#define MCF_GPT_GSR_PWMP (0x00000004)
81#define MCF_GPT_GSR_TEXP (0x00000008)
82#define MCF_GPT_GSR_PIN (0x00000100)
83#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
84#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
85
86/********************************************************************/
87
88#endif /* m548xgpt_h */
diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m548xsim.h
new file mode 100644
index 000000000000..149135ef30d2
--- /dev/null
+++ b/arch/m68k/include/asm/m548xsim.h
@@ -0,0 +1,55 @@
1/*
2 * m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
3 */
4
5#ifndef m548xsim_h
6#define m548xsim_h
7
8#define MCFINT_VECBASE 64
9
10/*
11 * Interrupt Controller Registers
12 */
13#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
14#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
15#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
16#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
17#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
18#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
19#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
20#define MCFINTC_IRLR 0x18 /* */
21#define MCFINTC_IACKL 0x19 /* */
22#define MCFINTC_ICR0 0x40 /* Base ICR register */
23
24/*
25 * Define system peripheral IRQ usage.
26 */
27#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
28#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
29
30/*
31 * Generic GPIO support
32 */
33#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
34#define MCFGPIO_IRQ_MAX -1
35#define MCFGPIO_IRQ_VECBASE -1
36
37/*
38 * Some PSC related definitions
39 */
40#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
41#define MCF_PAR_SDA (0x0008)
42#define MCF_PAR_SCL (0x0004)
43#define MCF_PAR_PSC_TXD (0x04)
44#define MCF_PAR_PSC_RXD (0x08)
45#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
46#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
47#define MCF_PAR_PSC_CTS_GPIO (0x00)
48#define MCF_PAR_PSC_CTS_BCLK (0x80)
49#define MCF_PAR_PSC_CTS_CTS (0xC0)
50#define MCF_PAR_PSC_RTS_GPIO (0x00)
51#define MCF_PAR_PSC_RTS_FSYNC (0x20)
52#define MCF_PAR_PSC_RTS_RTS (0x30)
53#define MCF_PAR_PSC_CANRX (0x40)
54
55#endif /* m548xsim_h */
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
index c042634fadaa..f49dfc09f70a 100644
--- a/arch/m68k/include/asm/mcfcache.h
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -107,7 +107,7 @@
107.endm 107.endm
108#endif /* CONFIG_M532x */ 108#endif /* CONFIG_M532x */
109 109
110#if defined(CONFIG_M5407) 110#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
111/* 111/*
112 * Version 4 cores have a true harvard style separate instruction 112 * Version 4 cores have a true harvard style separate instruction
113 * and data cache. Invalidate and enable cache, also enable write 113 * and data cache. Invalidate and enable cache, also enable write
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index 9c70a67bf85f..6901fd68165b 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -41,6 +41,8 @@
41#elif defined(CONFIG_M5407) 41#elif defined(CONFIG_M5407)
42#include <asm/m5407sim.h> 42#include <asm/m5407sim.h>
43#include <asm/mcfintc.h> 43#include <asm/mcfintc.h>
44#elif defined(CONFIG_M548x)
45#include <asm/m548xsim.h>
44#endif 46#endif
45 47
46/****************************************************************************/ 48/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
new file mode 100644
index 000000000000..d0d0ecba5333
--- /dev/null
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -0,0 +1,44 @@
1/****************************************************************************/
2
3/*
4 * mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
8 */
9
10/****************************************************************************/
11#ifndef mcfslt_h
12#define mcfslt_h
13/****************************************************************************/
14
15/*
16 * Get address specific defines for the 547x.
17 */
18#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
19#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
20
21
22/*
23 * Define the SLT timer register set addresses.
24 */
25#define MCFSLT_STCNT 0x00 /* Terminal count */
26#define MCFSLT_SCR 0x04 /* Control */
27#define MCFSLT_SCNT 0x08 /* Current count */
28#define MCFSLT_SSR 0x0C /* Status */
29
30/*
31 * Bit definitions for the SCR control register.
32 */
33#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
34#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
35#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
36
37/*
38 * Bit definitions for the SSR status register.
39 */
40#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
41#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
42
43/****************************************************************************/
44#endif /* mcfslt_h */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 01a8716c5fc5..af16f3be4e19 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -47,6 +47,11 @@
47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ 47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ 48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ 49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
50#elif defined(CONFIG_M548x)
51#define MCFUART_BASE1 0x8600 /* on M548x */
52#define MCFUART_BASE2 0x8700 /* on M548x */
53#define MCFUART_BASE3 0x8800 /* on M548x */
54#define MCFUART_BASE4 0x8900 /* on M548x */
50#endif 55#endif
51 56
52 57
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index fd28178b5877..9287150e5fb0 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -175,6 +175,11 @@ config M5407
175 help 175 help
176 Motorola ColdFire 5407 processor support. 176 Motorola ColdFire 5407 processor support.
177 177
178config M548x
179 bool "MCF548x"
180 help
181 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
182
178endchoice 183endchoice
179 184
180config M527x 185config M527x
@@ -185,7 +190,7 @@ config M527x
185 190
186config COLDFIRE 191config COLDFIRE
187 bool 192 bool
188 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407) 193 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x)
189 select GENERIC_GPIO 194 select GENERIC_GPIO
190 select ARCH_REQUIRE_GPIOLIB 195 select ARCH_REQUIRE_GPIOLIB
191 default y 196 default y
diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile
index 14042574ac21..026ef16fa68e 100644
--- a/arch/m68knommu/Makefile
+++ b/arch/m68knommu/Makefile
@@ -25,6 +25,7 @@ platform-$(CONFIG_M528x) := 528x
25platform-$(CONFIG_M5307) := 5307 25platform-$(CONFIG_M5307) := 5307
26platform-$(CONFIG_M532x) := 532x 26platform-$(CONFIG_M532x) := 532x
27platform-$(CONFIG_M5407) := 5407 27platform-$(CONFIG_M5407) := 5407
28platform-$(CONFIG_M548x) := 548x
28PLATFORM := $(platform-y) 29PLATFORM := $(platform-y)
29 30
30board-$(CONFIG_PILOT) := pilot 31board-$(CONFIG_PILOT) := pilot
@@ -73,6 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire
73cpuclass-$(CONFIG_M5307) := coldfire 74cpuclass-$(CONFIG_M5307) := coldfire
74cpuclass-$(CONFIG_M532x) := coldfire 75cpuclass-$(CONFIG_M532x) := coldfire
75cpuclass-$(CONFIG_M5407) := coldfire 76cpuclass-$(CONFIG_M5407) := coldfire
77cpuclass-$(CONFIG_M548x) := coldfire
76cpuclass-$(CONFIG_M68328) := 68328 78cpuclass-$(CONFIG_M68328) := 68328
77cpuclass-$(CONFIG_M68EZ328) := 68328 79cpuclass-$(CONFIG_M68EZ328) := 68328
78cpuclass-$(CONFIG_M68VZ328) := 68328 80cpuclass-$(CONFIG_M68VZ328) := 68328
@@ -100,6 +102,7 @@ cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307)
100cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) 102cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200)
101cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) 103cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
102cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) 104cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200)
105cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200)
103cflags-$(CONFIG_M68328) := -m68000 106cflags-$(CONFIG_M68328) := -m68000
104cflags-$(CONFIG_M68EZ328) := -m68000 107cflags-$(CONFIG_M68EZ328) := -m68000
105cflags-$(CONFIG_M68VZ328) := -m68000 108cflags-$(CONFIG_M68VZ328) := -m68000
diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/548x/Makefile
new file mode 100644
index 000000000000..e6035e7a2d3f
--- /dev/null
+++ b/arch/m68knommu/platform/548x/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o
18
diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/548x/config.c
new file mode 100644
index 000000000000..9888846bd1cf
--- /dev/null
+++ b/arch/m68knommu/platform/548x/config.c
@@ -0,0 +1,115 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/548x/config.c
5 *
6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/m548xsim.h>
19#include <asm/mcfuart.h>
20#include <asm/m548xgpt.h>
21
22/***************************************************************************/
23
24static struct mcf_platform_uart m548x_uart_platform[] = {
25 {
26 .mapbase = MCF_MBAR + MCFUART_BASE1,
27 .irq = 64 + 35,
28 },
29 {
30 .mapbase = MCF_MBAR + MCFUART_BASE2,
31 .irq = 64 + 34,
32 },
33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE3,
35 .irq = 64 + 33,
36 },
37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE4,
39 .irq = 64 + 32,
40 },
41};
42
43static struct platform_device m548x_uart = {
44 .name = "mcfuart",
45 .id = 0,
46 .dev.platform_data = m548x_uart_platform,
47};
48
49static struct platform_device *m548x_devices[] __initdata = {
50 &m548x_uart,
51};
52
53
54/***************************************************************************/
55
56static void __init m548x_uart_init_line(int line, int irq)
57{
58 int rts_cts;
59
60 /* enable io pins */
61 switch (line) {
62 case 0:
63 rts_cts = 0; break;
64 case 1:
65 rts_cts = MCF_PAR_PSC_RTS_RTS; break;
66 case 2:
67 rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
68 case 3:
69 rts_cts = 0; break;
70 }
71 __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
72 MCF_MBAR + MCF_PAR_PSC(line));
73}
74
75static void __init m548x_uarts_init(void)
76{
77 const int nrlines = ARRAY_SIZE(m548x_uart_platform);
78 int line;
79
80 for (line = 0; (line < nrlines); line++)
81 m548x_uart_init_line(line, m548x_uart_platform[line].irq);
82}
83
84/***************************************************************************/
85
86static void mcf548x_reset(void)
87{
88 /* disable interrupts and enable the watchdog */
89 asm("movew #0x2700, %sr\n");
90 __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
91 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
92 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
93 MCF_MBAR + MCF_GPT_GMS0);
94}
95
96/***************************************************************************/
97
98void __init config_BSP(char *commandp, int size)
99{
100 mach_reset = mcf548x_reset;
101 m548x_uarts_init();
102}
103
104/***************************************************************************/
105
106static int __init init_BSP(void)
107{
108
109 platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
110 return 0;
111}
112
113arch_initcall(init_BSP);
114
115/***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index f72a0e5d9996..df62171d986c 100644
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o
26obj-$(CONFIG_M5307) += timers.o intc.o 26obj-$(CONFIG_M5307) += timers.o intc.o
27obj-$(CONFIG_M532x) += timers.o intc-simr.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o
28obj-$(CONFIG_M5407) += timers.o intc.o 28obj-$(CONFIG_M5407) += timers.o intc.o
29obj-$(CONFIG_M548x) += sltimers.o intc-2.o
29 30
30obj-y += pinmux.o gpio.o 31obj-y += pinmux.o gpio.o
31extra-y := head.o 32extra-y := head.o
diff --git a/arch/m68knommu/platform/coldfire/sltimers.c b/arch/m68knommu/platform/coldfire/sltimers.c
new file mode 100644
index 000000000000..0a1b937c3e18
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/sltimers.c
@@ -0,0 +1,145 @@
1/***************************************************************************/
2
3/*
4 * sltimers.c -- generic ColdFire slice timer support.
5 *
6 * Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
7 * based on
8 * timers.c -- generic ColdFire hardware timer support.
9 * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
10 */
11
12/***************************************************************************/
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/profile.h>
20#include <linux/clocksource.h>
21#include <asm/io.h>
22#include <asm/traps.h>
23#include <asm/machdep.h>
24#include <asm/coldfire.h>
25#include <asm/mcfslt.h>
26#include <asm/mcfsim.h>
27
28/***************************************************************************/
29
30#ifdef CONFIG_HIGHPROFILE
31
32/*
33 * By default use Slice Timer 1 as the profiler clock timer.
34 */
35#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a))
36
37/*
38 * Choose a reasonably fast profile timer. Make it an odd value to
39 * try and get good coverage of kernel operations.
40 */
41#define PROFILEHZ 1013
42
43irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
44{
45 /* Reset Slice Timer 1 */
46 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
47 if (current->pid)
48 profile_tick(CPU_PROFILING);
49 return IRQ_HANDLED;
50}
51
52static struct irqaction mcfslt_profile_irq = {
53 .name = "profile timer",
54 .flags = IRQF_DISABLED | IRQF_TIMER,
55 .handler = mcfslt_profile_tick,
56};
57
58void mcfslt_profile_init(void)
59{
60 printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
61 PROFILEHZ);
62
63 setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);
64
65 /* Set up TIMER 2 as high speed profile clock */
66 __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
67 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
68 PA(MCFSLT_SCR));
69
70}
71
72#endif /* CONFIG_HIGHPROFILE */
73
74/***************************************************************************/
75
76/*
77 * By default use Slice Timer 0 as the system clock timer.
78 */
79#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a))
80
81static u32 mcfslt_cycles_per_jiffy;
82static u32 mcfslt_cnt;
83
84static irqreturn_t mcfslt_tick(int irq, void *dummy)
85{
86 /* Reset Slice Timer 0 */
87 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
88 mcfslt_cnt += mcfslt_cycles_per_jiffy;
89 return arch_timer_interrupt(irq, dummy);
90}
91
92static struct irqaction mcfslt_timer_irq = {
93 .name = "timer",
94 .flags = IRQF_DISABLED | IRQF_TIMER,
95 .handler = mcfslt_tick,
96};
97
98static cycle_t mcfslt_read_clk(struct clocksource *cs)
99{
100 unsigned long flags;
101 u32 cycles;
102 u16 scnt;
103
104 local_irq_save(flags);
105 scnt = __raw_readl(TA(MCFSLT_SCNT));
106 cycles = mcfslt_cnt;
107 local_irq_restore(flags);
108
109 /* substract because slice timers count down */
110 return cycles - scnt;
111}
112
113static struct clocksource mcfslt_clk = {
114 .name = "slt",
115 .rating = 250,
116 .read = mcfslt_read_clk,
117 .shift = 20,
118 .mask = CLOCKSOURCE_MASK(32),
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
120};
121
122void hw_timer_init(void)
123{
124 mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
125 /*
126 * The coldfire slice timer (SLT) runs from STCNT to 0 included,
127 * then STCNT again and so on. It counts thus actually
128 * STCNT + 1 steps for 1 tick, not STCNT. So if you want
129 * n cycles, initialize STCNT with n - 1.
130 */
131 __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
132 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
133 TA(MCFSLT_SCR));
134 /* initialize mcfslt_cnt knowing that slice timers count down */
135 mcfslt_cnt = mcfslt_cycles_per_jiffy;
136
137 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
138
139 mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
140 clocksource_register(&mcfslt_clk);
141
142#ifdef CONFIG_HIGHPROFILE
143 mcfslt_profile_init();
144#endif
145}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 00:52:13 -0500