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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-03-12 11:10:28 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-03-20 06:48:04 -0400
commitea2d8a427fa99b70457518c8d3516f46e572b95d (patch)
treed2161defc02f655cb4c6fedb6250dc730cca4c3c
parentf4896f1529c43fb0688164ed33aebdf525a34fb7 (diff)
drm/i915: Store the converted link rates in intel_dp->supported_rates[]
No point in converting from hardware format every single time, just store the rates in the final format under intel_dp. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Todd Previte <tprevite@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c33
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h3
2 files changed, 21 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a9b984734b1a..f71ede776f2b 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1144,8 +1144,6 @@ static int
1144intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates) 1144intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
1145{ 1145{
1146 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1146 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1147 int i = 0;
1148 uint16_t val;
1149 1147
1150 if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) { 1148 if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
1151 /* 1149 /*
@@ -1153,18 +1151,12 @@ intel_read_sink_rates(struct intel_dp *intel_dp, int *sink_rates)
1153 * link rate table method, so read link rates from 1151 * link rate table method, so read link rates from
1154 * supported_link_rates 1152 * supported_link_rates
1155 */ 1153 */
1156 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) { 1154 memcpy(sink_rates, intel_dp->supported_rates,
1157 val = le16_to_cpu(intel_dp->supported_rates[i]); 1155 sizeof(intel_dp->supported_rates));
1158 if (val == 0)
1159 break;
1160
1161 sink_rates[i] = val * 200;
1162 }
1163 1156
1164 if (i <= 0) 1157 return intel_dp->num_supported_rates;
1165 DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
1166 } 1158 }
1167 return i; 1159 return 0;
1168} 1160}
1169 1161
1170static int 1162static int
@@ -3754,10 +3746,23 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
3754 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && 3746 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3755 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && 3747 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3756 (rev >= 0x03)) { /* eDp v1.4 or higher */ 3748 (rev >= 0x03)) { /* eDp v1.4 or higher */
3749 __le16 supported_rates[DP_MAX_SUPPORTED_RATES];
3750 int i;
3751
3757 intel_dp_dpcd_read_wake(&intel_dp->aux, 3752 intel_dp_dpcd_read_wake(&intel_dp->aux,
3758 DP_SUPPORTED_LINK_RATES, 3753 DP_SUPPORTED_LINK_RATES,
3759 intel_dp->supported_rates, 3754 supported_rates,
3760 sizeof(intel_dp->supported_rates)); 3755 sizeof(supported_rates));
3756
3757 for (i = 0; i < ARRAY_SIZE(supported_rates); i++) {
3758 int val = le16_to_cpu(supported_rates[i]);
3759
3760 if (val == 0)
3761 break;
3762
3763 intel_dp->supported_rates[i] = val * 200;
3764 }
3765 intel_dp->num_supported_rates = i;
3761 } 3766 }
3762 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3767 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3763 DP_DWN_STRM_PORT_PRESENT)) 3768 DP_DWN_STRM_PORT_PRESENT))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c77128c67cf8..69c8437be611 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -627,7 +627,8 @@ struct intel_dp {
627 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 627 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
628 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; 628 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
629 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 629 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
630 __le16 supported_rates[DP_MAX_SUPPORTED_RATES]; 630 uint8_t num_supported_rates;
631 int supported_rates[DP_MAX_SUPPORTED_RATES];
631 struct drm_dp_aux aux; 632 struct drm_dp_aux aux;
632 uint8_t train_set[4]; 633 uint8_t train_set[4];
633 int panel_power_up_delay; 634 int panel_power_up_delay;