diff options
author | Lothar Waßmann <LW@KARO-electronics.de> | 2014-11-17 04:51:17 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2014-11-18 15:19:31 -0500 |
commit | ea209de3dded8acd37677cf4e2f5fc06b791e052 (patch) | |
tree | 8c60304e0c9715684260fe63acf4015e5e2e2bc6 | |
parent | 9a9f9dd7c4653daf3f183f35c9a44d97ce9a91f1 (diff) |
net: fec: indentation cleanup
consistently use TABs for indentation
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/freescale/fec.h | 108 |
1 files changed, 54 insertions, 54 deletions
diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/freescale/fec.h index 9af296a1ca99..3047db4f8c7b 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h | |||
@@ -213,60 +213,60 @@ struct bufdesc_ex { | |||
213 | * The following definitions courtesy of commproc.h, which where | 213 | * The following definitions courtesy of commproc.h, which where |
214 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). | 214 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). |
215 | */ | 215 | */ |
216 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ | 216 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ |
217 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | 217 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ |
218 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | 218 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ |
219 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | 219 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ |
220 | #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ | 220 | #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ |
221 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | 221 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ |
222 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | 222 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ |
223 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | 223 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ |
224 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | 224 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ |
225 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | 225 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ |
226 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | 226 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ |
227 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | 227 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ |
228 | 228 | ||
229 | /* Buffer descriptor control/status used by Ethernet receive. | 229 | /* Buffer descriptor control/status used by Ethernet receive. |
230 | */ | 230 | */ |
231 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | 231 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) |
232 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | 232 | #define BD_ENET_RX_WRAP ((ushort)0x2000) |
233 | #define BD_ENET_RX_INTR ((ushort)0x1000) | 233 | #define BD_ENET_RX_INTR ((ushort)0x1000) |
234 | #define BD_ENET_RX_LAST ((ushort)0x0800) | 234 | #define BD_ENET_RX_LAST ((ushort)0x0800) |
235 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | 235 | #define BD_ENET_RX_FIRST ((ushort)0x0400) |
236 | #define BD_ENET_RX_MISS ((ushort)0x0100) | 236 | #define BD_ENET_RX_MISS ((ushort)0x0100) |
237 | #define BD_ENET_RX_LG ((ushort)0x0020) | 237 | #define BD_ENET_RX_LG ((ushort)0x0020) |
238 | #define BD_ENET_RX_NO ((ushort)0x0010) | 238 | #define BD_ENET_RX_NO ((ushort)0x0010) |
239 | #define BD_ENET_RX_SH ((ushort)0x0008) | 239 | #define BD_ENET_RX_SH ((ushort)0x0008) |
240 | #define BD_ENET_RX_CR ((ushort)0x0004) | 240 | #define BD_ENET_RX_CR ((ushort)0x0004) |
241 | #define BD_ENET_RX_OV ((ushort)0x0002) | 241 | #define BD_ENET_RX_OV ((ushort)0x0002) |
242 | #define BD_ENET_RX_CL ((ushort)0x0001) | 242 | #define BD_ENET_RX_CL ((ushort)0x0001) |
243 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | 243 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ |
244 | 244 | ||
245 | /* Enhanced buffer descriptor control/status used by Ethernet receive */ | 245 | /* Enhanced buffer descriptor control/status used by Ethernet receive */ |
246 | #define BD_ENET_RX_VLAN 0x00000004 | 246 | #define BD_ENET_RX_VLAN 0x00000004 |
247 | 247 | ||
248 | /* Buffer descriptor control/status used by Ethernet transmit. | 248 | /* Buffer descriptor control/status used by Ethernet transmit. |
249 | */ | 249 | */ |
250 | #define BD_ENET_TX_READY ((ushort)0x8000) | 250 | #define BD_ENET_TX_READY ((ushort)0x8000) |
251 | #define BD_ENET_TX_PAD ((ushort)0x4000) | 251 | #define BD_ENET_TX_PAD ((ushort)0x4000) |
252 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | 252 | #define BD_ENET_TX_WRAP ((ushort)0x2000) |
253 | #define BD_ENET_TX_INTR ((ushort)0x1000) | 253 | #define BD_ENET_TX_INTR ((ushort)0x1000) |
254 | #define BD_ENET_TX_LAST ((ushort)0x0800) | 254 | #define BD_ENET_TX_LAST ((ushort)0x0800) |
255 | #define BD_ENET_TX_TC ((ushort)0x0400) | 255 | #define BD_ENET_TX_TC ((ushort)0x0400) |
256 | #define BD_ENET_TX_DEF ((ushort)0x0200) | 256 | #define BD_ENET_TX_DEF ((ushort)0x0200) |
257 | #define BD_ENET_TX_HB ((ushort)0x0100) | 257 | #define BD_ENET_TX_HB ((ushort)0x0100) |
258 | #define BD_ENET_TX_LC ((ushort)0x0080) | 258 | #define BD_ENET_TX_LC ((ushort)0x0080) |
259 | #define BD_ENET_TX_RL ((ushort)0x0040) | 259 | #define BD_ENET_TX_RL ((ushort)0x0040) |
260 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | 260 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) |
261 | #define BD_ENET_TX_UN ((ushort)0x0002) | 261 | #define BD_ENET_TX_UN ((ushort)0x0002) |
262 | #define BD_ENET_TX_CSL ((ushort)0x0001) | 262 | #define BD_ENET_TX_CSL ((ushort)0x0001) |
263 | #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ | 263 | #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ |
264 | 264 | ||
265 | /*enhanced buffer descriptor control/status used by Ethernet transmit*/ | 265 | /* enhanced buffer descriptor control/status used by Ethernet transmit */ |
266 | #define BD_ENET_TX_INT 0x40000000 | 266 | #define BD_ENET_TX_INT 0x40000000 |
267 | #define BD_ENET_TX_TS 0x20000000 | 267 | #define BD_ENET_TX_TS 0x20000000 |
268 | #define BD_ENET_TX_PINS 0x10000000 | 268 | #define BD_ENET_TX_PINS 0x10000000 |
269 | #define BD_ENET_TX_IINS 0x08000000 | 269 | #define BD_ENET_TX_IINS 0x08000000 |
270 | 270 | ||
271 | 271 | ||
272 | /* This device has up to three irqs on some platforms */ | 272 | /* This device has up to three irqs on some platforms */ |
@@ -301,7 +301,7 @@ struct bufdesc_ex { | |||
301 | #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ | 301 | #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ |
302 | #define IDLE_SLOPE(X) ((X == 1) ? (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ | 302 | #define IDLE_SLOPE(X) ((X == 1) ? (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ |
303 | (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) | 303 | (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) |
304 | #define RCMR_MATCHEN (0x1 << 16) | 304 | #define RCMR_MATCHEN (0x1 << 16) |
305 | #define RCMR_CMP_CFG(v, n) ((v & 0x7) << (n << 2)) | 305 | #define RCMR_CMP_CFG(v, n) ((v & 0x7) << (n << 2)) |
306 | #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ | 306 | #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ |
307 | RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) | 307 | RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) |
@@ -326,8 +326,8 @@ struct bufdesc_ex { | |||
326 | #define TX_RING_SIZE 512 /* Must be power of two */ | 326 | #define TX_RING_SIZE 512 /* Must be power of two */ |
327 | #define TX_RING_MOD_MASK 511 /* for this to work */ | 327 | #define TX_RING_MOD_MASK 511 /* for this to work */ |
328 | 328 | ||
329 | #define BD_ENET_RX_INT 0x00800000 | 329 | #define BD_ENET_RX_INT 0x00800000 |
330 | #define BD_ENET_RX_PTP ((ushort)0x0400) | 330 | #define BD_ENET_RX_PTP ((ushort)0x0400) |
331 | #define BD_ENET_RX_ICE 0x00000020 | 331 | #define BD_ENET_RX_ICE 0x00000020 |
332 | #define BD_ENET_RX_PCR 0x00000010 | 332 | #define BD_ENET_RX_PCR 0x00000010 |
333 | #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) | 333 | #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) |
@@ -364,8 +364,8 @@ struct bufdesc_ex { | |||
364 | #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */ | 364 | #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */ |
365 | #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */ | 365 | #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */ |
366 | 366 | ||
367 | #define FEC_VLAN_TAG_LEN 0x04 | 367 | #define FEC_VLAN_TAG_LEN 0x04 |
368 | #define FEC_ETHTYPE_LEN 0x02 | 368 | #define FEC_ETHTYPE_LEN 0x02 |
369 | 369 | ||
370 | /* Controller is ENET-MAC */ | 370 | /* Controller is ENET-MAC */ |
371 | #define FEC_QUIRK_ENET_MAC (1 << 0) | 371 | #define FEC_QUIRK_ENET_MAC (1 << 0) |
@@ -390,7 +390,7 @@ struct bufdesc_ex { | |||
390 | * frames not being transmitted until there is a 0-to-1 transition on | 390 | * frames not being transmitted until there is a 0-to-1 transition on |
391 | * ENET_TDAR[TDAR]. | 391 | * ENET_TDAR[TDAR]. |
392 | */ | 392 | */ |
393 | #define FEC_QUIRK_ERR006358 (1 << 7) | 393 | #define FEC_QUIRK_ERR006358 (1 << 7) |
394 | /* ENET IP hw AVB | 394 | /* ENET IP hw AVB |
395 | * | 395 | * |
396 | * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. | 396 | * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. |