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authorLaxman Dewangan <ldewangan@nvidia.com>2013-01-08 05:57:44 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-01-16 01:15:17 -0500
commite9ea096dd2259454e0d09d0b0445fe8f0117add4 (patch)
tree7feeb18200f00e0a9c7f6deba1aa04a801914d61
parent42d34191545be343909417dd05db799686f2e48e (diff)
serial: tegra: add serial driver
NVIDIA's Tegra has multiple UART controller which supports: - APB DMA based controller fifo read/write. - End Of Data interrupt in incoming data to know whether end of frame achieve or not. - HW controlled RTS and CTS flow control to reduce SW overhead. Add serial driver to use all above feature. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Alan Cox <alan@linux.intel.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt24
-rw-r--r--drivers/tty/serial/Kconfig11
-rw-r--r--drivers/tty/serial/Makefile1
-rw-r--r--drivers/tty/serial/serial-tegra.c1399
4 files changed, 1435 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
new file mode 100644
index 000000000000..392a4493eebd
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt
@@ -0,0 +1,24 @@
1NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
2
3Required properties:
4- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
5- reg: Should contain UART controller registers location and length.
6- interrupts: Should contain UART controller interrupts.
7- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
8 request selector for this UART controller.
9
10Optional properties:
11- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
12 only if all 8 lines of UART controller are pinmuxed.
13
14Example:
15
16serial@70006000 {
17 compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart";
18 reg = <0x70006000 0x40>;
19 reg-shift = <2>;
20 interrupts = <0 36 0x04>;
21 nvidia,dma-request-selector = <&apbdma 8>;
22 nvidia,enable-modem-interrupt;
23 status = "disabled";
24};
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 59c23d038106..aff3cd356662 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -269,6 +269,17 @@ config SERIAL_SIRFSOC_CONSOLE
269 your boot loader about how to pass options to the kernel at 269 your boot loader about how to pass options to the kernel at
270 boot time.) 270 boot time.)
271 271
272config SERIAL_TEGRA
273 tristate "NVIDIA Tegra20/30 SoC serial controller"
274 depends on ARCH_TEGRA && TEGRA20_APB_DMA
275 select SERIAL_CORE
276 help
277 Support for the on-chip UARTs on the NVIDIA Tegra series SOCs
278 providing /dev/ttyHS0, 1, 2, 3 and 4 (note, some machines may not
279 provide all of these ports, depending on how the serial port
280 are enabled). This driver uses the APB DMA to achieve higher baudrate
281 and better performance.
282
272config SERIAL_MAX3100 283config SERIAL_MAX3100
273 tristate "MAX3100 support" 284 tristate "MAX3100 support"
274 depends on SPI 285 depends on SPI
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index df1b998c436b..82e4306bf962 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
80obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o 80obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
81obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o 81obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
82obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o 82obj-$(CONFIG_SERIAL_SIRFSOC) += sirfsoc_uart.o
83obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o
83obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o 84obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o
84obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o 85obj-$(CONFIG_SERIAL_EFM32_UART) += efm32-uart.o
85obj-$(CONFIG_SERIAL_ARC) += arc_uart.o 86obj-$(CONFIG_SERIAL_ARC) += arc_uart.o
diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
new file mode 100644
index 000000000000..cc4072f50352
--- /dev/null
+++ b/drivers/tty/serial/serial-tegra.c
@@ -0,0 +1,1399 @@
1/*
2 * serial_tegra.c
3 *
4 * High-speed serial driver for NVIDIA Tegra SoCs
5 *
6 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author: Laxman Dewangan <ldewangan@nvidia.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include <linux/clk.h>
24#include <linux/debugfs.h>
25#include <linux/delay.h>
26#include <linux/dmaengine.h>
27#include <linux/dma-mapping.h>
28#include <linux/dmapool.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/pagemap.h>
35#include <linux/platform_device.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
38#include <linux/serial_core.h>
39#include <linux/serial_reg.h>
40#include <linux/slab.h>
41#include <linux/string.h>
42#include <linux/termios.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45
46#include <mach/clk.h>
47
48#define TEGRA_UART_TYPE "TEGRA_UART"
49#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
50#define BYTES_TO_ALIGN(x) ((unsigned long)(x) & 0x3)
51
52#define TEGRA_UART_RX_DMA_BUFFER_SIZE 4096
53#define TEGRA_UART_LSR_TXFIFO_FULL 0x100
54#define TEGRA_UART_IER_EORD 0x20
55#define TEGRA_UART_MCR_RTS_EN 0x40
56#define TEGRA_UART_MCR_CTS_EN 0x20
57#define TEGRA_UART_LSR_ANY (UART_LSR_OE | UART_LSR_BI | \
58 UART_LSR_PE | UART_LSR_FE)
59#define TEGRA_UART_IRDA_CSR 0x08
60#define TEGRA_UART_SIR_ENABLED 0x80
61
62#define TEGRA_UART_TX_PIO 1
63#define TEGRA_UART_TX_DMA 2
64#define TEGRA_UART_MIN_DMA 16
65#define TEGRA_UART_FIFO_SIZE 32
66
67/*
68 * Tx fifo trigger level setting in tegra uart is in
69 * reverse way then conventional uart.
70 */
71#define TEGRA_UART_TX_TRIG_16B 0x00
72#define TEGRA_UART_TX_TRIG_8B 0x10
73#define TEGRA_UART_TX_TRIG_4B 0x20
74#define TEGRA_UART_TX_TRIG_1B 0x30
75
76#define TEGRA_UART_MAXIMUM 5
77
78/* Default UART setting when started: 115200 no parity, stop, 8 data bits */
79#define TEGRA_UART_DEFAULT_BAUD 115200
80#define TEGRA_UART_DEFAULT_LSR UART_LCR_WLEN8
81
82/* Tx transfer mode */
83#define TEGRA_TX_PIO 1
84#define TEGRA_TX_DMA 2
85
86/**
87 * tegra_uart_chip_data: SOC specific data.
88 *
89 * @tx_fifo_full_status: Status flag available for checking tx fifo full.
90 * @allow_txfifo_reset_fifo_mode: allow_tx fifo reset with fifo mode or not.
91 * Tegra30 does not allow this.
92 * @support_clk_src_div: Clock source support the clock divider.
93 */
94struct tegra_uart_chip_data {
95 bool tx_fifo_full_status;
96 bool allow_txfifo_reset_fifo_mode;
97 bool support_clk_src_div;
98};
99
100struct tegra_uart_port {
101 struct uart_port uport;
102 const struct tegra_uart_chip_data *cdata;
103
104 struct clk *uart_clk;
105 unsigned int current_baud;
106
107 /* Register shadow */
108 unsigned long fcr_shadow;
109 unsigned long mcr_shadow;
110 unsigned long lcr_shadow;
111 unsigned long ier_shadow;
112 bool rts_active;
113
114 int tx_in_progress;
115 unsigned int tx_bytes;
116
117 bool enable_modem_interrupt;
118
119 bool rx_timeout;
120 int rx_in_progress;
121 int symb_bit;
122 int dma_req_sel;
123
124 struct dma_chan *rx_dma_chan;
125 struct dma_chan *tx_dma_chan;
126 dma_addr_t rx_dma_buf_phys;
127 dma_addr_t tx_dma_buf_phys;
128 unsigned char *rx_dma_buf_virt;
129 unsigned char *tx_dma_buf_virt;
130 struct dma_async_tx_descriptor *tx_dma_desc;
131 struct dma_async_tx_descriptor *rx_dma_desc;
132 dma_cookie_t tx_cookie;
133 dma_cookie_t rx_cookie;
134 int tx_bytes_requested;
135 int rx_bytes_requested;
136};
137
138static void tegra_uart_start_next_tx(struct tegra_uart_port *tup);
139static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup);
140
141static inline unsigned long tegra_uart_read(struct tegra_uart_port *tup,
142 unsigned long reg)
143{
144 return readl(tup->uport.membase + (reg << tup->uport.regshift));
145}
146
147static inline void tegra_uart_write(struct tegra_uart_port *tup, unsigned val,
148 unsigned long reg)
149{
150 writel(val, tup->uport.membase + (reg << tup->uport.regshift));
151}
152
153static inline struct tegra_uart_port *to_tegra_uport(struct uart_port *u)
154{
155 return container_of(u, struct tegra_uart_port, uport);
156}
157
158static unsigned int tegra_uart_get_mctrl(struct uart_port *u)
159{
160 struct tegra_uart_port *tup = to_tegra_uport(u);
161
162 /*
163 * RI - Ring detector is active
164 * CD/DCD/CAR - Carrier detect is always active. For some reason
165 * linux has different names for carrier detect.
166 * DSR - Data Set ready is active as the hardware doesn't support it.
167 * Don't know if the linux support this yet?
168 * CTS - Clear to send. Always set to active, as the hardware handles
169 * CTS automatically.
170 */
171 if (tup->enable_modem_interrupt)
172 return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
173 return TIOCM_CTS;
174}
175
176static void set_rts(struct tegra_uart_port *tup, bool active)
177{
178 unsigned long mcr;
179
180 mcr = tup->mcr_shadow;
181 if (active)
182 mcr |= TEGRA_UART_MCR_RTS_EN;
183 else
184 mcr &= ~TEGRA_UART_MCR_RTS_EN;
185 if (mcr != tup->mcr_shadow) {
186 tegra_uart_write(tup, mcr, UART_MCR);
187 tup->mcr_shadow = mcr;
188 }
189 return;
190}
191
192static void set_dtr(struct tegra_uart_port *tup, bool active)
193{
194 unsigned long mcr;
195
196 mcr = tup->mcr_shadow;
197 if (active)
198 mcr |= UART_MCR_DTR;
199 else
200 mcr &= ~UART_MCR_DTR;
201 if (mcr != tup->mcr_shadow) {
202 tegra_uart_write(tup, mcr, UART_MCR);
203 tup->mcr_shadow = mcr;
204 }
205 return;
206}
207
208static void tegra_uart_set_mctrl(struct uart_port *u, unsigned int mctrl)
209{
210 struct tegra_uart_port *tup = to_tegra_uport(u);
211 unsigned long mcr;
212 int dtr_enable;
213
214 mcr = tup->mcr_shadow;
215 tup->rts_active = !!(mctrl & TIOCM_RTS);
216 set_rts(tup, tup->rts_active);
217
218 dtr_enable = !!(mctrl & TIOCM_DTR);
219 set_dtr(tup, dtr_enable);
220 return;
221}
222
223static void tegra_uart_break_ctl(struct uart_port *u, int break_ctl)
224{
225 struct tegra_uart_port *tup = to_tegra_uport(u);
226 unsigned long lcr;
227
228 lcr = tup->lcr_shadow;
229 if (break_ctl)
230 lcr |= UART_LCR_SBC;
231 else
232 lcr &= ~UART_LCR_SBC;
233 tegra_uart_write(tup, lcr, UART_LCR);
234 tup->lcr_shadow = lcr;
235}
236
237/* Wait for a symbol-time. */
238static void tegra_uart_wait_sym_time(struct tegra_uart_port *tup,
239 unsigned int syms)
240{
241 if (tup->current_baud)
242 udelay(DIV_ROUND_UP(syms * tup->symb_bit * 1000000,
243 tup->current_baud));
244}
245
246static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bits)
247{
248 unsigned long fcr = tup->fcr_shadow;
249
250 if (tup->cdata->allow_txfifo_reset_fifo_mode) {
251 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
252 tegra_uart_write(tup, fcr, UART_FCR);
253 } else {
254 fcr &= ~UART_FCR_ENABLE_FIFO;
255 tegra_uart_write(tup, fcr, UART_FCR);
256 udelay(60);
257 fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
258 tegra_uart_write(tup, fcr, UART_FCR);
259 fcr |= UART_FCR_ENABLE_FIFO;
260 tegra_uart_write(tup, fcr, UART_FCR);
261 }
262
263 /* Dummy read to ensure the write is posted */
264 tegra_uart_read(tup, UART_SCR);
265
266 /* Wait for the flush to propagate. */
267 tegra_uart_wait_sym_time(tup, 1);
268}
269
270static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int baud)
271{
272 unsigned long rate;
273 unsigned int divisor;
274 unsigned long lcr;
275 int ret;
276
277 if (tup->current_baud == baud)
278 return 0;
279
280 if (tup->cdata->support_clk_src_div) {
281 rate = baud * 16;
282 ret = clk_set_rate(tup->uart_clk, rate);
283 if (ret < 0) {
284 dev_err(tup->uport.dev,
285 "clk_set_rate() failed for rate %lu\n", rate);
286 return ret;
287 }
288 divisor = 1;
289 } else {
290 rate = clk_get_rate(tup->uart_clk);
291 divisor = DIV_ROUND_CLOSEST(rate, baud * 16);
292 }
293
294 lcr = tup->lcr_shadow;
295 lcr |= UART_LCR_DLAB;
296 tegra_uart_write(tup, lcr, UART_LCR);
297
298 tegra_uart_write(tup, divisor & 0xFF, UART_TX);
299 tegra_uart_write(tup, ((divisor >> 8) & 0xFF), UART_IER);
300
301 lcr &= ~UART_LCR_DLAB;
302 tegra_uart_write(tup, lcr, UART_LCR);
303
304 /* Dummy read to ensure the write is posted */
305 tegra_uart_read(tup, UART_SCR);
306
307 tup->current_baud = baud;
308
309 /* wait two character intervals at new rate */
310 tegra_uart_wait_sym_time(tup, 2);
311 return 0;
312}
313
314static char tegra_uart_decode_rx_error(struct tegra_uart_port *tup,
315 unsigned long lsr)
316{
317 char flag = TTY_NORMAL;
318
319 if (unlikely(lsr & TEGRA_UART_LSR_ANY)) {
320 if (lsr & UART_LSR_OE) {
321 /* Overrrun error */
322 flag |= TTY_OVERRUN;
323 tup->uport.icount.overrun++;
324 dev_err(tup->uport.dev, "Got overrun errors\n");
325 } else if (lsr & UART_LSR_PE) {
326 /* Parity error */
327 flag |= TTY_PARITY;
328 tup->uport.icount.parity++;
329 dev_err(tup->uport.dev, "Got Parity errors\n");
330 } else if (lsr & UART_LSR_FE) {
331 flag |= TTY_FRAME;
332 tup->uport.icount.frame++;
333 dev_err(tup->uport.dev, "Got frame errors\n");
334 } else if (lsr & UART_LSR_BI) {
335 dev_err(tup->uport.dev, "Got Break\n");
336 tup->uport.icount.brk++;
337 /* If FIFO read error without any data, reset Rx FIFO */
338 if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
339 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_RCVR);
340 }
341 }
342 return flag;
343}
344
345static int tegra_uart_request_port(struct uart_port *u)
346{
347 return 0;
348}
349
350static void tegra_uart_release_port(struct uart_port *u)
351{
352 /* Nothing to do here */
353}
354
355static void tegra_uart_fill_tx_fifo(struct tegra_uart_port *tup, int max_bytes)
356{
357 struct circ_buf *xmit = &tup->uport.state->xmit;
358 int i;
359
360 for (i = 0; i < max_bytes; i++) {
361 BUG_ON(uart_circ_empty(xmit));
362 if (tup->cdata->tx_fifo_full_status) {
363 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
364 if ((lsr & TEGRA_UART_LSR_TXFIFO_FULL))
365 break;
366 }
367 tegra_uart_write(tup, xmit->buf[xmit->tail], UART_TX);
368 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
369 tup->uport.icount.tx++;
370 }
371}
372
373static void tegra_uart_start_pio_tx(struct tegra_uart_port *tup,
374 unsigned int bytes)
375{
376 if (bytes > TEGRA_UART_MIN_DMA)
377 bytes = TEGRA_UART_MIN_DMA;
378
379 tup->tx_in_progress = TEGRA_UART_TX_PIO;
380 tup->tx_bytes = bytes;
381 tup->ier_shadow |= UART_IER_THRI;
382 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
383}
384
385static void tegra_uart_tx_dma_complete(void *args)
386{
387 struct tegra_uart_port *tup = args;
388 struct circ_buf *xmit = &tup->uport.state->xmit;
389 struct dma_tx_state state;
390 unsigned long flags;
391 int count;
392
393 dmaengine_tx_status(tup->tx_dma_chan, tup->rx_cookie, &state);
394 count = tup->tx_bytes_requested - state.residue;
395 async_tx_ack(tup->tx_dma_desc);
396 spin_lock_irqsave(&tup->uport.lock, flags);
397 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
398 tup->tx_in_progress = 0;
399 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
400 uart_write_wakeup(&tup->uport);
401 tegra_uart_start_next_tx(tup);
402 spin_unlock_irqrestore(&tup->uport.lock, flags);
403}
404
405static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup,
406 unsigned long count)
407{
408 struct circ_buf *xmit = &tup->uport.state->xmit;
409 dma_addr_t tx_phys_addr;
410
411 dma_sync_single_for_device(tup->uport.dev, tup->tx_dma_buf_phys,
412 UART_XMIT_SIZE, DMA_TO_DEVICE);
413
414 tup->tx_bytes = count & ~(0xF);
415 tx_phys_addr = tup->tx_dma_buf_phys + xmit->tail;
416 tup->tx_dma_desc = dmaengine_prep_slave_single(tup->tx_dma_chan,
417 tx_phys_addr, tup->tx_bytes, DMA_MEM_TO_DEV,
418 DMA_PREP_INTERRUPT);
419 if (!tup->tx_dma_desc) {
420 dev_err(tup->uport.dev, "Not able to get desc for Tx\n");
421 return -EIO;
422 }
423
424 tup->tx_dma_desc->callback = tegra_uart_tx_dma_complete;
425 tup->tx_dma_desc->callback_param = tup;
426 tup->tx_in_progress = TEGRA_UART_TX_DMA;
427 tup->tx_bytes_requested = tup->tx_bytes;
428 tup->tx_cookie = dmaengine_submit(tup->tx_dma_desc);
429 dma_async_issue_pending(tup->tx_dma_chan);
430 return 0;
431}
432
433static void tegra_uart_start_next_tx(struct tegra_uart_port *tup)
434{
435 unsigned long tail;
436 unsigned long count;
437 struct circ_buf *xmit = &tup->uport.state->xmit;
438
439 tail = (unsigned long)&xmit->buf[xmit->tail];
440 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
441 if (!count)
442 return;
443
444 if (count < TEGRA_UART_MIN_DMA)
445 tegra_uart_start_pio_tx(tup, count);
446 else if (BYTES_TO_ALIGN(tail) > 0)
447 tegra_uart_start_pio_tx(tup, BYTES_TO_ALIGN(tail));
448 else
449 tegra_uart_start_tx_dma(tup, count);
450}
451
452/* Called by serial core driver with u->lock taken. */
453static void tegra_uart_start_tx(struct uart_port *u)
454{
455 struct tegra_uart_port *tup = to_tegra_uport(u);
456 struct circ_buf *xmit = &u->state->xmit;
457
458 if (!uart_circ_empty(xmit) && !tup->tx_in_progress)
459 tegra_uart_start_next_tx(tup);
460}
461
462static unsigned int tegra_uart_tx_empty(struct uart_port *u)
463{
464 struct tegra_uart_port *tup = to_tegra_uport(u);
465 unsigned int ret = 0;
466 unsigned long flags;
467
468 spin_lock_irqsave(&u->lock, flags);
469 if (!tup->tx_in_progress) {
470 unsigned long lsr = tegra_uart_read(tup, UART_LSR);
471 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
472 ret = TIOCSER_TEMT;
473 }
474 spin_unlock_irqrestore(&u->lock, flags);
475 return ret;
476}
477
478static void tegra_uart_stop_tx(struct uart_port *u)
479{
480 struct tegra_uart_port *tup = to_tegra_uport(u);
481 struct circ_buf *xmit = &tup->uport.state->xmit;
482 struct dma_tx_state state;
483 int count;
484
485 dmaengine_terminate_all(tup->tx_dma_chan);
486 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state);
487 count = tup->tx_bytes_requested - state.residue;
488 async_tx_ack(tup->tx_dma_desc);
489 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
490 tup->tx_in_progress = 0;
491 return;
492}
493
494static void tegra_uart_handle_tx_pio(struct tegra_uart_port *tup)
495{
496 struct circ_buf *xmit = &tup->uport.state->xmit;
497
498 tegra_uart_fill_tx_fifo(tup, tup->tx_bytes);
499 tup->tx_in_progress = 0;
500 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
501 uart_write_wakeup(&tup->uport);
502 tegra_uart_start_next_tx(tup);
503 return;
504}
505
506static void tegra_uart_handle_rx_pio(struct tegra_uart_port *tup,
507 struct tty_struct *tty)
508{
509 do {
510 char flag = TTY_NORMAL;
511 unsigned long lsr = 0;
512 unsigned char ch;
513
514 lsr = tegra_uart_read(tup, UART_LSR);
515 if (!(lsr & UART_LSR_DR))
516 break;
517
518 flag = tegra_uart_decode_rx_error(tup, lsr);
519 ch = (unsigned char) tegra_uart_read(tup, UART_RX);
520 tup->uport.icount.rx++;
521
522 if (!uart_handle_sysrq_char(&tup->uport, ch) && tty)
523 tty_insert_flip_char(tty, ch, flag);
524 } while (1);
525
526 return;
527}
528
529static void tegra_uart_copy_rx_to_tty(struct tegra_uart_port *tup,
530 struct tty_struct *tty, int count)
531{
532 int copied;
533
534 tup->uport.icount.rx += count;
535 if (!tty) {
536 dev_err(tup->uport.dev, "No tty port\n");
537 return;
538 }
539 dma_sync_single_for_cpu(tup->uport.dev, tup->rx_dma_buf_phys,
540 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
541 copied = tty_insert_flip_string(tty,
542 ((unsigned char *)(tup->rx_dma_buf_virt)), count);
543 if (copied != count) {
544 WARN_ON(1);
545 dev_err(tup->uport.dev, "RxData copy to tty layer failed\n");
546 }
547 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
548 TEGRA_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
549}
550
551static void tegra_uart_rx_dma_complete(void *args)
552{
553 struct tegra_uart_port *tup = args;
554 struct uart_port *u = &tup->uport;
555 int count = tup->rx_bytes_requested;
556 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
557 unsigned long flags;
558
559 async_tx_ack(tup->rx_dma_desc);
560 spin_lock_irqsave(&u->lock, flags);
561
562 /* Deactivate flow control to stop sender */
563 if (tup->rts_active)
564 set_rts(tup, false);
565
566 /* If we are here, DMA is stopped */
567 if (count)
568 tegra_uart_copy_rx_to_tty(tup, tty, count);
569
570 tegra_uart_handle_rx_pio(tup, tty);
571 if (tty) {
572 tty_flip_buffer_push(tty);
573 tty_kref_put(tty);
574 }
575 tegra_uart_start_rx_dma(tup);
576
577 /* Activate flow control to start transfer */
578 if (tup->rts_active)
579 set_rts(tup, true);
580
581 spin_unlock_irqrestore(&u->lock, flags);
582}
583
584static void tegra_uart_handle_rx_dma(struct tegra_uart_port *tup)
585{
586 struct dma_tx_state state;
587 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
588 int count;
589
590 /* Deactivate flow control to stop sender */
591 if (tup->rts_active)
592 set_rts(tup, false);
593
594 dmaengine_terminate_all(tup->rx_dma_chan);
595 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
596 count = tup->rx_bytes_requested - state.residue;
597
598 /* If we are here, DMA is stopped */
599 if (count)
600 tegra_uart_copy_rx_to_tty(tup, tty, count);
601
602 tegra_uart_handle_rx_pio(tup, tty);
603 if (tty) {
604 tty_flip_buffer_push(tty);
605 tty_kref_put(tty);
606 }
607 tegra_uart_start_rx_dma(tup);
608
609 if (tup->rts_active)
610 set_rts(tup, true);
611}
612
613static int tegra_uart_start_rx_dma(struct tegra_uart_port *tup)
614{
615 unsigned int count = TEGRA_UART_RX_DMA_BUFFER_SIZE;
616
617 tup->rx_dma_desc = dmaengine_prep_slave_single(tup->rx_dma_chan,
618 tup->rx_dma_buf_phys, count, DMA_DEV_TO_MEM,
619 DMA_PREP_INTERRUPT);
620 if (!tup->rx_dma_desc) {
621 dev_err(tup->uport.dev, "Not able to get desc for Rx\n");
622 return -EIO;
623 }
624
625 tup->rx_dma_desc->callback = tegra_uart_rx_dma_complete;
626 tup->rx_dma_desc->callback_param = tup;
627 dma_sync_single_for_device(tup->uport.dev, tup->rx_dma_buf_phys,
628 count, DMA_TO_DEVICE);
629 tup->rx_bytes_requested = count;
630 tup->rx_cookie = dmaengine_submit(tup->rx_dma_desc);
631 dma_async_issue_pending(tup->rx_dma_chan);
632 return 0;
633}
634
635static void tegra_uart_handle_modem_signal_change(struct uart_port *u)
636{
637 struct tegra_uart_port *tup = to_tegra_uport(u);
638 unsigned long msr;
639
640 msr = tegra_uart_read(tup, UART_MSR);
641 if (!(msr & UART_MSR_ANY_DELTA))
642 return;
643
644 if (msr & UART_MSR_TERI)
645 tup->uport.icount.rng++;
646 if (msr & UART_MSR_DDSR)
647 tup->uport.icount.dsr++;
648 /* We may only get DDCD when HW init and reset */
649 if (msr & UART_MSR_DDCD)
650 uart_handle_dcd_change(&tup->uport, msr & UART_MSR_DCD);
651 /* Will start/stop_tx accordingly */
652 if (msr & UART_MSR_DCTS)
653 uart_handle_cts_change(&tup->uport, msr & UART_MSR_CTS);
654 return;
655}
656
657static irqreturn_t tegra_uart_isr(int irq, void *data)
658{
659 struct tegra_uart_port *tup = data;
660 struct uart_port *u = &tup->uport;
661 unsigned long iir;
662 unsigned long ier;
663 bool is_rx_int = false;
664 unsigned long flags;
665
666 spin_lock_irqsave(&u->lock, flags);
667 while (1) {
668 iir = tegra_uart_read(tup, UART_IIR);
669 if (iir & UART_IIR_NO_INT) {
670 if (is_rx_int) {
671 tegra_uart_handle_rx_dma(tup);
672 if (tup->rx_in_progress) {
673 ier = tup->ier_shadow;
674 ier |= (UART_IER_RLSI | UART_IER_RTOIE |
675 TEGRA_UART_IER_EORD);
676 tup->ier_shadow = ier;
677 tegra_uart_write(tup, ier, UART_IER);
678 }
679 }
680 spin_unlock_irqrestore(&u->lock, flags);
681 return IRQ_HANDLED;
682 }
683
684 switch ((iir >> 1) & 0x7) {
685 case 0: /* Modem signal change interrupt */
686 tegra_uart_handle_modem_signal_change(u);
687 break;
688
689 case 1: /* Transmit interrupt only triggered when using PIO */
690 tup->ier_shadow &= ~UART_IER_THRI;
691 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
692 tegra_uart_handle_tx_pio(tup);
693 break;
694
695 case 4: /* End of data */
696 case 6: /* Rx timeout */
697 case 2: /* Receive */
698 if (!is_rx_int) {
699 is_rx_int = true;
700 /* Disable Rx interrupts */
701 ier = tup->ier_shadow;
702 ier |= UART_IER_RDI;
703 tegra_uart_write(tup, ier, UART_IER);
704 ier &= ~(UART_IER_RDI | UART_IER_RLSI |
705 UART_IER_RTOIE | TEGRA_UART_IER_EORD);
706 tup->ier_shadow = ier;
707 tegra_uart_write(tup, ier, UART_IER);
708 }
709 break;
710
711 case 3: /* Receive error */
712 tegra_uart_decode_rx_error(tup,
713 tegra_uart_read(tup, UART_LSR));
714 break;
715
716 case 5: /* break nothing to handle */
717 case 7: /* break nothing to handle */
718 break;
719 }
720 }
721}
722
723static void tegra_uart_stop_rx(struct uart_port *u)
724{
725 struct tegra_uart_port *tup = to_tegra_uport(u);
726 struct tty_struct *tty = tty_port_tty_get(&tup->uport.state->port);
727 struct dma_tx_state state;
728 unsigned long ier;
729 int count;
730
731 if (tup->rts_active)
732 set_rts(tup, false);
733
734 if (!tup->rx_in_progress)
735 return;
736
737 tegra_uart_wait_sym_time(tup, 1); /* wait a character interval */
738
739 ier = tup->ier_shadow;
740 ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
741 TEGRA_UART_IER_EORD);
742 tup->ier_shadow = ier;
743 tegra_uart_write(tup, ier, UART_IER);
744 tup->rx_in_progress = 0;
745 if (tup->rx_dma_chan) {
746 dmaengine_terminate_all(tup->rx_dma_chan);
747 dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state);
748 async_tx_ack(tup->rx_dma_desc);
749 count = tup->rx_bytes_requested - state.residue;
750 tegra_uart_copy_rx_to_tty(tup, tty, count);
751 tegra_uart_handle_rx_pio(tup, tty);
752 } else {
753 tegra_uart_handle_rx_pio(tup, tty);
754 }
755 if (tty) {
756 tty_flip_buffer_push(tty);
757 tty_kref_put(tty);
758 }
759 return;
760}
761
762static void tegra_uart_hw_deinit(struct tegra_uart_port *tup)
763{
764 unsigned long flags;
765 unsigned long char_time = DIV_ROUND_UP(10000000, tup->current_baud);
766 unsigned long fifo_empty_time = tup->uport.fifosize * char_time;
767 unsigned long wait_time;
768 unsigned long lsr;
769 unsigned long msr;
770 unsigned long mcr;
771
772 /* Disable interrupts */
773 tegra_uart_write(tup, 0, UART_IER);
774
775 lsr = tegra_uart_read(tup, UART_LSR);
776 if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
777 msr = tegra_uart_read(tup, UART_MSR);
778 mcr = tegra_uart_read(tup, UART_MCR);
779 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
780 dev_err(tup->uport.dev,
781 "Tx Fifo not empty, CTS disabled, waiting\n");
782
783 /* Wait for Tx fifo to be empty */
784 while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
785 wait_time = min(fifo_empty_time, 100lu);
786 udelay(wait_time);
787 fifo_empty_time -= wait_time;
788 if (!fifo_empty_time) {
789 msr = tegra_uart_read(tup, UART_MSR);
790 mcr = tegra_uart_read(tup, UART_MCR);
791 if ((mcr & TEGRA_UART_MCR_CTS_EN) &&
792 (msr & UART_MSR_CTS))
793 dev_err(tup->uport.dev,
794 "Slave not ready\n");
795 break;
796 }
797 lsr = tegra_uart_read(tup, UART_LSR);
798 }
799 }
800
801 spin_lock_irqsave(&tup->uport.lock, flags);
802 /* Reset the Rx and Tx FIFOs */
803 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
804 tup->current_baud = 0;
805 spin_unlock_irqrestore(&tup->uport.lock, flags);
806
807 clk_disable_unprepare(tup->uart_clk);
808}
809
810static int tegra_uart_hw_init(struct tegra_uart_port *tup)
811{
812 int ret;
813
814 tup->fcr_shadow = 0;
815 tup->mcr_shadow = 0;
816 tup->lcr_shadow = 0;
817 tup->ier_shadow = 0;
818 tup->current_baud = 0;
819
820 clk_prepare_enable(tup->uart_clk);
821
822 /* Reset the UART controller to clear all previous status.*/
823 tegra_periph_reset_assert(tup->uart_clk);
824 udelay(10);
825 tegra_periph_reset_deassert(tup->uart_clk);
826
827 tup->rx_in_progress = 0;
828 tup->tx_in_progress = 0;
829
830 /*
831 * Set the trigger level
832 *
833 * For PIO mode:
834 *
835 * For receive, this will interrupt the CPU after that many number of
836 * bytes are received, for the remaining bytes the receive timeout
837 * interrupt is received. Rx high watermark is set to 4.
838 *
839 * For transmit, if the trasnmit interrupt is enabled, this will
840 * interrupt the CPU when the number of entries in the FIFO reaches the
841 * low watermark. Tx low watermark is set to 16 bytes.
842 *
843 * For DMA mode:
844 *
845 * Set the Tx trigger to 16. This should match the DMA burst size that
846 * programmed in the DMA registers.
847 */
848 tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
849 tup->fcr_shadow |= UART_FCR_R_TRIG_01;
850 tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
851 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
852
853 /*
854 * Initialize the UART with default configuration
855 * (115200, N, 8, 1) so that the receive DMA buffer may be
856 * enqueued
857 */
858 tup->lcr_shadow = TEGRA_UART_DEFAULT_LSR;
859 tegra_set_baudrate(tup, TEGRA_UART_DEFAULT_BAUD);
860 tup->fcr_shadow |= UART_FCR_DMA_SELECT;
861 tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
862
863 ret = tegra_uart_start_rx_dma(tup);
864 if (ret < 0) {
865 dev_err(tup->uport.dev, "Not able to start Rx DMA\n");
866 return ret;
867 }
868 tup->rx_in_progress = 1;
869
870 /*
871 * Enable IE_RXS for the receive status interrupts like line errros.
872 * Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
873 *
874 * If using DMA mode, enable EORD instead of receive interrupt which
875 * will interrupt after the UART is done with the receive instead of
876 * the interrupt when the FIFO "threshold" is reached.
877 *
878 * EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
879 * the DATA is sitting in the FIFO and couldn't be transferred to the
880 * DMA as the DMA size alignment(4 bytes) is not met. EORD will be
881 * triggered when there is a pause of the incomming data stream for 4
882 * characters long.
883 *
884 * For pauses in the data which is not aligned to 4 bytes, we get
885 * both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
886 * then the EORD.
887 */
888 tup->ier_shadow = UART_IER_RLSI | UART_IER_RTOIE | TEGRA_UART_IER_EORD;
889 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
890 return 0;
891}
892
893static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup,
894 bool dma_to_memory)
895{
896 struct dma_chan *dma_chan;
897 unsigned char *dma_buf;
898 dma_addr_t dma_phys;
899 int ret;
900 struct dma_slave_config dma_sconfig;
901 dma_cap_mask_t mask;
902
903 dma_cap_zero(mask);
904 dma_cap_set(DMA_SLAVE, mask);
905 dma_chan = dma_request_channel(mask, NULL, NULL);
906 if (!dma_chan) {
907 dev_err(tup->uport.dev,
908 "Dma channel is not available, will try later\n");
909 return -EPROBE_DEFER;
910 }
911
912 if (dma_to_memory) {
913 dma_buf = dma_alloc_coherent(tup->uport.dev,
914 TEGRA_UART_RX_DMA_BUFFER_SIZE,
915 &dma_phys, GFP_KERNEL);
916 if (!dma_buf) {
917 dev_err(tup->uport.dev,
918 "Not able to allocate the dma buffer\n");
919 dma_release_channel(dma_chan);
920 return -ENOMEM;
921 }
922 } else {
923 dma_phys = dma_map_single(tup->uport.dev,
924 tup->uport.state->xmit.buf, UART_XMIT_SIZE,
925 DMA_TO_DEVICE);
926 dma_buf = tup->uport.state->xmit.buf;
927 }
928
929 dma_sconfig.slave_id = tup->dma_req_sel;
930 if (dma_to_memory) {
931 dma_sconfig.src_addr = tup->uport.mapbase;
932 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
933 dma_sconfig.src_maxburst = 4;
934 } else {
935 dma_sconfig.dst_addr = tup->uport.mapbase;
936 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
937 dma_sconfig.dst_maxburst = 16;
938 }
939
940 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
941 if (ret < 0) {
942 dev_err(tup->uport.dev,
943 "Dma slave config failed, err = %d\n", ret);
944 goto scrub;
945 }
946
947 if (dma_to_memory) {
948 tup->rx_dma_chan = dma_chan;
949 tup->rx_dma_buf_virt = dma_buf;
950 tup->rx_dma_buf_phys = dma_phys;
951 } else {
952 tup->tx_dma_chan = dma_chan;
953 tup->tx_dma_buf_virt = dma_buf;
954 tup->tx_dma_buf_phys = dma_phys;
955 }
956 return 0;
957
958scrub:
959 dma_release_channel(dma_chan);
960 return ret;
961}
962
963static void tegra_uart_dma_channel_free(struct tegra_uart_port *tup,
964 bool dma_to_memory)
965{
966 struct dma_chan *dma_chan;
967
968 if (dma_to_memory) {
969 dma_free_coherent(tup->uport.dev, TEGRA_UART_RX_DMA_BUFFER_SIZE,
970 tup->rx_dma_buf_virt, tup->rx_dma_buf_phys);
971 dma_chan = tup->rx_dma_chan;
972 tup->rx_dma_chan = NULL;
973 tup->rx_dma_buf_phys = 0;
974 tup->rx_dma_buf_virt = NULL;
975 } else {
976 dma_unmap_single(tup->uport.dev, tup->tx_dma_buf_phys,
977 UART_XMIT_SIZE, DMA_TO_DEVICE);
978 dma_chan = tup->tx_dma_chan;
979 tup->tx_dma_chan = NULL;
980 tup->tx_dma_buf_phys = 0;
981 tup->tx_dma_buf_virt = NULL;
982 }
983 dma_release_channel(dma_chan);
984}
985
986static int tegra_uart_startup(struct uart_port *u)
987{
988 struct tegra_uart_port *tup = to_tegra_uport(u);
989 int ret;
990
991 ret = tegra_uart_dma_channel_allocate(tup, false);
992 if (ret < 0) {
993 dev_err(u->dev, "Tx Dma allocation failed, err = %d\n", ret);
994 return ret;
995 }
996
997 ret = tegra_uart_dma_channel_allocate(tup, true);
998 if (ret < 0) {
999 dev_err(u->dev, "Rx Dma allocation failed, err = %d\n", ret);
1000 goto fail_rx_dma;
1001 }
1002
1003 ret = tegra_uart_hw_init(tup);
1004 if (ret < 0) {
1005 dev_err(u->dev, "Uart HW init failed, err = %d\n", ret);
1006 goto fail_hw_init;
1007 }
1008
1009 ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
1010 dev_name(u->dev), tup);
1011 if (ret < 0) {
1012 dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
1013 goto fail_hw_init;
1014 }
1015 return 0;
1016
1017fail_hw_init:
1018 tegra_uart_dma_channel_free(tup, true);
1019fail_rx_dma:
1020 tegra_uart_dma_channel_free(tup, false);
1021 return ret;
1022}
1023
1024static void tegra_uart_shutdown(struct uart_port *u)
1025{
1026 struct tegra_uart_port *tup = to_tegra_uport(u);
1027
1028 tegra_uart_hw_deinit(tup);
1029
1030 tup->rx_in_progress = 0;
1031 tup->tx_in_progress = 0;
1032
1033 tegra_uart_dma_channel_free(tup, true);
1034 tegra_uart_dma_channel_free(tup, false);
1035 free_irq(u->irq, tup);
1036}
1037
1038static void tegra_uart_enable_ms(struct uart_port *u)
1039{
1040 struct tegra_uart_port *tup = to_tegra_uport(u);
1041
1042 if (tup->enable_modem_interrupt) {
1043 tup->ier_shadow |= UART_IER_MSI;
1044 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1045 }
1046}
1047
1048static void tegra_uart_set_termios(struct uart_port *u,
1049 struct ktermios *termios, struct ktermios *oldtermios)
1050{
1051 struct tegra_uart_port *tup = to_tegra_uport(u);
1052 unsigned int baud;
1053 unsigned long flags;
1054 unsigned int lcr;
1055 int symb_bit = 1;
1056 struct clk *parent_clk = clk_get_parent(tup->uart_clk);
1057 unsigned long parent_clk_rate = clk_get_rate(parent_clk);
1058 int max_divider = (tup->cdata->support_clk_src_div) ? 0x7FFF : 0xFFFF;
1059
1060 max_divider *= 16;
1061 spin_lock_irqsave(&u->lock, flags);
1062
1063 /* Changing configuration, it is safe to stop any rx now */
1064 if (tup->rts_active)
1065 set_rts(tup, false);
1066
1067 /* Clear all interrupts as configuration is going to be change */
1068 tegra_uart_write(tup, tup->ier_shadow | UART_IER_RDI, UART_IER);
1069 tegra_uart_read(tup, UART_IER);
1070 tegra_uart_write(tup, 0, UART_IER);
1071 tegra_uart_read(tup, UART_IER);
1072
1073 /* Parity */
1074 lcr = tup->lcr_shadow;
1075 lcr &= ~UART_LCR_PARITY;
1076
1077 /* CMSPAR isn't supported by this driver */
1078 termios->c_cflag &= ~CMSPAR;
1079
1080 if ((termios->c_cflag & PARENB) == PARENB) {
1081 symb_bit++;
1082 if (termios->c_cflag & PARODD) {
1083 lcr |= UART_LCR_PARITY;
1084 lcr &= ~UART_LCR_EPAR;
1085 lcr &= ~UART_LCR_SPAR;
1086 } else {
1087 lcr |= UART_LCR_PARITY;
1088 lcr |= UART_LCR_EPAR;
1089 lcr &= ~UART_LCR_SPAR;
1090 }
1091 }
1092
1093 lcr &= ~UART_LCR_WLEN8;
1094 switch (termios->c_cflag & CSIZE) {
1095 case CS5:
1096 lcr |= UART_LCR_WLEN5;
1097 symb_bit += 5;
1098 break;
1099 case CS6:
1100 lcr |= UART_LCR_WLEN6;
1101 symb_bit += 6;
1102 break;
1103 case CS7:
1104 lcr |= UART_LCR_WLEN7;
1105 symb_bit += 7;
1106 break;
1107 default:
1108 lcr |= UART_LCR_WLEN8;
1109 symb_bit += 8;
1110 break;
1111 }
1112
1113 /* Stop bits */
1114 if (termios->c_cflag & CSTOPB) {
1115 lcr |= UART_LCR_STOP;
1116 symb_bit += 2;
1117 } else {
1118 lcr &= ~UART_LCR_STOP;
1119 symb_bit++;
1120 }
1121
1122 tegra_uart_write(tup, lcr, UART_LCR);
1123 tup->lcr_shadow = lcr;
1124 tup->symb_bit = symb_bit;
1125
1126 /* Baud rate. */
1127 baud = uart_get_baud_rate(u, termios, oldtermios,
1128 parent_clk_rate/max_divider,
1129 parent_clk_rate/16);
1130 spin_unlock_irqrestore(&u->lock, flags);
1131 tegra_set_baudrate(tup, baud);
1132 if (tty_termios_baud_rate(termios))
1133 tty_termios_encode_baud_rate(termios, baud, baud);
1134 spin_lock_irqsave(&u->lock, flags);
1135
1136 /* Flow control */
1137 if (termios->c_cflag & CRTSCTS) {
1138 tup->mcr_shadow |= TEGRA_UART_MCR_CTS_EN;
1139 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1140 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1141 /* if top layer has asked to set rts active then do so here */
1142 if (tup->rts_active)
1143 set_rts(tup, true);
1144 } else {
1145 tup->mcr_shadow &= ~TEGRA_UART_MCR_CTS_EN;
1146 tup->mcr_shadow &= ~TEGRA_UART_MCR_RTS_EN;
1147 tegra_uart_write(tup, tup->mcr_shadow, UART_MCR);
1148 }
1149
1150 /* update the port timeout based on new settings */
1151 uart_update_timeout(u, termios->c_cflag, baud);
1152
1153 /* Make sure all write has completed */
1154 tegra_uart_read(tup, UART_IER);
1155
1156 /* Reenable interrupt */
1157 tegra_uart_write(tup, tup->ier_shadow, UART_IER);
1158 tegra_uart_read(tup, UART_IER);
1159
1160 spin_unlock_irqrestore(&u->lock, flags);
1161 return;
1162}
1163
1164/*
1165 * Flush any TX data submitted for DMA and PIO. Called when the
1166 * TX circular buffer is reset.
1167 */
1168static void tegra_uart_flush_buffer(struct uart_port *u)
1169{
1170 struct tegra_uart_port *tup = to_tegra_uport(u);
1171
1172 tup->tx_bytes = 0;
1173 if (tup->tx_dma_chan)
1174 dmaengine_terminate_all(tup->tx_dma_chan);
1175 return;
1176}
1177
1178static const char *tegra_uart_type(struct uart_port *u)
1179{
1180 return TEGRA_UART_TYPE;
1181}
1182
1183static struct uart_ops tegra_uart_ops = {
1184 .tx_empty = tegra_uart_tx_empty,
1185 .set_mctrl = tegra_uart_set_mctrl,
1186 .get_mctrl = tegra_uart_get_mctrl,
1187 .stop_tx = tegra_uart_stop_tx,
1188 .start_tx = tegra_uart_start_tx,
1189 .stop_rx = tegra_uart_stop_rx,
1190 .flush_buffer = tegra_uart_flush_buffer,
1191 .enable_ms = tegra_uart_enable_ms,
1192 .break_ctl = tegra_uart_break_ctl,
1193 .startup = tegra_uart_startup,
1194 .shutdown = tegra_uart_shutdown,
1195 .set_termios = tegra_uart_set_termios,
1196 .type = tegra_uart_type,
1197 .request_port = tegra_uart_request_port,
1198 .release_port = tegra_uart_release_port,
1199};
1200
1201static struct uart_driver tegra_uart_driver = {
1202 .owner = THIS_MODULE,
1203 .driver_name = "tegra_hsuart",
1204 .dev_name = "ttyTHS",
1205 .cons = 0,
1206 .nr = TEGRA_UART_MAXIMUM,
1207};
1208
1209static int tegra_uart_parse_dt(struct platform_device *pdev,
1210 struct tegra_uart_port *tup)
1211{
1212 struct device_node *np = pdev->dev.of_node;
1213 u32 of_dma[2];
1214 int port;
1215
1216 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1217 of_dma, 2) >= 0) {
1218 tup->dma_req_sel = of_dma[1];
1219 } else {
1220 dev_err(&pdev->dev, "missing dma requestor in device tree\n");
1221 return -EINVAL;
1222 }
1223
1224 port = of_alias_get_id(np, "serial");
1225 if (port < 0) {
1226 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", port);
1227 return port;
1228 }
1229 tup->uport.line = port;
1230
1231 tup->enable_modem_interrupt = of_property_read_bool(np,
1232 "nvidia,enable-modem-interrupt");
1233 return 0;
1234}
1235
1236struct tegra_uart_chip_data tegra20_uart_chip_data = {
1237 .tx_fifo_full_status = false,
1238 .allow_txfifo_reset_fifo_mode = true,
1239 .support_clk_src_div = false,
1240};
1241
1242struct tegra_uart_chip_data tegra30_uart_chip_data = {
1243 .tx_fifo_full_status = true,
1244 .allow_txfifo_reset_fifo_mode = false,
1245 .support_clk_src_div = true,
1246};
1247
1248static struct of_device_id tegra_uart_of_match[] = {
1249 {
1250 .compatible = "nvidia,tegra30-hsuart",
1251 .data = &tegra30_uart_chip_data,
1252 }, {
1253 .compatible = "nvidia,tegra20-hsuart",
1254 .data = &tegra20_uart_chip_data,
1255 }, {
1256 },
1257};
1258MODULE_DEVICE_TABLE(of, tegra_uart_of_match);
1259
1260static int tegra_uart_probe(struct platform_device *pdev)
1261{
1262 struct tegra_uart_port *tup;
1263 struct uart_port *u;
1264 struct resource *resource;
1265 int ret;
1266 const struct tegra_uart_chip_data *cdata;
1267 const struct of_device_id *match;
1268
1269 match = of_match_device(of_match_ptr(tegra_uart_of_match),
1270 &pdev->dev);
1271 if (!match) {
1272 dev_err(&pdev->dev, "Error: No device match found\n");
1273 return -ENODEV;
1274 }
1275 cdata = match->data;
1276
1277 tup = devm_kzalloc(&pdev->dev, sizeof(*tup), GFP_KERNEL);
1278 if (!tup) {
1279 dev_err(&pdev->dev, "Failed to allocate memory for tup\n");
1280 return -ENOMEM;
1281 }
1282
1283 ret = tegra_uart_parse_dt(pdev, tup);
1284 if (ret < 0)
1285 return ret;
1286
1287 u = &tup->uport;
1288 u->dev = &pdev->dev;
1289 u->ops = &tegra_uart_ops;
1290 u->type = PORT_TEGRA;
1291 u->fifosize = 32;
1292 tup->cdata = cdata;
1293
1294 platform_set_drvdata(pdev, tup);
1295 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1296 if (!resource) {
1297 dev_err(&pdev->dev, "No IO memory resource\n");
1298 return -ENODEV;
1299 }
1300
1301 u->mapbase = resource->start;
1302 u->membase = devm_request_and_ioremap(&pdev->dev, resource);
1303 if (!u->membase) {
1304 dev_err(&pdev->dev, "memregion/iomap address req failed\n");
1305 return -EADDRNOTAVAIL;
1306 }
1307
1308 tup->uart_clk = devm_clk_get(&pdev->dev, NULL);
1309 if (IS_ERR(tup->uart_clk)) {
1310 dev_err(&pdev->dev, "Couldn't get the clock\n");
1311 return PTR_ERR(tup->uart_clk);
1312 }
1313
1314 u->iotype = UPIO_MEM32;
1315 u->irq = platform_get_irq(pdev, 0);
1316 u->regshift = 2;
1317 ret = uart_add_one_port(&tegra_uart_driver, u);
1318 if (ret < 0) {
1319 dev_err(&pdev->dev, "Failed to add uart port, err %d\n", ret);
1320 return ret;
1321 }
1322 return ret;
1323}
1324
1325static int tegra_uart_remove(struct platform_device *pdev)
1326{
1327 struct tegra_uart_port *tup = platform_get_drvdata(pdev);
1328 struct uart_port *u = &tup->uport;
1329
1330 uart_remove_one_port(&tegra_uart_driver, u);
1331 return 0;
1332}
1333
1334#ifdef CONFIG_PM_SLEEP
1335static int tegra_uart_suspend(struct device *dev)
1336{
1337 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1338 struct uart_port *u = &tup->uport;
1339
1340 return uart_suspend_port(&tegra_uart_driver, u);
1341}
1342
1343static int tegra_uart_resume(struct device *dev)
1344{
1345 struct tegra_uart_port *tup = dev_get_drvdata(dev);
1346 struct uart_port *u = &tup->uport;
1347
1348 return uart_resume_port(&tegra_uart_driver, u);
1349}
1350#endif
1351
1352static const struct dev_pm_ops tegra_uart_pm_ops = {
1353 SET_SYSTEM_SLEEP_PM_OPS(tegra_uart_suspend, tegra_uart_resume)
1354};
1355
1356static struct platform_driver tegra_uart_platform_driver = {
1357 .probe = tegra_uart_probe,
1358 .remove = tegra_uart_remove,
1359 .driver = {
1360 .name = "serial-tegra",
1361 .of_match_table = of_match_ptr(tegra_uart_of_match),
1362 .pm = &tegra_uart_pm_ops,
1363 },
1364};
1365
1366static int __init tegra_uart_init(void)
1367{
1368 int ret;
1369
1370 ret = uart_register_driver(&tegra_uart_driver);
1371 if (ret < 0) {
1372 pr_err("Could not register %s driver\n",
1373 tegra_uart_driver.driver_name);
1374 return ret;
1375 }
1376
1377 ret = platform_driver_register(&tegra_uart_platform_driver);
1378 if (ret < 0) {
1379 pr_err("Uart platfrom driver register failed, e = %d\n", ret);
1380 uart_unregister_driver(&tegra_uart_driver);
1381 return ret;
1382 }
1383 return 0;
1384}
1385
1386static void __exit tegra_uart_exit(void)
1387{
1388 pr_info("Unloading tegra uart driver\n");
1389 platform_driver_unregister(&tegra_uart_platform_driver);
1390 uart_unregister_driver(&tegra_uart_driver);
1391}
1392
1393module_init(tegra_uart_init);
1394module_exit(tegra_uart_exit);
1395
1396MODULE_ALIAS("platform:serial-tegra");
1397MODULE_DESCRIPTION("High speed UART driver for tegra chipset");
1398MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1399MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 10:36:36 -0500