diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2013-03-20 05:15:28 -0400 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-04-04 03:09:08 -0400 |
| commit | e932900a3279b5dbb6d8f43c7b369003620e137c (patch) | |
| tree | 9278ee3e2b6f951a72ef5479029f836403950a11 | |
| parent | 3d5a96582303e28c48699f3faaf920ef7d43e6f2 (diff) | |
arm: zynq: Use standard timer binding
Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.
Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 45 | ||||
| -rw-r--r-- | arch/arm/boot/dts/zynq-zc702.dts | 10 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/common.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-zynq/timer.c | 261 |
4 files changed, 195 insertions, 122 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 5914b5654591..51243db2e9e4 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
| @@ -111,56 +111,23 @@ | |||
| 111 | }; | 111 | }; |
| 112 | 112 | ||
| 113 | ttc0: ttc0@f8001000 { | 113 | ttc0: ttc0@f8001000 { |
| 114 | #address-cells = <1>; | 114 | interrupt-parent = <&intc>; |
| 115 | #size-cells = <0>; | 115 | interrupts = < 0 10 4 0 11 4 0 12 4 >; |
| 116 | compatible = "xlnx,ttc"; | 116 | compatible = "cdns,ttc"; |
| 117 | reg = <0xF8001000 0x1000>; | 117 | reg = <0xF8001000 0x1000>; |
| 118 | clocks = <&cpu_clk 3>; | 118 | clocks = <&cpu_clk 3>; |
| 119 | clock-names = "cpu_1x"; | 119 | clock-names = "cpu_1x"; |
| 120 | clock-ranges; | 120 | clock-ranges; |
| 121 | |||
| 122 | ttc0_0: ttc0.0 { | ||
| 123 | status = "disabled"; | ||
| 124 | reg = <0>; | ||
| 125 | interrupts = <0 10 4>; | ||
| 126 | }; | ||
| 127 | ttc0_1: ttc0.1 { | ||
| 128 | status = "disabled"; | ||
| 129 | reg = <1>; | ||
| 130 | interrupts = <0 11 4>; | ||
| 131 | }; | ||
| 132 | ttc0_2: ttc0.2 { | ||
| 133 | status = "disabled"; | ||
| 134 | reg = <2>; | ||
| 135 | interrupts = <0 12 4>; | ||
| 136 | }; | ||
| 137 | }; | 121 | }; |
| 138 | 122 | ||
| 139 | ttc1: ttc1@f8002000 { | 123 | ttc1: ttc1@f8002000 { |
| 140 | #interrupt-parent = <&intc>; | 124 | interrupt-parent = <&intc>; |
| 141 | #address-cells = <1>; | 125 | interrupts = < 0 37 4 0 38 4 0 39 4 >; |
| 142 | #size-cells = <0>; | 126 | compatible = "cdns,ttc"; |
| 143 | compatible = "xlnx,ttc"; | ||
| 144 | reg = <0xF8002000 0x1000>; | 127 | reg = <0xF8002000 0x1000>; |
| 145 | clocks = <&cpu_clk 3>; | 128 | clocks = <&cpu_clk 3>; |
| 146 | clock-names = "cpu_1x"; | 129 | clock-names = "cpu_1x"; |
| 147 | clock-ranges; | 130 | clock-ranges; |
| 148 | |||
| 149 | ttc1_0: ttc1.0 { | ||
| 150 | status = "disabled"; | ||
| 151 | reg = <0>; | ||
| 152 | interrupts = <0 37 4>; | ||
| 153 | }; | ||
| 154 | ttc1_1: ttc1.1 { | ||
| 155 | status = "disabled"; | ||
| 156 | reg = <1>; | ||
| 157 | interrupts = <0 38 4>; | ||
| 158 | }; | ||
| 159 | ttc1_2: ttc1.2 { | ||
| 160 | status = "disabled"; | ||
| 161 | reg = <2>; | ||
| 162 | interrupts = <0 39 4>; | ||
| 163 | }; | ||
| 164 | }; | 131 | }; |
| 165 | }; | 132 | }; |
| 166 | }; | 133 | }; |
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index c772942a399a..86f44d5b0265 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts | |||
| @@ -32,13 +32,3 @@ | |||
| 32 | &ps_clk { | 32 | &ps_clk { |
| 33 | clock-frequency = <33333330>; | 33 | clock-frequency = <33333330>; |
| 34 | }; | 34 | }; |
| 35 | |||
| 36 | &ttc0_0 { | ||
| 37 | status = "ok"; | ||
| 38 | compatible = "xlnx,ttc-counter-clocksource"; | ||
| 39 | }; | ||
| 40 | |||
| 41 | &ttc0_1 { | ||
| 42 | status = "ok"; | ||
| 43 | compatible = "xlnx,ttc-counter-clockevent"; | ||
| 44 | }; | ||
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 5c8983218183..76493b050beb 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 22 | #include <linux/clk/zynq.h> | 22 | #include <linux/clk/zynq.h> |
| 23 | #include <linux/clocksource.h> | ||
| 23 | #include <linux/of_address.h> | 24 | #include <linux/of_address.h> |
| 24 | #include <linux/of_irq.h> | 25 | #include <linux/of_irq.h> |
| 25 | #include <linux/of_platform.h> | 26 | #include <linux/of_platform.h> |
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c index f9fbc9c1e7a6..82357d94a0e0 100644 --- a/arch/arm/mach-zynq/timer.c +++ b/arch/arm/mach-zynq/timer.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * This file contains driver for the Xilinx PS Timer Counter IP. | 2 | * This file contains driver for the Xilinx PS Timer Counter IP. |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2011 Xilinx | 4 | * Copyright (C) 2011-2013 Xilinx |
| 5 | * | 5 | * |
| 6 | * based on arch/mips/kernel/time.c timer driver | 6 | * based on arch/mips/kernel/time.c timer driver |
| 7 | * | 7 | * |
| @@ -15,6 +15,7 @@ | |||
| 15 | * GNU General Public License for more details. | 15 | * GNU General Public License for more details. |
| 16 | */ | 16 | */ |
| 17 | 17 | ||
| 18 | #include <linux/clk.h> | ||
| 18 | #include <linux/interrupt.h> | 19 | #include <linux/interrupt.h> |
| 19 | #include <linux/clockchips.h> | 20 | #include <linux/clockchips.h> |
| 20 | #include <linux/of_address.h> | 21 | #include <linux/of_address.h> |
| @@ -24,6 +25,21 @@ | |||
| 24 | #include "common.h" | 25 | #include "common.h" |
| 25 | 26 | ||
| 26 | /* | 27 | /* |
| 28 | * This driver configures the 2 16-bit count-up timers as follows: | ||
| 29 | * | ||
| 30 | * T1: Timer 1, clocksource for generic timekeeping | ||
| 31 | * T2: Timer 2, clockevent source for hrtimers | ||
| 32 | * T3: Timer 3, <unused> | ||
| 33 | * | ||
| 34 | * The input frequency to the timer module for emulation is 2.5MHz which is | ||
| 35 | * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32, | ||
| 36 | * the timers are clocked at 78.125KHz (12.8 us resolution). | ||
| 37 | |||
| 38 | * The input frequency to the timer module in silicon is configurable and | ||
| 39 | * obtained from device tree. The pre-scaler of 32 is used. | ||
| 40 | */ | ||
| 41 | |||
| 42 | /* | ||
| 27 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 | 43 | * Timer Register Offset Definitions of Timer 1, Increment base address by 4 |
| 28 | * and use same offsets for Timer 2 | 44 | * and use same offsets for Timer 2 |
| 29 | */ | 45 | */ |
| @@ -44,17 +60,24 @@ | |||
| 44 | #define PRESCALE 2048 /* The exponent must match this */ | 60 | #define PRESCALE 2048 /* The exponent must match this */ |
| 45 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) | 61 | #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1) |
| 46 | #define CLK_CNTRL_PRESCALE_EN 1 | 62 | #define CLK_CNTRL_PRESCALE_EN 1 |
| 47 | #define CNT_CNTRL_RESET (1<<4) | 63 | #define CNT_CNTRL_RESET (1 << 4) |
| 48 | 64 | ||
| 49 | /** | 65 | /** |
| 50 | * struct xttcps_timer - This definition defines local timer structure | 66 | * struct xttcps_timer - This definition defines local timer structure |
| 51 | * | 67 | * |
| 52 | * @base_addr: Base address of timer | 68 | * @base_addr: Base address of timer |
| 53 | **/ | 69 | * @clk: Associated clock source |
| 70 | * @clk_rate_change_nb Notifier block for clock rate changes | ||
| 71 | */ | ||
| 54 | struct xttcps_timer { | 72 | struct xttcps_timer { |
| 55 | void __iomem *base_addr; | 73 | void __iomem *base_addr; |
| 74 | struct clk *clk; | ||
| 75 | struct notifier_block clk_rate_change_nb; | ||
| 56 | }; | 76 | }; |
| 57 | 77 | ||
| 78 | #define to_xttcps_timer(x) \ | ||
| 79 | container_of(x, struct xttcps_timer, clk_rate_change_nb) | ||
| 80 | |||
| 58 | struct xttcps_timer_clocksource { | 81 | struct xttcps_timer_clocksource { |
| 59 | struct xttcps_timer xttc; | 82 | struct xttcps_timer xttc; |
| 60 | struct clocksource cs; | 83 | struct clocksource cs; |
| @@ -66,7 +89,6 @@ struct xttcps_timer_clocksource { | |||
| 66 | struct xttcps_timer_clockevent { | 89 | struct xttcps_timer_clockevent { |
| 67 | struct xttcps_timer xttc; | 90 | struct xttcps_timer xttc; |
| 68 | struct clock_event_device ce; | 91 | struct clock_event_device ce; |
| 69 | |||
