Merge tag 'irqchip-core-3.17' of git://git.infradead.org/users/jcooper/linux into irq/core

irqchip core changes for v3.17
 * nvic: use generic noop function
 * spear_shirq: generic cleanup, simplification, and refactoring

3 files changed, 141 insertions, 240 deletions

diff --git a/drivers/irqchip/irq-nvic.c b/drivers/irqchip/irq-nvic.c
index 70bdf6edb7bb..4ff0805fca01 100644
--- a/drivers/irqchip/irq-nvic.c
+++ b/drivers/irqchip/irq-nvic.c
@@ -49,14 +49,6 @@ nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
         handle_IRQ(irq, regs);
 }
 
-static void nvic_eoi(struct irq_data *d)
-{
-        /*
-         * This is a no-op as end of interrupt is signaled by the exception
-         * return sequence.
-         */
-}
-
 static int __init nvic_of_init(struct device_node *node,
                                struct device_node *parent)
 {
@@ -102,7 +94,10 @@ static int __init nvic_of_init(struct device_node *node,
                 gc->chip_types[0].regs.disable = NVIC_ICER;
                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
                 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
-                gc->chip_types[0].chip.irq_eoi = nvic_eoi;
+                /* This is a no-op as end of interrupt is signaled by the
+                 * exception return sequence.
+                 */
+                gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
 
                 /* disable interrupts */
                 writel_relaxed(~0, gc->reg_base + NVIC_ICER);
diff --git a/drivers/irqchip/spear-shirq.c b/drivers/irqchip/spear-shirq.c
index 6ce6bd3441bf..9c145a7cb056 100644
--- a/drivers/irqchip/spear-shirq.c
+++ b/drivers/irqchip/spear-shirq.c
@@ -19,7 +19,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
-#include <linux/irqchip/spear-shirq.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -27,20 +26,73 @@
 
 #include "irqchip.h"
 
-static DEFINE_SPINLOCK(lock);
+/*
+ * struct spear_shirq: shared irq structure
+ *
+ * base:        Base register address
+ * status_reg:  Status register offset for chained interrupt handler
+ * mask_reg:    Mask register offset for irq chip
+ * mask:        Mask to apply to the status register
+ * virq_base:   Base virtual interrupt number
+ * nr_irqs:     Number of interrupts handled by this block
+ * offset:      Bit offset of the first interrupt
+ * irq_chip:    Interrupt controller chip used for this instance,
+ *              if NULL group is disabled, but accounted
+ */
+struct spear_shirq {
+        void __iomem            *base;
+        u32                     status_reg;
+        u32                     mask_reg;
+        u32                     mask;
+        u32                     virq_base;
+        u32                     nr_irqs;
+        u32                     offset;
+        struct irq_chip         *irq_chip;
+};
 
 /* spear300 shared irq registers offsets and masks */
 #define SPEAR300_INT_ENB_MASK_REG       0x54
 #define SPEAR300_INT_STS_MASK_REG       0x58
 
+static DEFINE_RAW_SPINLOCK(shirq_lock);
+
+static void shirq_irq_mask(struct irq_data *d)
+{
+        struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
+        u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
+        u32 __iomem *reg = shirq->base + shirq->mask_reg;
+
+        raw_spin_lock(&shirq_lock);
+        val = readl(reg) & ~(0x1 << shift);
+        writel(val, reg);
+        raw_spin_unlock(&shirq_lock);
+}
+
+static void shirq_irq_unmask(struct irq_data *d)
+{
+        struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
+        u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
+        u32 __iomem *reg = shirq->base + shirq->mask_reg;
+
+        raw_spin_lock(&shirq_lock);
+        val = readl(reg) | (0x1 << shift);
+        writel(val, reg);
+        raw_spin_unlock(&shirq_lock);
+}
+
+static struct irq_chip shirq_chip = {
+        .name           = "spear-shirq",
+        .irq_mask       = shirq_irq_mask,
+        .irq_unmask     = shirq_irq_unmask,
+};
+
 static struct spear_shirq spear300_shirq_ras1 = {
-        .irq_nr = 9,
-        .irq_bit_off = 0,
-        .regs = {
-                .enb_reg = SPEAR300_INT_ENB_MASK_REG,
-                .status_reg = SPEAR300_INT_STS_MASK_REG,
-                .clear_reg = -1,
-        },
+        .offset         = 0,
+        .nr_irqs        = 9,
+        .mask           = ((0x1 << 9) - 1) << 0,
+        .irq_chip       = &shirq_chip,
+        .status_reg     = SPEAR300_INT_STS_MASK_REG,
+        .mask_reg       = SPEAR300_INT_ENB_MASK_REG,
 };
 
 static struct spear_shirq *spear300_shirq_blocks[] = {
@@ -51,43 +103,35 @@ static struct spear_shirq *spear300_shirq_blocks[] = {
 #define SPEAR310_INT_STS_MASK_REG       0x04
 
 static struct spear_shirq spear310_shirq_ras1 = {
-        .irq_nr = 8,
-        .irq_bit_off = 0,
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .clear_reg = -1,
-        },
+        .offset         = 0,
+        .nr_irqs        = 8,
+        .mask           = ((0x1 << 8) - 1) << 0,
+        .irq_chip       = &dummy_irq_chip,
+        .status_reg     = SPEAR310_INT_STS_MASK_REG,
 };
 
 static struct spear_shirq spear310_shirq_ras2 = {
-        .irq_nr = 5,
-        .irq_bit_off = 8,
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .clear_reg = -1,
-        },
+        .offset         = 8,
+        .nr_irqs        = 5,
+        .mask           = ((0x1 << 5) - 1) << 8,
+        .irq_chip       = &dummy_irq_chip,
+        .status_reg     = SPEAR310_INT_STS_MASK_REG,
 };
 
 static struct spear_shirq spear310_shirq_ras3 = {
-        .irq_nr = 1,
-        .irq_bit_off = 13,
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .clear_reg = -1,
-        },
+        .offset         = 13,
+        .nr_irqs        = 1,
+        .mask           = ((0x1 << 1) - 1) << 13,
+        .irq_chip       = &dummy_irq_chip,
+        .status_reg     = SPEAR310_INT_STS_MASK_REG,
 };
 
 static struct spear_shirq spear310_shirq_intrcomm_ras = {
-        .irq_nr = 3,
-        .irq_bit_off = 14,
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR310_INT_STS_MASK_REG,
-                .clear_reg = -1,
-        },
+        .offset         = 14,
+        .nr_irqs        = 3,
+        .mask           = ((0x1 << 3) - 1) << 14,
+        .irq_chip       = &dummy_irq_chip,
+        .status_reg     = SPEAR310_INT_STS_MASK_REG,
 };
 
 static struct spear_shirq *spear310_shirq_blocks[] = {
@@ -102,50 +146,34 @@ static struct spear_shirq *spear310_shirq_blocks[] = {
 #define SPEAR320_INT_CLR_MASK_REG               0x04
 #define SPEAR320_INT_ENB_MASK_REG               0x08
 
-static struct spear_shirq spear320_shirq_ras1 = {
-        .irq_nr = 3,
-        .irq_bit_off = 7,
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR320_INT_STS_MASK_REG,
-                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
-                .reset_to_clear = 1,
-        },
+static struct spear_shirq spear320_shirq_ras3 = {
+        .offset         = 0,
+        .nr_irqs        = 7,
+        .mask           = ((0x1 << 7) - 1) << 0,
 };
 
-static struct spear_shirq spear320_shirq_ras2 = {
-        .irq_nr = 1,
-        .irq_bit_off = 10,
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR320_INT_STS_MASK_REG,
-                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
-                .reset_to_clear = 1,
-        },
+static struct spear_shirq spear320_shirq_ras1 = {
+        .offset         = 7,
+        .nr_irqs        = 3,
+        .mask           = ((0x1 << 3) - 1) << 7,
+        .irq_chip       = &dummy_irq_chip,
+        .status_reg     = SPEAR320_INT_STS_MASK_REG,
 };
 
-static struct spear_shirq spear320_shirq_ras3 = {
-        .irq_nr = 7,
-        .irq_bit_off = 0,
-        .invalid_irq = 1,
-        .regs = {
-                .enb_reg = SPEAR320_INT_ENB_MASK_REG,
-                .reset_to_enb = 1,
-                .status_reg = SPEAR320_INT_STS_MASK_REG,
-                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
-                .reset_to_clear = 1,
-        },
+static struct spear_shirq spear320_shirq_ras2 = {
+        .offset         = 10,
+        .nr_irqs        = 1,
+        .mask           = ((0x1 << 1) - 1) << 10,
+        .irq_chip       = &dummy_irq_chip,
+        .status_reg     = SPEAR320_INT_STS_MASK_REG,
 };
 
 static struct spear_shirq spear320_shirq_intrcomm_ras = {
-        .irq_nr = 11,
-        .irq_bit_off = 11,
-        .regs = {
-                .enb_reg = -1,
-                .status_reg = SPEAR320_INT_STS_MASK_REG,
-                .clear_reg = SPEAR320_INT_CLR_MASK_REG,
-                .reset_to_clear = 1,
-        },
+        .offset         = 11,
+        .nr_irqs        = 11,
+        .mask           = ((0x1 << 11) - 1) << 11,
+        .irq_chip       = &dummy_irq_chip,
+        .status_reg     = SPEAR320_INT_STS_MASK_REG,
 };
 
 static struct spear_shirq *spear320_shirq_blocks[] = {
@@ -155,104 +183,46 @@ static struct spear_shirq *spear320_shirq_blocks[] = {
         &spear320_shirq_intrcomm_ras,
 };
 
-static void shirq_irq_mask_unmask(struct irq_data *d, bool mask)
-{
-        struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
-        u32 val, offset = d->irq - shirq->irq_base;
-        unsigned long flags;
-
-        if (shirq->regs.enb_reg == -1)
-                return;
-
-        spin_lock_irqsave(&lock, flags);
-        val = readl(shirq->base + shirq->regs.enb_reg);
-
-        if (mask ^ shirq->regs.reset_to_enb)
-                val &= ~(0x1 << shirq->irq_bit_off << offset);
-        else
-                val |= 0x1 << shirq->irq_bit_off << offset;
-
-        writel(val, shirq->base + shirq->regs.enb_reg);
-        spin_unlock_irqrestore(&lock, flags);
-
-}
-
-static void shirq_irq_mask(struct irq_data *d)
-{
-        shirq_irq_mask_unmask(d, 1);
-}
-
-static void shirq_irq_unmask(struct irq_data *d)
-{
-        shirq_irq_mask_unmask(d, 0);
-}
-
-static struct irq_chip shirq_chip = {
-        .name           = "spear-shirq",
-        .irq_ack        = shirq_irq_mask,
-        .irq_mask       = shirq_irq_mask,
-        .irq_unmask     = shirq_irq_unmask,
-};
-
 static void shirq_handler(unsigned irq, struct irq_desc *desc)
 {
-        u32 i, j, val, mask, tmp;
-        struct irq_chip *chip;
         struct spear_shirq *shirq = irq_get_handler_data(irq);
+        u32 pend;
 
-        chip = irq_get_chip(irq);
-        chip->irq_ack(&desc->irq_data);
-
-        mask = ((0x1 << shirq->irq_nr) - 1) << shirq->irq_bit_off;
-        while ((val = readl(shirq->base + shirq->regs.status_reg) &
-                                mask)) {
-
-                val >>= shirq->irq_bit_off;
-                for (i = 0, j = 1; i < shirq->irq_nr; i++, j <<= 1) {
-
-                        if (!(j & val))
-                                continue;
+        pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
+        pend >>= shirq->offset;
 
-                        generic_handle_irq(shirq->irq_base + i);
+        while (pend) {
+                int irq = __ffs(pend);
 
-                        /* clear interrupt */
-                        if (shirq->regs.clear_reg == -1)
-                                continue;
-
-                        tmp = readl(shirq->base + shirq->regs.clear_reg);
-                        if (shirq->regs.reset_to_clear)
-                                tmp &= ~(j << shirq->irq_bit_off);
-                        else
-                                tmp |= (j << shirq->irq_bit_off);
-                        writel(tmp, shirq->base + shirq->regs.clear_reg);
-                }
+                pend &= ~(0x1 << irq);
+                generic_handle_irq(shirq->virq_base + irq);
         }
-        chip->irq_unmask(&desc->irq_data);
 }
 
-static void __init spear_shirq_register(struct spear_shirq *shirq)
+static void __init spear_shirq_register(struct spear_shirq *shirq,
+                                        int parent_irq)
 {
         int i;
 
-        if (shirq->invalid_irq)
+        if (!shirq->irq_chip)
                 return;
 
-        irq_set_chained_handler(shirq->irq, shirq_handler);
-        for (i = 0; i < shirq->irq_nr; i++) {
-                irq_set_chip_and_handler(shirq->irq_base + i,
-                                         &shirq_chip, handle_simple_irq);
-                set_irq_flags(shirq->irq_base + i, IRQF_VALID);
-                irq_set_chip_data(shirq->irq_base + i, shirq);
-        }
+        irq_set_chained_handler(parent_irq, shirq_handler);
+        irq_set_handler_data(parent_irq, shirq);
 
-        irq_set_handler_data(shirq->irq, shirq);
+        for (i = 0; i < shirq->nr_irqs; i++) {
+                irq_set_chip_and_handler(shirq->virq_base + i,
+                                         shirq->irq_chip, handle_simple_irq);
+                set_irq_flags(shirq->virq_base + i, IRQF_VALID);
+                irq_set_chip_data(shirq->virq_base + i, shirq);
+        }
 }
 
 static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
                 struct device_node *np)
 {
-        int i, irq_base, hwirq = 0, irq_nr = 0;
-        static struct irq_domain *shirq_domain;
+        int i, parent_irq, virq_base, hwirq = 0, nr_irqs = 0;
+        struct irq_domain *shirq_domain;
         void __iomem *base;
 
         base = of_iomap(np, 0);
@@ -262,15 +232,15 @@ static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
         }
 
         for (i = 0; i < block_nr; i++)
-                irq_nr += shirq_blocks[i]->irq_nr;
+                nr_irqs += shirq_blocks[i]->nr_irqs;
 
-        irq_base = irq_alloc_descs(-1, 0, irq_nr, 0);
-        if (IS_ERR_VALUE(irq_base)) {
+        virq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
+        if (IS_ERR_VALUE(virq_base)) {
                 pr_err("%s: irq desc alloc failed\n", __func__);
                 goto err_unmap;
         }
 
-        shirq_domain = irq_domain_add_legacy(np, irq_nr, irq_base, 0,
+        shirq_domain = irq_domain_add_legacy(np, nr_irqs, virq_base, 0,
                         &irq_domain_simple_ops, NULL);
         if (WARN_ON(!shirq_domain)) {
                 pr_warn("%s: irq domain init failed\n", __func__);
@@ -279,41 +249,41 @@ static int __init shirq_init(struct spear_shirq **shirq_blocks, int block_nr,
 
         for (i = 0; i < block_nr; i++) {
                 shirq_blocks[i]->base = base;
-                shirq_blocks[i]->irq_base = irq_find_mapping(shirq_domain,
+                shirq_blocks[i]->virq_base = irq_find_mapping(shirq_domain,
                                 hwirq);
-                shirq_blocks[i]->irq = irq_of_parse_and_map(np, i);
 
-                spear_shirq_register(shirq_blocks[i]);
-                hwirq += shirq_blocks[i]->irq_nr;
+                parent_irq = irq_of_parse_and_map(np, i);
+                spear_shirq_register(shirq_blocks[i], parent_irq);
+                hwirq += shirq_blocks[i]->nr_irqs;
         }
 
         return 0;
 
 err_free_desc:
-        irq_free_descs(irq_base, irq_nr);
+        irq_free_descs(virq_base, nr_irqs);
 err_unmap:
         iounmap(base);
         return -ENXIO;
 }
 
-int __init spear300_shirq_of_init(struct device_node *np,
-                struct device_node *parent)
+static int __init spear300_shirq_of_init(struct device_node *np,
+                                         struct device_node *parent)
 {
         return shirq_init(spear300_shirq_blocks,
                         ARRAY_SIZE(spear300_shirq_blocks), np);
 }
 IRQCHIP_DECLARE(spear300_shirq, "st,spear300-shirq", spear300_shirq_of_init);
 
-int __init spear310_shirq_of_init(struct device_node *np,
-                struct device_node *parent)
+static int __init spear310_shirq_of_init(struct device_node *np,
+                                         struct device_node *parent)
 {
         return shirq_init(spear310_shirq_blocks,
                         ARRAY_SIZE(spear310_shirq_blocks), np);
 }
 IRQCHIP_DECLARE(spear310_shirq, "st,spear310-shirq", spear310_shirq_of_init);
 
-int __init spear320_shirq_of_init(struct device_node *np,
-                struct device_node *parent)
+static int __init spear320_shirq_of_init(struct device_node *np,
+                                         struct device_node *parent)
 {
         return shirq_init(spear320_shirq_blocks,
                         ARRAY_SIZE(spear320_shirq_blocks), np);
diff --git a/include/linux/irqchip/spear-shirq.h b/include/linux/irqchip/spear-shirq.h
deleted file mode 100644
index c8be16d213a3..000000000000
--- a/include/linux/irqchip/spear-shirq.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * SPEAr platform shared irq layer header file
- *
- * Copyright (C) 2009-2012 ST Microelectronics
- * Viresh Kumar <viresh.linux@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __SPEAR_SHIRQ_H
-#define __SPEAR_SHIRQ_H
-
-#include <linux/irq.h>
-#include <linux/types.h>
-
-/*
- * struct shirq_regs: shared irq register configuration
- *
- * enb_reg: enable register offset
- * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
- * status_reg: status register offset
- * status_reg_mask: status register valid mask
- * clear_reg: clear register offset
- * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
- */
-struct shirq_regs {
-        u32 enb_reg;
-        u32 reset_to_enb;
-        u32 status_reg;
-        u32 clear_reg;
-        u32 reset_to_clear;
-};
-
-/*
- * struct spear_shirq: shared irq structure
- *
- * irq: hardware irq number
- * irq_base: base irq in linux domain
- * irq_nr: no. of shared interrupts in a particular block
- * irq_bit_off: starting bit offset in the status register
- * invalid_irq: irq group is currently disabled
- * base: base address of shared irq register
- * regs: register configuration for shared irq block
- */
-struct spear_shirq {
-        u32 irq;
-        u32 irq_base;
-        u32 irq_nr;
-        u32 irq_bit_off;
-        int invalid_irq;
-        void __iomem *base;
-        struct shirq_regs regs;
-};
-
-int __init spear300_shirq_of_init(struct device_node *np,
-                struct device_node *parent);
-int __init spear310_shirq_of_init(struct device_node *np,
-                struct device_node *parent);
-int __init spear320_shirq_of_init(struct device_node *np,
-                struct device_node *parent);
-
-#endif /* __SPEAR_SHIRQ_H */