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authorScott Wood <scottwood@freescale.com>2014-05-05 21:35:10 -0400
committerScott Wood <scottwood@freescale.com>2014-05-22 19:10:42 -0400
commite83eb028bb980cecc85b050aa626df384723aff2 (patch)
tree4e58df362d96f4f5e38d1c0b3b5cc064b88b69c5
parent8cb59788b342903f2912ecef0df4aaadd12e5843 (diff)
powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chips
Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Diana Craciun <diana.craciun@freescale.com>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi4
10 files changed, 27 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index b5daa4c812c2..5290df83ff30 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -262,6 +262,7 @@
262 interrupts = < 262 interrupts = <
263 24 2 0 0 263 24 2 0 0
264 16 2 1 30>; 264 16 2 1 30>;
265 fsl,portid-mapping = <0x0f000000>;
265 266
266 pamu0: pamu@0 { 267 pamu0: pamu@0 {
267 reg = <0 0x1000>; 268 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 22f3b14517de..b1ea147f2995 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 5abd1fccedb8..cd63cb1b1042 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -289,6 +289,7 @@
289 interrupts = < 289 interrupts = <
290 24 2 0 0 290 24 2 0 0
291 16 2 1 30>; 291 16 2 1 30>;
292 fsl,portid-mapping = <0x0f000000>;
292 293
293 pamu0: pamu@0 { 294 pamu0: pamu@0 {
294 reg = <0 0x1000>; 295 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index 468e8be8ac6f..dc5f4b362c24 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -84,6 +84,7 @@
84 reg = <0>; 84 reg = <0>;
85 clocks = <&mux0>; 85 clocks = <&mux0>;
86 next-level-cache = <&L2_0>; 86 next-level-cache = <&L2_0>;
87 fsl,portid-mapping = <0x80000000>;
87 L2_0: l2-cache { 88 L2_0: l2-cache {
88 next-level-cache = <&cpc>; 89 next-level-cache = <&cpc>;
89 }; 90 };
@@ -93,6 +94,7 @@
93 reg = <1>; 94 reg = <1>;
94 clocks = <&mux1>; 95 clocks = <&mux1>;
95 next-level-cache = <&L2_1>; 96 next-level-cache = <&L2_1>;
97 fsl,portid-mapping = <0x40000000>;
96 L2_1: l2-cache { 98 L2_1: l2-cache {
97 next-level-cache = <&cpc>; 99 next-level-cache = <&cpc>;
98 }; 100 };
@@ -102,6 +104,7 @@
102 reg = <2>; 104 reg = <2>;
103 clocks = <&mux2>; 105 clocks = <&mux2>;
104 next-level-cache = <&L2_2>; 106 next-level-cache = <&L2_2>;
107 fsl,portid-mapping = <0x20000000>;
105 L2_2: l2-cache { 108 L2_2: l2-cache {
106 next-level-cache = <&cpc>; 109 next-level-cache = <&cpc>;
107 }; 110 };
@@ -111,6 +114,7 @@
111 reg = <3>; 114 reg = <3>;
112 clocks = <&mux3>; 115 clocks = <&mux3>;
113 next-level-cache = <&L2_3>; 116 next-level-cache = <&L2_3>;
117 fsl,portid-mapping = <0x10000000>;
114 L2_3: l2-cache { 118 L2_3: l2-cache {
115 next-level-cache = <&cpc>; 119 next-level-cache = <&cpc>;
116 }; 120 };
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index bf0e7c960c8a..12947ccddf25 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -297,6 +297,7 @@
297 interrupts = < 297 interrupts = <
298 24 2 0 0 298 24 2 0 0
299 16 2 1 30>; 299 16 2 1 30>;
300 fsl,portid-mapping = <0x00f80000>;
300 301
301 pamu0: pamu@0 { 302 pamu0: pamu@0 {
302 reg = <0 0x1000>; 303 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 0040b5a5379e..38bde0958672 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
@@ -119,6 +123,7 @@
119 reg = <4>; 123 reg = <4>;
120 clocks = <&mux4>; 124 clocks = <&mux4>;
121 next-level-cache = <&L2_4>; 125 next-level-cache = <&L2_4>;
126 fsl,portid-mapping = <0x08000000>;
122 L2_4: l2-cache { 127 L2_4: l2-cache {
123 next-level-cache = <&cpc>; 128 next-level-cache = <&cpc>;
124 }; 129 };
@@ -128,6 +133,7 @@
128 reg = <5>; 133 reg = <5>;
129 clocks = <&mux5>; 134 clocks = <&mux5>;
130 next-level-cache = <&L2_5>; 135 next-level-cache = <&L2_5>;
136 fsl,portid-mapping = <0x04000000>;
131 L2_5: l2-cache { 137 L2_5: l2-cache {
132 next-level-cache = <&cpc>; 138 next-level-cache = <&cpc>;
133 }; 139 };
@@ -137,6 +143,7 @@
137 reg = <6>; 143 reg = <6>;
138 clocks = <&mux6>; 144 clocks = <&mux6>;
139 next-level-cache = <&L2_6>; 145 next-level-cache = <&L2_6>;
146 fsl,portid-mapping = <0x02000000>;
140 L2_6: l2-cache { 147 L2_6: l2-cache {
141 next-level-cache = <&cpc>; 148 next-level-cache = <&cpc>;
142 }; 149 };
@@ -146,6 +153,7 @@
146 reg = <7>; 153 reg = <7>;
147 clocks = <&mux7>; 154 clocks = <&mux7>;
148 next-level-cache = <&L2_7>; 155 next-level-cache = <&L2_7>;
156 fsl,portid-mapping = <0x01000000>;
149 L2_7: l2-cache { 157 L2_7: l2-cache {
150 next-level-cache = <&cpc>; 158 next-level-cache = <&cpc>;
151 }; 159 };
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index f7ca9f4d5c04..4c4a2b0436b2 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -294,6 +294,7 @@
294 interrupts = < 294 interrupts = <
295 24 2 0 0 295 24 2 0 0
296 16 2 1 30>; 296 16 2 1 30>;
297 fsl,portid-mapping = <0x3c000000>;
297 298
298 pamu0: pamu@0 { 299 pamu0: pamu@0 {
299 reg = <0 0x1000>; 300 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index fe1a2e6613b4..1cc61e126e4c 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -90,6 +90,7 @@
90 reg = <0>; 90 reg = <0>;
91 clocks = <&mux0>; 91 clocks = <&mux0>;
92 next-level-cache = <&L2_0>; 92 next-level-cache = <&L2_0>;
93 fsl,portid-mapping = <0x80000000>;
93 L2_0: l2-cache { 94 L2_0: l2-cache {
94 next-level-cache = <&cpc>; 95 next-level-cache = <&cpc>;
95 }; 96 };
@@ -99,6 +100,7 @@
99 reg = <1>; 100 reg = <1>;
100 clocks = <&mux1>; 101 clocks = <&mux1>;
101 next-level-cache = <&L2_1>; 102 next-level-cache = <&L2_1>;
103 fsl,portid-mapping = <0x40000000>;
102 L2_1: l2-cache { 104 L2_1: l2-cache {
103 next-level-cache = <&cpc>; 105 next-level-cache = <&cpc>;
104 }; 106 };
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 91477b57d461..67296fdd9698 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -248,6 +248,7 @@
248 #size-cells = <1>; 248 #size-cells = <1>;
249 interrupts = <24 2 0 0 249 interrupts = <24 2 0 0
250 16 2 1 30>; 250 16 2 1 30>;
251 fsl,portid-mapping = <0x0f800000>;
251 252
252 pamu0: pamu@0 { 253 pamu0: pamu@0 {
253 reg = <0 0x1000>; 254 reg = <0 0x1000>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 3674686687cb..b048a2be05a8 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -83,6 +83,7 @@
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>; 84 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
86 fsl,portid-mapping = <0x80000000>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
88 }; 89 };
@@ -92,6 +93,7 @@
92 reg = <1>; 93 reg = <1>;
93 clocks = <&mux1>; 94 clocks = <&mux1>;
94 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
96 fsl,portid-mapping = <0x40000000>;
95 L2_1: l2-cache { 97 L2_1: l2-cache {
96 next-level-cache = <&cpc>; 98 next-level-cache = <&cpc>;
97 }; 99 };
@@ -101,6 +103,7 @@
101 reg = <2>; 103 reg = <2>;
102 clocks = <&mux2>; 104 clocks = <&mux2>;
103 next-level-cache = <&L2_2>; 105 next-level-cache = <&L2_2>;
106 fsl,portid-mapping = <0x20000000>;
104 L2_2: l2-cache { 107 L2_2: l2-cache {
105 next-level-cache = <&cpc>; 108 next-level-cache = <&cpc>;
106 }; 109 };
@@ -110,6 +113,7 @@
110 reg = <3>; 113 reg = <3>;
111 clocks = <&mux3>; 114 clocks = <&mux3>;
112 next-level-cache = <&L2_3>; 115 next-level-cache = <&L2_3>;
116 fsl,portid-mapping = <0x10000000>;
113 L2_3: l2-cache { 117 L2_3: l2-cache {
114 next-level-cache = <&cpc>; 118 next-level-cache = <&cpc>;
115 }; 119 };
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 12:20:54 -0400