diff options
author | Adrian Bunk <bunk@kernel.org> | 2008-07-16 12:25:44 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2008-07-20 09:38:19 -0400 |
commit | e76812eddcebe06403934c868f3a707fd5bc167d (patch) | |
tree | b99f9ad29113262d7d5ff9bbac487e60aaaf7686 | |
parent | fc22c3571c86cc36f4eb29336ce40c04a666ee98 (diff) |
[MIPS] Remove asm-mips/mips-boards/atlas{,int}.h
asm-mips/mips-boards/atlas{,int}.h are now obsolete.
Signed-off-by: Adrian Bunk <bunk@kernel.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | include/asm-mips/mips-boards/atlas.h | 80 | ||||
-rw-r--r-- | include/asm-mips/mips-boards/atlasint.h | 109 |
2 files changed, 0 insertions, 189 deletions
diff --git a/include/asm-mips/mips-boards/atlas.h b/include/asm-mips/mips-boards/atlas.h deleted file mode 100644 index a8ae12d120ee..000000000000 --- a/include/asm-mips/mips-boards/atlas.h +++ /dev/null | |||
@@ -1,80 +0,0 @@ | |||
1 | /* | ||
2 | * Carsten Langgaard, carstenl@mips.com | ||
3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | ||
4 | * | ||
5 | * ######################################################################## | ||
6 | * | ||
7 | * This program is free software; you can distribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License (Version 2) as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
14 | * for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License along | ||
17 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
18 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
19 | * | ||
20 | * ######################################################################## | ||
21 | * | ||
22 | * Defines of the Atlas board specific address-MAP, registers, etc. | ||
23 | * | ||
24 | */ | ||
25 | #ifndef _MIPS_ATLAS_H | ||
26 | #define _MIPS_ATLAS_H | ||
27 | |||
28 | #include <asm/addrspace.h> | ||
29 | |||
30 | /* | ||
31 | * Atlas RTC-device indirect register access. | ||
32 | */ | ||
33 | #define ATLAS_RTC_ADR_REG 0x1f000800 | ||
34 | #define ATLAS_RTC_DAT_REG 0x1f000808 | ||
35 | |||
36 | /* | ||
37 | * Atlas interrupt controller register base. | ||
38 | */ | ||
39 | #define ATLAS_ICTRL_REGS_BASE 0x1f000000 | ||
40 | |||
41 | /* | ||
42 | * Atlas registers are memory mapped on 64-bit aligned boundaries and | ||
43 | * only word access are allowed. | ||
44 | */ | ||
45 | struct atlas_ictrl_regs { | ||
46 | volatile unsigned int intraw; | ||
47 | int dummy1; | ||
48 | volatile unsigned int intseten; | ||
49 | int dummy2; | ||
50 | volatile unsigned int intrsten; | ||
51 | int dummy3; | ||
52 | volatile unsigned int intenable; | ||
53 | int dummy4; | ||
54 | volatile unsigned int intstatus; | ||
55 | int dummy5; | ||
56 | }; | ||
57 | |||
58 | /* | ||
59 | * Atlas UART register base. | ||
60 | */ | ||
61 | #define ATLAS_UART_REGS_BASE 0x1f000900 | ||
62 | #define ATLAS_BASE_BAUD ( 3686400 / 16 ) | ||
63 | |||
64 | /* | ||
65 | * Atlas PSU standby register. | ||
66 | */ | ||
67 | #define ATLAS_PSUSTBY_REG 0x1f000600 | ||
68 | #define ATLAS_GOSTBY 0x4d | ||
69 | |||
70 | /* | ||
71 | * We make a universal assumption about the way the bootloader (YAMON) | ||
72 | * have located the Philips SAA9730 chip. | ||
73 | * This is not ideal, but is needed for setting up remote debugging as | ||
74 | * soon as possible. | ||
75 | */ | ||
76 | #define ATLAS_SAA9730_REG 0x10800000 | ||
77 | |||
78 | #define ATLAS_SAA9730_BAUDCLOCK 3692300 | ||
79 | |||
80 | #endif /* !(_MIPS_ATLAS_H) */ | ||
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h deleted file mode 100644 index 93ba1c1b2a4f..000000000000 --- a/include/asm-mips/mips-boards/atlasint.h +++ /dev/null | |||
@@ -1,109 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved. | ||
3 | * Authors: Carsten Langgaard <carstenl@mips.com> | ||
4 | * Maciej W. Rozycki <macro@mips.com> | ||
5 | * | ||
6 | * ######################################################################## | ||
7 | * | ||
8 | * This program is free software; you can distribute it and/or modify it | ||
9 | * under the terms of the GNU General Public License (Version 2) as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
15 | * for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along | ||
18 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
19 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
20 | * | ||
21 | * ######################################################################## | ||
22 | * | ||
23 | * Defines for the Atlas interrupt controller. | ||
24 | * | ||
25 | */ | ||
26 | #ifndef _MIPS_ATLASINT_H | ||
27 | #define _MIPS_ATLASINT_H | ||
28 | |||
29 | #include <irq.h> | ||
30 | |||
31 | /* CPU interrupt offsets */ | ||
32 | #define MIPSCPU_INT_SW0 0 | ||
33 | #define MIPSCPU_INT_SW1 1 | ||
34 | #define MIPSCPU_INT_MB0 2 | ||
35 | #define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0 | ||
36 | #define MIPSCPU_INT_MB1 3 | ||
37 | #define MIPSCPU_INT_MB2 4 | ||
38 | #define MIPSCPU_INT_MB3 5 | ||
39 | #define MIPSCPU_INT_MB4 6 | ||
40 | |||
41 | /* | ||
42 | * Interrupts 8..39 are used for Atlas interrupt controller interrupts | ||
43 | */ | ||
44 | #define ATLAS_INT_BASE 8 | ||
45 | #define ATLAS_INT_UART (ATLAS_INT_BASE + 0) | ||
46 | #define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1) | ||
47 | #define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2) | ||
48 | #define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3) | ||
49 | #define ATLAS_INT_RTC (ATLAS_INT_BASE + 4) | ||
50 | #define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5) | ||
51 | #define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6) | ||
52 | #define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7) | ||
53 | #define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8) | ||
54 | #define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9) | ||
55 | #define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10) | ||
56 | #define ATLAS_INT_PCID (ATLAS_INT_BASE + 11) | ||
57 | #define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12) | ||
58 | #define ATLAS_INT_DEG (ATLAS_INT_BASE + 13) | ||
59 | #define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14) | ||
60 | #define ATLAS_INT_INTA (ATLAS_INT_BASE + 15) | ||
61 | #define ATLAS_INT_INTB (ATLAS_INT_BASE + 16) | ||
62 | #define ATLAS_INT_ETH ATLAS_INT_INTB | ||
63 | #define ATLAS_INT_INTC (ATLAS_INT_BASE + 17) | ||
64 | #define ATLAS_INT_SCSI ATLAS_INT_INTC | ||
65 | #define ATLAS_INT_INTD (ATLAS_INT_BASE + 18) | ||
66 | #define ATLAS_INT_SERR (ATLAS_INT_BASE + 19) | ||
67 | #define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20) | ||
68 | #define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21) | ||
69 | #define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22) | ||
70 | #define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23) | ||
71 | #define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24) | ||
72 | #define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25) | ||
73 | #define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26) | ||
74 | #define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27) | ||
75 | #define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28) | ||
76 | #define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29) | ||
77 | #define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30) | ||
78 | #define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31) | ||
79 | #define ATLAS_INT_END (ATLAS_INT_BASE + 31) | ||
80 | |||
81 | /* | ||
82 | * Interrupts 64..127 are used for Soc-it Classic interrupts | ||
83 | */ | ||
84 | #define MSC01C_INT_BASE 64 | ||
85 | |||
86 | /* SOC-it Classic interrupt offsets */ | ||
87 | #define MSC01C_INT_TMR 0 | ||
88 | #define MSC01C_INT_PCI 1 | ||
89 | |||
90 | /* | ||
91 | * Interrupts 64..127 are used for Soc-it EIC interrupts | ||
92 | */ | ||
93 | #define MSC01E_INT_BASE 64 | ||
94 | |||
95 | /* SOC-it EIC interrupt offsets */ | ||
96 | #define MSC01E_INT_SW0 1 | ||
97 | #define MSC01E_INT_SW1 2 | ||
98 | #define MSC01E_INT_MB0 3 | ||
99 | #define MSC01E_INT_ATLAS MSC01E_INT_MB0 | ||
100 | #define MSC01E_INT_MB1 4 | ||
101 | #define MSC01E_INT_MB2 5 | ||
102 | #define MSC01E_INT_MB3 6 | ||
103 | #define MSC01E_INT_MB4 7 | ||
104 | #define MSC01E_INT_TMR 8 | ||
105 | #define MSC01E_INT_PCI 9 | ||
106 | #define MSC01E_INT_PERFCTR 10 | ||
107 | #define MSC01E_INT_CPUCTR 11 | ||
108 | |||
109 | #endif /* !(_MIPS_ATLASINT_H) */ | ||