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authorYan, Zheng <zheng.z.yan@intel.com>2014-09-04 19:08:26 -0400
committerIngo Molnar <mingo@kernel.org>2014-09-24 08:48:21 -0400
commite735b9db12d76d45f74aee78bd63bbd2f8f480e1 (patch)
treeac69d5ad0c9f3dfde4e720d413d05a3ac4be61e2
parentfdda3c4aacec30bdf3c10904d0c32409145dc1b6 (diff)
perf/x86/intel/uncore: Add Haswell-EP uncore support
The uncore subsystem in Haswell-EP is similar to Sandy/Ivy Bridge-EP. There are some differences in config register encoding and pci device IDs. The Haswell-EP uncore also supports a few new events. Add the Haswell-EP driver to the snbep split driver. Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> [ Add missing break. Add imc events. Add cbox nc/isoc/c6. ] Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: eranian@google.com Link: http://lkml.kernel.org/r/1409872109-31645-2-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.c7
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.h2
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c608
3 files changed, 615 insertions, 2 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 812ec5d8218a..2b0fa02268b7 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -883,6 +883,9 @@ static int __init uncore_pci_init(void)
883 case 62: /* Ivy Bridge-EP */ 883 case 62: /* Ivy Bridge-EP */
884 ret = ivbep_uncore_pci_init(); 884 ret = ivbep_uncore_pci_init();
885 break; 885 break;
886 case 63: /* Haswell-EP */
887 ret = hswep_uncore_pci_init();
888 break;
886 case 42: /* Sandy Bridge */ 889 case 42: /* Sandy Bridge */
887 ret = snb_uncore_pci_init(); 890 ret = snb_uncore_pci_init();
888 break; 891 break;
@@ -1190,7 +1193,9 @@ static int __init uncore_cpu_init(void)
1190 case 62: /* Ivy Bridge-EP */ 1193 case 62: /* Ivy Bridge-EP */
1191 ivbep_uncore_cpu_init(); 1194 ivbep_uncore_cpu_init();
1192 break; 1195 break;
1193 1196 case 63: /* Haswell-EP */
1197 hswep_uncore_cpu_init();
1198 break;
1194 default: 1199 default:
1195 return 0; 1200 return 0;
1196 } 1201 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index 1d7e89416018..18eb78bbdd10 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -332,6 +332,8 @@ int snbep_uncore_pci_init(void);
332void snbep_uncore_cpu_init(void); 332void snbep_uncore_cpu_init(void);
333int ivbep_uncore_pci_init(void); 333int ivbep_uncore_pci_init(void);
334void ivbep_uncore_cpu_init(void); 334void ivbep_uncore_cpu_init(void);
335int hswep_uncore_pci_init(void);
336void hswep_uncore_cpu_init(void);
335 337
336/* perf_event_intel_uncore_nhmex.c */ 338/* perf_event_intel_uncore_nhmex.c */
337void nhmex_uncore_cpu_init(void); 339void nhmex_uncore_cpu_init(void);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index 6606ed05d311..a4fe9fa0e29a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -163,6 +163,53 @@
163#define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \ 163#define __BITS_VALUE(x, i, n) ((typeof(x))(((x) >> ((i) * (n))) & \
164 ((1ULL << (n)) - 1))) 164 ((1ULL << (n)) - 1)))
165 165
166/* Haswell-EP Ubox */
167#define HSWEP_U_MSR_PMON_CTR0 0x705
168#define HSWEP_U_MSR_PMON_CTL0 0x709
169#define HSWEP_U_MSR_PMON_FILTER 0x707
170
171#define HSWEP_U_MSR_PMON_UCLK_FIXED_CTL 0x703
172#define HSWEP_U_MSR_PMON_UCLK_FIXED_CTR 0x704
173
174#define HSWEP_U_MSR_PMON_BOX_FILTER_TID (0x1 << 0)
175#define HSWEP_U_MSR_PMON_BOX_FILTER_CID (0x1fULL << 1)
176#define HSWEP_U_MSR_PMON_BOX_FILTER_MASK \
177 (HSWEP_U_MSR_PMON_BOX_FILTER_TID | \
178 HSWEP_U_MSR_PMON_BOX_FILTER_CID)
179
180/* Haswell-EP CBo */
181#define HSWEP_C0_MSR_PMON_CTR0 0xe08
182#define HSWEP_C0_MSR_PMON_CTL0 0xe01
183#define HSWEP_C0_MSR_PMON_BOX_CTL 0xe00
184#define HSWEP_C0_MSR_PMON_BOX_FILTER0 0xe05
185#define HSWEP_CBO_MSR_OFFSET 0x10
186
187
188#define HSWEP_CB0_MSR_PMON_BOX_FILTER_TID (0x3fULL << 0)
189#define HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK (0xfULL << 6)
190#define HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE (0x7fULL << 17)
191#define HSWEP_CB0_MSR_PMON_BOX_FILTER_NID (0xffffULL << 32)
192#define HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC (0x1ffULL << 52)
193#define HSWEP_CB0_MSR_PMON_BOX_FILTER_C6 (0x1ULL << 61)
194#define HSWEP_CB0_MSR_PMON_BOX_FILTER_NC (0x1ULL << 62)
195#define HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC (0x1ULL << 63)
196
197
198/* Haswell-EP Sbox */
199#define HSWEP_S0_MSR_PMON_CTR0 0x726
200#define HSWEP_S0_MSR_PMON_CTL0 0x721
201#define HSWEP_S0_MSR_PMON_BOX_CTL 0x720
202#define HSWEP_SBOX_MSR_OFFSET 0xa
203#define HSWEP_S_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
204 SNBEP_CBO_PMON_CTL_TID_EN)
205
206/* Haswell-EP PCU */
207#define HSWEP_PCU_MSR_PMON_CTR0 0x717
208#define HSWEP_PCU_MSR_PMON_CTL0 0x711
209#define HSWEP_PCU_MSR_PMON_BOX_CTL 0x710
210#define HSWEP_PCU_MSR_PMON_BOX_FILTER 0x715
211
212
166DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); 213DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
167DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21"); 214DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
168DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); 215DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
@@ -175,13 +222,21 @@ DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
175DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); 222DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
176DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); 223DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
177DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4"); 224DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
225DEFINE_UNCORE_FORMAT_ATTR(filter_tid2, filter_tid, "config1:0");
226DEFINE_UNCORE_FORMAT_ATTR(filter_tid3, filter_tid, "config1:0-5");
227DEFINE_UNCORE_FORMAT_ATTR(filter_cid, filter_cid, "config1:5");
178DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8"); 228DEFINE_UNCORE_FORMAT_ATTR(filter_link, filter_link, "config1:5-8");
229DEFINE_UNCORE_FORMAT_ATTR(filter_link2, filter_link, "config1:6-8");
179DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17"); 230DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
180DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47"); 231DEFINE_UNCORE_FORMAT_ATTR(filter_nid2, filter_nid, "config1:32-47");
181DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22"); 232DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
182DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22"); 233DEFINE_UNCORE_FORMAT_ATTR(filter_state2, filter_state, "config1:17-22");
234DEFINE_UNCORE_FORMAT_ATTR(filter_state3, filter_state, "config1:17-23");
183DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31"); 235DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
184DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60"); 236DEFINE_UNCORE_FORMAT_ATTR(filter_opc2, filter_opc, "config1:52-60");
237DEFINE_UNCORE_FORMAT_ATTR(filter_nc, filter_nc, "config1:62");
238DEFINE_UNCORE_FORMAT_ATTR(filter_c6, filter_c6, "config1:61");
239DEFINE_UNCORE_FORMAT_ATTR(filter_isoc, filter_isoc, "config1:63");
185DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7"); 240DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
186DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15"); 241DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
187DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23"); 242DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
@@ -857,7 +912,6 @@ static void snbep_qpi_enable_event(struct intel_uncore_box *box, struct perf_eve
857 if (reg1->idx != EXTRA_REG_NONE) { 912 if (reg1->idx != EXTRA_REG_NONE) {
858 int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER; 913 int idx = box->pmu->pmu_idx + SNBEP_PCI_QPI_PORT0_FILTER;
859 struct pci_dev *filter_pdev = uncore_extra_pci_dev[box->phys_id][idx]; 914 struct pci_dev *filter_pdev = uncore_extra_pci_dev[box->phys_id][idx];
860 WARN_ON_ONCE(!filter_pdev);
861 if (filter_pdev) { 915 if (filter_pdev) {
862 pci_write_config_dword(filter_pdev, reg1->reg, 916 pci_write_config_dword(filter_pdev, reg1->reg,
863 (u32)reg1->config); 917 (u32)reg1->config);
@@ -1643,3 +1697,555 @@ int ivbep_uncore_pci_init(void)
1643 return 0; 1697 return 0;
1644} 1698}
1645/* end of IvyTown uncore support */ 1699/* end of IvyTown uncore support */
1700
1701/* Haswell-EP uncore support */
1702static struct attribute *hswep_uncore_ubox_formats_attr[] = {
1703 &format_attr_event.attr,
1704 &format_attr_umask.attr,
1705 &format_attr_edge.attr,
1706 &format_attr_inv.attr,
1707 &format_attr_thresh5.attr,
1708 &format_attr_filter_tid2.attr,
1709 &format_attr_filter_cid.attr,
1710 NULL,
1711};
1712
1713static struct attribute_group hswep_uncore_ubox_format_group = {
1714 .name = "format",
1715 .attrs = hswep_uncore_ubox_formats_attr,
1716};
1717
1718static int hswep_ubox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1719{
1720 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1721 reg1->reg = HSWEP_U_MSR_PMON_FILTER;
1722 reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK;
1723 reg1->idx = 0;
1724 return 0;
1725}
1726
1727static struct intel_uncore_ops hswep_uncore_ubox_ops = {
1728 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1729 .hw_config = hswep_ubox_hw_config,
1730 .get_constraint = uncore_get_constraint,
1731 .put_constraint = uncore_put_constraint,
1732};
1733
1734static struct intel_uncore_type hswep_uncore_ubox = {
1735 .name = "ubox",
1736 .num_counters = 2,
1737 .num_boxes = 1,
1738 .perf_ctr_bits = 44,
1739 .fixed_ctr_bits = 48,
1740 .perf_ctr = HSWEP_U_MSR_PMON_CTR0,
1741 .event_ctl = HSWEP_U_MSR_PMON_CTL0,
1742 .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
1743 .fixed_ctr = HSWEP_U_MSR_PMON_UCLK_FIXED_CTR,
1744 .fixed_ctl = HSWEP_U_MSR_PMON_UCLK_FIXED_CTL,
1745 .num_shared_regs = 1,
1746 .ops = &hswep_uncore_ubox_ops,
1747 .format_group = &hswep_uncore_ubox_format_group,
1748};
1749
1750static struct attribute *hswep_uncore_cbox_formats_attr[] = {
1751 &format_attr_event.attr,
1752 &format_attr_umask.attr,
1753 &format_attr_edge.attr,
1754 &format_attr_tid_en.attr,
1755 &format_attr_thresh8.attr,
1756 &format_attr_filter_tid3.attr,
1757 &format_attr_filter_link2.attr,
1758 &format_attr_filter_state3.attr,
1759 &format_attr_filter_nid2.attr,
1760 &format_attr_filter_opc2.attr,
1761 &format_attr_filter_nc.attr,
1762 &format_attr_filter_c6.attr,
1763 &format_attr_filter_isoc.attr,
1764 NULL,
1765};
1766
1767static struct attribute_group hswep_uncore_cbox_format_group = {
1768 .name = "format",
1769 .attrs = hswep_uncore_cbox_formats_attr,
1770};
1771
1772static struct event_constraint hswep_uncore_cbox_constraints[] = {
1773 UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
1774 UNCORE_EVENT_CONSTRAINT(0x09, 0x1),
1775 UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
1776 UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
1777 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
1778 UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
1779 UNCORE_EVENT_CONSTRAINT(0x3e, 0x1),
1780 EVENT_CONSTRAINT_END
1781};
1782
1783static struct extra_reg hswep_uncore_cbox_extra_regs[] = {
1784 SNBEP_CBO_EVENT_EXTRA_REG(SNBEP_CBO_PMON_CTL_TID_EN,
1785 SNBEP_CBO_PMON_CTL_TID_EN, 0x1),
1786 SNBEP_CBO_EVENT_EXTRA_REG(0x0334, 0xffff, 0x4),
1787 SNBEP_CBO_EVENT_EXTRA_REG(0x0534, 0xffff, 0x4),
1788 SNBEP_CBO_EVENT_EXTRA_REG(0x0934, 0xffff, 0x4),
1789 SNBEP_CBO_EVENT_EXTRA_REG(0x1134, 0xffff, 0x4),
1790 SNBEP_CBO_EVENT_EXTRA_REG(0x2134, 0xffff, 0x4),
1791 SNBEP_CBO_EVENT_EXTRA_REG(0x4134, 0xffff, 0x4),
1792 SNBEP_CBO_EVENT_EXTRA_REG(0x4037, 0x40ff, 0x8),
1793 SNBEP_CBO_EVENT_EXTRA_REG(0x4028, 0x40ff, 0x8),
1794 SNBEP_CBO_EVENT_EXTRA_REG(0x4032, 0x40ff, 0x8),
1795 SNBEP_CBO_EVENT_EXTRA_REG(0x4029, 0x40ff, 0x8),
1796 SNBEP_CBO_EVENT_EXTRA_REG(0x4033, 0x40ff, 0x8),
1797 SNBEP_CBO_EVENT_EXTRA_REG(0x402A, 0x40ff, 0x8),
1798 SNBEP_CBO_EVENT_EXTRA_REG(0x0135, 0xffff, 0x12),
1799 SNBEP_CBO_EVENT_EXTRA_REG(0x0335, 0xffff, 0x10),
1800 SNBEP_CBO_EVENT_EXTRA_REG(0x4135, 0xffff, 0x18),
1801 SNBEP_CBO_EVENT_EXTRA_REG(0x4435, 0xffff, 0x8),
1802 SNBEP_CBO_EVENT_EXTRA_REG(0x4835, 0xffff, 0x8),
1803 SNBEP_CBO_EVENT_EXTRA_REG(0x5035, 0xffff, 0x8),
1804 SNBEP_CBO_EVENT_EXTRA_REG(0x4335, 0xffff, 0x18),
1805 SNBEP_CBO_EVENT_EXTRA_REG(0x4a35, 0xffff, 0x8),
1806 SNBEP_CBO_EVENT_EXTRA_REG(0x2335, 0xffff, 0x10),
1807 SNBEP_CBO_EVENT_EXTRA_REG(0x8335, 0xffff, 0x10),
1808 SNBEP_CBO_EVENT_EXTRA_REG(0x2135, 0xffff, 0x10),
1809 SNBEP_CBO_EVENT_EXTRA_REG(0x8135, 0xffff, 0x10),
1810 SNBEP_CBO_EVENT_EXTRA_REG(0x0136, 0xffff, 0x10),
1811 SNBEP_CBO_EVENT_EXTRA_REG(0x0336, 0xffff, 0x10),
1812 SNBEP_CBO_EVENT_EXTRA_REG(0x4136, 0xffff, 0x18),
1813 SNBEP_CBO_EVENT_EXTRA_REG(0x4436, 0xffff, 0x8),
1814 SNBEP_CBO_EVENT_EXTRA_REG(0x4836, 0xffff, 0x8),
1815 SNBEP_CBO_EVENT_EXTRA_REG(0x4336, 0xffff, 0x18),
1816 SNBEP_CBO_EVENT_EXTRA_REG(0x4a36, 0xffff, 0x8),
1817 SNBEP_CBO_EVENT_EXTRA_REG(0x2336, 0xffff, 0x10),
1818 SNBEP_CBO_EVENT_EXTRA_REG(0x8336, 0xffff, 0x10),
1819 SNBEP_CBO_EVENT_EXTRA_REG(0x2136, 0xffff, 0x10),
1820 SNBEP_CBO_EVENT_EXTRA_REG(0x8136, 0xffff, 0x10),
1821 SNBEP_CBO_EVENT_EXTRA_REG(0x5036, 0xffff, 0x8),
1822 EVENT_EXTRA_END
1823};
1824
1825static u64 hswep_cbox_filter_mask(int fields)
1826{
1827 u64 mask = 0;
1828 if (fields & 0x1)
1829 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_TID;
1830 if (fields & 0x2)
1831 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_LINK;
1832 if (fields & 0x4)
1833 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_STATE;
1834 if (fields & 0x8)
1835 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NID;
1836 if (fields & 0x10) {
1837 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_OPC;
1838 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_NC;
1839 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_C6;
1840 mask |= HSWEP_CB0_MSR_PMON_BOX_FILTER_ISOC;
1841 }
1842 return mask;
1843}
1844
1845static struct event_constraint *
1846hswep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
1847{
1848 return __snbep_cbox_get_constraint(box, event, hswep_cbox_filter_mask);
1849}
1850
1851static int hswep_cbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1852{
1853 struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
1854 struct extra_reg *er;
1855 int idx = 0;
1856
1857 for (er = hswep_uncore_cbox_extra_regs; er->msr; er++) {
1858 if (er->event != (event->hw.config & er->config_mask))
1859 continue;
1860 idx |= er->idx;
1861 }
1862
1863 if (idx) {
1864 reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 +
1865 HSWEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
1866 reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx);
1867 reg1->idx = idx;
1868 }
1869 return 0;
1870}
1871
1872static void hswep_cbox_enable_event(struct intel_uncore_box *box,
1873 struct perf_event *event)
1874{
1875 struct hw_perf_event *hwc = &event->hw;
1876 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1877
1878 if (reg1->idx != EXTRA_REG_NONE) {
1879 u64 filter = uncore_shared_reg_config(box, 0);
1880 wrmsrl(reg1->reg, filter & 0xffffffff);
1881 wrmsrl(reg1->reg + 1, filter >> 32);
1882 }
1883
1884 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
1885}
1886
1887static struct intel_uncore_ops hswep_uncore_cbox_ops = {
1888 .init_box = snbep_uncore_msr_init_box,
1889 .disable_box = snbep_uncore_msr_disable_box,
1890 .enable_box = snbep_uncore_msr_enable_box,
1891 .disable_event = snbep_uncore_msr_disable_event,
1892 .enable_event = hswep_cbox_enable_event,
1893 .read_counter = uncore_msr_read_counter,
1894 .hw_config = hswep_cbox_hw_config,
1895 .get_constraint = hswep_cbox_get_constraint,
1896 .put_constraint = snbep_cbox_put_constraint,
1897};
1898
1899static struct intel_uncore_type hswep_uncore_cbox = {
1900 .name = "cbox",
1901 .num_counters = 4,
1902 .num_boxes = 18,
1903 .perf_ctr_bits = 44,
1904 .event_ctl = HSWEP_C0_MSR_PMON_CTL0,
1905 .perf_ctr = HSWEP_C0_MSR_PMON_CTR0,
1906 .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
1907 .box_ctl = HSWEP_C0_MSR_PMON_BOX_CTL,
1908 .msr_offset = HSWEP_CBO_MSR_OFFSET,
1909 .num_shared_regs = 1,
1910 .constraints = hswep_uncore_cbox_constraints,
1911 .ops = &hswep_uncore_cbox_ops,
1912 .format_group = &hswep_uncore_cbox_format_group,
1913};
1914
1915static struct attribute *hswep_uncore_sbox_formats_attr[] = {
1916 &format_attr_event.attr,
1917 &format_attr_umask.attr,
1918 &format_attr_edge.attr,
1919 &format_attr_tid_en.attr,
1920 &format_attr_inv.attr,
1921 &format_attr_thresh8.attr,
1922 NULL,
1923};
1924
1925static struct attribute_group hswep_uncore_sbox_format_group = {
1926 .name = "format",
1927 .attrs = hswep_uncore_sbox_formats_attr,
1928};
1929
1930static struct intel_uncore_type hswep_uncore_sbox = {
1931 .name = "sbox",
1932 .num_counters = 4,
1933 .num_boxes = 4,
1934 .perf_ctr_bits = 44,
1935 .event_ctl = HSWEP_S0_MSR_PMON_CTL0,
1936 .perf_ctr = HSWEP_S0_MSR_PMON_CTR0,
1937 .event_mask = HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
1938 .box_ctl = HSWEP_S0_MSR_PMON_BOX_CTL,
1939 .msr_offset = HSWEP_SBOX_MSR_OFFSET,
1940 .ops = &snbep_uncore_msr_ops,
1941 .format_group = &hswep_uncore_sbox_format_group,
1942};
1943
1944static int hswep_pcu_hw_config(struct intel_uncore_box *box, struct perf_event *event)
1945{
1946 struct hw_perf_event *hwc = &event->hw;
1947 struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
1948 int ev_sel = hwc->config & SNBEP_PMON_CTL_EV_SEL_MASK;
1949
1950 if (ev_sel >= 0xb && ev_sel <= 0xe) {
1951 reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER;
1952 reg1->idx = ev_sel - 0xb;
1953 reg1->config = event->attr.config1 & (0xff << reg1->idx);
1954 }
1955 return 0;
1956}
1957
1958static struct intel_uncore_ops hswep_uncore_pcu_ops = {
1959 SNBEP_UNCORE_MSR_OPS_COMMON_INIT(),
1960 .hw_config = hswep_pcu_hw_config,
1961 .get_constraint = snbep_pcu_get_constraint,
1962 .put_constraint = snbep_pcu_put_constraint,
1963};
1964
1965static struct intel_uncore_type hswep_uncore_pcu = {
1966 .name = "pcu",
1967 .num_counters = 4,
1968 .num_boxes = 1,
1969 .perf_ctr_bits = 48,
1970 .perf_ctr = HSWEP_PCU_MSR_PMON_CTR0,
1971 .event_ctl = HSWEP_PCU_MSR_PMON_CTL0,
1972 .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
1973 .box_ctl = HSWEP_PCU_MSR_PMON_BOX_CTL,
1974 .num_shared_regs = 1,
1975 .ops = &hswep_uncore_pcu_ops,
1976 .format_group = &snbep_uncore_pcu_format_group,
1977};
1978
1979static struct intel_uncore_type *hswep_msr_uncores[] = {
1980 &hswep_uncore_ubox,
1981 &hswep_uncore_cbox,
1982 &hswep_uncore_sbox,
1983 &hswep_uncore_pcu,
1984 NULL,
1985};
1986
1987void hswep_uncore_cpu_init(void)
1988{
1989 if (hswep_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
1990 hswep_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
1991 uncore_msr_uncores = hswep_msr_uncores;
1992}
1993
1994static struct intel_uncore_type hswep_uncore_ha = {
1995 .name = "ha",
1996 .num_counters = 5,
1997 .num_boxes = 2,
1998 .perf_ctr_bits = 48,
1999 SNBEP_UNCORE_PCI_COMMON_INIT(),
2000};
2001
2002static struct uncore_event_desc hswep_uncore_imc_events[] = {
2003 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x00,umask=0x00"),
2004 INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
2005 INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
2006 { /* end: all zeroes */ },
2007};
2008
2009static struct intel_uncore_type hswep_uncore_imc = {
2010 .name = "imc",
2011 .num_counters = 5,
2012 .num_boxes = 8,
2013 .perf_ctr_bits = 48,
2014 .fixed_ctr_bits = 48,
2015 .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
2016 .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
2017 .event_descs = hswep_uncore_imc_events,
2018 SNBEP_UNCORE_PCI_COMMON_INIT(),
2019};
2020
2021static struct intel_uncore_ops hswep_uncore_irp_ops = {
2022 .init_box = snbep_uncore_pci_init_box,
2023 .disable_box = snbep_uncore_pci_disable_box,
2024 .enable_box = snbep_uncore_pci_enable_box,
2025 .disable_event = ivbep_uncore_irp_disable_event,
2026 .enable_event = ivbep_uncore_irp_enable_event,
2027 .read_counter = ivbep_uncore_irp_read_counter,
2028};
2029
2030static struct intel_uncore_type hswep_uncore_irp = {
2031 .name = "irp",
2032 .num_counters = 4,
2033 .num_boxes = 1,
2034 .perf_ctr_bits = 48,
2035 .event_mask = SNBEP_PMON_RAW_EVENT_MASK,
2036 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2037 .ops = &hswep_uncore_irp_ops,
2038 .format_group = &snbep_uncore_format_group,
2039};
2040
2041static struct intel_uncore_type hswep_uncore_qpi = {
2042 .name = "qpi",
2043 .num_counters = 5,
2044 .num_boxes = 3,
2045 .perf_ctr_bits = 48,
2046 .perf_ctr = SNBEP_PCI_PMON_CTR0,
2047 .event_ctl = SNBEP_PCI_PMON_CTL0,
2048 .event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
2049 .box_ctl = SNBEP_PCI_PMON_BOX_CTL,
2050 .num_shared_regs = 1,
2051 .ops = &snbep_uncore_qpi_ops,
2052 .format_group = &snbep_uncore_qpi_format_group,
2053};
2054
2055static struct event_constraint hswep_uncore_r2pcie_constraints[] = {
2056 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
2057 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2058 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
2059 UNCORE_EVENT_CONSTRAINT(0x23, 0x1),
2060 UNCORE_EVENT_CONSTRAINT(0x24, 0x1),
2061 UNCORE_EVENT_CONSTRAINT(0x25, 0x1),
2062 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
2063 UNCORE_EVENT_CONSTRAINT(0x27, 0x1),
2064 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
2065 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
2066 UNCORE_EVENT_CONSTRAINT(0x2a, 0x1),
2067 UNCORE_EVENT_CONSTRAINT(0x2b, 0x3),
2068 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
2069 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
2070 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
2071 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
2072 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
2073 UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
2074 EVENT_CONSTRAINT_END
2075};
2076
2077static struct intel_uncore_type hswep_uncore_r2pcie = {
2078 .name = "r2pcie",
2079 .num_counters = 4,
2080 .num_boxes = 1,
2081 .perf_ctr_bits = 48,
2082 .constraints = hswep_uncore_r2pcie_constraints,
2083 SNBEP_UNCORE_PCI_COMMON_INIT(),
2084};
2085
2086static struct event_constraint hswep_uncore_r3qpi_constraints[] = {
2087 UNCORE_EVENT_CONSTRAINT(0x01, 0x3),
2088 UNCORE_EVENT_CONSTRAINT(0x07, 0x7),
2089 UNCORE_EVENT_CONSTRAINT(0x08, 0x7),
2090 UNCORE_EVENT_CONSTRAINT(0x09, 0x7),
2091 UNCORE_EVENT_CONSTRAINT(0x0a, 0x7),
2092 UNCORE_EVENT_CONSTRAINT(0x0e, 0x7),
2093 UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
2094 UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
2095 UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
2096 UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
2097 UNCORE_EVENT_CONSTRAINT(0x14, 0x3),
2098 UNCORE_EVENT_CONSTRAINT(0x15, 0x3),
2099 UNCORE_EVENT_CONSTRAINT(0x1f, 0x3),
2100 UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
2101 UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
2102 UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
2103 UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
2104 UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
2105 UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
2106 UNCORE_EVENT_CONSTRAINT(0x28, 0x3),
2107 UNCORE_EVENT_CONSTRAINT(0x29, 0x3),
2108 UNCORE_EVENT_CONSTRAINT(0x2c, 0x3),
2109 UNCORE_EVENT_CONSTRAINT(0x2d, 0x3),
2110 UNCORE_EVENT_CONSTRAINT(0x2e, 0x3),
2111 UNCORE_EVENT_CONSTRAINT(0x2f, 0x3),
2112 UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
2113 UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
2114 UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
2115 UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
2116 UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
2117 UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
2118 UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
2119 UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
2120 EVENT_CONSTRAINT_END
2121};
2122
2123static struct intel_uncore_type hswep_uncore_r3qpi = {
2124 .name = "r3qpi",
2125 .num_counters = 4,
2126 .num_boxes = 3,
2127 .perf_ctr_bits = 44,
2128 .constraints = hswep_uncore_r3qpi_constraints,
2129 SNBEP_UNCORE_PCI_COMMON_INIT(),
2130};
2131
2132enum {
2133 HSWEP_PCI_UNCORE_HA,
2134 HSWEP_PCI_UNCORE_IMC,
2135 HSWEP_PCI_UNCORE_IRP,
2136 HSWEP_PCI_UNCORE_QPI,
2137 HSWEP_PCI_UNCORE_R2PCIE,
2138 HSWEP_PCI_UNCORE_R3QPI,
2139};
2140
2141static struct intel_uncore_type *hswep_pci_uncores[] = {
2142 [HSWEP_PCI_UNCORE_HA] = &hswep_uncore_ha,
2143 [HSWEP_PCI_UNCORE_IMC] = &hswep_uncore_imc,
2144 [HSWEP_PCI_UNCORE_IRP] = &hswep_uncore_irp,
2145 [HSWEP_PCI_UNCORE_QPI] = &hswep_uncore_qpi,
2146 [HSWEP_PCI_UNCORE_R2PCIE] = &hswep_uncore_r2pcie,
2147 [HSWEP_PCI_UNCORE_R3QPI] = &hswep_uncore_r3qpi,
2148 NULL,
2149};
2150
2151static DEFINE_PCI_DEVICE_TABLE(hswep_uncore_pci_ids) = {
2152 { /* Home Agent 0 */
2153 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f30),
2154 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 0),
2155 },
2156 { /* Home Agent 1 */
2157 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f38),
2158 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_HA, 1),
2159 },
2160 { /* MC0 Channel 0 */
2161 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb0),
2162 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 0),
2163 },
2164 { /* MC0 Channel 1 */
2165 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb1),
2166 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 1),
2167 },
2168 { /* MC0 Channel 2 */
2169 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb4),
2170 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 2),
2171 },
2172 { /* MC0 Channel 3 */
2173 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fb5),
2174 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 3),
2175 },
2176 { /* MC1 Channel 0 */
2177 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd0),
2178 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 4),
2179 },
2180 { /* MC1 Channel 1 */
2181 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd1),
2182 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 5),
2183 },
2184 { /* MC1 Channel 2 */
2185 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd4),
2186 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 6),
2187 },
2188 { /* MC1 Channel 3 */
2189 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2fd5),
2190 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IMC, 7),
2191 },
2192 { /* IRP */
2193 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f39),
2194 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_IRP, 0),
2195 },
2196 { /* QPI0 Port 0 */
2197 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f32),
2198 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 0),
2199 },
2200 { /* QPI0 Port 1 */
2201 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f33),
2202 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 1),
2203 },
2204 { /* QPI1 Port 2 */
2205 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3a),
2206 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_QPI, 2),
2207 },
2208 { /* R2PCIe */
2209 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f34),
2210 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R2PCIE, 0),
2211 },
2212 { /* R3QPI0 Link 0 */
2213 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f36),
2214 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 0),
2215 },
2216 { /* R3QPI0 Link 1 */
2217 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f37),
2218 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 1),
2219 },
2220 { /* R3QPI1 Link 2 */
2221 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f3e),
2222 .driver_data = UNCORE_PCI_DEV_DATA(HSWEP_PCI_UNCORE_R3QPI, 2),
2223 },
2224 { /* QPI Port 0 filter */
2225 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f86),
2226 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2227 SNBEP_PCI_QPI_PORT0_FILTER),
2228 },
2229 { /* QPI Port 1 filter */
2230 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x2f96),
2231 .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
2232 SNBEP_PCI_QPI_PORT1_FILTER),
2233 },
2234 { /* end: all zeroes */ }
2235};
2236
2237static struct pci_driver hswep_uncore_pci_driver = {
2238 .name = "hswep_uncore",
2239 .id_table = hswep_uncore_pci_ids,
2240};
2241
2242int hswep_uncore_pci_init(void)
2243{
2244 int ret = snbep_pci2phy_map_init(0x2f1e);
2245 if (ret)
2246 return ret;
2247 uncore_pci_uncores = hswep_pci_uncores;
2248 uncore_pci_driver = &hswep_uncore_pci_driver;
2249 return 0;
2250}
2251/* end of Haswell-EP uncore support */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 16:47:24 -0400