diff options
| author | Feng Kan <fkan@apm.com> | 2014-07-30 17:56:58 -0400 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2014-08-19 11:07:46 -0400 |
| commit | e5f81539f657af7e9f54ea37986fde8f92acef22 (patch) | |
| tree | 1e48f8a6807a0b8a301930fb57bede3baf4532fa | |
| parent | 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9 (diff) | |
irqchip: gic: Replace hex numbers with defines.
This is to cleanup some hex numbers used in the code and replace
them with defines to make the code cleaner.
Signed-off-by: Feng Kan <fkan@apm.com>
Reviewed-by: Anup Patel <apatel@apm.com>
Link: https://lkml.kernel.org/r/1406757419-18729-2-git-send-email-fkan@apm.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| -rw-r--r-- | drivers/irqchip/irq-gic-common.c | 15 | ||||
| -rw-r--r-- | drivers/irqchip/irq-gic.c | 25 | ||||
| -rw-r--r-- | include/linux/irqchip/arm-gic.h | 15 |
3 files changed, 37 insertions, 18 deletions
diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 60ac704d2090..61541ff24397 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c | |||
| @@ -74,20 +74,22 @@ void __init gic_dist_config(void __iomem *base, int gic_irqs, | |||
| 74 | * Set all global interrupts to be level triggered, active low. | 74 | * Set all global interrupts to be level triggered, active low. |
| 75 | */ | 75 | */ |
| 76 | for (i = 32; i < gic_irqs; i += 16) | 76 | for (i = 32; i < gic_irqs; i += 16) |
| 77 | writel_relaxed(0, base + GIC_DIST_CONFIG + i / 4); | 77 | writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, |
| 78 | base + GIC_DIST_CONFIG + i / 4); | ||
| 78 | 79 | ||
| 79 | /* | 80 | /* |
| 80 | * Set priority on all global interrupts. | 81 | * Set priority on all global interrupts. |
| 81 | */ | 82 | */ |
| 82 | for (i = 32; i < gic_irqs; i += 4) | 83 | for (i = 32; i < gic_irqs; i += 4) |
| 83 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i); | 84 | writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); |
| 84 | 85 | ||
| 85 | /* | 86 | /* |
| 86 | * Disable all interrupts. Leave the PPI and SGIs alone | 87 | * Disable all interrupts. Leave the PPI and SGIs alone |
| 87 | * as they are enabled by redistributor registers. | 88 | * as they are enabled by redistributor registers. |
| 88 | */ | 89 | */ |
| 89 | for (i = 32; i < gic_irqs; i += 32) | 90 | for (i = 32; i < gic_irqs; i += 32) |
| 90 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i / 8); | 91 | writel_relaxed(GICD_INT_EN_CLR_X32, |
| 92 | base + GIC_DIST_ENABLE_CLEAR + i / 8); | ||
| 91 | 93 | ||
| 92 | if (sync_access) | 94 | if (sync_access) |
| 93 | sync_access(); | 95 | sync_access(); |
| @@ -101,14 +103,15 @@ void gic_cpu_config(void __iomem *base, void (*sync_access)(void)) | |||
| 101 | * Deal with the banked PPI and SGI interrupts - disable all | 103 | * Deal with the banked PPI and SGI interrupts - disable all |
| 102 | * PPI interrupts, ensure all SGI interrupts are enabled. | 104 | * PPI interrupts, ensure all SGI interrupts are enabled. |
| 103 | */ | 105 | */ |
| 104 | writel_relaxed(0xffff0000, base + GIC_DIST_ENABLE_CLEAR); | 106 | writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR); |
| 105 | writel_relaxed(0x0000ffff, base + GIC_DIST_ENABLE_SET); | 107 | writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); |
| 106 | 108 | ||
| 107 | /* | 109 | /* |
| 108 | * Set priority on PPI and SGI interrupts | 110 | * Set priority on PPI and SGI interrupts |
| 109 | */ | 111 | */ |
| 110 | for (i = 0; i < 32; i += 4) | 112 | for (i = 0; i < 32; i += 4) |
| 111 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); | 113 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
| 114 | base + GIC_DIST_PRI + i * 4 / 4); | ||
| 112 | 115 | ||
| 113 | if (sync_access) | 116 | if (sync_access) |
| 114 | sync_access(); | 117 | sync_access(); |
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 4b959e606fe8..35847453cecb 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c | |||
| @@ -298,8 +298,8 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) | |||
| 298 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); | 298 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
| 299 | raw_spin_unlock(&irq_controller_lock); | 299 | raw_spin_unlock(&irq_controller_lock); |
| 300 | 300 | ||
| 301 | gic_irq = (status & 0x3ff); | 301 | gic_irq = (status & GICC_IAR_INT_ID_MASK); |
| 302 | if (gic_irq == 1023) | 302 | if (gic_irq == GICC_INT_SPURIOUS) |
| 303 | goto out; | 303 | goto out; |
| 304 | 304 | ||
| 305 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); | 305 | cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); |
| @@ -360,7 +360,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) | |||
| 360 | unsigned int gic_irqs = gic->gic_irqs; | 360 | unsigned int gic_irqs = gic->gic_irqs; |
| 361 | void __iomem *base = gic_data_dist_base(gic); | 361 | void __iomem *base = gic_data_dist_base(gic); |
| 362 | 362 | ||
| 363 | writel_relaxed(0, base + GIC_DIST_CTRL); | 363 | writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); |
| 364 | 364 | ||
| 365 | /* | 365 | /* |
| 366 | * Set all global interrupts to this CPU only. | 366 | * Set all global interrupts to this CPU only. |
| @@ -373,7 +373,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic) | |||
| 373 | 373 | ||
| 374 | gic_dist_config(base, gic_irqs, NULL); | 374 | gic_dist_config(base, gic_irqs, NULL); |
| 375 | 375 | ||
| 376 | writel_relaxed(1, base + GIC_DIST_CTRL); | 376 | writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); |
| 377 | } | 377 | } |
| 378 | 378 | ||
| 379 | static void gic_cpu_init(struct gic_chip_data *gic) | 379 | static void gic_cpu_init(struct gic_chip_data *gic) |
| @@ -400,8 +400,8 @@ static void gic_cpu_init(struct gic_chip_data *gic) | |||
| 400 | 400 | ||
| 401 | gic_cpu_config(dist_base, NULL); | 401 | gic_cpu_config(dist_base, NULL); |
| 402 | 402 | ||
| 403 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); | 403 | writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); |
| 404 | writel_relaxed(1, base + GIC_CPU_CTRL); | 404 | writel_relaxed(GICC_ENABLE, base + GIC_CPU_CTRL); |
| 405 | } | 405 | } |
| 406 | 406 | ||
| 407 | void gic_cpu_if_down(void) | 407 | void gic_cpu_if_down(void) |
| @@ -467,14 +467,14 @@ static void gic_dist_restore(unsigned int gic_nr) | |||
| 467 | if (!dist_base) | 467 | if (!dist_base) |
| 468 | return; | 468 | return; |
| 469 | 469 | ||
| 470 | writel_relaxed(0, dist_base + GIC_DIST_CTRL); | 470 | writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); |
| 471 | 471 | ||
| 472 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | 472 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) |
| 473 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | 473 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], |
| 474 | dist_base + GIC_DIST_CONFIG + i * 4); | 474 | dist_base + GIC_DIST_CONFIG + i * 4); |
| 475 | 475 | ||
| 476 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | 476 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| 477 | writel_relaxed(0xa0a0a0a0, | 477 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
| 478 | dist_base + GIC_DIST_PRI + i * 4); | 478 | dist_base + GIC_DIST_PRI + i * 4); |
| 479 | 479 | ||
| 480 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | 480 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) |
| @@ -485,7 +485,7 @@ static void gic_dist_restore(unsigned int gic_nr) | |||
| 485 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | 485 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], |
| 486 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | 486 | dist_base + GIC_DIST_ENABLE_SET + i * 4); |
| 487 | 487 | ||
| 488 | writel_relaxed(1, dist_base + GIC_DIST_CTRL); | 488 | writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); |
| 489 | } | 489 | } |
| 490 | 490 | ||
| 491 | static void gic_cpu_save(unsigned int gic_nr) | 491 | static void gic_cpu_save(unsigned int gic_nr) |
| @@ -539,10 +539,11 @@ static void gic_cpu_restore(unsigned int gic_nr) | |||
| 539 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | 539 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); |
| 540 | 540 | ||
| 541 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | 541 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) |
| 542 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); | 542 | writel_relaxed(GICD_INT_DEF_PRI_X4, |
| 543 | dist_base + GIC_DIST_PRI + i * 4); | ||
| 543 | 544 | ||
| 544 | writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); | 545 | writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); |
| 545 | writel_relaxed(1, cpu_base + GIC_CPU_CTRL); | 546 | writel_relaxed(GICC_ENABLE, cpu_base + GIC_CPU_CTRL); |
| 546 | } | 547 | } |
| 547 | 548 | ||
| 548 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | 549 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) |
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h index 45e2d8c15bd2..5cb9d41af5be 100644 --- a/include/linux/irqchip/arm-gic.h +++ b/include/linux/irqchip/arm-gic.h | |||
| @@ -21,7 +21,10 @@ | |||
| 21 | #define GIC_CPU_ACTIVEPRIO 0xd0 | 21 | #define GIC_CPU_ACTIVEPRIO 0xd0 |
| 22 | #define GIC_CPU_IDENT 0xfc | 22 | #define GIC_CPU_IDENT 0xfc |
| 23 | 23 | ||
| 24 | #define GICC_ENABLE 0x1 | ||
| 25 | #define GICC_INT_PRI_THRESHOLD 0xf0 | ||
| 24 | #define GICC_IAR_INT_ID_MASK 0x3ff | 26 | #define GICC_IAR_INT_ID_MASK 0x3ff |
| 27 | #define GICC_INT_SPURIOUS 1023 | ||
| 25 | 28 | ||
| 26 | #define GIC_DIST_CTRL 0x000 | 29 | #define GIC_DIST_CTRL 0x000 |
| 27 | #define GIC_DIST_CTR 0x004 | 30 | #define GIC_DIST_CTR 0x004 |
| @@ -39,6 +42,18 @@ | |||
| 39 | #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 | 42 | #define GIC_DIST_SGI_PENDING_CLEAR 0xf10 |
| 40 | #define GIC_DIST_SGI_PENDING_SET 0xf20 | 43 | #define GIC_DIST_SGI_PENDING_SET 0xf20 |
| 41 | 44 | ||
| 45 | #define GICD_ENABLE 0x1 | ||
| 46 | #define GICD_DISABLE 0x0 | ||
| 47 | #define GICD_INT_ACTLOW_LVLTRIG 0x0 | ||
| 48 | #define GICD_INT_EN_CLR_X32 0xffffffff | ||
| 49 | #define GICD_INT_EN_SET_SGI 0x0000ffff | ||
| 50 | #define G | ||
