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authorMagnus Damm <damm@opensource.se>2010-02-08 22:36:03 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-02-09 04:01:46 -0500
commite4e430c611db75f58d3ca33869e182a530859426 (patch)
treecab56f54b4f8b8f1392b83d38ece53484b60996b
parent6673be73809c8aa1ca5255c83f4fc85c43fdbfab (diff)
ARM: mach-shmobile: sh7372 INTCA support
Add support for the sh7372 INTCA hardware block. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat
-rw-r--r--arch/arm/mach-shmobile/Makefile2
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c367
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c42
3 files changed, 368 insertions, 43 deletions
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 7864f6299af7..89ea4b0ea52d 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -8,7 +8,7 @@ obj-y := timer.o console.o
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o 9obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o 10obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7367.o intc-sh7377.o
11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7367.o intc-sh7372.o
12 12
13# Board objects 13# Board objects
14obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o 14obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
new file mode 100644
index 000000000000..c6e747f92462
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -0,0 +1,367 @@
1/*
2 * sh7372 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24#include <linux/sh_intc.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27
28enum {
29 UNUSED_INTCA = 0,
30
31 /* interrupt sources INTCA */
32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
33 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
34 IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
35 IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
36 DIRC,
37 CRYPT_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
39 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
40 MFI_MFIM, MFI_MFIS,
41 BBIF1, BBIF2,
42 USBHSDMAC_USHDMI,
43 USBHS_USHI0, USBHS_USHI1,
44 _3DG_SGX540,
45 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
46 KEYSC_KEY,
47 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
48 MSIOF2, MSIOF1,
49 SCIFA4, SCIFA5, SCIFB,
50 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
51 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
52 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
53 IRREM,
54 IRDA,
55 TPU0,
56 TTI20,
57 DDM,
58 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
59 RWDT0,
60 DMAC_1_DEI0, DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3,
61 DMAC_2_DEI4, DMAC_2_DEI5, DMAC_2_DADERR,
62 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
63 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
64 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
65 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
66 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
67 HDMI,
68 SPU2_SPU0, SPU2_SPU1,
69 FSI, FMSI,
70 MIPI_HSI,
71 IPMMU_IPMMUD,
72 CEC_CEC_1, CEC_CEC_2,
73 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
74 MFIS2,
75 CPORTR2S,
76 CMT14, CMT15,
77 MMC_MMC_ERR, MMC_MMC_NOR,
78 IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
79 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
80 USB0_USB0I1, USB0_USB0I0,
81 USB1_USB1I1, USB1_USB1I0,
82 USHSDMI,
83
84 /* interrupt groups INTCA */
85 DMAC_1, DMAC_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
86 AP_ARM1, AP_ARM2, USBHS, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
87};
88
89static struct intc_vect intca_vectors[] = {
90 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
91 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
92 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
93 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
94 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
95 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
96 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
97 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
98 INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
99 INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
100 INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
101 INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
102 INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
103 INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
104 INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
105 INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
106 INTC_VECT(DIRC, 0x0560),
107 INTC_VECT(CRYPT_STD, 0x0700),
108 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
109 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
110 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
111 INTC_VECT(AP_ARM_COMMRX, 0x0860),
112 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
113 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
114 INTC_VECT(USBHSDMAC_USHDMI, 0x0a00),
115 INTC_VECT(USBHS_USHI0, 0x0a20), INTC_VECT(USBHS_USHI1, 0x0a40),
116 INTC_VECT(_3DG_SGX540, 0x0a60),
117 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
118 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
119 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
120 INTC_VECT(KEYSC_KEY, 0x0be0),
121 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
122 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
123 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
124 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
125 INTC_VECT(SCIFB, 0x0d60),
126 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
127 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
128 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
129 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
130 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
131 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
132 INTC_VECT(IRREM, 0x0f60),
133 INTC_VECT(IRDA, 0x0480),
134 INTC_VECT(TPU0, 0x04a0),
135 INTC_VECT(TTI20, 0x1100),
136 INTC_VECT(DDM, 0x1140),
137 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
138 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
139 INTC_VECT(RWDT0, 0x1280),
140 INTC_VECT(DMAC_1_DEI0, 0x2000), INTC_VECT(DMAC_1_DEI1, 0x2020),
141 INTC_VECT(DMAC_1_DEI2, 0x2040), INTC_VECT(DMAC_1_DEI3, 0x2060),
142 INTC_VECT(DMAC_2_DEI4, 0x2080), INTC_VECT(DMAC_2_DEI5, 0x20a0),
143 INTC_VECT(DMAC_2_DADERR, 0x20c0),
144 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
145 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
146 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
147 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
148 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
149 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
150 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
151 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
152 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1d20),
153 INTC_VECT(SHWYSTAT_COM, 0x1340),
154 INTC_VECT(HDMI, 0x17e0),
155 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
156 INTC_VECT(FSI, 0x1840),
157 INTC_VECT(FMSI, 0x1860),
158 INTC_VECT(MIPI_HSI, 0x18e0),
159 INTC_VECT(IPMMU_IPMMUD, 0x1920),
160 INTC_VECT(CEC_CEC_1, 0x1940), INTC_VECT(CEC_CEC_2, 0x1960),
161 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
162 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
163 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
164 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
165 INTC_VECT(MFIS2, 0x1a00),
166 INTC_VECT(CPORTR2S, 0x1a20),
167 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
168 INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
169 INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
170 INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
171 INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
172 INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
173 INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
174 INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
175 INTC_VECT(USHSDMI, 0x1d00),
176};
177
178static struct intc_group intca_groups[] __initdata = {
179 INTC_GROUP(DMAC_1, DMAC_1_DEI0,
180 DMAC_1_DEI1, DMAC_1_DEI2, DMAC_1_DEI3),
181 INTC_GROUP(DMAC_2, DMAC_2_DEI4,
182 DMAC_2_DEI5, DMAC_2_DADERR),
183 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
184 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
185 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
186 DMAC2_2_DEI5, DMAC2_2_DADERR),
187 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
188 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
189 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
190 DMAC3_2_DEI5, DMAC3_2_DADERR),
191 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMTX),
192 INTC_GROUP(USBHS, USBHS_USHI0, USBHS_USHI1),
193 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
194 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
195 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
196 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
197 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
198 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
199 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
200 SDHI1_SDHI1I2),
201 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
202 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
203 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
204};
205
206static struct intc_mask_reg intca_mask_registers[] = {
207 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
208 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
209 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
210 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
211 { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
212 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
213 { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
214 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
215
216 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
217 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
218 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
219 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
220 { 0, CRYPT_STD, DIRC, 0,
221 DMAC_1_DEI3, DMAC_1_DEI2, DMAC_1_DEI1, DMAC_1_DEI0 } },
222 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
223 { 0, 0, 0, 0,
224 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
225 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
226 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
227 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
228 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
229 { DDM, 0, 0, 0,
230 0, 0, 0, 0 } },
231 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
232 { KEYSC_KEY, DMAC_2_DADERR, DMAC_2_DEI5, DMAC_2_DEI4,
233 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
234 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
235 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
236 0, 0, MSIOF2, 0 } },
237 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
238 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
239 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
240 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
241 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
242 TTI20, USBHSDMAC_USHDMI, 0, 0 } },
243 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
244 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
245 CMT2, 0, 0, _3DG_SGX540 } },
246 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
247 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
248 0, 0, 0, 0 } },
249 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
250 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
251 0, 0, IRREM, 0 } },
252 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
253 { 0, 0, TPU0, 0,
254 0, 0, 0, 0 } },
255 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
256 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
257 0, CMT3, 0, RWDT0 } },
258 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
259 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
260 0, 0, 0, 0 } },
261 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
262 { 0, 0, 0, 0,
263 0, 0, 0, HDMI } },
264 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
265 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
266 0, 0, 0, MIPI_HSI } },
267 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
268 { 0, IPMMU_IPMMUD, CEC_CEC_1, CEC_CEC_2,
269 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
270 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
271 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
272 { MFIS2, CPORTR2S, CMT14, CMT15,
273 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
274 { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
275 { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
276 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
277 { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
278 { 0, 0, 0, 0,
279 USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
280 { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
281 { USBHSDMAC_USHDMI, 0, 0, 0,
282 0, 0, 0, 0 } },
283};
284
285static struct intc_prio_reg intca_prio_registers[] = {
286 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
287 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
288 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
289 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
290 { 0xe6900018, 0, 32, 4, /* INTPRI10A */
291 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
292 { 0xe690001c, 0, 32, 4, /* INTPRI30A */
293 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
294
295 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
296 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
297 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
298 CMT1_CMT11, AP_ARM1 } },
299 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
300 CMT1_CMT12, 0 } },
301 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC_1, MFI_MFIS,
302 MFI_MFIM, 0 } },
303 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC_2,
304 _3DG_SGX540, CMT1_CMT10 } },
305 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
306 SCIFA2, SCIFA3 } },
307 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC_USHDMI,
308 FLCTL, SDHI0 } },
309 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
310 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2, 0, TTI20 } },
311 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
312 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
313 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
314 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
315 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
316 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
317 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
318 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
319 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
320 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
321 CEC_CEC_1, CEC_CEC_2 } },
322 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
323 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
324 CMT14, CMT15 } },
325 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
326 MMC_MMC_ERR, MMC_MMC_NOR } },
327 { 0xe6940040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
328 IIC4_WAITI4, IIC4_DTEI4 } },
329 { 0xe6940044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
330 IIC3_WAITI3, IIC3_DTEI3 } },
331 { 0xe6940048, 0, 16, 4, /* IPRSA3 */ { 0, 0, 0, 0 } },
332 { 0xe694004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
333 USB1_USB1I1, USB1_USB1I0 } },
334 { 0xe6940050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC_USHDMI, 0, 0, 0 } },
335};
336
337static struct intc_sense_reg intca_sense_registers[] __initdata = {
338 { 0xe6900000, 16, 2, /* ICR1A */
339 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
340 { 0xe6900004, 16, 2, /* ICR2A */
341 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
342 { 0xe6900008, 16, 2, /* ICR3A */
343 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
344 { 0xe690000c, 16, 2, /* ICR4A */
345 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
346};
347
348static struct intc_mask_reg intca_ack_registers[] __initdata = {
349 { 0xe6900020, 0, 8, /* INTREQ00A */
350 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
351 { 0xe6900024, 0, 8, /* INTREQ10A */
352 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
353 { 0xe6900028, 0, 8, /* INTREQ20A */
354 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
355 { 0xe690002c, 0, 8, /* INTREQ30A */
356 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
357};
358
359static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
360 intca_vectors, intca_groups,
361 intca_mask_registers, intca_prio_registers,
362 intca_sense_registers, intca_ack_registers);
363
364void __init sh7372_init_irq(void)
365{
366 register_intc_controller(&intca_desc);
367}
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index db972e61c071..1d1153290f59 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -197,45 +197,3 @@ void __init sh7372_add_early_devices(void)
197 early_platform_add_devices(sh7372_early_devices, 197 early_platform_add_devices(sh7372_early_devices,
198 ARRAY_SIZE(sh7372_early_devices)); 198 ARRAY_SIZE(sh7372_early_devices));
199} 199}
200
201enum {
202 UNUSED = 0,
203
204 /* interrupt sources INTCA */
205
206 SCIFA0, SCIFA1, SCIFA2, SCIFA3, SCIFA4, SCIFA5, SCIFB,
207 CMT10,
208};
209
210static struct intc_vect vectors[] = {
211 INTC_VECT(CMT10, 0xb00),
212 INTC_VECT(SCIFA0, 0xc00), INTC_VECT(SCIFA1, 0xc20),
213 INTC_VECT(SCIFA2, 0xc40), INTC_VECT(SCIFA3, 0xc60),
214 INTC_VECT(SCIFA4, 0xd20), INTC_VECT(SCIFA5, 0xd40),
215 INTC_VECT(SCIFB, 0xd60),
216};
217
218static struct intc_mask_reg mask_registers[] = {
219 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
220 { 0, 0, 0, 0, SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
221 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
222 { SCIFB, SCIFA5, SCIFA4, 0, 0, 0, 0, 0 } },
223 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
224 { 0, 0, 0, CMT10, 0, 0, 0, 0 } },
225};
226
227static struct intc_prio_reg prio_registers[] = {
228 { 0xe6940014, 0, 16, 4, /* IPRFA */ { 0, 0, 0, CMT10 } },
229 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
230 SCIFA2, SCIFA3 } },
231 { 0xe6940020, 0, 16, 4, /* IPRIA */ { 0, SCIFA4, 0, 0 } },
232 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, 0 } },
233};
234
235static DECLARE_INTC_DESC(intc_desc, "sh7372", vectors, NULL, mask_registers,
236 prio_registers, NULL);
237
238void __init sh7372_init_irq(void)
239{
240 register_intc_controller(&intc_desc);
241}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 16:45:32 -0500