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authorManu Abraham <abraham.manu@gmail.com>2009-04-06 14:45:20 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-06-16 17:20:37 -0400
commite415c689a8842670e161581f060575c14957f073 (patch)
treeed18153bcad93a377f0ab6b5ac27554de9a9b614
parent2460cdac94082c7046ab595bf643338e6faed6cb (diff)
V4L/DVB (11579): Initial go at TT S2-1600
[mchehab@redhat.com: fix compilation when the new drivers aren't selected] Signed-off-by: Manu Abraham <manu@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/dvb/frontends/Kconfig22
-rw-r--r--drivers/media/dvb/frontends/Makefile4
-rw-r--r--drivers/media/dvb/frontends/isl6423.c293
-rw-r--r--drivers/media/dvb/frontends/isl6423.h63
-rw-r--r--drivers/media/dvb/frontends/stv090x.c3928
-rw-r--r--drivers/media/dvb/frontends/stv090x.h93
-rw-r--r--drivers/media/dvb/frontends/stv090x_priv.h274
-rw-r--r--drivers/media/dvb/frontends/stv090x_reg.h2300
-rw-r--r--drivers/media/dvb/frontends/stv6110x.c372
-rw-r--r--drivers/media/dvb/frontends/stv6110x.h71
-rw-r--r--drivers/media/dvb/frontends/stv6110x_priv.h77
-rw-r--r--drivers/media/dvb/frontends/stv6110x_reg.h82
-rw-r--r--drivers/media/dvb/ttpci/budget-ci.c83
13 files changed, 7661 insertions, 1 deletions
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 23e4cffeba38..be967ac09a39 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -35,6 +35,21 @@ config DVB_STB6100
35 A Silicon tuner from ST used in conjunction with the STB0899 35 A Silicon tuner from ST used in conjunction with the STB0899
36 demodulator. Say Y when you want to support this tuner. 36 demodulator. Say Y when you want to support this tuner.
37 37
38config DVB_STV090x
39 tristate "STV0900/STV0903(A/B) based"
40 depends on DVB_CORE && I2C
41 default m if DVB_FE_CUSTOMISE
42 help
43 DVB-S/S2/DSS Multistandard Professional/Broadcast demodulators.
44 Say Y when you want to support these frontends.
45
46config DVB_STV6110x
47 tristate "STV6110/(A) based tuners"
48 depends on DVB_CORE && I2C
49 default m if DVB_FE_CUSTOMISE
50 help
51 A Silicon tuner that supports DVB-S and DVB-S2 modes
52
38comment "DVB-S (satellite) frontends" 53comment "DVB-S (satellite) frontends"
39 depends on DVB_CORE 54 depends on DVB_CORE
40 55
@@ -506,6 +521,13 @@ config DVB_ISL6421
506 help 521 help
507 An SEC control chip. 522 An SEC control chip.
508 523
524config DVB_ISL6423
525 tristate "ISL6423 SEC controller"
526 depends on DVB_CORE && I2C
527 default m if DVB_FE_CUSTOMISE
528 help
529 A SEC controller chip from Intersil
530
509config DVB_LGS8GL5 531config DVB_LGS8GL5
510 tristate "Silicon Legend LGS-8GL5 demodulator (OFDM)" 532 tristate "Silicon Legend LGS-8GL5 demodulator (OFDM)"
511 depends on DVB_CORE && I2C 533 depends on DVB_CORE && I2C
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index bc2b00abd106..832473c1e512 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -71,4 +71,6 @@ obj-$(CONFIG_DVB_STB6000) += stb6000.o
71obj-$(CONFIG_DVB_S921) += s921.o 71obj-$(CONFIG_DVB_S921) += s921.o
72obj-$(CONFIG_DVB_STV6110) += stv6110.o 72obj-$(CONFIG_DVB_STV6110) += stv6110.o
73obj-$(CONFIG_DVB_STV0900) += stv0900.o 73obj-$(CONFIG_DVB_STV0900) += stv0900.o
74 74obj-$(CONFIG_DVB_STV090x) += stv090x.o
75obj-$(CONFIG_DVB_STV6110x) += stv6110x.o
76obj-$(CONFIG_DVB_ISL6423) += isl6423.o
diff --git a/drivers/media/dvb/frontends/isl6423.c b/drivers/media/dvb/frontends/isl6423.c
new file mode 100644
index 000000000000..c1943dcb8db6
--- /dev/null
+++ b/drivers/media/dvb/frontends/isl6423.c
@@ -0,0 +1,293 @@
1/*
2 Intersil ISL6423 SEC and LNB Power supply controller
3
4 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include <linux/delay.h>
22#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28
29#include "dvb_frontend.h"
30#include "isl6423.h"
31
32static unsigned int verbose;
33module_param(verbose, int, 0644);
34MODULE_PARM_DESC(verbose, "Set Verbosity level");
35
36#define FE_ERROR 0
37#define FE_NOTICE 1
38#define FE_INFO 2
39#define FE_DEBUG 3
40#define FE_DEBUGREG 4
41
42#define dprintk(__y, __z, format, arg...) do { \
43 if (__z) { \
44 if ((verbose > FE_ERROR) && (verbose > __y)) \
45 printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
46 else if ((verbose > FE_NOTICE) && (verbose > __y)) \
47 printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
48 else if ((verbose > FE_INFO) && (verbose > __y)) \
49 printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
50 else if ((verbose > FE_DEBUG) && (verbose > __y)) \
51 printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
52 } else { \
53 if (verbose > __y) \
54 printk(format, ##arg); \
55 } \
56} while (0)
57
58struct isl6423_dev {
59 const struct isl6423_config *config;
60 struct i2c_adapter *i2c;
61
62 u8 reg_3;
63 u8 reg_4;
64
65 unsigned int verbose;
66};
67
68static int isl6423_write(struct isl6423_dev *isl6423, u8 reg)
69{
70 struct i2c_adapter *i2c = isl6423->i2c;
71 u8 addr = isl6423->config->addr;
72 int err = 0;
73
74 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = &reg, .len = 1 };
75
76 err = i2c_transfer(i2c, &msg, 1);
77 if (err < 0)
78 goto exit;
79 return 0;
80
81exit:
82 dprintk(FE_ERROR, 1, "I/O error <%d>", err);
83 return err;
84}
85
86static int isl6423_set_modulation(struct dvb_frontend *fe)
87{
88 struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
89 const struct isl6423_config *config = isl6423->config;
90 int err = 0;
91 u8 reg_2 = 0;
92
93 reg_2 = 0x01 << 5;
94
95 if (config->mod_extern)
96 reg_2 |= (1 << 3);
97 else
98 reg_2 |= (1 << 4);
99
100 err = isl6423_write(isl6423, reg_2);
101 if (err < 0)
102 goto exit;
103 return 0;
104
105exit:
106 dprintk(FE_ERROR, 1, "I/O error <%d>", err);
107 return err;
108}
109
110static int isl6423_voltage_boost(struct dvb_frontend *fe, long arg)
111{
112 struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
113 u8 reg_3 = isl6423->reg_3;
114 u8 reg_4 = isl6423->reg_4;
115 int err = 0;
116
117 if (arg) {
118 /* EN = 1, VSPEN = 1, VBOT = 1 */
119 reg_4 |= (1 << 4);
120 reg_4 |= 0x1;
121 reg_3 |= (1 << 3);
122 } else {
123 /* EN = 1, VSPEN = 1, VBOT = 0 */
124 reg_4 |= (1 << 4);
125 reg_4 &= ~0x1;
126 reg_3 |= (1 << 3);
127 }
128 err = isl6423_write(isl6423, reg_3);
129 if (err < 0)
130 goto exit;
131
132 err = isl6423_write(isl6423, reg_4);
133 if (err < 0)
134 goto exit;
135
136 return 0;
137exit:
138 dprintk(FE_ERROR, 1, "I/O error <%d>", err);
139 return err;
140}
141
142
143static int isl6423_set_voltage(struct dvb_frontend *fe,
144 enum fe_sec_voltage voltage)
145{
146 struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
147 u8 reg_4 = isl6423->reg_4;
148 int err = 0;
149
150 /* SR4H = 0, SR4M = 1, SR4L = 1 */
151 reg_4 = 0x03 << 5;
152
153 switch (voltage) {
154 case SEC_VOLTAGE_OFF:
155 /* EN = 0 */
156 reg_4 &= ~(1 << 4);
157 break;
158
159 case SEC_VOLTAGE_13:
160 /* EN = 1, VSPEN = 1, VTOP = 0, VBOT = 0 */
161 reg_4 |= (1 << 4);
162 reg_4 &= ~0x3;
163 break;
164
165 case SEC_VOLTAGE_18:
166 /* EN = 1, VSPEN = 1, VTOP = 1, VBOT = 0 */
167 reg_4 |= (1 << 4);
168 reg_4 |= 0x2;
169 reg_4 &= ~0x1;
170 break;
171
172 default:
173 break;
174 }
175 err = isl6423_write(isl6423, reg_4);
176 if (err < 0)
177 goto exit;
178
179 return 0;
180exit:
181 dprintk(FE_ERROR, 1, "I/O error <%d>", err);
182 return err;
183}
184
185static int isl6423_set_current(struct dvb_frontend *fe)
186{
187 struct isl6423_dev *isl6423 = (struct isl6423_dev *) fe->sec_priv;
188 u8 reg_3 = isl6423->reg_3;
189 const struct isl6423_config *config = isl6423->config;
190 int err = 0;
191
192 /* SR3H = 0, SR3M = 1, SR3L = 0 */
193 reg_3 = 0x02 << 5;
194
195 switch (config->current_max) {
196 case SEC_CURRENT_275m:
197 /* 275mA */
198 /* ISELH = 0, ISELL = 0 */
199 reg_3 &= ~0x3;
200 break;
201
202 case SEC_CURRENT_515m:
203 /* 515mA */
204 /* ISELH = 0, ISELL = 1 */
205 reg_3 &= ~0x2;
206 reg_3 |= 0x1;
207 break;
208
209 case SEC_CURRENT_635m:
210 /* 635mA */
211 /* ISELH = 1, ISELL = 0 */
212 reg_3 &= ~0x1;
213 reg_3 |= 0x2;
214 break;
215
216 case SEC_CURRENT_800m:
217 /* 800mA */
218 /* ISELH = 1, ISELL = 1 */
219 reg_3 |= 0x3;
220 break;
221 }
222
223 err = isl6423_write(isl6423, reg_3);
224 if (err < 0)
225 goto exit;
226
227 switch (config->curlim) {
228 case SEC_CURRENT_LIM_ON:
229 /* DCL = 1 */
230 reg_3 |= 0x10;
231 break;
232
233 case SEC_CURRENT_LIM_OFF:
234 /* DCL = 0 */
235 reg_3 &= ~0x10;
236 break;
237 }
238
239 err = isl6423_write(isl6423, reg_3);
240 if (err < 0)
241 goto exit;
242
243 return 0;
244exit:
245 dprintk(FE_ERROR, 1, "I/O error <%d>", err);
246 return err;
247}
248
249static void isl6423_release(struct dvb_frontend *fe)
250{
251 isl6423_set_voltage(fe, SEC_VOLTAGE_OFF);
252
253 kfree(fe->sec_priv);
254 fe->sec_priv = NULL;
255}
256
257struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
258 struct i2c_adapter *i2c,
259 const struct isl6423_config *config)
260{
261 struct isl6423_dev *isl6423;
262
263 isl6423 = kzalloc(sizeof(struct isl6423_dev), GFP_KERNEL);
264 if (!isl6423)
265 return NULL;
266
267 isl6423->config = config;
268 isl6423->i2c = i2c;
269 fe->sec_priv = isl6423;
270
271 if (isl6423_set_current(fe))
272 goto exit;
273
274 if (isl6423_set_modulation(fe))
275 goto exit;
276
277 fe->ops.release_sec = isl6423_release;
278 fe->ops.set_voltage = isl6423_set_voltage;
279 fe->ops.enable_high_lnb_voltage = isl6423_voltage_boost;
280 isl6423->verbose = verbose;
281
282 return fe;
283
284exit:
285 kfree(isl6423);
286 fe->sec_priv = NULL;
287 return NULL;
288}
289EXPORT_SYMBOL(isl6423_attach);
290
291MODULE_DESCRIPTION("ISL6423 SEC");
292MODULE_AUTHOR("Manu Abraham");
293MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/isl6423.h b/drivers/media/dvb/frontends/isl6423.h
new file mode 100644
index 000000000000..e1a37fba01ca
--- /dev/null
+++ b/drivers/media/dvb/frontends/isl6423.h
@@ -0,0 +1,63 @@
1/*
2 Intersil ISL6423 SEC and LNB Power supply controller
3
4 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#ifndef __ISL_6423_H
22#define __ISL_6423_H
23
24#include <linux/dvb/frontend.h>
25
26enum isl6423_current {
27 SEC_CURRENT_275m = 0,
28 SEC_CURRENT_515m,
29 SEC_CURRENT_635m,
30 SEC_CURRENT_800m,
31};
32
33enum isl6423_curlim {
34 SEC_CURRENT_LIM_ON = 1,
35 SEC_CURRENT_LIM_OFF
36};
37
38struct isl6423_config {
39 enum isl6423_current current_max;
40 enum isl6423_curlim curlim;
41 u8 addr;
42 u8 mod_extern;
43};
44
45#if defined(CONFIG_DVB_ISL6423) || (defined(CONFIG_DVB_ISL6423_MODULE) && defined(MODULE))
46
47
48extern struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
49 struct i2c_adapter *i2c,
50 const struct isl6423_config *config);
51
52#else
53static inline struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe,
54 struct i2c_adapter *i2c,
55 const struct isl6423_config *config)
56{
57 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
58 return NULL;
59}
60
61#endif /* CONFIG_DVB_ISL6423 */
62
63#endif /* __ISL_6423_H */
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c
new file mode 100644
index 000000000000..a65f1b7849a1
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x.c
@@ -0,0 +1,3928 @@
1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/string.h>
26#include <linux/mutex.h>
27
28#include <linux/dvb/frontend.h>
29#include "dvb_frontend.h"
30
31#include "stv6110x.h" /* for demodulator internal modes */
32
33#include "stv090x_reg.h"
34#include "stv090x.h"
35#include "stv090x_priv.h"
36
37static unsigned int verbose;
38module_param(verbose, int, 0644);
39
40struct mutex demod_lock;
41
42/* DVBS1 and DSS C/N Lookup table */
43static const struct stv090x_tab stv090x_s1cn_tab[] = {
44 { 0, 8917 }, /* 0.0dB */
45 { 5, 8801 }, /* 0.5dB */
46 { 10, 8667 }, /* 1.0dB */
47 { 15, 8522 }, /* 1.5dB */
48 { 20, 8355 }, /* 2.0dB */
49 { 25, 8175 }, /* 2.5dB */
50 { 30, 7979 }, /* 3.0dB */
51 { 35, 7763 }, /* 3.5dB */
52 { 40, 7530 }, /* 4.0dB */
53 { 45, 7282 }, /* 4.5dB */
54 { 50, 7026 }, /* 5.0dB */
55 { 55, 6781 }, /* 5.5dB */
56 { 60, 6514 }, /* 6.0dB */
57 { 65, 6241 }, /* 6.5dB */
58 { 70, 5965 }, /* 7.0dB */
59 { 75, 5690 }, /* 7.5dB */
60 { 80, 5424 }, /* 8.0dB */
61 { 85, 5161 }, /* 8.5dB */
62 { 90, 4902 }, /* 9.0dB */
63 { 95, 4654 }, /* 9.5dB */
64 { 100, 4417 }, /* 10.0dB */
65 { 105, 4186 }, /* 10.5dB */
66 { 110, 3968 }, /* 11.0dB */
67 { 115, 3757 }, /* 11.5dB */
68 { 120, 3558 }, /* 12.0dB */
69 { 125, 3366 }, /* 12.5dB */
70 { 130, 3185 }, /* 13.0dB */
71 { 135, 3012 }, /* 13.5dB */
72 { 140, 2850 }, /* 14.0dB */
73 { 145, 2698 }, /* 14.5dB */
74 { 150, 2550 }, /* 15.0dB */
75 { 160, 2283 }, /* 16.0dB */
76 { 170, 2042 }, /* 17.0dB */
77 { 180, 1827 }, /* 18.0dB */
78 { 190, 1636 }, /* 19.0dB */
79 { 200, 1466 }, /* 20.0dB */
80 { 210, 1315 }, /* 21.0dB */
81 { 220, 1181 }, /* 22.0dB */
82 { 230, 1064 }, /* 23.0dB */
83 { 240, 960 }, /* 24.0dB */
84 { 250, 869 }, /* 25.0dB */
85 { 260, 792 }, /* 26.0dB */
86 { 270, 724 }, /* 27.0dB */
87 { 280, 665 }, /* 28.0dB */
88 { 290, 616 }, /* 29.0dB */
89 { 300, 573 }, /* 30.0dB */
90 { 310, 537 }, /* 31.0dB */
91 { 320, 507 }, /* 32.0dB */
92 { 330, 483 }, /* 33.0dB */
93 { 400, 398 }, /* 40.0dB */
94 { 450, 381 }, /* 45.0dB */
95 { 500, 377 } /* 50.0dB */
96};
97
98/* DVBS2 C/N Lookup table */
99static const struct stv090x_tab stv090x_s2cn_tab[] = {
100 { -30, 13348 }, /* -3.0dB */
101 { -20, 12640 }, /* -2d.0B */
102 { -10, 11883 }, /* -1.0dB */
103 { 0, 11101 }, /* -0.0dB */
104 { 5, 10718 }, /* 0.5dB */
105 { 10, 10339 }, /* 1.0dB */
106 { 15, 9947 }, /* 1.5dB */
107 { 20, 9552 }, /* 2.0dB */
108 { 25, 9183 }, /* 2.5dB */
109 { 30, 8799 }, /* 3.0dB */
110 { 35, 8422 }, /* 3.5dB */
111 { 40, 8062 }, /* 4.0dB */
112 { 45, 7707 }, /* 4.5dB */
113 { 50, 7353 }, /* 5.0dB */
114 { 55, 7025 }, /* 5.5dB */
115 { 60, 6684 }, /* 6.0dB */
116 { 65, 6331 }, /* 6.5dB */
117 { 70, 6036 }, /* 7.0dB */
118 { 75, 5727 }, /* 7.5dB */
119 { 80, 5437 }, /* 8.0dB */
120 { 85, 5164 }, /* 8.5dB */
121 { 90, 4902 }, /* 9.0dB */
122 { 95, 4653 }, /* 9.5dB */
123 { 100, 4408 }, /* 10.0dB */
124 { 105, 4187 }, /* 10.5dB */
125 { 110, 3961 }, /* 11.0dB */
126 { 115, 3751 }, /* 11.5dB */
127 { 120, 3558 }, /* 12.0dB */
128 { 125, 3368 }, /* 12.5dB */
129 { 130, 3191 }, /* 13.0dB */
130 { 135, 3017 }, /* 13.5dB */
131 { 140, 2862 }, /* 14.0dB */
132 { 145, 2710 }, /* 14.5dB */
133 { 150, 2565 }, /* 15.0dB */
134 { 160, 2300 }, /* 16.0dB */
135 { 170, 2058 }, /* 17.0dB */
136 { 180, 1849 }, /* 18.0dB */
137 { 190, 1663 }, /* 19.0dB */
138 { 200, 1495 }, /* 20.0dB */
139 { 210, 1349 }, /* 21.0dB */
140 { 220, 1222 }, /* 22.0dB */
141 { 230, 1110 }, /* 23.0dB */
142 { 240, 1011 }, /* 24.0dB */
143 { 250, 925 }, /* 25.0dB */
144 { 260, 853 }, /* 26.0dB */
145 { 270, 789 }, /* 27.0dB */
146 { 280, 734 }, /* 28.0dB */
147 { 290, 690 }, /* 29.0dB */
148 { 300, 650 }, /* 30.0dB */
149 { 310, 619 }, /* 31.0dB */
150 { 320, 593 }, /* 32.0dB */
151 { 330, 571 }, /* 33.0dB */
152 { 400, 498 }, /* 40.0dB */
153 { 450, 484 }, /* 45.0dB */
154 { 500, 481 } /* 50.0dB */
155};
156
157/* RF level C/N lookup table */
158static const struct stv090x_tab stv090x_rf_tab[] = {
159 { -5, 0xcaa1 }, /* -5dBm */
160 { -10, 0xc229 }, /* -10dBm */
161 { -15, 0xbb08 }, /* -15dBm */
162 { -20, 0xb4bc }, /* -20dBm */
163 { -25, 0xad5a }, /* -25dBm */
164 { -30, 0xa298 }, /* -30dBm */
165 { -35, 0x98a8 }, /* -35dBm */
166 { -40, 0x8389 }, /* -40dBm */
167 { -45, 0x59be }, /* -45dBm */
168 { -50, 0x3a14 }, /* -50dBm */
169 { -55, 0x2d11 }, /* -55dBm */
170 { -60, 0x210d }, /* -60dBm */
171 { -65, 0xa14f }, /* -65dBm */
172 { -70, 0x07aa } /* -70dBm */
173};
174
175
176static struct stv090x_reg stv0900_initval[] = {
177
178 { STV090x_OUTCFG, 0x00 },
179 { STV090x_AGCRF1CFG, 0x11 },
180 { STV090x_AGCRF2CFG, 0x13 },
181 { STV090x_TSTTNR2, 0x21 },
182 { STV090x_TSTTNR4, 0x21 },
183 { STV090x_P2_DISTXCTL, 0x22 },
184 { STV090x_P2_F22TX, 0xc0 },
185 { STV090x_P2_F22RX, 0xc0 },
186 { STV090x_P2_DISRXCTL, 0x00 },
187 { STV090x_P2_DMDCFGMD, 0xF9 },
188 { STV090x_P2_DEMOD, 0x08 },
189 { STV090x_P2_DMDCFG3, 0xc4 },
190 { STV090x_P2_CARFREQ, 0xed },
191 { STV090x_P2_LDT, 0xd0 },
192 { STV090x_P2_LDT2, 0xb8 },
193 { STV090x_P2_TMGCFG, 0xd2 },
194 { STV090x_P2_TMGTHRISE, 0x20 },
195 { STV090x_P1_TMGCFG, 0xd2 },
196
197 { STV090x_P2_TMGTHFALL, 0x00 },
198 { STV090x_P2_FECSPY, 0x88 },
199 { STV090x_P2_FSPYDATA, 0x3a },
200 { STV090x_P2_FBERCPT4, 0x00 },
201 { STV090x_P2_FSPYBER, 0x10 },
202 { STV090x_P2_ERRCTRL1, 0x35 },
203 { STV090x_P2_ERRCTRL2, 0xc1 },
204 { STV090x_P2_CFRICFG, 0xf8 },
205 { STV090x_P2_NOSCFG, 0x1c },
206 { STV090x_P2_CORRELMANT, 0x70 },
207 { STV090x_P2_CORRELABS, 0x88 },
208 { STV090x_P2_AGC2REF, 0x38 },
209 { STV090x_P2_CARCFG, 0xe4 },
210 { STV090x_P2_ACLC, 0x1A },
211 { STV090x_P2_BCLC, 0x09 },
212 { STV090x_P2_CARHDR, 0x08 },
213 { STV090x_P2_KREFTMG, 0xc1 },
214 { STV090x_P2_SFRUPRATIO, 0xf0 },
215 { STV090x_P2_SFRLOWRATIO, 0x70 },
216 { STV090x_P2_SFRSTEP, 0x58 },
217 { STV090x_P2_TMGCFG2, 0x01 },
218 { STV090x_P2_CAR2CFG, 0x26 },
219 { STV090x_P2_BCLC2S2Q, 0x86 },
220 { STV090x_P2_BCLC2S28, 0x86 },
221 { STV090x_P2_SMAPCOEF7, 0x77 },
222 { STV090x_P2_SMAPCOEF6, 0x85 },
223 { STV090x_P2_SMAPCOEF5, 0x77 },
224 { STV090x_P2_TSCFGL, 0x20 },
225 { STV090x_P2_DMDCFG2, 0x3b },
226 { STV090x_P2_MODCODLST0, 0xff },
227 { STV090x_P2_MODCODLST1, 0xff },
228 { STV090x_P2_MODCODLST2, 0xff },
229 { STV090x_P2_MODCODLST3, 0xff },
230 { STV090x_P2_MODCODLST4, 0xff },
231 { STV090x_P2_MODCODLST5, 0xff },
232 { STV090x_P2_MODCODLST6, 0xff },
233 { STV090x_P2_MODCODLST7, 0xcc },
234 { STV090x_P2_MODCODLST8, 0xcc },
235 { STV090x_P2_MODCODLST9, 0xcc },
236 { STV090x_P2_MODCODLSTA, 0xcc },
237 { STV090x_P2_MODCODLSTB, 0xcc },
238 { STV090x_P2_MODCODLSTC, 0xcc },
239 { STV090x_P2_MODCODLSTD, 0xcc },
240 { STV090x_P2_MODCODLSTE, 0xcc },
241 { STV090x_P2_MODCODLSTF, 0xcf },
242 { STV090x_P1_DISTXCTL, 0x22 },
243 { STV090x_P1_F22TX, 0xc0 },
244 { STV090x_P1_F22RX, 0xc0 },
245 { STV090x_P1_DISRXCTL, 0x00 },
246 { STV090x_P1_DMDCFGMD, 0xf9 },
247 { STV090x_P1_DEMOD, 0x08 },
248 { STV090x_P1_DMDCFG3, 0xc4 },
249 { STV090x_P1_CARFREQ, 0xed },
250 { STV090x_P1_LDT, 0xd0 },
251 { STV090x_P1_LDT2, 0xb8 },
252 { STV090x_P1_TMGCFG, 0xd2 },
253 { STV090x_P1_TMGTHRISE, 0x20 },
254 { STV090x_P1_TMGTHFALL, 0x00 },
255 { STV090x_P1_SFRUPRATIO, 0xf0 },
256 { STV090x_P1_SFRLOWRATIO, 0x70 },
257 { STV090x_P1_TSCFGL, 0x20 },
258 { STV090x_P1_FECSPY, 0x88 },
259 { STV090x_P1_FSPYDATA, 0x3a },
260 { STV090x_P1_FBERCPT4, 0x00 },
261 { STV090x_P1_FSPYBER, 0x10 },
262 { STV090x_P1_ERRCTRL1, 0x35 },
263 { STV090x_P1_ERRCTRL2, 0xc1 },
264 { STV090x_P1_CFRICFG, 0xf8 },
265 { STV090x_P1_NOSCFG, 0x1c },
266 { STV090x_P1_CORRELMANT, 0x70 },
267 { STV090x_P1_CORRELABS, 0x88 },
268 { STV090x_P1_AGC2REF, 0x38 },
269 { STV090x_P1_CARCFG, 0xe4 },
270 { STV090x_P1_ACLC, 0x1A },
271 { STV090x_P1_BCLC, 0x09 },
272 { STV090x_P1_CARHDR, 0x08 },
273 { STV090x_P1_KREFTMG, 0xc1 },
274 { STV090x_P1_SFRSTEP, 0x58 },
275 { STV090x_P1_TMGCFG2, 0x01 },
276 { STV090x_P1_CAR2CFG, 0x26 },
277 { STV090x_P1_BCLC2S2Q, 0x86 },
278 { STV090x_P1_BCLC2S28, 0x86 },
279 { STV090x_P1_SMAPCOEF7, 0x77 },
280 { STV090x_P1_SMAPCOEF6, 0x85 },
281 { STV090x_P1_SMAPCOEF5, 0x77 },
282 { STV090x_P1_DMDCFG2, 0x3b },
283 { STV090x_P1_MODCODLST0, 0xff },
284 { STV090x_P1_MODCODLST1, 0xff },
285 { STV090x_P1_MODCODLST2, 0xff },
286 { STV090x_P1_MODCODLST3, 0xff },
287 { STV090x_P1_MODCODLST4, 0xff },
288 { STV090x_P1_MODCODLST5, 0xff },
289 { STV090x_P1_MODCODLST6, 0xff },
290 { STV090x_P1_MODCODLST7, 0xcc },
291 { STV090x_P1_MODCODLST8, 0xcc },
292 { STV090x_P1_MODCODLST9, 0xcc },
293 { STV090x_P1_MODCODLSTA, 0xcc },
294 { STV090x_P1_MODCODLSTB, 0xcc },
295 { STV090x_P1_MODCODLSTC, 0xcc },
296 { STV090x_P1_MODCODLSTD, 0xcc },
297 { STV090x_P1_MODCODLSTE, 0xcc },
298 { STV090x_P1_MODCODLSTF, 0xcf },
299 { STV090x_GENCFG, 0x1d },
300 { STV090x_NBITER_NF4, 0x37 },
301 { STV090x_NBITER_NF5, 0x29 },
302 { STV090x_NBITER_NF6, 0x37 },
303 { STV090x_NBITER_NF7, 0x33 },
304 { STV090x_NBITER_NF8, 0x31 },
305 { STV090x_NBITER_NF9, 0x2f },
306 { STV090x_NBITER_NF10, 0x39 },
307 { STV090x_NBITER_NF11, 0x3a },
308 { STV090x_NBITER_NF12, 0x29 },
309 { STV090x_NBITER_NF13, 0x37 },
310 { STV090x_NBITER_NF14, 0x33 },
311 { STV090x_NBITER_NF15, 0x2f },
312 { STV090x_NBITER_NF16, 0x39 },
313 { STV090x_NBITER_NF17, 0x3a },
314 { STV090x_NBITERNOERR, 0x04 },
315 { STV090x_GAINLLR_NF4, 0x0C },
316 { STV090x_GAINLLR_NF5, 0x0F },
317 { STV090x_GAINLLR_NF6, 0x11 },
318 { STV090x_GAINLLR_NF7, 0x14 },
319 { STV090x_GAINLLR_NF8, 0x17 },
320 { STV090x_GAINLLR_NF9, 0x19 },
321 { STV090x_GAINLLR_NF10, 0x20 },
322 { STV090x_GAINLLR_NF11, 0x21 },
323 { STV090x_GAINLLR_NF12, 0x0D },
324 { STV090x_GAINLLR_NF13, 0x0F },
325 { STV090x_GAINLLR_NF14, 0x13 },
326 { STV090x_GAINLLR_NF15, 0x1A },
327 { STV090x_GAINLLR_NF16, 0x1F },
328 { STV090x_GAINLLR_NF17, 0x21 },
329 { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
330 { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
331 { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
332 { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
333};
334
335static struct stv090x_reg stv0903_initval[] = {
336 { STV090x_OUTCFG, 0x00 },
337 { STV090x_AGCRF1CFG, 0x11 },
338 { STV090x_STOPCLK1, 0x48 },
339 { STV090x_STOPCLK2, 0x14 },
340 { STV090x_TSTTNR1, 0x27 },
341 { STV090x_TSTTNR2, 0x21 },
342 { STV090x_P1_DISTXCTL, 0x22 },
343 { STV090x_P1_F22TX, 0xc0 },
344 { STV090x_P1_F22RX, 0xc0 },
345 { STV090x_P1_DISRXCTL, 0x00 },
346 { STV090x_P1_DMDCFGMD, 0xF9 },
347 { STV090x_P1_DEMOD, 0x08 },
348 { STV090x_P1_DMDCFG3, 0xc4 },
349 { STV090x_P1_CARFREQ, 0xed },
350 { STV090x_P1_TNRCFG2, 0x82 },
351 { STV090x_P1_LDT, 0xd0 },
352 { STV090x_P1_LDT2, 0xb8 },
353 { STV090x_P1_TMGCFG, 0xd2 },
354 { STV090x_P1_TMGTHRISE, 0x20 },
355 { STV090x_P1_TMGTHFALL, 0x00 },
356 { STV090x_P1_SFRUPRATIO, 0xf0 },
357 { STV090x_P1_SFRLOWRATIO, 0x70 },
358 { STV090x_P1_TSCFGL, 0x20 },
359 { STV090x_P1_FECSPY, 0x88 },
360 { STV090x_P1_FSPYDATA, 0x3a },
361 { STV090x_P1_FBERCPT4, 0x00 },
362 { STV090x_P1_FSPYBER, 0x10 },
363 { STV090x_P1_ERRCTRL1, 0x35 },
364 { STV090x_P1_ERRCTRL2, 0xc1 },
365 { STV090x_P1_CFRICFG, 0xf8 },
366 { STV090x_P1_NOSCFG, 0x1c },
367 { STV090x_P1_CORRELMANT, 0x70 },
368 { STV090x_P1_CORRELABS, 0x88 },
369 { STV090x_P1_AGC2REF, 0x38 } ,
370 { STV090x_P1_CARCFG, 0xe4 },
371 { STV090x_P1_ACLC, 0x1A },
372 { STV090x_P1_BCLC, 0x09 } ,
373 { STV090x_P1_CARHDR, 0x08 },
374 { STV090x_P1_KREFTMG, 0xc1 },
375 { STV090x_P1_SFRSTEP, 0x58 },
376 { STV090x_P1_TMGCFG2, 0x01 },
377 { STV090x_P1_CAR2CFG, 0x26 },
378 { STV090x_P1_BCLC2S2Q, 0x86 },
379 { STV090x_P1_BCLC2S28, 0x86 },
380 { STV090x_P1_SMAPCOEF7, 0x77 },
381 { STV090x_P1_SMAPCOEF6, 0x85 },
382 { STV090x_P1_SMAPCOEF5, 0x77 },
383 { STV090x_P1_DMDCFG2, 0x3b },
384 { STV090x_P1_MODCODLST0, 0xff },
385 { STV090x_P1_MODCODLST1, 0xff },
386 { STV090x_P1_MODCODLST2, 0xff },
387 { STV090x_P1_MODCODLST3, 0xff },
388 { STV090x_P1_MODCODLST4, 0xff },
389 { STV090x_P1_MODCODLST5, 0xff },
390 { STV090x_P1_MODCODLST6, 0xff },
391 { STV090x_P1_MODCODLST7, 0xcc },
392 { STV090x_P1_MODCODLST8, 0xcc },
393 { STV090x_P1_MODCODLST9, 0xcc },
394 { STV090x_P1_MODCODLSTA, 0xcc },
395 { STV090x_P1_MODCODLSTB, 0xcc },
396 { STV090x_P1_MODCODLSTC, 0xcc },
397 { STV090x_P1_MODCODLSTD, 0xcc },
398 { STV090x_P1_MODCODLSTE, 0xcc },
399 { STV090x_P1_MODCODLSTF, 0xcf },
400 { STV090x_GENCFG, 0x1c },
401 { STV090x_NBITER_NF4, 0x37 },
402 { STV090x_NBITER_NF5, 0x29 },
403 { STV090x_NBITER_NF6, 0x37 },
404 { STV090x_NBITER_NF7, 0x33 },
405 { STV090x_NBITER_NF8, 0x31 },
406 { STV090x_NBITER_NF9, 0x2f },
407 { STV090x_NBITER_NF10, 0x39 },
408 { STV090x_NBITER_NF11, 0x3a },
409 { STV090x_NBITER_NF12, 0x29 },
410 { STV090x_NBITER_NF13, 0x37 },
411 { STV090x_NBITER_NF14, 0x33 },
412 { STV090x_NBITER_NF15, 0x2f },
413 { STV090x_NBITER_NF16, 0x39 },
414 { STV090x_NBITER_NF17, 0x3a },
415 { STV090x_NBITERNOERR, 0x04 },
416 { STV090x_GAINLLR_NF4, 0x0C },
417 { STV090x_GAINLLR_NF5, 0x0F },
418 { STV090x_GAINLLR_NF6, 0x11 },
419 { STV090x_GAINLLR_NF7, 0x14 },
420 { STV090x_GAINLLR_NF8, 0x17 },
421 { STV090x_GAINLLR_NF9, 0x19 },
422 { STV090x_GAINLLR_NF10, 0x20 },
423 { STV090x_GAINLLR_NF11, 0x21 },
424 { STV090x_GAINLLR_NF12, 0x0D },
425 { STV090x_GAINLLR_NF13, 0x0F },
426 { STV090x_GAINLLR_NF14, 0x13 },
427 { STV090x_GAINLLR_NF15, 0x1A },
428 { STV090x_GAINLLR_NF16, 0x1F },
429 { STV090x_GAINLLR_NF17, 0x21 },
430 { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
431 { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
432};
433
434static struct stv090x_reg stv0900_cut20_val[] = {
435
436 { STV090x_P2_DMDCFG3, 0xe8 },
437 { STV090x_P2_CARFREQ, 0x38 },
438 { STV090x_P2_CARHDR, 0x20 },
439 { STV090x_P2_KREFTMG, 0x5a },
440 { STV090x_P2_SMAPCOEF7, 0x06 },
441 { STV090x_P2_SMAPCOEF6, 0x00 },
442 { STV090x_P2_SMAPCOEF5, 0x04 },
443 { STV090x_P2_NOSCFG, 0x0c },
444 { STV090x_P1_DMDCFG3, 0xe8 },
445 { STV090x_P1_CARFREQ, 0x38 },
446 { STV090x_P1_CARHDR, 0x20 },
447 { STV090x_P1_KREFTMG, 0x5a },
448 { STV090x_P1_SMAPCOEF7, 0x06 },
449 { STV090x_P1_SMAPCOEF6, 0x00 },
450 { STV090x_P1_SMAPCOEF5, 0x04 },
451 { STV090x_P1_NOSCFG, 0x0c },
452 { STV090x_GAINLLR_NF4, 0x21 },
453 { STV090x_GAINLLR_NF5, 0x21 },
454 { STV090x_GAINLLR_NF6, 0x20 },
455 { STV090x_GAINLLR_NF7, 0x1F },
456 { STV090x_GAINLLR_NF8, 0x1E },
457 { STV090x_GAINLLR_NF9, 0x1E },
458 { STV090x_GAINLLR_NF10, 0x1D },
459 { STV090x_GAINLLR_NF11, 0x1B },
460 { STV090x_GAINLLR_NF12, 0x20 },
461 { STV090x_GAINLLR_NF13, 0x20 },
462 { STV090x_GAINLLR_NF14, 0x20 },
463 { STV090x_GAINLLR_NF15, 0x20 },
464 { STV090x_GAINLLR_NF16, 0x20 },
465 { STV090x_GAINLLR_NF17, 0x21 },
466};
467
468static struct stv090x_reg stv0903_cut20_val[] = {
469 { STV090x_P1_DMDCFG3, 0xe8 },
470 { STV090x_P1_CARFREQ, 0x38 },
471 { STV090x_P1_CARHDR, 0x20 },
472 { STV090x_P1_KREFTMG, 0x5a },
473 { STV090x_P1_SMAPCOEF7, 0x06 },
474 { STV090x_P1_SMAPCOEF6, 0x00 },
475 { STV090x_P1_SMAPCOEF5, 0x04 },
476 { STV090x_P1_NOSCFG, 0x0c },
477 { STV090x_GAINLLR_NF4, 0x21 },
478 { STV090x_GAINLLR_NF5, 0x21 },
479 { STV090x_GAINLLR_NF6, 0x20 },
480 { STV090x_GAINLLR_NF7, 0x1F },
481 { STV090x_GAINLLR_NF8, 0x1E },
482 { STV090x_GAINLLR_NF9, 0x1E },
483 { STV090x_GAINLLR_NF10, 0x1D },
484 { STV090x_GAINLLR_NF11, 0x1B },
485 { STV090x_GAINLLR_NF12, 0x20 },
486 { STV090x_GAINLLR_NF13, 0x20 },
487 { STV090x_GAINLLR_NF14, 0x20 },
488 { STV090x_GAINLLR_NF15, 0x20 },
489 { STV090x_GAINLLR_NF16, 0x20 },
490 { STV090x_GAINLLR_NF17, 0x21 }
491};
492
493/* Cut 1.x Long Frame Tracking CR loop */
494static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
495 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
496 { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
497 { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
498 { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
499 { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
500 { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
501 { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
502 { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
503 { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
504 { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
505 { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
506 { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
507 { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
508 { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
509 { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
510};
511
512/* Cut 2.0 Long Frame Tracking CR loop */
513static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
514 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
515 { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
516 { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
517 { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
518 { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
519 { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
520 { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
521 { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
522 { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
523 { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
524 { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
525 { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
526 { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
527 { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
528 { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
529};
530
531
532/* Cut 2.0 Long Frame Tracking CR Loop */
533static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
534 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
535 { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
536 { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
537 { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
538 { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
539 { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
540 { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
541 { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
542 { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
543 { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
544 { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
545 { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
546};
547
548
549static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
550 /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
551 { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
552 { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
553 { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
554};
555
556
557/* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
558static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
559 /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
560 { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
561 { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
562 { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
563 { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
564};
565
566
567static inline s32 comp2(s32 __x, s32 __width)
568{
569 if (__width == 32)
570 return __x;
571 else
572 return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
573}
574
575static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
576{
577 const struct stv090x_config *config = state->config;
578 int ret;
579
580 u8 b0[] = { reg >> 8, reg & 0xff };
581 u8 buf;
582
583 struct i2c_msg msg[] = {
584 { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
585 { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
586 };
587
588 ret = i2c_transfer(state->i2c, msg, 2);
589 if (ret != 2) {
590 if (ret != -ERESTARTSYS)
591 dprintk(FE_ERROR, 1,
592 "Read error, Reg=[0x%02x], Status=%d",
593 reg, ret);
594
595 return ret < 0 ? ret : -EREMOTEIO;
596 }
597 if (unlikely(*state->verbose >= FE_DEBUGREG))
598 dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
599 reg, buf);
600
601 return (unsigned int) buf;
602}
603
604static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
605{
606 const struct stv090x_config *config = state->config;
607 int ret;
608 u8 buf[2 + count];
609 struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
610
611 buf[0] = reg >> 8;
612 buf[1] = reg & 0xff;
613 memcpy(&buf[2], data, count);
614
615 if (unlikely(*state->verbose >= FE_DEBUGREG)) {
616 int i;
617
618 printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
619 for (i = 0; i < count; i++)
620 printk(" %02x", data[i]);
621 printk("\n");
622 }
623
624 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
625 if (ret != 1) {
626 if (ret != -ERESTARTSYS)
627 dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
628 reg, data[0], count, ret);
629 return ret < 0 ? ret : -EREMOTEIO;
630 }
631
632 return 0;
633}
634
635static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
636{
637 return stv090x_write_regs(state, reg, &data, 1);
638}
639
640static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
641{
642 struct stv090x_state *state = fe->demodulator_priv;
643 u32 reg;
644
645 reg = STV090x_READ_DEMOD(state, I2CRPT);
646
647 if (enable) {
648 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
649 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
650 goto err;
651
652 } else {
653 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
654 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
655 goto err;
656 }
657 return 0;
658err:
659 dprintk(FE_ERROR, 1, "I/O error");
660 return -1;
661}
662
663static void stv090x_get_lock_tmg(struct stv090x_state *state)
664{
665 switch (state->algo) {
666 case STV090x_BLIND_SEARCH:
667 dprintk(FE_DEBUG, 1, "Blind Search");
668 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
669 state->DemodTimeout = 1500;
670 state->FecTimeout = 400;
671 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
672 state->DemodTimeout = 1000;
673 state->FecTimeout = 300;
674 } else { /*SR >20Msps*/
675 state->DemodTimeout = 700;
676 state->FecTimeout = 100;
677 }
678 break;
679
680 case STV090x_COLD_SEARCH:
681 case STV090x_WARM_SEARCH:
682 default:
683 dprintk(FE_DEBUG, 1, "Normal Search");
684 if (state->srate <= 1000000) { /*SR <=1Msps*/
685 state->DemodTimeout = 4500;
686 state->FecTimeout = 1700;
687 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
688 state->DemodTimeout = 2500;
689 state->FecTimeout = 1100;
690 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
691 state->DemodTimeout = 1000;
692 state->FecTimeout = 550;
693 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
694 state->DemodTimeout = 700;
695 state->FecTimeout = 250;
696 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
697 state->DemodTimeout = 400;
698 state->FecTimeout = 130;
699 } else { /*SR >20Msps*/
700 state->DemodTimeout = 300;
701 state->FecTimeout = 100;
702 }
703 break;
704 }
705
706 if (state->algo == STV090x_WARM_SEARCH)
707 state->DemodTimeout /= 2;
708}
709
710static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
711{
712 u32 sym;
713
714 if (srate > 6000000) {
715 sym = (srate / 1000) * 65536;
716 sym /= (state->mclk / 1000);
717 } else {
718 sym = (srate / 100) * 65536;
719 sym /= (state->mclk / 100);
720 }
721
722 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) /* MSB */
723 goto err;
724 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
725 goto err;
726 return 0;
727err:
728 dprintk(FE_ERROR, 1, "I/O error");
729 return -1;
730}
731
732static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
733{
734 u32 sym;
735
736 srate = 105 * (srate / 100);
737 if (srate > 6000000) {
738 sym = (srate / 1000) * 65536;
739 sym /= (clk / 1000);
740 } else {
741 sym = (srate / 100) * 65536;
742 sym /= (clk / 100);
743 }
744 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
745 goto err;
746 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
747 goto err;
748 return 0;
749err:
750 dprintk(FE_ERROR, 1, "I/O error");
751 return -1;
752}
753
754static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
755{
756 u32 sym;
757
758 srate = 95 * (srate / 100);
759 if (srate > 6000000) {
760 sym = (srate / 1000) * 65536;
761 sym /= (clk / 1000);
762 } else {
763 sym = (srate / 100) * 65536;
764 sym /= (clk / 100);
765 }
766 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
767 goto err;
768 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
769 goto err;
770 return 0;
771err:
772 dprintk(FE_ERROR, 1, "I/O error");
773 return -1;
774}
775
776static u32 stv090x_car_width(u32 srate, u32 rolloff)
777{
778 return srate + (srate * rolloff) / 100;
779}
780
781static int stv090x_set_vit_thacq(struct stv090x_state *state)
782{
783 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
784 goto err;
785 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
786 goto err;
787 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
788 goto err;
789 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
790 goto err;
791 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
792 goto err;
793 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
794 goto err;
795 return 0;
796err:
797 dprintk(FE_ERROR, 1, "I/O error");
798 return -1;
799}
800
801static int stv090x_set_vit_thtracq(struct stv090x_state *state)
802{
803 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
804 goto err;
805 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
806 goto err;
807 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
808 goto err;
809 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
810 goto err;
811 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
812 goto err;
813 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
814 goto err;
815 return 0;
816err:
817 dprintk(FE_ERROR, 1, "I/O error");
818 return -1;
819}
820
821static int stv090x_set_viterbi(struct stv090x_state *state)
822{
823 switch (state->search_mode) {
824 case STV090x_SEARCH_AUTO:
825 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
826 goto err;
827 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
828 goto err;
829 break;
830 case STV090x_SEARCH_DVBS1:
831 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
832 goto err;
833 switch (state->fec) {
834 case STV090x_PR12:
835 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
836 goto err;
837 break;
838
839 case STV090x_PR23:
840 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
841 goto err;
842 break;
843
844 case STV090x_PR34:
845 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
846 goto err;
847 break;
848
849 case STV090x_PR56:
850 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
851 goto err;
852 break;
853
854 case STV090x_PR78:
855 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
856 goto err;
857 break;
858
859 default:
860 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
861 goto err;
862 break;
863 }
864 break;
865 case STV090x_SEARCH_DSS:
866 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
867 goto err;
868 switch (state->fec) {
869 case STV090x_PR12:
870 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
871 goto err;
872 break;
873
874 case STV090x_PR23:
875 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
876 goto err;
877 break;
878
879 case STV090x_PR67:
880 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
881 goto err;
882 break;
883
884 default:
885 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
886 goto err;
887 break;
888 }
889 break;
890 default:
891 break;
892 }
893 return 0;
894err:
895 dprintk(FE_ERROR, 1, "I/O error");
896 return -1;
897}
898
899static int stv090x_stop_modcod(struct stv090x_state *state)
900{
901 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
902 goto err;
903 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
904 goto err;
905 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
906 goto err;
907 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
908 goto err;
909 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
910 goto err;
911 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
912 goto err;
913 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
914 goto err;
915 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
916 goto err;
917 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
918 goto err;
919 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
920 goto err;
921 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
922 goto err;
923 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
924 goto err;
925 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
926 goto err;
927 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
928 goto err;
929 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
930 goto err;
931 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
932 goto err;
933 return 0;
934err:
935 dprintk(FE_ERROR, 1, "I/O error");
936 return -1;
937}
938
939static int stv090x_activate_modcod(struct stv090x_state *state)
940{
941 u32 matype, modcod, f_mod, index;
942
943 if (state->dev_ver <= 0x11) {
944 msleep(5);
945 modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
946 matype = modcod & 0x03;
947 modcod = (modcod & 0x7f) >> 2;
948 index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
949
950 switch (matype) {
951 default:
952 case 0:
953 f_mod = 14;
954 break;
955 case 1:
956 f_mod = 13;
957 break;
958 case 2:
959 f_mod = 11;
960 break;
961 case 3:
962 f_mod = 7;
963 break;
964 }
965 if (matype <= 1) {
966 if (modcod % 2) {
967 if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
968 goto err;
969 } else {
970 if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
971 goto err;
972 }
973 }
974 } else if (state->dev_ver >= 0x12) {
975 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
976 goto err;
977 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
978 goto err;
979 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
980 goto err;
981 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
982 goto err;
983 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
984 goto err;
985 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
986 goto err;
987 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
988 goto err;
989 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
990 goto err;
991 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
992 goto err;
993 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
994 goto err;
995 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
996 goto err;
997 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
998 goto err;
999 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1000 goto err;
1001 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1002 goto err;
1003 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1004 goto err;
1005 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1006 goto err;
1007 }
1008 return 0;
1009err:
1010 dprintk(FE_ERROR, 1, "I/O error");
1011 return -1;
1012}
1013
1014static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1015{
1016 u32 reg;
1017
1018 switch (state->demod) {
1019 case STV090x_DEMODULATOR_0:
1020 mutex_lock(&demod_lock);
1021 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1022 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1023 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1024 goto err;
1025 mutex_unlock(&demod_lock);
1026 break;
1027
1028 case STV090x_DEMODULATOR_1:
1029 mutex_lock(&demod_lock);
1030 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1031 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1032 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1033 goto err;
1034 mutex_unlock(&demod_lock);
1035 break;
1036
1037 default:
1038 dprintk(FE_ERROR, 1, "Wrong demodulator!");
1039 break;
1040 }
1041 return 0;
1042err:
1043 mutex_unlock(&demod_lock);
1044 dprintk(FE_ERROR, 1, "I/O error");
1045 return -1;
1046}
1047
1048static int stv090x_delivery_search(struct stv090x_state *state)
1049{
1050 u32 reg;
1051
1052 switch (state->search_mode) {
1053 case STV090x_SEARCH_DVBS1:
1054 case STV090x_SEARCH_DSS:
1055 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1056 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1057 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1058 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1059 goto err;
1060
1061 /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
1062 if (stv090x_vitclk_ctl(state, 0) < 0)
1063 goto err;
1064
1065 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1066 goto err;
1067 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1068 goto err;
1069 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1070 goto err;
1071
1072 stv090x_set_vit_thacq(state);
1073 stv090x_set_viterbi(state);
1074 break;
1075
1076 case STV090x_SEARCH_DVBS2:
1077 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1078 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1079 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1080 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1081 goto err;
1082 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1083 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1084 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1085 goto err;
1086
1087 if (stv090x_vitclk_ctl(state, 1) < 0)
1088 goto err;
1089
1090 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1091 goto err;
1092 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1093 goto err;
1094 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1095 goto err;
1096
1097 if (state->demod_mode != STV090x_SINGLE) {
1098 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1099 stv090x_stop_modcod(state);
1100 else
1101 stv090x_activate_modcod(state);
1102 }
1103 break;
1104
1105 case STV090x_SEARCH_AUTO:
1106 default:
1107 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1108 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1109 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1110 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1111 goto err;
1112 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1113 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1114 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1115 goto err;
1116
1117 if (stv090x_vitclk_ctl(state, 1) < 0)
1118 goto err;
1119
1120 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1121 goto err;
1122 if (STV090x_WRITE_DEMOD(state, ACLC, 0x09) < 0)
1123 goto err;
1124 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1125 goto err;
1126
1127 if (state->demod_mode != STV090x_SINGLE) {
1128 if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
1129 stv090x_stop_modcod(state);
1130 else
1131 stv090x_activate_modcod(state);
1132 }
1133 stv090x_set_vit_thacq(state);
1134 stv090x_set_viterbi(state);
1135 break;
1136 }
1137 return 0;
1138err:
1139 dprintk(FE_ERROR, 1, "I/O error");
1140 return -1;
1141}
1142
1143static int stv090x_start_search(struct stv090x_state *state)
1144{
1145 u32 reg;
1146
1147 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1148 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1149 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1150 goto err;
1151
1152 if (state->dev_ver == 0x10) {
1153 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1154 goto err;
1155 }
1156 if (state->dev_ver < 0x20) {
1157 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1158 goto err;
1159 }
1160 if (state->srate <= 5000000) {
1161 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1162 goto err;
1163 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1164 goto err;
1165 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
1166 goto err;
1167 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1168 goto err;
1169 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1170 goto err;
1171
1172 /*enlarge the timing bandwith for Low SR*/
1173 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1174 goto err;
1175 } else {
1176 /* If the symbol rate is >5 Msps
1177 Set The carrier search up and low to auto mode */
1178 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1179 goto err;
1180 /*reduce the timing bandwith for high SR*/
1181 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1182 goto err;
1183 }
1184 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1185 goto err;
1186 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1187 goto err;
1188
1189 if (state->dev_ver >= 0x20) {
1190 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1191 goto err;
1192 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1193 goto err;
1194
1195 if ((state->search_mode == STV090x_DVBS1) ||
1196 (state->search_mode == STV090x_DSS) ||
1197 (state->search_mode == STV090x_SEARCH_AUTO)) {
1198
1199 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1200 goto err;
1201 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1202 goto err;
1203 }
1204 }
1205
1206 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1207 goto err;
1208 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1209 goto err;
1210 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1211 goto err;
1212
1213 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1214 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1215 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1216 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1217 goto err;
1218 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1219 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1220 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1221 goto err;
1222
1223 if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
1224 if (state->srate < 10000000) {
1225 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1226 goto err;
1227 } else {
1228 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1229 goto err;
1230 }
1231 } else {
1232 if (state->srate < 10000000) {
1233 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1234 goto err;
1235 } else {
1236 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1237 goto err;
1238 }
1239 }
1240
1241 switch (state->algo) {
1242 case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
1243 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1244 goto err;
1245 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1246 goto err;
1247 break;
1248
1249 case STV090x_COLD_SEARCH:/*The symbol rate is known*/
1250 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1251 goto err;
1252 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1253 goto err;
1254 break;
1255
1256 default:
1257 break;
1258 }
1259 return 0;
1260err:
1261 dprintk(FE_ERROR, 1, "I/O error");
1262 return -1;
1263}
1264
1265static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1266{
1267 u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
1268 s32 i, j, steps, dir;
1269
1270 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1271 goto err;
1272 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1273 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1274 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1275 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1276 goto err;
1277
1278 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1279 goto err;
1280 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1281 goto err;
1282 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1283 goto err;
1284 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1285 goto err;
1286 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1287 goto err;
1288 stv090x_set_srate(state, 1000000);
1289
1290 steps = -1 + state->search_range / 1000000;
1291 steps /= 2;
1292 steps = (2 * steps) + 1;
1293 if (steps < 0)
1294 steps = 1;
1295
1296 dir = 1;
1297 freq_step = (1000000 * 256) / (state->mclk / 256);
1298 freq_init = 0;
1299
1300 for (i = 0; i < steps; i++) {
1301 if (dir > 0)
1302 freq_init = freq_init + (freq_step * i);
1303 else
1304 freq_init = freq_init - (freq_step * i);
1305
1306 dir = -1;
1307
1308 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1309 goto err;
1310 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1311 goto err;
1312 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1313 goto err;
1314 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1315 goto err;
1316 msleep(10);
1317 for (j = 0; j < 10; j++) {
1318 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1319 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1320 }
1321 agc2 /= 10;
1322 agc2_min = 0xffff;
1323 if (agc2 < 0xffff)
1324 agc2_min = agc2;
1325 }
1326
1327 return agc2_min;
1328err:
1329 dprintk(FE_ERROR, 1, "I/O error");
1330 return -1;
1331}
1332
1333static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1334{
1335 u8 r3, r2, r1, r0;
1336 s32 srate, int_1, int_2, tmp_1, tmp_2;
1337 u32 pow2;
1338
1339 r3 = STV090x_READ_DEMOD(state, SFR3);
1340 r2 = STV090x_READ_DEMOD(state, SFR2);
1341 r1 = STV090x_READ_DEMOD(state, SFR1);
1342 r0 = STV090x_READ_DEMOD(state, SFR0);
1343
1344 srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
1345
1346 pow2 = 1 << 16;
1347 int_1 = clk / pow2;
1348 int_2 = srate / pow2;
1349
1350 tmp_1 = clk % pow2;
1351 tmp_2 = srate % pow2;
1352
1353 srate = (int_1 * int_2) +
1354 ((int_1 * tmp_2) / pow2) +
1355 ((int_2 * tmp_1) / pow2);
1356
1357 return srate;
1358}
1359
1360static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1361{
1362 struct dvb_frontend *fe = &state->frontend;
1363
1364 int tmg_lock = 0, i;
1365 s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
1366 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1367
1368 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1369 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1370 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1371 goto err;
1372 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1373 goto err;
1374 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1375 goto err;
1376 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1377 goto err;
1378 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1379 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1380 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
1381 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1382 goto err;
1383
1384 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1385 goto err;
1386 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1387 goto err;
1388 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1389 goto err;
1390 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1391 goto err;
1392 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1393 goto err;
1394 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
1395 goto err;
1396
1397 if (state->dev_ver >= 0x20) {
1398 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1399 goto err;
1400 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1401 goto err;
1402 } else {
1403 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1404 goto err;
1405 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
1406 goto err;
1407 }
1408
1409 if (state->srate <= 2000000)
1410 car_step = 1000;
1411 else if (state->srate <= 5000000)
1412 car_step = 2000;
1413 else if (state->srate <= 12000000)
1414 car_step = 3000;
1415 else
1416 car_step = 5000;
1417
1418 steps = -1 + ((state->search_range / 1000) / car_step);
1419 steps /= 2;
1420 steps = (2 * steps) + 1;
1421 if (steps < 0)
1422 steps = 1;
1423 else if (steps > 10) {
1424 steps = 11;
1425 car_step = (state->search_range / 1000) / 10;
1426 }
1427 cur_step = 0;
1428 dir = 1;
1429 freq = state->frequency;
1430
1431 while ((!tmg_lock) && (cur_step < steps)) {
1432 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1433 goto err;
1434 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1435 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
1436 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1437 goto err;
1438 msleep(50);
1439 for (i = 0; i < 10; i++) {
1440 reg = STV090x_READ_DEMOD(state, DSTATUS);
1441 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1442 tmg_cpt++;
1443 agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
1444 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1445 }
1446 agc2 /= 10;
1447 srate_coarse = stv090x_get_srate(state, state->mclk);
1448 cur_step++;
1449 dir *= -1;
1450 if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
1451 tmg_lock = 1;
1452 else if (cur_step < steps) {
1453 if (dir > 0)
1454 freq += cur_step * car_step;
1455 else
1456 freq -= cur_step * car_step;
1457
1458 /* Setup tuner */
1459 stv090x_i2c_gate_ctrl(fe, 1);
1460
1461 if (state->config->tuner_set_frequency)
1462 state->config->tuner_set_frequency(fe, state->frequency);
1463
1464 if (state->config->tuner_set_bandwidth)
1465 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1466
1467 stv090x_i2c_gate_ctrl(fe, 0);
1468 msleep(50);
1469 stv090x_i2c_gate_ctrl(fe, 1);
1470
1471 if (state->config->tuner_get_status)
1472 state->config->tuner_get_status(fe, &reg);
1473
1474 if (reg)
1475 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1476 else
1477 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1478
1479 stv090x_i2c_gate_ctrl(fe, 0);
1480
1481 }
1482 }
1483 if (!tmg_lock)
1484 srate_coarse = 0;
1485 else
1486 srate_coarse = stv090x_get_srate(state, state->mclk);
1487
1488 return srate_coarse;
1489err:
1490 dprintk(FE_ERROR, 1, "I/O error");
1491 return -1;
1492}
1493
1494static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1495{
1496 u32 srate_coarse, freq_coarse, sym, reg;
1497
1498 srate_coarse = stv090x_get_srate(state, state->mclk);
1499 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1500 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1501 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1502
1503 if (sym < state->srate)
1504 srate_coarse = 0;
1505 else {
1506 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1507 goto err;
1508 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
1509 goto err;
1510 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1511 goto err;
1512 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1513 goto err;
1514 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1515 goto err;
1516 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1517 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1518 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1519 goto err;
1520
1521 if (state->dev_ver >= 0x20) {
1522 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1523 goto err;
1524 } else {
1525 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1526 goto err;
1527 }
1528
1529 if (srate_coarse > 3000000) {
1530 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1531 sym = (sym / 1000) * 65536;
1532 sym /= (state->mclk / 1000);
1533 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1534 goto err;
1535 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1536 goto err;
1537 sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
1538 sym = (sym / 1000) * 65536;
1539 sym /= (state->mclk / 1000);
1540 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1541 goto err;
1542 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1543 goto err;
1544 sym = (srate_coarse / 1000) * 65536;
1545 sym /= (state->mclk / 1000);
1546 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1547 goto err;
1548 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1549 goto err;
1550 } else {
1551 sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
1552 sym = (sym / 100) * 65536;
1553 sym /= (state->mclk / 100);
1554 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1555 goto err;
1556 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1557 goto err;
1558 sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
1559 sym = (sym / 100) * 65536;
1560 sym /= (state->mclk / 100);
1561 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1562 goto err;
1563 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1564 goto err;
1565 sym = (srate_coarse / 100) * 65536;
1566 sym /= (state->mclk / 100);
1567 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1568 goto err;
1569 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1570 goto err;
1571 }
1572 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1573 goto err;
1574 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1575 goto err;
1576 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1577 goto err;
1578 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1579 goto err;
1580 }
1581
1582 return srate_coarse;
1583
1584err:
1585 dprintk(FE_ERROR, 1, "I/O error");
1586 return -1;
1587}
1588
1589static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1590{
1591 s32 timer = 0, lock = 0;
1592 u32 reg;
1593 u8 stat;
1594
1595 while ((timer < timeout) && (!lock)) {
1596 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1597 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1598
1599 switch (stat) {
1600 case 0: /* searching */
1601 case 1: /* first PLH detected */
1602 default:
1603 dprintk(FE_DEBUG, 1, "Demodulator searching ..");
1604 lock = 0;
1605 break;
1606 case 2: /* DVB-S2 mode */
1607 case 3: /* DVB-S1/legacy mode */
1608 reg = STV090x_READ_DEMOD(state, DSTATUS);
1609 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1610 break;
1611 }
1612
1613 if (!lock)
1614 msleep(10);
1615 else
1616 dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
1617
1618 timer += 10;
1619 }
1620 return lock;
1621}
1622
1623static int stv090x_blind_search(struct stv090x_state *state)
1624{
1625 u32 agc2, reg, srate_coarse;
1626 s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
1627 u8 k_ref, k_max, k_min;
1628 int coarse_fail, lock;
1629
1630 if (state->dev_ver < 0x20) {
1631 k_max = 233;
1632 k_min = 143;
1633 } else {
1634 k_max = 120;
1635 k_min = 30;
1636 }
1637
1638 agc2 = stv090x_get_agc2_min_level(state);
1639
1640 if (agc2 > STV090x_SEARCH_AGC2_TH) {
1641 lock = 0;
1642 } else {
1643 if (state->dev_ver == 0x10) {
1644 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
1645 goto err;
1646 }
1647 if (state->dev_ver < 0x20) {
1648 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
1649 goto err;
1650 }
1651
1652 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1653 goto err;
1654 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1655 goto err;
1656 if (state->dev_ver >= 0x20) {
1657 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1658 goto err;
1659 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1660 goto err;
1661 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1662 goto err;
1663 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
1664 goto err;
1665 }
1666
1667 k_ref = k_max;
1668 do {
1669 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
1670 goto err;
1671 if (stv090x_srate_srch_coarse(state) != 0) {
1672 srate_coarse = stv090x_srate_srch_fine(state);
1673 if (srate_coarse != 0) {
1674 stv090x_get_lock_tmg(state);
1675 lock = stv090x_get_dmdlock(state, timeout_dmd);
1676 } else {
1677 lock = 0;
1678 }
1679 } else {
1680 cpt_fail = 0;
1681 agc2_ovflw = 0;
1682 for (i = 0; i < 10; i++) {
1683 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1684 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1685 if (agc2 >= 0xff00)
1686 agc2_ovflw++;
1687 reg = STV090x_READ_DEMOD(state, DSTATUS2);
1688 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
1689 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
1690
1691 cpt_fail++;
1692 }
1693 if ((cpt_fail > 7) || (agc2_ovflw > 7))
1694 coarse_fail = 1;
1695
1696 lock = 0;
1697 }
1698 k_ref -= 30;
1699 } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
1700 }
1701
1702 return lock;
1703
1704err:
1705 dprintk(FE_ERROR, 1, "I/O error");
1706 return -1;
1707}
1708
1709static int stv090x_chk_tmg(struct stv090x_state *state)
1710{
1711 u32 reg;
1712 s32 tmg_cpt, i;
1713 u8 freq, tmg_thh, tmg_thl;
1714 int tmg_lock;
1715
1716 freq = STV090x_READ_DEMOD(state, CARFREQ);
1717 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
1718 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
1719 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1720 goto err;
1721 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1722 goto err;
1723
1724 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1725 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
1726 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1727 goto err;
1728 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
1729 goto err;
1730
1731 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
1732 goto err;
1733 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
1734 goto err;
1735
1736 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
1737 goto err;
1738 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1739 goto err;
1740 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
1741 goto err;
1742
1743 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
1744 goto err;
1745 msleep(10);
1746
1747 for (i = 0; i < 10; i++) {
1748 reg = STV090x_READ_DEMOD(state, DSTATUS);
1749 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1750 tmg_cpt++;
1751 msleep(1);
1752 }
1753 if (tmg_cpt >= 3)
1754 tmg_lock = 1;
1755
1756 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1757 goto err;
1758 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
1759 goto err;
1760 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
1761 goto err;
1762
1763 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
1764 goto err;
1765 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
1766 goto err;
1767 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
1768 goto err;
1769
1770 return tmg_lock;
1771
1772err:
1773 dprintk(FE_ERROR, 1, "I/O error");
1774 return -1;
1775}
1776
1777static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
1778{
1779 struct dvb_frontend *fe = &state->frontend;
1780
1781 u32 reg;
1782 s32 car_step, steps, cur_step, dir, freq, timeout_lock;
1783 int lock = 0;
1784
1785 if (state->srate >= 10000000)
1786 timeout_lock = timeout_dmd / 3;
1787 else
1788 timeout_lock = timeout_dmd / 2;
1789
1790 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
1791 if (!lock) {
1792 if (state->srate >= 10000000) {
1793 if (stv090x_chk_tmg(state)) {
1794 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1795 goto err;
1796 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1797 goto err;
1798 lock = stv090x_get_dmdlock(state, timeout_dmd);
1799 } else {
1800 lock = 0;
1801 }
1802 } else {
1803 if (state->srate <= 4000000)
1804 car_step = 1000;
1805 else if (state->srate <= 7000000)
1806 car_step = 2000;
1807 else if (state->srate <= 10000000)
1808 car_step = 3000;
1809 else
1810 car_step = 5000;
1811
1812 steps = (state->search_range / 1000) / car_step;
1813 steps /= 2;
1814 steps = 2 * (steps + 1);
1815 if (steps < 0)
1816 steps = 2;
1817 else if (steps > 12)
1818 steps = 12;
1819
1820 cur_step = 1;
1821 dir = 1;
1822
1823 if (!lock) {
1824 freq = state->frequency;
1825 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
1826 while ((cur_step <= steps) && (!lock)) {
1827 if (dir > 0)
1828 freq += cur_step * car_step;
1829 else
1830 freq -= cur_step * car_step;
1831
1832 /* Setup tuner */
1833 stv090x_i2c_gate_ctrl(fe, 1);
1834
1835 if (state->config->tuner_set_frequency)
1836 state->config->tuner_set_frequency(fe, state->frequency);
1837
1838 if (state->config->tuner_set_bandwidth)
1839 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
1840
1841 stv090x_i2c_gate_ctrl(fe, 0);
1842
1843 msleep(50);
1844
1845 stv090x_i2c_gate_ctrl(fe, 1);
1846
1847 if (state->config->tuner_get_status)
1848 state->config->tuner_get_status(fe, &reg);
1849
1850 if (reg)
1851 dprintk(FE_DEBUG, 1, "Tuner phase locked");
1852 else
1853 dprintk(FE_DEBUG, 1, "Tuner unlocked");
1854
1855 stv090x_i2c_gate_ctrl(fe, 0);
1856
1857 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
1858 if (state->delsys == STV090x_DVBS2) {
1859 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1860 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1861 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1862 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1863 goto err;
1864 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1865 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1866 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1867 goto err;
1868 }
1869 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1870 goto err;
1871 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1872 goto err;
1873 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1874 goto err;
1875 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1876 goto err;
1877 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
1878
1879 dir *= -1;
1880 cur_step++;
1881 }
1882 }
1883 }
1884 }
1885
1886 return lock;
1887
1888err:
1889 dprintk(FE_ERROR, 1, "I/O error");
1890 return -1;
1891}
1892
1893static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
1894{
1895 s32 timeout, inc, steps_max, srate, car_max;
1896
1897 srate = state->srate;
1898 car_max = state->search_range / 1000;
1899 car_max = 65536 * (car_max / 2);
1900 car_max /= (state->mclk / 1000);
1901
1902 if (car_max > 0x4000)
1903 car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
1904
1905 inc = srate;
1906 inc /= state->mclk / 1000;
1907 inc *= 256;
1908 inc *= 256;
1909 inc /= 1000;
1910
1911 switch (state->algo) {
1912 case STV090x_SEARCH_DVBS1:
1913 case STV090x_SEARCH_DSS:
1914 inc *= 3; /* freq step = 3% of srate */
1915 timeout = 20;
1916 break;
1917
1918 case STV090x_SEARCH_DVBS2:
1919 inc *= 4;
1920 timeout = 25;
1921 break;
1922
1923 case STV090x_SEARCH_AUTO:
1924 default:
1925 inc *= 3;
1926 timeout = 25;
1927 break;
1928 }
1929 inc /= 100;
1930 if ((inc > car_max) || (inc < 0))
1931 inc = car_max / 2; /* increment <= 1/8 Mclk */
1932
1933 timeout *= 27500; /* 27.5 Msps reference */
1934 if (srate > 0)
1935 timeout /= (srate / 1000);
1936
1937 if ((timeout > 100) || (timeout < 0))
1938 timeout = 100;
1939
1940 steps_max = (car_max / inc) + 1; /* min steps = 3 */
1941 if ((steps_max > 100) || (steps_max < 0)) {
1942 steps_max = 100; /* max steps <= 100 */
1943 inc = car_max / steps_max;
1944 }
1945 *freq_inc = inc;
1946 *timeout_sw = timeout;
1947 *steps = steps_max;
1948
1949 return 0;
1950}
1951
1952static int stv090x_chk_signal(struct stv090x_state *state)
1953{
1954 s32 offst_car, agc2, car_max;
1955 int no_signal;
1956
1957 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
1958 offst_car |= STV090x_READ_DEMOD(state, CFR1);
1959
1960 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
1961 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
1962 car_max = state->search_range / 1000;
1963
1964 car_max += (car_max / 10); /* 10% margin */
1965 car_max = (65536 * car_max / 2);
1966 car_max /= state->mclk / 1000;
1967
1968 if (car_max > 0x4000)
1969 car_max = 0x4000;
1970
1971 if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
1972 no_signal = 1;
1973 dprintk(FE_DEBUG, 1, "No Signal");
1974 } else {
1975 no_signal = 0;
1976 dprintk(FE_DEBUG, 1, "Found Signal");
1977 }
1978
1979 return no_signal;
1980}
1981
1982static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
1983{
1984 int no_signal, lock = 0;
1985 s32 cpt_step, offst_freq, car_max;
1986 u32 reg;
1987
1988 car_max = state->search_range / 1000;
1989 car_max += (car_max / 10);
1990 car_max = (65536 * car_max / 2);
1991 car_max /= (state->mclk / 1000);
1992 if (car_max > 0x4000)
1993 car_max = 0x4000;
1994
1995 if (zigzag)
1996 offst_freq = 0;
1997 else
1998 offst_freq = -car_max + inc;
1999
2000 cpt_step = 0;
2001 do {
2002 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2003 goto err;
2004 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2005 goto err;
2006 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2007 goto err;
2008 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2009 goto err;
2010
2011 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2012 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2013 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2014 goto err;
2015
2016 if (state->dev_ver == 0x12) {
2017 reg = STV090x_READ_DEMOD(state, TSCFGH);
2018 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
2019 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2020 goto err;
2021 }
2022
2023 if (zigzag) {
2024 if (offst_freq >= 0)
2025 offst_freq = -offst_freq - 2 * inc;
2026 else
2027 offst_freq = -offst_freq;
2028 } else {
2029 offst_freq += 2 * inc;
2030 }
2031
2032 lock = stv090x_get_dmdlock(state, timeout);
2033 no_signal = stv090x_chk_signal(state);
2034
2035 } while ((!lock) &&
2036 (!no_signal) &&
2037 ((offst_freq - inc) < car_max) &&
2038 ((offst_freq + inc) > -car_max) &&
2039 (cpt_step < steps_max));
2040
2041 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2042 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2043 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2044 goto err;
2045
2046 return lock;
2047err:
2048 dprintk(FE_ERROR, 1, "I/O error");
2049 return -1;
2050}
2051
2052static int stv090x_sw_algo(struct stv090x_state *state)
2053{
2054 int no_signal, zigzag, lock = 0;
2055 u32 reg;
2056
2057 s32 dvbs2_fly_wheel;
2058 s32 inc, timeout_step, trials, steps_max;
2059
2060 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
2061
2062 switch (state->algo) {
2063 case STV090x_SEARCH_DVBS1:
2064 case STV090x_SEARCH_DSS:
2065 /* accelerate the frequency detector */
2066 if (state->dev_ver >= 0x20) {
2067 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2068 goto err;
2069 } else {
2070 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2071 goto err;
2072 }
2073 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2074 goto err;
2075 zigzag = 0;
2076 break;
2077
2078 case STV090x_SEARCH_DVBS2:
2079 if (state->dev_ver >= 0x20) {
2080 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2081 goto err;
2082 } else {
2083 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2084 goto err;
2085 }
2086 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2087 goto err;
2088 zigzag = 1;
2089 break;
2090
2091 case STV090x_SEARCH_AUTO:
2092 default:
2093 /* accelerate the frequency detector */
2094 if (state->dev_ver >= 0x20) {
2095 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2096 goto err;
2097 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2098 goto err;
2099 } else {
2100 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
2101 goto err;
2102 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2103 goto err;
2104 }
2105 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x69) < 0)
2106 goto err;
2107 zigzag = 0;
2108 break;
2109 }
2110
2111 trials = 0;
2112 do {
2113 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2114 no_signal = stv090x_chk_signal(state);
2115 trials++;
2116
2117 /*run the SW search 2 times maximum*/
2118 if (lock || no_signal || (trials == 2)) {
2119 /*Check if the demod is not losing lock in DVBS2*/
2120 if (state->dev_ver >= 0x20) {
2121 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2122 goto err;
2123 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2124 goto err;
2125 } else {
2126 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
2127 goto err;
2128 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
2129 goto err;
2130 }
2131
2132 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2133 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2134 /*Check if the demod is not losing lock in DVBS2*/
2135 msleep(timeout_step);
2136 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2137 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2138 if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
2139 msleep(timeout_step);
2140 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2141 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2142 }
2143 if (dvbs2_fly_wheel < 0xd) {
2144 /*FALSE lock, The demod is loosing lock */
2145 lock = 0;
2146 if (trials < 2) {
2147 if (state->dev_ver >= 0x20) {
2148 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2149 goto err;
2150 } else {
2151 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
2152 goto err;
2153 }
2154 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2155 goto err;
2156 }
2157 }
2158 }
2159 }
2160 } while ((!lock) && (trials < 2) && (!no_signal));
2161
2162 return lock;
2163err:
2164 dprintk(FE_ERROR, 1, "I/O error");
2165 return -1;
2166}
2167
2168static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2169{
2170 u32 reg;
2171 enum stv090x_delsys delsys;
2172
2173 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2174 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2175 delsys = STV090x_DVBS2;
2176 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2177 reg = STV090x_READ_DEMOD(state, FECM);
2178 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2179 delsys = STV090x_DSS;
2180 else
2181 delsys = STV090x_DVBS1;
2182 } else {
2183 delsys = STV090x_ERROR;
2184 }
2185
2186 return delsys;
2187}
2188
2189/* in Hz */
2190static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2191{
2192 s32 derot, int_1, int_2, tmp_1, tmp_2;
2193 u32 pow2;
2194
2195 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2196 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2197 derot |= STV090x_READ_DEMOD(state, CFR0);
2198
2199 derot = comp2(derot, 24);
2200 pow2 = 1 << 12;
2201 int_1 = state->mclk / pow2;
2202 int_2 = derot / pow2;
2203
2204 tmp_1 = state->mclk % pow2;
2205 tmp_2 = derot % pow2;
2206
2207 derot = (int_1 * int_2) +
2208 ((int_1 * tmp_2) / pow2) +
2209 ((int_1 * tmp_1) / pow2);
2210
2211 return derot;
2212}
2213
2214static int stv090x_get_viterbi(struct stv090x_state *state)
2215{
2216 u32 reg, rate;
2217
2218 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2219 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2220
2221 switch (rate) {
2222 case 13:
2223 state->fec = STV090x_PR12;
2224 break;
2225
2226 case 18:
2227 state->fec = STV090x_PR23;
2228 break;
2229
2230 case 21:
2231 state->fec = STV090x_PR34;
2232 break;
2233
2234 case 24:
2235 state->fec = STV090x_PR56;
2236 break;
2237
2238 case 25:
2239 state->fec = STV090x_PR67;
2240 break;
2241
2242 case 26:
2243 state->fec = STV090x_PR78;
2244 break;
2245
2246 default:
2247 state->fec = STV090x_PRERR;
2248 break;
2249 }
2250
2251 return 0;
2252}
2253
2254static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2255{
2256 struct dvb_frontend *fe = &state->frontend;
2257
2258 u8 tmg;
2259 u32 reg;
2260 s32 i = 0, offst_freq;
2261
2262 msleep(5);
2263
2264 if (state->algo == STV090x_BLIND_SEARCH) {
2265 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2266 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2267 while ((i <= 50) && (!tmg) && (tmg != 0xff)) {
2268 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2269 msleep(5);
2270 i += 5;
2271 }
2272 }
2273 state->delsys = stv090x_get_std(state);
2274
2275 stv090x_i2c_gate_ctrl(fe, 1);
2276
2277 if (state->config->tuner_get_frequency)
2278 state->config->tuner_get_frequency(fe, &state->frequency);
2279
2280 stv090x_i2c_gate_ctrl(fe, 0);
2281
2282 offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
2283 state->frequency += offst_freq;
2284 stv090x_get_viterbi(state);
2285 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2286 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2287 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2288 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2289 reg = STV090x_READ_DEMOD(state, TMGOBS);
2290 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2291 reg = STV090x_READ_DEMOD(state, FECM);
2292 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2293
2294 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2295
2296 stv090x_i2c_gate_ctrl(fe, 1);
2297
2298 if (state->config->tuner_get_frequency)
2299 state->config->tuner_get_frequency(fe, &state->frequency);
2300
2301 stv090x_i2c_gate_ctrl(fe, 0);
2302
2303 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2304 return STV090x_RANGEOK;
2305 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2306 return STV090x_RANGEOK;
2307 else
2308 return STV090x_OUTOFRANGE; /* Out of Range */
2309 } else {
2310 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2311 return STV090x_RANGEOK;
2312 else
2313 return STV090x_OUTOFRANGE;
2314 }
2315
2316 return STV090x_OUTOFRANGE;
2317}
2318
2319static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2320{
2321 s32 offst_tmg;
2322 s32 pow2;
2323
2324 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2325 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2326 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2327
2328 pow2 = 1 << 24;
2329
2330 offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
2331 if (!offst_tmg)
2332 offst_tmg = 1;
2333
2334 offst_tmg = ((s32) srate * 10) / (pow2 / offst_tmg);
2335 offst_tmg /= 320;
2336
2337 return offst_tmg;
2338}
2339
2340static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2341{
2342 u8 aclc = 0x29;
2343 s32 i;
2344 struct stv090x_long_frame_crloop *car_loop;
2345
2346 if (state->dev_ver <= 0x12)
2347 car_loop = stv090x_s2_crl;
2348 else if (state->dev_ver == 0x20)
2349 car_loop = stv090x_s2_crl_cut20;
2350 else
2351 car_loop = stv090x_s2_crl;
2352
2353
2354 if (modcod < STV090x_QPSK_12) {
2355 i = 0;
2356 while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2357 i++;
2358
2359 if (i >= 3)
2360 i = 2;
2361
2362 } else {
2363 i = 0;
2364 while ((i < 14) && (modcod != car_loop[i].modcod))
2365 i++;
2366
2367 if (i >= 14) {
2368 i = 0;
2369 while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
2370 i++;
2371
2372 if (i >= 11)
2373 i = 10;
2374 }
2375 }
2376
2377 if (modcod <= STV090x_QPSK_25) {
2378 if (pilots) {
2379 if (state->srate <= 3000000)
2380 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
2381 else if (state->srate <= 7000000)
2382 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
2383 else if (state->srate <= 15000000)
2384 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
2385 else if (state->srate <= 25000000)
2386 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
2387 else
2388 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
2389 } else {
2390 if (state->srate <= 3000000)
2391 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
2392 else if (state->srate <= 7000000)
2393 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
2394 else if (state->srate <= 15000000)
2395 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
2396 else if (state->srate <= 25000000)
2397 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
2398 else
2399 aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
2400 }
2401
2402 } else if (modcod <= STV090x_8PSK_910) {
2403 if (pilots) {
2404 if (state->srate <= 3000000)
2405 aclc = car_loop[i].crl_pilots_on_2;
2406 else if (state->srate <= 7000000)
2407 aclc = car_loop[i].crl_pilots_on_5;
2408 else if (state->srate <= 15000000)
2409 aclc = car_loop[i].crl_pilots_on_10;
2410 else if (state->srate <= 25000000)
2411 aclc = car_loop[i].crl_pilots_on_20;
2412 else
2413 aclc = car_loop[i].crl_pilots_on_30;
2414 } else {
2415 if (state->srate <= 3000000)
2416 aclc = car_loop[i].crl_pilots_off_2;
2417 else if (state->srate <= 7000000)
2418 aclc = car_loop[i].crl_pilots_off_5;
2419 else if (state->srate <= 15000000)
2420 aclc = car_loop[i].crl_pilots_off_10;
2421 else if (state->srate <= 25000000)
2422 aclc = car_loop[i].crl_pilots_off_20;
2423 else
2424 aclc = car_loop[i].crl_pilots_off_30;
2425 }
2426 } else { /* 16APSK and 32APSK */
2427 if (state->srate <= 3000000)
2428 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
2429 else if (state->srate <= 7000000)
2430 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
2431 else if (state->srate <= 15000000)
2432 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
2433 else if (state->srate <= 25000000)
2434 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
2435 else
2436 aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
2437 }
2438
2439 return aclc;
2440}
2441
2442static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2443{
2444 s32 index = 0;
2445 u8 aclc = 0x0b;
2446
2447 switch (state->modulation) {
2448 case STV090x_QPSK:
2449 default:
2450 index = 0;
2451 break;
2452 case STV090x_8PSK:
2453 index = 1;
2454 break;
2455 case STV090x_16APSK:
2456 index = 2;
2457 break;
2458 case STV090x_32APSK:
2459 index = 3;
2460 break;
2461 }
2462
2463 switch (state->dev_ver) {
2464 case 0x20:
2465 if (state->srate <= 3000000)
2466 aclc = stv090x_s2_short_crl[index].crl_cut20_2;
2467 else if (state->srate <= 7000000)
2468 aclc = stv090x_s2_short_crl[index].crl_cut20_5;
2469 else if (state->srate <= 15000000)
2470 aclc = stv090x_s2_short_crl[index].crl_cut20_10;
2471 else if (state->srate <= 25000000)
2472 aclc = stv090x_s2_short_crl[index].crl_cut20_20;
2473 else
2474 aclc = stv090x_s2_short_crl[index].crl_cut20_30;
2475 break;
2476
2477 case 0x12:
2478 default:
2479 if (state->srate <= 3000000)
2480 aclc = stv090x_s2_short_crl[index].crl_cut12_2;
2481 else if (state->srate <= 7000000)
2482 aclc = stv090x_s2_short_crl[index].crl_cut12_5;
2483 else if (state->srate <= 15000000)
2484 aclc = stv090x_s2_short_crl[index].crl_cut12_10;
2485 else if (state->srate <= 25000000)
2486 aclc = stv090x_s2_short_crl[index].crl_cut12_20;
2487 else
2488 aclc = stv090x_s2_short_crl[index].crl_cut12_30;
2489 break;
2490 }
2491
2492 return aclc;
2493}
2494
2495static int stv090x_optimize_track(struct stv090x_state *state)
2496{
2497 struct dvb_frontend *fe = &state->frontend;
2498
2499 enum stv090x_rolloff rolloff;
2500 enum stv090x_modcod modcod;
2501
2502 s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
2503 u32 reg;
2504
2505 srate = stv090x_get_srate(state, state->mclk);
2506 srate += stv090x_get_tmgoffst(state, srate);
2507
2508 switch (state->delsys) {
2509 case STV090x_DVBS1:
2510 case STV090x_DSS:
2511 if (state->algo == STV090x_SEARCH_AUTO) {
2512 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2513 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2514 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2515 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2516 goto err;
2517 }
2518 reg = STV090x_READ_DEMOD(state, DEMOD);
2519 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2520 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2521 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2522 goto err;
2523 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2524 goto err;
2525 break;
2526
2527 case STV090x_DVBS2:
2528 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2529 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2530 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2531 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2532 goto err;
2533 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2534 goto err;
2535 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2536 goto err;
2537 if (state->frame_len == STV090x_LONG_FRAME) {
2538 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2539 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2540 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2541 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2542 if (modcod <= STV090x_QPSK_910) {
2543 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2544 } else if (modcod <= STV090x_8PSK_910) {
2545 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2546 goto err;
2547 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2548 goto err;
2549 }
2550 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2551 if (modcod <= STV090x_16APSK_910) {
2552 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2553 goto err;
2554 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2555 goto err;
2556 } else {
2557 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2558 goto err;
2559 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2560 goto err;
2561 }
2562 }
2563 } else {
2564 /*Carrier loop setting for short frame*/
2565 aclc = stv090x_optimize_carloop_short(state);
2566 if (state->modulation == STV090x_QPSK) {
2567 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2568 goto err;
2569 } else if (state->modulation == STV090x_8PSK) {
2570 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2571 goto err;
2572 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2573 goto err;
2574 } else if (state->modulation == STV090x_16APSK) {
2575 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2576 goto err;
2577 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2578 goto err;
2579 } else if (state->modulation == STV090x_32APSK) {
2580 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2581 goto err;
2582 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2583 goto err;
2584 }
2585 }
2586 if (state->dev_ver <= 0x11) {
2587 if (state->demod_mode != STV090x_SINGLE)
2588 stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
2589 }
2590 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2591 break;
2592
2593 case STV090x_UNKNOWN:
2594 default:
2595 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2596 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2597 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2598 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2599 goto err;
2600 break;
2601 }
2602
2603 f_1 = STV090x_READ_DEMOD(state, CFR2);
2604 f_0 = STV090x_READ_DEMOD(state, CFR1);
2605 reg = STV090x_READ_DEMOD(state, TMGOBS);
2606 rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2607
2608 if (state->algo == STV090x_BLIND_SEARCH) {
2609 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2610 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2611 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2612 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2613 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2614 goto err;
2615 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
2616 goto err;
2617 stv090x_set_srate(state, srate);
2618 stv090x_set_max_srate(state, state->mclk, srate);
2619 stv090x_set_min_srate(state, state->mclk, srate);
2620 blind_tune = 1;
2621 }
2622
2623 if (state->dev_ver >= 0x20) {
2624 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2625 (state->search_mode == STV090x_SEARCH_DSS) ||
2626 (state->search_mode == STV090x_SEARCH_AUTO)) {
2627
2628 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2629 goto err;
2630 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2631 goto err;
2632 }
2633 }
2634
2635 if (state->dev_ver < 0x20) {
2636 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
2637 goto err;
2638 }
2639 if (state->dev_ver == 0x10) {
2640 if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
2641 goto err;
2642 }
2643
2644 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2645 goto err;
2646
2647 if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
2648
2649 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2650 goto err;
2651 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2652 goto err;
2653 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
2654
2655 if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
2656
2657 if (state->algo != STV090x_WARM_SEARCH) {
2658
2659 stv090x_i2c_gate_ctrl(fe, 1);
2660
2661 if (state->config->tuner_set_bandwidth)
2662 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2663
2664 stv090x_i2c_gate_ctrl(fe, 0);
2665
2666 }
2667 }
2668 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
2669 msleep(50); /* blind search: wait 50ms for SR stabilization */
2670 else
2671 msleep(5);
2672
2673 stv090x_get_lock_tmg(state);
2674
2675 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
2676 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2677 goto err;
2678 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2679 goto err;
2680 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2681 goto err;
2682 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2683 goto err;
2684
2685 i = 0;
2686
2687 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
2688
2689 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2690 goto err;
2691 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2692 goto err;
2693 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
2694 goto err;
2695 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2696 goto err;
2697 i++;
2698 }
2699 }
2700
2701 }
2702
2703 if (state->dev_ver >= 0x20) {
2704 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2705 goto err;
2706 }
2707 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
2708 stv090x_set_vit_thtracq(state);
2709
2710 return 0;
2711err:
2712 dprintk(FE_ERROR, 1, "I/O error");
2713 return -1;
2714}
2715
2716static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
2717{
2718 s32 timer = 0, lock = 0, stat;
2719 u32 reg;
2720
2721 while ((timer < timeout) && (!lock)) {
2722 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2723 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
2724
2725 switch (stat) {
2726 case 0: /* searching */
2727 case 1: /* first PLH detected */
2728 default:
2729 lock = 0;
2730 break;
2731
2732 case 2: /* DVB-S2 mode */
2733 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
2734 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
2735 break;
2736
2737 case 3: /* DVB-S1/legacy mode */
2738 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
2739 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
2740 break;
2741 }
2742 if (!lock) {
2743 msleep(10);
2744 timer += 10;
2745 }
2746 }
2747 return lock;
2748}
2749
2750static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
2751{
2752 u32 reg;
2753 s32 timer = 0;
2754 int lock;
2755
2756 lock = stv090x_get_dmdlock(state, timeout_dmd);
2757 if (lock)
2758 lock = stv090x_get_feclock(state, timeout_fec);
2759
2760 if (lock) {
2761 lock = 0;
2762
2763 while ((timer < timeout_fec) && (!lock)) {
2764 reg = STV090x_READ_DEMOD(state, TSSTATUS);
2765 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
2766 msleep(1);
2767 timer++;
2768 }
2769 }
2770
2771 return lock;
2772}
2773
2774static int stv090x_set_s2rolloff(struct stv090x_state *state)
2775{
2776 s32 rolloff;
2777 u32 reg;
2778
2779 if (state->dev_ver == 0x10) {
2780 reg = STV090x_READ_DEMOD(state, DEMOD);
2781 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
2782 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2783 goto err;
2784 rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
2785 reg = STV090x_READ_DEMOD(state, DEMOD);
2786 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
2787 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2788 goto err;
2789 } else {
2790 reg = STV090x_READ_DEMOD(state, DEMOD);
2791 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
2792 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2793 goto err;
2794 }
2795 return 0;
2796err:
2797 dprintk(FE_ERROR, 1, "I/O error");
2798 return -1;
2799}
2800
2801static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
2802{
2803 s32 srate, f_1, f_2;
2804 enum stv090x_signal_state signal_state = STV090x_NODATA;
2805 u32 reg;
2806 int lock;
2807
2808 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2809 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
2810 srate = stv090x_get_srate(state, state->mclk);
2811 srate += stv090x_get_tmgoffst(state, state->srate);
2812
2813 if (state->algo == STV090x_BLIND_SEARCH)
2814 stv090x_set_srate(state, state->srate);
2815
2816 stv090x_get_lock_tmg(state);
2817
2818 f_1 = STV090x_READ_DEMOD(state, CFR2);
2819 f_2 = STV090x_READ_DEMOD(state, CFR1);
2820
2821 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2822 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
2823 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2824 goto err;
2825
2826 reg = STV090x_READ_DEMOD(state, DEMOD);
2827 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
2828 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2829 goto err;
2830 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
2831 goto err;
2832 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2833 goto err;
2834 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2835 goto err;
2836 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2837 goto err;
2838
2839 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2840 lock = 1;
2841 stv090x_get_sig_params(state);
2842 stv090x_optimize_track(state);
2843 } else {
2844 reg = STV090x_READ_DEMOD(state, DEMOD);
2845 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
2846 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2847 goto err;
2848 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2849 goto err;
2850 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
2851 goto err;
2852 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
2853 goto err;
2854 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
2855 goto err;
2856 if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
2857 lock = 1;
2858 signal_state = stv090x_get_sig_params(state);
2859 stv090x_optimize_track(state);
2860 }
2861 }
2862 } else {
2863 lock = 0;
2864 }
2865
2866 return signal_state;
2867
2868err:
2869 dprintk(FE_ERROR, 1, "I/O error");
2870 return -1;
2871}
2872
2873static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
2874{
2875 struct dvb_frontend *fe = &state->frontend;
2876 enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
2877 u32 reg;
2878 s32 timeout_dmd = 500, timeout_fec = 50;
2879 int lock = 0, low_sr, no_signal = 0;
2880
2881 reg = STV090x_READ_DEMOD(state, TSCFGH);
2882 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
2883 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2884 goto err;
2885
2886 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
2887 goto err;
2888
2889 if (state->dev_ver >= 0x20) {
2890 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
2891 goto err;
2892 } else {
2893 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
2894 goto err;
2895 }
2896
2897 stv090x_get_lock_tmg(state);
2898
2899 if (state->algo == STV090x_BLIND_SEARCH) {
2900 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
2901 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
2902 goto err;
2903 stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
2904 } else {
2905 /* known srate */
2906 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
2907 goto err;
2908 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
2909 goto err;
2910
2911 if (state->srate >= 10000000) {
2912 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
2913 goto err;
2914 } else {
2915 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
2916 goto err;
2917 }
2918
2919 if (state->dev_ver >= 0x20) {
2920 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
2921 goto err;
2922 if (state->algo == STV090x_COLD_SEARCH)
2923 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 1000000)) / 10;
2924 else if (state->algo == STV090x_WARM_SEARCH)
2925 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
2926 } else {
2927 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
2928 goto err;
2929 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
2930 }
2931 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
2932 goto err;
2933 stv090x_set_srate(state, state->srate);
2934 stv090x_set_max_srate(state, state->mclk, state->srate);
2935 stv090x_set_min_srate(state, state->mclk, state->srate);
2936
2937 if (state->srate >= 10000000)
2938 low_sr = 1;
2939 }
2940
2941 /* Setup tuner */
2942 stv090x_i2c_gate_ctrl(fe, 1);
2943
2944 if (state->config->tuner_set_bbgain)
2945 state->config->tuner_set_bbgain(fe, 10); /* 10dB */
2946
2947 if (state->config->tuner_set_frequency)
2948 state->config->tuner_set_frequency(fe, state->frequency);
2949
2950 if (state->config->tuner_set_bandwidth)
2951 state->config->tuner_set_bandwidth(fe, state->tuner_bw);
2952
2953 stv090x_i2c_gate_ctrl(fe, 0);
2954
2955 msleep(50);
2956
2957 stv090x_i2c_gate_ctrl(fe, 1);
2958
2959 if (state->config->tuner_get_status)
2960 state->config->tuner_get_status(fe, &reg);
2961
2962 if (reg)
2963 dprintk(FE_DEBUG, 1, "Tuner phase locked");
2964 else
2965 dprintk(FE_DEBUG, 1, "Tuner unlocked");
2966
2967 stv090x_i2c_gate_ctrl(fe, 0);
2968
2969 reg = STV090x_READ_DEMOD(state, DEMOD);
2970 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
2971 STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
2972 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2973 goto err;
2974 stv090x_delivery_search(state);
2975 if (state->algo == STV090x_BLIND_SEARCH)
2976 stv090x_start_search(state);
2977
2978 if (state->dev_ver == 0x12) {
2979 reg = STV090x_READ_DEMOD(state, TSCFGH);
2980 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
2981 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2982 goto err;
2983 msleep(3);
2984 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
2985 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2986 goto err;
2987 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
2988 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
2989 goto err;
2990 }
2991
2992 if (state->algo == STV090x_BLIND_SEARCH)
2993 lock = stv090x_blind_search(state);
2994 else if (state->algo == STV090x_COLD_SEARCH)
2995 lock = stv090x_get_coldlock(state, timeout_dmd);
2996 else if (state->algo == STV090x_WARM_SEARCH)
2997 lock = stv090x_get_dmdlock(state, timeout_dmd);
2998
2999 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3000 if (!low_sr) {
3001 if (stv090x_chk_tmg(state))
3002 lock = stv090x_sw_algo(state);
3003 }
3004 }
3005
3006 if (lock)
3007 signal_state = stv090x_get_sig_params(state);
3008
3009 if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
3010 stv090x_optimize_track(state);
3011 if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
3012 if (stv090x_get_std(state) == STV090x_DVBS1) {
3013 msleep(20);
3014 reg = STV090x_READ_DEMOD(state, TSCFGH);
3015 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3016 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3017 goto err;
3018 } else {
3019 reg = STV090x_READ_DEMOD(state, TSCFGH);
3020 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3021 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3022 goto err;
3023 msleep(3);
3024 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3025 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3026 goto err;
3027 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3028 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3029 goto err;
3030 }
3031 } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
3032 reg = STV090x_READ_DEMOD(state, TSCFGH);
3033 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3034 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3035 goto err;
3036 msleep(3);
3037 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3038 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3039 goto err;
3040
3041 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3042 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3043 goto err;
3044 }
3045
3046 if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
3047 lock = 1;
3048 if (state->delsys == STV090x_DVBS2) {
3049 stv090x_set_s2rolloff(state);
3050 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
3051 goto err;
3052 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
3053 goto err;
3054 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3055 goto err;
3056 } else {
3057 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3058 goto err;
3059 }
3060 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3061 goto err;
3062 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3063 goto err;
3064 } else {
3065 lock = 0;
3066 signal_state = STV090x_NODATA;
3067 no_signal = stv090x_chk_signal(state);
3068 }
3069 }
3070 if ((signal_state == STV090x_NODATA) && (!no_signal)) {
3071 if (state->dev_ver <= 0x11) {
3072 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3073 if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS2) && (state->inversion == INVERSION_AUTO))
3074 signal_state = stv090x_acq_fixs1(state);
3075 }
3076 }
3077 return signal_state;
3078
3079err:
3080 dprintk(FE_ERROR, 1, "I/O error");
3081 return -1;
3082}
3083
3084static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
3085{
3086 struct stv090x_state *state = fe->demodulator_priv;
3087 struct dtv_frontend_properties *props = &fe->dtv_property_cache;
3088
3089 state->delsys = props->delivery_system;
3090 state->frequency = p->frequency;
3091 state->srate = p->u.qpsk.symbol_rate;
3092
3093 if (!stv090x_algo(state)) {
3094 dprintk(FE_DEBUG, 1, "Search success!");
3095 return DVBFE_ALGO_SEARCH_SUCCESS;
3096 } else {
3097 dprintk(FE_DEBUG, 1, "Search failed!");
3098 return DVBFE_ALGO_SEARCH_FAILED;
3099 }
3100
3101 return DVBFE_ALGO_SEARCH_ERROR;
3102}
3103
3104/* FIXME! */
3105static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
3106{
3107 struct stv090x_state *state = fe->demodulator_priv;
3108 u32 reg;
3109 u8 search_state;
3110 int locked = 0;
3111
3112 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3113 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3114
3115 switch (search_state) {
3116 case 0: /* searching */
3117 case 1: /* first PLH detected */
3118 default:
3119 dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
3120 locked = 0;
3121 break;
3122
3123 case 2: /* DVB-S2 mode */
3124 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
3125 reg = STV090x_READ_DEMOD(state, DSTATUS);
3126 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3127 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3128 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3129 locked = 1;
3130 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3131 }
3132 }
3133 break;
3134
3135 case 3: /* DVB-S1/legacy mode */
3136 dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
3137 reg = STV090x_READ_DEMOD(state, DSTATUS);
3138 if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
3139 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3140 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3141 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3142 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
3143 locked = 1;
3144 *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
3145 }
3146 }
3147 }
3148 break;
3149 }
3150
3151 return locked;
3152}
3153
3154static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
3155{
3156 struct stv090x_state *state = fe->demodulator_priv;
3157
3158 s32 count_4, count_3, count_2, count_1, count_0, count;
3159 u32 reg, h, m, l;
3160 enum fe_status status;
3161
3162 if (!stv090x_read_status(fe, &status)) {
3163 *per = 1 << 23; /* Max PER */
3164 } else {
3165 /* Counter 2 */
3166 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3167 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3168
3169 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3170 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3171
3172 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3173 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3174
3175 *per = ((h << 16) | (m << 8) | l);
3176
3177 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3178 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3179 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3180 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3181 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3182
3183 if ((!count_4) && (!count_3)) {
3184 count = (count_2 & 0xff) << 16;
3185 count |= (count_1 & 0xff) << 8;
3186 count |= count_0 & 0xff;
3187 } else {
3188 count = 1 << 24;
3189 }
3190 if (count == 0)
3191 *per = 1;
3192 }
3193 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3194 goto err;
3195 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3196 goto err;
3197
3198 return 0;
3199err:
3200 dprintk(FE_ERROR, 1, "I/O error");
3201 return -1;
3202}
3203
3204static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
3205{
3206 int res = 0;
3207 int min = 0, med;
3208
3209 if (val < tab[min].read)
3210 res = tab[min].real;
3211 else if (val >= tab[max].read)
3212 res = tab[max].real;
3213 else {
3214 while ((max - min) > 1) {
3215 med = (max + min) / 2;
3216 if (val >= tab[min].read && val < tab[med].read)
3217 max = med;
3218 else
3219 min = med;
3220 }
3221 res = ((val - tab[min].read) *
3222 (tab[max].real - tab[min].real) /
3223 (tab[max].read - tab[min].read)) +
3224 tab[min].real;
3225 }
3226
3227 return res;
3228}
3229
3230static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
3231{
3232 struct stv090x_state *state = fe->demodulator_priv;
3233 u32 reg;
3234 s32 agc;
3235
3236 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3237 agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3238
3239 *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
3240 if (agc > stv090x_rf_tab[0].read)
3241 *strength = 5;
3242 else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
3243 *strength = -100;
3244
3245 return 0;
3246}
3247
3248static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
3249{
3250 struct stv090x_state *state = fe->demodulator_priv;
3251 u32 reg_0, reg_1, reg, i;
3252 s32 val_0, val_1, val = 0;
3253 u8 lock_f;
3254
3255 switch (state->delsys) {
3256 case STV090x_DVBS2:
3257 reg = STV090x_READ_DEMOD(state, DSTATUS);
3258 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3259 if (lock_f) {
3260 msleep(5);
3261 for (i = 0; i < 16; i++) {
3262 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3263 val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3264 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3265 val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
3266 val += MAKEWORD16(val_1, val_0);
3267 msleep(1);
3268 }
3269 val /= 16;
3270 *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
3271 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
3272 *cnr = 1000;
3273 }
3274 break;
3275
3276 case STV090x_DVBS1:
3277 case STV090x_DSS:
3278 reg = STV090x_READ_DEMOD(state, DSTATUS);
3279 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3280 if (lock_f) {
3281 msleep(5);
3282 for (i = 0; i < 16; i++) {
3283 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3284 val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3285 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3286 val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
3287 val += MAKEWORD16(val_1, val_0);
3288 msleep(1);
3289 }
3290 val /= 16;
3291 *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
3292 if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
3293 *cnr = 1000;
3294 }
3295 break;
3296 default:
3297 break;
3298 }
3299
3300 return 0;
3301}
3302
3303static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3304{
3305 struct stv090x_state *state = fe->demodulator_priv;
3306 u32 reg;
3307
3308 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3309 switch (tone) {
3310 case SEC_TONE_ON:
3311 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3312 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3313 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3314 goto err;
3315 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3316 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3317 goto err;
3318 break;
3319
3320 case SEC_TONE_OFF:
3321 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3322 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3323 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3324 goto err;
3325 break;
3326 default:
3327 return -EINVAL;
3328 }
3329
3330 return 0;
3331err:
3332 dprintk(FE_ERROR, 1, "I/O error");
3333 return -1;
3334}
3335
3336
3337static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
3338{
3339 return DVBFE_ALGO_CUSTOM;
3340}
3341
3342static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
3343{
3344 struct stv090x_state *state = fe->demodulator_priv;
3345 u32 reg, idle = 0, fifo_full = 1;
3346 int i;
3347
3348 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3349 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3350 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3351 goto err;
3352
3353 for (i = 0; i < cmd->msg_len; i++) {
3354
3355 while (fifo_full) {
3356 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3357 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3358 }
3359
3360 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3361 goto err;
3362 i++;
3363 }
3364 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3365 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3366 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3367 goto err;
3368
3369 i = 0;
3370
3371 while ((!idle) && (i < 10)) {
3372 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3373 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3374 msleep(10);
3375 i++;
3376 }
3377
3378 return 0;
3379err:
3380 dprintk(FE_ERROR, 1, "I/O error");
3381 return -1;
3382}
3383
3384static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
3385{
3386 struct stv090x_state *state = fe->demodulator_priv;
3387 u32 reg = 0, i = 0, rx_end = 0;
3388
3389 while ((rx_end != 1) && (i < 10)) {
3390 msleep(10);
3391 i++;
3392 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3393 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3394 }
3395
3396 if (rx_end) {
3397 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3398 for (i = 0; i < reply->msg_len; i++)
3399 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3400 }
3401
3402 return 0;
3403}
3404
3405static int stv090x_sleep(struct dvb_frontend *fe)
3406{
3407 struct stv090x_state *state = fe->demodulator_priv;
3408 u32 reg;
3409
3410 dprintk(FE_DEBUG, 1, "Set %s to sleep",
3411 state->device == STV0900 ? "STV0900" : "STV0903");
3412
3413 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3414 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
3415 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3416 goto err;
3417
3418 return 0;
3419err:
3420 dprintk(FE_ERROR, 1, "I/O error");
3421 return -1;
3422}
3423
3424static int stv090x_wakeup(struct dvb_frontend *fe)
3425{
3426 struct stv090x_state *state = fe->demodulator_priv;
3427 u32 reg;
3428
3429 dprintk(FE_DEBUG, 1, "Wake %s from standby",
3430 state->device == STV0900 ? "STV0900" : "STV0903");
3431
3432 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3433 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
3434 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
3435 goto err;
3436
3437 return 0;
3438err:
3439 dprintk(FE_ERROR, 1, "I/O error");
3440 return -1;
3441}
3442
3443static void stv090x_release(struct dvb_frontend *fe)
3444{
3445 struct stv090x_state *state = fe->demodulator_priv;
3446
3447 kfree(state);
3448}
3449
3450static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
3451{
3452 u32 reg;
3453
3454 switch (ldpc_mode) {
3455 case STV090x_DUAL:
3456 default:
3457 reg = stv090x_read_reg(state, STV090x_GENCFG);
3458 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
3459 /* follow LDPC default state */
3460 if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
3461 goto err;
3462 state->demod_mode = STV090x_DUAL;
3463 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3464 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3465 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3466 goto err;
3467 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3468 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3469 goto err;
3470 }
3471 break;
3472
3473 case STV090x_SINGLE:
3474 if (state->demod == STV090x_DEMODULATOR_1) {
3475 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
3476 goto err;
3477 } else {
3478 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
3479 goto err;
3480 }
3481
3482 reg = stv090x_read_reg(state, STV090x_TSTRES0);
3483 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
3484 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3485 goto err;
3486 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
3487 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
3488 goto err;
3489
3490 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3491 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
3492 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3493 goto err;
3494 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
3495 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3496 goto err;
3497 break;
3498 }
3499
3500 return 0;
3501err:
3502 dprintk(FE_ERROR, 1, "I/O error");
3503 return -1;
3504}
3505
3506/* return (Hz), clk in Hz*/
3507static u32 stv090x_get_mclk(struct stv090x_state *state)
3508{
3509 const struct stv090x_config *config = state->config;
3510 u32 div, reg;
3511 u8 ratio;
3512
3513 div = stv090x_read_reg(state, STV090x_NCOARSE);
3514 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3515 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
3516
3517 return (div + 1) * config->xtal / ratio; /* kHz */
3518}
3519
3520static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
3521{
3522 const struct stv090x_config *config = state->config;
3523 u32 reg, div, clk_sel;
3524
3525 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
3526 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
3527
3528 div = ((clk_sel * mclk) / config->xtal) - 1;
3529
3530 reg = stv090x_read_reg(state, STV090x_NCOARSE);
3531 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
3532 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
3533 goto err;
3534
3535 state->mclk = stv090x_get_mclk(state);
3536
3537 return 0;
3538err:
3539 dprintk(FE_ERROR, 1, "I/O error");
3540 return -1;
3541}
3542
3543static int stv090x_set_tspath(struct stv090x_state *state)
3544{
3545 u32 reg;
3546
3547 if (state->dev_ver >= 0x20) {
3548 switch (state->config->ts1_mode) {
3549 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3550 case STV090x_TSMODE_DVBCI:
3551 switch (state->config->ts2_mode) {
3552 case STV090x_TSMODE_SERIAL_PUNCTURED:
3553 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3554 default:
3555 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
3556 break;
3557
3558 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3559 case STV090x_TSMODE_DVBCI:
3560 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
3561 goto err;
3562 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3563 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3564 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3565 goto err;
3566 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
3567 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3568 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
3569 goto err;
3570 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3571 goto err;
3572 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3573 goto err;
3574 break;
3575 }
3576 break;
3577
3578 case STV090x_TSMODE_SERIAL_PUNCTURED:
3579 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3580 default:
3581 switch (state->config->ts2_mode) {
3582 case STV090x_TSMODE_SERIAL_PUNCTURED:
3583 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3584 default:
3585 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3586 goto err;
3587 break;
3588
3589 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3590 case STV090x_TSMODE_DVBCI:
3591 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
3592 goto err;
3593 break;
3594 }
3595 break;
3596 }
3597 } else {
3598 switch (state->config->ts1_mode) {
3599 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3600 case STV090x_TSMODE_DVBCI:
3601 switch (state->config->ts2_mode) {
3602 case STV090x_TSMODE_SERIAL_PUNCTURED:
3603 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3604 default:
3605 break;
3606
3607 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3608 case STV090x_TSMODE_DVBCI:
3609 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3610 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
3611 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3612 goto err;
3613 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
3614 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
3615 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
3616 goto err;
3617 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
3618 goto err;
3619 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
3620 goto err;
3621 break;
3622 }
3623 break;
3624
3625 case STV090x_TSMODE_SERIAL_PUNCTURED:
3626 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3627 default:
3628 switch (state->config->ts2_mode) {
3629 case STV090x_TSMODE_SERIAL_PUNCTURED:
3630 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3631 default:
3632 break;
3633
3634 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3635 case STV090x_TSMODE_DVBCI:
3636 break;
3637 }
3638 break;
3639 }
3640 }
3641
3642 switch (state->config->ts1_mode) {
3643 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3644 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3645 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3646 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3647 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3648 goto err;
3649 break;
3650
3651 case STV090x_TSMODE_DVBCI:
3652 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3653 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3654 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3655 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3656 goto err;
3657 break;
3658
3659 case STV090x_TSMODE_SERIAL_PUNCTURED:
3660 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3661 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3662 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3663 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3664 goto err;
3665 break;
3666
3667 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3668 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3669 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3670 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3671 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3672 goto err;
3673 break;
3674
3675 default:
3676 break;
3677 }
3678
3679 switch (state->config->ts2_mode) {
3680 case STV090x_TSMODE_PARALLEL_PUNCTURED:
3681 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3682 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3683 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3684 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3685 goto err;
3686 break;
3687
3688 case STV090x_TSMODE_DVBCI:
3689 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3690 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
3691 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3692 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3693 goto err;
3694 break;
3695
3696 case STV090x_TSMODE_SERIAL_PUNCTURED:
3697 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3698 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3699 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
3700 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3701 goto err;
3702 break;
3703
3704 case STV090x_TSMODE_SERIAL_CONTINUOUS:
3705 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3706 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
3707 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
3708 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3709 goto err;
3710 break;
3711
3712 default:
3713 break;
3714 }
3715 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
3716 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3717 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3718 goto err;
3719 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3720 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
3721 goto err;
3722
3723 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
3724 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
3725 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3726 goto err;
3727 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
3728 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
3729 goto err;
3730
3731 return 0;
3732err:
3733 dprintk(FE_ERROR, 1, "I/O error");
3734 return -1;
3735}
3736
3737static int stv090x_init(struct dvb_frontend *fe)
3738{
3739 struct stv090x_state *state = fe->demodulator_priv;
3740 const struct stv090x_config *config = state->config;
3741 u32 reg;
3742
3743 stv090x_ldpc_mode(state, state->demod_mode);
3744
3745 reg = STV090x_READ_DEMOD(state, TNRCFG2);
3746 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
3747 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
3748 goto err;
3749 reg = STV090x_READ_DEMOD(state, DEMOD);
3750 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
3751 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3752 goto err;
3753
3754 stv090x_i2c_gate_ctrl(fe, 1);
3755
3756 if (config->tuner_init)
3757 config->tuner_init(fe);
3758
3759 stv090x_i2c_gate_ctrl(fe, 0);
3760
3761 stv090x_set_tspath(state);
3762
3763 return 0;
3764err:
3765 dprintk(FE_ERROR, 1, "I/O error");
3766 return -1;
3767}
3768
3769static int stv090x_setup(struct dvb_frontend *fe)
3770{
3771 struct stv090x_state *state = fe->demodulator_priv;
3772 const struct stv090x_config *config = state->config;
3773 const struct stv090x_reg *stv090x_initval = NULL;
3774 const struct stv090x_reg *stv090x_cut20_val = NULL;
3775 unsigned long t1_size = 0, t2_size = 0;
3776
3777 int i;
3778
3779 if (state->device == STV0900) {
3780 dprintk(FE_DEBUG, 1, "Initializing STV0900");
3781 stv090x_initval = stv0900_initval;
3782 t1_size = ARRAY_SIZE(stv0900_initval);
3783 stv090x_cut20_val = stv0900_cut20_val;
3784 t2_size = ARRAY_SIZE(stv0900_cut20_val);
3785 } else if (state->device == STV0903) {
3786 dprintk(FE_DEBUG, 1, "Initializing STV0903");
3787 stv090x_initval = stv0903_initval;
3788 t1_size = ARRAY_SIZE(stv0903_initval);
3789 stv090x_cut20_val = stv0903_cut20_val;
3790 t2_size = ARRAY_SIZE(stv0903_cut20_val);
3791 }
3792
3793 /* STV090x init */
3794 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
3795 goto err;
3796
3797 msleep(5);
3798
3799 if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
3800 goto err;
3801
3802 if (STV090x_WRITE_DEMOD(state, I2CRPT, 0x00) < 0) /* repeater OFF */
3803 goto err;
3804
3805 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
3806 goto err;
3807 msleep(5);
3808 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
3809 goto err;
3810 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
3811 goto err;
3812 msleep(5);
3813
3814 /* write initval */
3815 for (i = 0; i < t1_size; i++) {
3816 dprintk(FE_DEBUG, 1, "Setting up initial values");
3817 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
3818 goto err;
3819 }
3820
3821 if (state->dev_ver >= 0x20) {
3822 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
3823 goto err;
3824
3825 /* write cut20_val*/
3826 dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
3827 for (i = 0; i < t2_size; i++) {
3828 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
3829 goto err;
3830 }
3831 }
3832
3833 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
3834 goto err;
3835 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
3836 goto err;
3837
3838 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
3839 msleep(5);
3840 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
3841 goto err;
3842 stv090x_get_mclk(state);
3843
3844 return 0;
3845err:
3846 dprintk(FE_ERROR, 1, "I/O error");
3847 return -1;
3848}
3849
3850static struct dvb_frontend_ops stv090x_ops = {
3851
3852 .info = {
3853 .name = "STV090x Multistandard",
3854 },
3855
3856 .release = stv090x_release,
3857 .init = stv090x_init,
3858
3859 .sleep = stv090x_sleep,
3860 .get_frontend_algo = stv090x_frontend_algo,
3861
3862 .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
3863
3864 .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
3865 .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
3866 .set_tone = stv090x_set_tone,
3867
3868 .search = stv090x_search,
3869 .read_status = stv090x_read_status,
3870 .read_ber = stv090x_read_per,
3871 .read_signal_strength = stv090x_read_signal_strength,
3872 .read_snr = stv090x_read_cnr
3873};
3874
3875
3876struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
3877 struct i2c_adapter *i2c,
3878 enum stv090x_demodulator demod)
3879{
3880 struct stv090x_state *state = NULL;
3881
3882 state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
3883 if (state == NULL)
3884 goto error;
3885
3886 state->verbose = &verbose;
3887 state->config = config;
3888 state->i2c = i2c;
3889 state->frontend.ops = stv090x_ops;
3890 state->frontend.demodulator_priv = state;
3891 state->demod_mode = config->demod_mode; /* Single or Dual mode */
3892 state->device = config->device;
3893 state->rolloff = 35; /* default */
3894
3895 if (state->demod == STV090x_DEMODULATOR_0)
3896 mutex_init(&demod_lock);
3897
3898 if (stv090x_sleep(&state->frontend) < 0) {
3899 dprintk(FE_ERROR, 1, "Error putting device to sleep");
3900 goto error;
3901 }
3902
3903 if (stv090x_setup(&state->frontend) < 0) {
3904 dprintk(FE_ERROR, 1, "Error setting up device");
3905 goto error;
3906 }
3907 if (stv090x_wakeup(&state->frontend) < 0) {
3908 dprintk(FE_ERROR, 1, "Error waking device");
3909 goto error;
3910 }
3911 state->dev_ver = stv090x_read_reg(state, STV090x_MID);
3912
3913 dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
3914 state->device == STV0900 ? "STV0900" : "STV0903",
3915 demod,
3916 state->dev_ver);
3917
3918 return &state->frontend;
3919
3920error:
3921 kfree(state);
3922 return NULL;
3923}
3924EXPORT_SYMBOL(stv090x_attach);
3925MODULE_PARM_DESC(verbose, "Set Verbosity level");
3926MODULE_AUTHOR("Manu Abraham");
3927MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
3928MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stv090x.h b/drivers/media/dvb/frontends/stv090x.h
new file mode 100644
index 000000000000..e56489cb5b92
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x.h
@@ -0,0 +1,93 @@
1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STV090x_H
23#define __STV090x_H
24
25enum stv090x_demodulator {
26 STV090x_DEMODULATOR_0 = 1,
27 STV090x_DEMODULATOR_1
28};
29
30enum stv090x_device {
31 STV0903 = 0,
32 STV0900,
33};
34
35enum stv090x_mode {
36 STV090x_DUAL = 0,
37 STV090x_SINGLE
38};
39
40enum stv090x_tsmode {
41 STV090x_TSMODE_SERIAL_PUNCTURED = 1,
42 STV090x_TSMODE_SERIAL_CONTINUOUS,
43 STV090x_TSMODE_PARALLEL_PUNCTURED,
44 STV090x_TSMODE_DVBCI
45};
46
47enum stv090x_clkmode {
48 STV090x_CLK_INT = 0, /* Clk i/p = CLKI */
49 STV090x_CLK_EXT = 2 /* Clk i/p = XTALI */
50};
51
52struct stv090x_config {
53 enum stv090x_device device;
54 enum stv090x_mode demod_mode;
55 enum stv090x_clkmode clk_mode;
56
57 u32 xtal; /* default: 8000000 */
58 u8 address; /* default: 0x68 */
59
60 u32 ref_clk; /* default: 16000000 FIXME to tuner config */
61
62 u8 ts1_mode;
63 u8 ts2_mode;
64
65 int (*tuner_init) (struct dvb_frontend *fe);
66 int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode);
67 int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
68 int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency);
69 int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth);
70 int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth);
71 int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain);
72 int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
73 int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
74 int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
75};
76
77#if defined(CONFIG_DVB_STV090x) || (defined(CONFIG_DVB_STV090x_MODULE) && defined(MODULE))
78
79extern struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
80 struct i2c_adapter *i2c,
81 enum stv090x_demodulator demod);
82#else
83
84static inline struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
85 struct i2c_adapter *i2c,
86 enum stv090x_demodulator demod)
87{
88 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
89 return NULL;
90}
91#endif /* CONFIG_DVB_STV090x */
92
93#endif /* __STV090x_H */
diff --git a/drivers/media/dvb/frontends/stv090x_priv.h b/drivers/media/dvb/frontends/stv090x_priv.h
new file mode 100644
index 000000000000..9d536226e9f3
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x_priv.h
@@ -0,0 +1,274 @@
1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STV090x_PRIV_H
23#define __STV090x_PRIV_H
24
25#include "dvb_frontend.h"
26
27#define FE_ERROR 0
28#define FE_NOTICE 1
29#define FE_INFO 2
30#define FE_DEBUG 3
31#define FE_DEBUGREG 4
32
33#define dprintk(__y, __z, format, arg...) do { \
34 if (__z) { \
35 if ((verbose > FE_ERROR) && (verbose > __y)) \
36 printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
37 else if ((verbose > FE_NOTICE) && (verbose > __y)) \
38 printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
39 else if ((verbose > FE_INFO) && (verbose > __y)) \
40 printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
41 else if ((verbose > FE_DEBUG) && (verbose > __y)) \
42 printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
43 } else { \
44 if (verbose > __y) \
45 printk(format, ##arg); \
46 } \
47} while (0)
48
49#define STV090x_READ_DEMOD(__state, __reg) (( \
50 (__state)->demod == STV090x_DEMODULATOR_1) ? \
51 stv090x_read_reg(__state, STV090x_P2_##__reg) : \
52 stv090x_read_reg(__state, STV090x_P1_##__reg))
53
54#define STV090x_WRITE_DEMOD(__state, __reg, __data) (( \
55 (__state)->demod == STV090x_DEMODULATOR_1) ? \
56 stv090x_write_reg(__state, STV090x_P2_##__reg, __data) :\
57 stv090x_write_reg(__state, STV090x_P1_##__reg, __data))
58
59#define STV090x_ADDR_OFFST(__state, __x) (( \
60 (__state->demod) == STV090x_DEMODULATOR_1) ? \
61 STV090x_P1_##__x : \
62 STV090x_P2_##__x)
63
64
65#define STV090x_SETFIELD(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_##bitf) - 1) <<\
66 STV090x_OFFST_##bitf))) | \
67 (val << STV090x_OFFST_##bitf))
68
69#define STV090x_GETFIELD(val, bitf) ((val >> STV090x_OFFST_##bitf) & ((1 << STV090x_WIDTH_##bitf) - 1))
70
71
72#define STV090x_SETFIELD_Px(mask, bitf, val) (mask = (mask & (~(((1 << STV090x_WIDTH_Px_##bitf) - 1) <<\
73 STV090x_OFFST_Px_##bitf))) | \
74 (val << STV090x_OFFST_Px_##bitf))
75
76#define STV090x_GETFIELD_Px(val, bitf) ((val >> STV090x_OFFST_Px_##bitf) & ((1 << STV090x_WIDTH_Px_##bitf) - 1))
77
78#define MAKEWORD16(__a, __b) (((__a) << 8) | (__b))
79
80#define STV090x_SEARCH_AGC2_TH 700
81
82enum stv090x_signal_state {
83 STV090x_NOCARRIER,
84 STV090x_NODATA,
85 STV090x_DATAOK,
86 STV090x_RANGEOK,
87 STV090x_OUTOFRANGE
88};
89
90enum stv090x_fec {
91 STV090x_PR12 = 0,
92 STV090x_PR23,
93 STV090x_PR34,
94 STV090x_PR45,
95 STV090x_PR56,
96 STV090x_PR67,
97 STV090x_PR78,
98 STV090x_PR89,
99 STV090x_PR910,
100 STV090x_PRERR
101};
102
103enum stv090x_modulation {
104 STV090x_QPSK,
105 STV090x_8PSK,
106 STV090x_16APSK,
107 STV090x_32APSK,
108 STV090x_UNKNOWN
109};
110
111enum stv090x_frame {
112 STV090x_LONG_FRAME,
113 STV090x_SHORT_FRAME
114};
115
116enum stv090x_pilot {
117 STV090x_PILOTS_OFF,
118 STV090x_PILOTS_ON
119};
120
121enum stv090x_rolloff {
122 STV090x_RO_35,
123 STV090x_RO_25,
124 STV090x_RO_20
125};
126
127enum stv090x_inversion {
128 STV090x_IQ_AUTO,
129 STV090x_IQ_NORMAL,
130 STV090x_IQ_SWAP
131};
132
133enum stv090x_modcod {
134 STV090x_DUMMY_PLF = 0,
135 STV090x_QPSK_14,
136 STV090x_QPSK_13,
137 STV090x_QPSK_25,
138 STV090x_QPSK_12,
139 STV090x_QPSK_35,
140 STV090x_QPSK_23,
141 STV090x_QPSK_34,
142 STV090x_QPSK_45,
143 STV090x_QPSK_56,
144 STV090x_QPSK_89,
145 STV090x_QPSK_910,
146 STV090x_8PSK_35,
147 STV090x_8PSK_23,
148 STV090x_8PSK_34,
149 STV090x_8PSK_56,
150 STV090x_8PSK_89,
151 STV090x_8PSK_910,
152 STV090x_16APSK_23,
153 STV090x_16APSK_34,
154 STV090x_16APSK_45,
155 STV090x_16APSK_56,
156 STV090x_16APSK_89,
157 STV090x_16APSK_910,
158 STV090x_32APSK_34,
159 STV090x_32APSK_45,
160 STV090x_32APSK_56,
161 STV090x_32APSK_89,
162 STV090x_32APSK_910,
163 STV090x_MODCODE_UNKNOWN
164};
165
166enum stv090x_search {
167 STV090x_SEARCH_DSS = 0,
168 STV090x_SEARCH_DVBS1,
169 STV090x_SEARCH_DVBS2,
170 STV090x_SEARCH_AUTO
171};
172
173enum stv090x_algo {
174 STV090x_BLIND_SEARCH,
175 STV090x_COLD_SEARCH,
176 STV090x_WARM_SEARCH
177};
178
179enum stv090x_delsys {
180 STV090x_ERROR = 0,
181 STV090x_DVBS1 = 1,
182 STV090x_DVBS2,
183 STV090x_DSS
184};
185
186struct stv090x_long_frame_crloop {
187 enum stv090x_modcod modcod;
188
189 u8 crl_pilots_on_2;
190 u8 crl_pilots_off_2;
191 u8 crl_pilots_on_5;
192 u8 crl_pilots_off_5;
193 u8 crl_pilots_on_10;
194 u8 crl_pilots_off_10;
195 u8 crl_pilots_on_20;
196 u8 crl_pilots_off_20;
197 u8 crl_pilots_on_30;
198 u8 crl_pilots_off_30;
199};
200
201struct stv090x_short_frame_crloop {
202 enum stv090x_modulation modulation;
203
204 u8 crl_cut12_2; /* Cut 1.2, SR <= 3M */
205 u8 crl_cut20_2; /* Cut 2.0, SR < 3M */
206 u8 crl_cut12_5; /* Cut 1.2, 3 < SR <= 7M */
207 u8 crl_cut20_5; /* Cut 2.0, 3 < SR <= 7M */
208 u8 crl_cut12_10; /* Cut 1.2, 7 < SR <= 15M */
209 u8 crl_cut20_10; /* Cut 2.0, 7 < SR <= 15M */
210 u8 crl_cut12_20; /* Cut 1.2, 10 < SR <= 25M */
211 u8 crl_cut20_20; /* Cut 2.0, 10 < SR <= 25M */
212 u8 crl_cut12_30; /* Cut 1.2, 25 < SR <= 45M */
213 u8 crl_cut20_30; /* Cut 2.0, 10 < SR <= 45M */
214};
215
216
217struct stv090x_short_frame_vsmod_crloop {
218 enum stv090x_modulation modulation;
219
220 u8 crl_2; /* < 3M */
221 u8 crl_5; /* 3 < SR <= 7M */
222 u8 crl_10; /* 7 < SR <= 15M */
223 u8 crl_20; /* 10 < SR <= 25M */
224 u8 crl_30; /* 10 < SR <= 45M */
225};
226
227struct stv090x_reg {
228 u16 addr;
229 u8 data;
230};
231
232struct stv090x_tab {
233 s32 real;
234 s32 read;
235};
236
237struct stv090x_state {
238 enum stv090x_device device;
239 enum stv090x_demodulator demod;
240 enum stv090x_mode demod_mode;
241 u32 dev_ver;
242
243 struct i2c_adapter *i2c;
244 const struct stv090x_config *config;
245 struct dvb_frontend frontend;
246
247 u32 *verbose; /* Cached module verbosity */
248
249 enum stv090x_delsys delsys;
250 enum stv090x_fec fec;
251 enum stv090x_modulation modulation;
252 enum stv090x_modcod modcod;
253 enum stv090x_search search_mode;
254 enum stv090x_frame frame_len;
255 enum stv090x_pilot pilots;
256 enum stv090x_rolloff rolloff;
257 enum stv090x_inversion inversion;
258 enum stv090x_algo algo;
259
260 u32 frequency;
261 u32 srate;
262
263 s32 mclk; /* Masterclock Divider factor */
264 s32 tuner_bw;
265
266 u32 tuner_refclk;
267
268 s32 search_range;
269
270 s32 DemodTimeout;
271 s32 FecTimeout;
272};
273
274#endif /* __STV090x_PRIV_H */
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h
new file mode 100644
index 000000000000..b59eca9539cd
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv090x_reg.h
@@ -0,0 +1,2300 @@
1/*
2 STV0900/0903 Multistandard Broadcast Frontend driver
3 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
4
5 Copyright (C) ST Microelectronics
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20*/
21
22#ifndef __STV090x_REG_H
23#define __STV090x_REG_H
24
25#define STV090x_MID 0xf100
26#define STV090x_OFFST_MCHIP_IDENT_FIELD 4
27#define STV090x_WIDTH_MCHIP_IDENT_FIELD 4
28#define STV090x_OFFST_MRELEASE_FIELD 0
29#define STV090x_WIDTH_MRELEASE_FIELD 4
30
31#define STV090x_DACR1 0xf113
32#define STV090x_OFFST_DACR1_MODE_FIELD 5
33#define STV090x_WIDTH_DACR1_MODE_FIELD 3
34#define STV090x_OFFST_DACR1_VALUE_FIELD 0
35#define STV090x_WIDTH_DACR1_VALUE_FIELD 4
36
37#define STV090x_DACR2 0xf114
38#define STV090x_OFFST_DACR2_VALUE_FIELD 0
39#define STV090x_WIDTH_DACR2_VALUE_FIELD 8
40
41#define STV090x_OUTCFG 0xf11c
42#define STV090x_OFFST_OUTSERRS1_HZ_FIELD 6
43#define STV090x_WIDTH_OUTSERRS1_HZ_FIELD 1
44#define STV090x_OFFST_OUTSERRS2_HZ_FIELD 5
45#define STV090x_WIDTH_OUTSERRS2_HZ_FIELD 1
46#define STV090x_OFFST_OUTSERRS3_HZ_FIELD 4
47#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1
48#define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3
49#define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1
50
51#define STV090x_IRQSTATUS3 0xf120
52#define STV090x_OFFST_SPLL_LOCK_FIELD 5
53#define STV090x_WIDTH_SPLL_LOCK_FIELD 1
54#define STV090x_OFFST_SSTREAM_LCK_3_FIELD 4
55#define STV090x_WIDTH_SSTREAM_LCK_3_FIELD 1
56#define STV090x_OFFST_SSTREAM_LCK_2_FIELD 3
57#define STV090x_WIDTH_SSTREAM_LCK_2_FIELD 1
58#define STV090x_OFFST_SSTREAM_LCK_1_FIELD 2
59#define STV090x_WIDTH_SSTREAM_LCK_1_FIELD 1
60#define STV090x_OFFST_SDVBS1_PRF_2_FIELD 1
61#define STV090x_WIDTH_SDVBS1_PRF_2_FIELD 1
62#define STV090x_OFFST_SDVBS1_PRF_1_FIELD 0
63#define STV090x_WIDTH_SDVBS1_PRF_1_FIELD 1
64
65#define STV090x_IRQSTATUS2 0xf121
66#define STV090x_OFFST_SSPY_ENDSIM_3_FIELD 7
67#define STV090x_WIDTH_SSPY_ENDSIM_3_FIELD 1
68#define STV090x_OFFST_SSPY_ENDSIM_2_FIELD 6
69#define STV090x_WIDTH_SSPY_ENDSIM_2_FIELD 1
70#define STV090x_OFFST_SSPY_ENDSIM_1_FIELD 5
71#define STV090x_WIDTH_SSPY_ENDSIM_1_FIELD 1
72#define STV090x_OFFST_SPKTDEL_ERROR_2_FIELD 4
73#define STV090x_WIDTH_SPKTDEL_ERROR_2_FIELD 1
74#define STV090x_OFFST_SPKTDEL_LOCKB_2_FIELD 3
75#define STV090x_WIDTH_SPKTDEL_LOCKB_2_FIELD 1
76#define STV090x_OFFST_SPKTDEL_LOCK_2_FIELD 2
77#define STV090x_WIDTH_SPKTDEL_LOCK_2_FIELD 1
78#define STV090x_OFFST_SPKTDEL_ERROR_1_FIELD 1
79#define STV090x_WIDTH_SPKTDEL_ERROR_1_FIELD 1
80#define STV090x_OFFST_SPKTDEL_LOCKB_1_FIELD 0
81#define STV090x_WIDTH_SPKTDEL_LOCKB_1_FIELD 1
82
83#define STV090x_IRQSTATUS1 0xf122
84#define STV090x_OFFST_SPKTDEL_LOCK_1_FIELD 7
85#define STV090x_WIDTH_SPKTDEL_LOCK_1_FIELD 1
86#define STV090x_OFFST_SDEMOD_LOCKB_2_FIELD 2
87#define STV090x_WIDTH_SDEMOD_LOCKB_2_FIELD 1
88#define STV090x_OFFST_SDEMOD_LOCK_2_FIELD 1
89#define STV090x_WIDTH_SDEMOD_LOCK_2_FIELD 1
90#define STV090x_OFFST_SDEMOD_IRQ_2_FIELD 0
91#define STV090x_WIDTH_SDEMOD_IRQ_2_FIELD 1
92
93#define STV090x_IRQSTATUS0 0xf123
94#define STV090x_OFFST_SDEMOD_LOCKB_1_FIELD 7
95#define STV090x_WIDTH_SDEMOD_LOCKB_1_FIELD 1
96#define STV090x_OFFST_SDEMOD_LOCK_1_FIELD 6
97#define STV090x_WIDTH_SDEMOD_LOCK_1_FIELD 1
98#define STV090x_OFFST_SDEMOD_IRQ_1_FIELD 5
99#define STV090x_WIDTH_SDEMOD_IRQ_1_FIELD 1
100#define STV090x_OFFST_SBCH_ERRFLAG_FIELD 4
101#define STV090x_WIDTH_SBCH_ERRFLAG_FIELD 1
102#define STV090x_OFFST_SDISEQC2RX_IRQ_FIELD 3
103#define STV090x_WIDTH_SDISEQC2RX_IRQ_FIELD 1
104#define STV090x_OFFST_SDISEQC2TX_IRQ_FIELD 2
105#define STV090x_WIDTH_SDISEQC2TX_IRQ_FIELD 1
106#define STV090x_OFFST_SDISEQC1RX_IRQ_FIELD 1
107#define STV090x_WIDTH_SDISEQC1RX_IRQ_FIELD 1
108#define STV090x_OFFST_SDISEQC1TX_IRQ_FIELD 0
109#define STV090x_WIDTH_SDISEQC1TX_IRQ_FIELD 1
110
111#define STV090x_IRQMASK3 0xf124
112#define STV090x_OFFST_MPLL_LOCK_FIELD 5
113#define STV090x_WIDTH_MPLL_LOCK_FIELD 1
114#define STV090x_OFFST_MSTREAM_LCK_3_FIELD 2
115#define STV090x_WIDTH_MSTREAM_LCK_3_FIELD 3
116#define STV090x_OFFST_MSTREAM_LCK_2_FIELD 2
117#define STV090x_WIDTH_MSTREAM_LCK_2_FIELD 3
118#define STV090x_OFFST_MSTREAM_LCK_1_FIELD 2
119#define STV090x_WIDTH_MSTREAM_LCK_1_FIELD 3
120#define STV090x_OFFST_MDVBS1_PRF_2_FIELD 1
121#define STV090x_WIDTH_MDVBS1_PRF_2_FIELD 1
122#define STV090x_OFFST_MDVBS1_PRF_1_FIELD 0
123#define STV090x_WIDTH_MDVBS1_PRF_1_FIELD 1
124
125#define STV090x_IRQMASK2 0xf125
126#define STV090x_OFFST_MSPY_ENDSIM_3_FIELD 5
127#define STV090x_WIDTH_MSPY_ENDSIM_3_FIELD 3
128#define STV090x_OFFST_MSPY_ENDSIM_2_FIELD 5
129#define STV090x_WIDTH_MSPY_ENDSIM_2_FIELD 3
130#define STV090x_OFFST_MSPY_ENDSIM_1_FIELD 5
131#define STV090x_WIDTH_MSPY_ENDSIM_1_FIELD 3
132#define STV090x_OFFST_MPKTDEL_ERROR_2_FIELD 4
133#define STV090x_WIDTH_MPKTDEL_ERROR_2_FIELD 1
134#define STV090x_OFFST_MPKTDEL_LOCKB_2_FIELD 3
135#define STV090x_WIDTH_MPKTDEL_LOCKB_2_FIELD 1
136#define STV090x_OFFST_MPKTDEL_LOCK_2_FIELD 2
137#define STV090x_WIDTH_MPKTDEL_LOCK_2_FIELD 1
138#define STV090x_OFFST_MPKTDEL_ERROR_1_FIELD 1
139#define STV090x_WIDTH_MPKTDEL_ERROR_1_FIELD 1
140#define STV090x_OFFST_MPKTDEL_LOCKB_1_FIELD 0
141#define STV090x_WIDTH_MPKTDEL_LOCKB_1_FIELD 1
142
143#define STV090x_IRQMASK1 0xf126
144#define STV090x_OFFST_MPKTDEL_LOCK_1_FIELD 7
145#define STV090x_WIDTH_MPKTDEL_LOCK_1_FIELD 1
146#define STV090x_OFFST_MEXTPINB2_FIELD 6
147#define STV090x_WIDTH_MEXTPINB2_FIELD 1
148#define STV090x_OFFST_MEXTPIN2_FIELD 5
149#define STV090x_WIDTH_MEXTPIN2_FIELD 1
150#define STV090x_OFFST_MEXTPINB1_FIELD 4
151#define STV090x_WIDTH_MEXTPINB1_FIELD 1
152#define STV090x_OFFST_MEXTPIN1_FIELD 3
153#define STV090x_WIDTH_MEXTPIN1_FIELD 1
154#define STV090x_OFFST_MDEMOD_LOCKB_2_FIELD 2
155#define STV090x_WIDTH_MDEMOD_LOCKB_2_FIELD 1
156#define STV090x_OFFST_MDEMOD_LOCK_2_FIELD 1
157#define STV090x_WIDTH_MDEMOD_LOCK_2_FIELD 1
158#define STV090x_OFFST_MDEMOD_IRQ_2_FIELD 0
159#define STV090x_WIDTH_MDEMOD_IRQ_2_FIELD 1
160
161#define STV090x_IRQMASK0 0xf127
162#define STV090x_OFFST_MDEMOD_LOCKB_1_FIELD 7
163#define STV090x_WIDTH_MDEMOD_LOCKB_1_FIELD 1
164#define STV090x_OFFST_MDEMOD_LOCK_1_FIELD 6
165#define STV090x_WIDTH_MDEMOD_LOCK_1_FIELD 1
166#define STV090x_OFFST_MDEMOD_IRQ_1_FIELD 5
167#define STV090x_WIDTH_MDEMOD_IRQ_1_FIELD 1
168#define STV090x_OFFST_MBCH_ERRFLAG_FIELD 4
169#define STV090x_WIDTH_MBCH_ERRFLAG_FIELD 1
170#define STV090x_OFFST_MDISEQC2RX_IRQ_FIELD 3
171#define STV090x_WIDTH_MDISEQC2RX_IRQ_FIELD 1
172#define STV090x_OFFST_MDISEQC2TX_IRQ_FIELD 2
173#define STV090x_WIDTH_MDISEQC2TX_IRQ_FIELD 1
174#define STV090x_OFFST_MDISEQC1RX_IRQ_FIELD 1
175#define STV090x_WIDTH_MDISEQC1RX_IRQ_FIELD 1
176#define STV090x_OFFST_MDISEQC1TX_IRQ_FIELD 0
177#define STV090x_WIDTH_MDISEQC1TX_IRQ_FIELD 1
178
179#define STV090x_I2CCFG 0xf129
180#define STV090x_OFFST_12C_FASTMODE_FIELD 3
181#define STV090x_WIDTH_12C_FASTMODE_FIELD 1
182#define STV090x_OFFST_12CADDR_INC_FIELD 0
183#define STV090x_WIDTH_12CADDR_INC_FIELD 2
184
185#define STV090x_Px_I2CRPT(__x) (0xf12a + (__x - 1) * 0x1)
186#define STV090x_P1_I2CRPT STV090x_Px_I2CRPT(1)
187#define STV090x_P2_I2CRPT STV090x_Px_I2CRPT(2)
188#define STV090x_OFFST_Px_I2CT_ON_FIELD 7
189#define STV090x_WIDTH_Px_I2CT_ON_FIELD 1
190#define STV090x_OFFST_Px_ENARPT_LEVEL_FIELD 4
191#define STV090x_WIDTH_Px_ENARPT_LEVEL_FIELD 3
192#define STV090x_OFFST_Px_SCLT_DELAY_FIELD 3
193#define STV090x_WIDTH_Px_SCLT_DELAY_FIELD 1
194#define STV090x_OFFST_Px_STOP_ENABLE_FIELD 2
195#define STV090x_WIDTH_Px_STOP_ENABLE_FIELD 1
196#define STV090x_OFFST_Px_STOP_SDAT2SDA_FIELD 1
197#define STV090x_WIDTH_Px_STOP_SDAT2SDA_FIELD 1
198
199#define STV090x_CLKI2CFG 0xf140
200#define STV090x_OFFST_CLKI2_OPD_FIELD 7
201#define STV090x_WIDTH_CLKI2_OPD_FIELD 1
202#define STV090x_OFFST_CLKI2_CONFIG_FIELD 1
203#define STV090x_WIDTH_CLKI2_CONFIG_FIELD 6
204#define STV090x_OFFST_CLKI2_XOR_FIELD 0
205#define STV090x_WIDTH_CLKI2_XOR_FIELD 1
206
207#define STV090x_GPIOxCFG(__x) (0xf141 + (__x - 1))
208#define STV090x_GPIO1CFG STV090x_GPIOxCFG(1)
209#define STV090x_GPIO2CFG STV090x_GPIOxCFG(2)
210#define STV090x_GPIO3CFG STV090x_GPIOxCFG(3)
211#define STV090x_GPIO4CFG STV090x_GPIOxCFG(4)
212#define STV090x_GPIO5CFG STV090x_GPIOxCFG(5)
213#define STV090x_GPIO6CFG STV090x_GPIOxCFG(6)
214#define STV090x_GPIO7CFG STV090x_GPIOxCFG(7)
215#define STV090x_GPIO8CFG STV090x_GPIOxCFG(8)
216#define STV090x_GPIO9CFG STV090x_GPIOxCFG(9)
217#define STV090x_GPIO10CFG STV090x_GPIOxCFG(10)
218#define STV090x_GPIO11CFG STV090x_GPIOxCFG(11)
219#define STV090x_GPIO12CFG STV090x_GPIOxCFG(12)
220#define STV090x_GPIO13CFG STV090x_GPIOxCFG(13)
221#define STV090x_OFFST_GPIOx_OPD_FIELD 7
222#define STV090x_WIDTH_GPIOx_OPD_FIELD 1
223#define STV090x_OFFST_GPIOx_CONFIG_FIELD 1
224#define STV090x_WIDTH_GPIOx_CONFIG_FIELD 6
225#define STV090x_OFFST_GPIOx_XOR_FIELD 0
226#define STV090x_WIDTH_GPIOx_XOR_FIELD 1
227
228#define STV090x_CSxCFG(__x) (0xf14e + __x * 0x1)
229#define STV090x_CS0CFG STV090x_CSxCFG(0)
230#define STV090x_CS1CFG STV090x_CSxCFG(1)
231#define STV090x_OFFST_CSX_OPD_FIELD 7
232#define STV090x_WIDTH_CSX_OPD_FIELD 1
233#define STV090x_OFFST_CSX_CONFIG_FIELD 1
234#define STV090x_WIDTH_CSX_CONFIG_FIELD 6
235#define STV090x_OFFST_CSX_XOR_FIELD 0
236#define STV090x_WIDTH_CSX_XOR_FIELD 1
237
238
239#define STV090x_STDBYCFG 0xf150
240#define STV090x_OFFST_STDBY_OPD_FIELD 7
241#define STV090x_WIDTH_STDBY_OPD_FIELD 1
242#define STV090x_OFFST_STDBY_CONFIG_FIELD 1
243#define STV090x_WIDTH_STDBY_CONFIG_FIELD 6
244#define STV090x_OFFST_STDBY_XOR_FIELD 0
245#define STV090x_WIDTH_STDBY_XOR_FIELD 1
246
247#define STV090x_DIRCLKCFG 0xf151
248#define STV090x_OFFST_DIRCLK_OPD_FIELD 7
249#define STV090x_WIDTH_DIRCLK_OPD_FIELD 1
250#define STV090x_OFFST_DIRCLK_CONFIG_FIELD 1
251#define STV090x_WIDTH_DIRCLK_CONFIG_FIELD 6
252#define STV090x_OFFST_DIRCLK_XOR_FIELD 0
253#define STV090x_WIDTH_DIRCLK_XOR_FIELD 1
254
255
256#define STV090x_AGCRFxCFG(__x) (0xf152 + (__x - 1) * 0x4)
257#define STV090x_AGCRF1CFG STV090x_AGCRFxCFG(1)
258#define STV090x_AGCRF2CFG STV090x_AGCRFxCFG(2)
259#define STV090x_OFFST_AGCRFx_OPD_FIELD 7
260#define STV090x_WIDTH_AGCRFx_OPD_FIELD 1
261#define STV090x_OFFST_AGCRFx_CONFIG_FIELD 1
262#define STV090x_WIDTH_AGCRFx_CONFIG_FIELD 6
263#define STV090x_OFFST_AGCRFx_XOR_FIELD 0
264#define STV090x_WIDTH_AGCRFx_XOR_FIELD 1
265
266#define STV090x_SDATxCFG(__x) (0xf153 + (__x - 1) * 0x4)
267#define STV090x_SDAT1CFG STV090x_SDATxCFG(1)
268#define STV090x_SDAT2CFG STV090x_SDATxCFG(2)
269#define STV090x_OFFST_SDATx_OPD_FIELD 7
270#define STV090x_WIDTH_SDATx_OPD_FIELD 1
271#define STV090x_OFFST_SDATx_CONFIG_FIELD 1
272#define STV090x_WIDTH_SDATx_CONFIG_FIELD 6
273#define STV090x_OFFST_SDATx_XOR_FIELD 0
274#define STV090x_WIDTH_SDATx_XOR_FIELD 1
275
276#define STV090x_SCLTxCFG(__x) (0xf154 + (__x - 1) * 0x4)
277#define STV090x_SCLT1CFG STV090x_SCLTxCFG(1)
278#define STV090x_SCLT2CFG STV090x_SCLTxCFG(2)
279#define STV090x_OFFST_SCLTx_OPD_FIELD 7
280#define STV090x_WIDTH_SCLTx_OPD_FIELD 1
281#define STV090x_OFFST_SCLTx_CONFIG_FIELD 1
282#define STV090x_WIDTH_SCLTx_CONFIG_FIELD 6
283#define STV090x_OFFST_SCLTx_XOR_FIELD 0
284#define STV090x_WIDTH_SCLTx_XOR_FIELD 1
285
286#define STV090x_DISEQCOxCFG(__x) (0xf155 + (__x - 1) * 0x4)
287#define STV090x_DISEQCO1CFG STV090x_DISEQCOxCFG(1)
288#define STV090x_DISEQCO2CFG STV090x_DISEQCOxCFG(2)
289#define STV090x_OFFST_DISEQCOx_OPD_FIELD 7
290#define STV090x_WIDTH_DISEQCOx_OPD_FIELD 1
291#define STV090x_OFFST_DISEQCOx_CONFIG_FIELD 1
292#define STV090x_WIDTH_DISEQCOx_CONFIG_FIELD 6
293#define STV090x_OFFST_DISEQCOx_XOR_FIELD 0
294#define STV090x_WIDTH_DISEQCOx_XOR_FIELD 1
295
296#define STV090x_CLKOUT27CFG 0xf15a
297#define STV090x_OFFST_CLKOUT27_OPD_FIELD 7
298#define STV090x_WIDTH_CLKOUT27_OPD_FIELD 1
299#define STV090x_OFFST_CLKOUT27_CONFIG_FIELD 1
300#define STV090x_WIDTH_CLKOUT27_CONFIG_FIELD 6
301#define STV090x_OFFST_CLKOUT27_XOR_FIELD 0
302#define STV090x_WIDTH_CLKOUT27_XOR_FIELD 1
303
304#define STV090x_ERRORxCFG(__x) (0xf15b + (__x - 1) * 0x5)
305#define STV090x_ERROR1CFG STV090x_ERRORxCFG(1)
306#define STV090x_ERROR2CFG STV090x_ERRORxCFG(2)
307#define STV090x_ERROR3CFG STV090x_ERRORxCFG(3)
308#define STV090x_OFFST_ERRORx_OPD_FIELD 7
309#define STV090x_WIDTH_ERRORx_OPD_FIELD 1
310#define STV090x_OFFST_ERRORx_CONFIG_FIELD 1
311#define STV090x_WIDTH_ERRORx_CONFIG_FIELD 6
312#define STV090x_OFFST_ERRORx_XOR_FIELD 0
313#define STV090x_WIDTH_ERRORx_XOR_FIELD 1
314
315#define STV090x_DPNxCFG(__x) (0xf15c + (__x - 1) * 0x5)
316#define STV090x_DPN1CFG STV090x_DPNxCFG(1)
317#define STV090x_DPN2CFG STV090x_DPNxCFG(2)
318#define STV090x_DPN3CFG STV090x_DPNxCFG(3)
319#define STV090x_OFFST_DPNx_OPD_FIELD 7
320#define STV090x_WIDTH_DPNx_OPD_FIELD 1
321#define STV090x_OFFST_DPNx_CONFIG_FIELD 1
322#define STV090x_WIDTH_DPNx_CONFIG_FIELD 6
323#define STV090x_OFFST_DPNx_XOR_FIELD 0
324#define STV090x_WIDTH_DPNx_XOR_FIELD 1
325
326#define STV090x_STROUTxCFG(__x) (0xf15d + (__x - 1) * 0x5)
327#define STV090x_STROUT1CFG STV090x_STROUTxCFG(1)
328#define STV090x_STROUT2CFG STV090x_STROUTxCFG(2)
329#define STV090x_STROUT3CFG STV090x_STROUTxCFG(3)
330#define STV090x_OFFST_STROUTx_OPD_FIELD 7
331#define STV090x_WIDTH_STROUTx_OPD_FIELD 1
332#define STV090x_OFFST_STROUTx_CONFIG_FIELD 1
333#define STV090x_WIDTH_STROUTx_CONFIG_FIELD 6
334#define STV090x_OFFST_STROUTx_XOR_FIELD 0
335#define STV090x_WIDTH_STROUTx_XOR_FIELD 1
336
337#define STV090x_CLKOUTxCFG(__x) (0xf15e + (__x - 1) * 0x5)
338#define STV090x_CLKOUT1CFG STV090x_CLKOUTxCFG(1)
339#define STV090x_CLKOUT2CFG STV090x_CLKOUTxCFG(2)
340#define STV090x_CLKOUT3CFG STV090x_CLKOUTxCFG(3)
341#define STV090x_OFFST_CLKOUTx_OPD_FIELD 7
342#define STV090x_WIDTH_CLKOUTx_OPD_FIELD 1
343#define STV090x_OFFST_CLKOUTx_CONFIG_FIELD 1
344#define STV090x_WIDTH_CLKOUTx_CONFIG_FIELD 6
345#define STV090x_OFFST_CLKOUTx_XOR_FIELD 0
346#define STV090x_WIDTH_CLKOUTx_XOR_FIELD 1
347
348#define STV090x_DATAxCFG(__x) (0xf15f + (__x - 71) * 0x5)
349#define STV090x_DATA71CFG STV090x_DATAxCFG(71)
350#define STV090x_DATA72CFG STV090x_DATAxCFG(72)
351#define STV090x_DATA73CFG STV090x_DATAxCFG(73)
352#define STV090x_OFFST_DATAx_OPD_FIELD 7
353#define STV090x_WIDTH_DATAx_OPD_FIELD 1
354#define STV090x_OFFST_DATAx_CONFIG_FIELD 1
355#define STV090x_WIDTH_DATAx_CONFIG_FIELD 6
356#define STV090x_OFFST_DATAx_XOR_FIELD 0
357#define STV090x_WIDTH_DATAx_XOR_FIELD 1
358
359#define STV090x_NCOARSE 0xf1b3
360#define STV090x_OFFST_M_DIV_FIELD 0
361#define STV090x_WIDTH_M_DIV_FIELD 8
362
363#define STV090x_SYNTCTRL 0xf1b6
364#define STV090x_OFFST_STANDBY_FIELD 7
365#define STV090x_WIDTH_STANDBY_FIELD 1
366#define STV090x_OFFST_BYPASSPLLCORE_FIELD 6
367#define STV090x_WIDTH_BYPASSPLLCORE_FIELD 1
368#define STV090x_OFFST_SELX1RATIO_FIELD 5
369#define STV090x_WIDTH_SELX1RATIO_FIELD 1
370#define STV090x_OFFST_STOP_PLL_FIELD 3
371#define STV090x_WIDTH_SELX1RATIO_FIELD 1
372#define STV090x_OFFST_BYPASSPLLFSK_FIELD 2
373#define STV090x_WIDTH_BYPASSPLLFSK_FIELD 1
374#define STV090x_OFFST_SELOSCI_FIELD 1
375#define STV090x_WIDTH_SELOSCI_FIELD 1
376#define STV090x_OFFST_BYPASSPLLADC_FIELD 0
377#define STV090x_WIDTH_BYPASSPLLADC_FIELD 1
378
379#define STV090x_FILTCTRL 0xf1b7
380#define STV090x_OFFST_INV_CLK135_FIELD 7
381#define STV090x_WIDTH_INV_CLK135_FIELD 1
382#define STV090x_OFFST_SEL_FSKCKDIV_FIELD 2
383#define STV090x_WIDTH_SEL_FSKCKDIV_FIELD 1
384#define STV090x_OFFST_INV_CLKFSK_FIELD 1
385#define STV090x_WIDTH_INV_CLKFSK_FIELD 1
386#define STV090x_OFFST_BYPASS_APPLI_FIELD 0
387#define STV090x_WIDTH_BYPASS_APPLI_FIELD 1
388
389#define STV090x_PLLSTAT 0xf1b8
390#define STV090x_OFFST_PLLLOCK_FIELD 0
391#define STV090x_WIDTH_PLLLOCK_FIELD 1
392
393#define STV090x_STOPCLK1 0xf1c2
394#define STV090x_OFFST_STOP_CLKPKDT2_FIELD 6
395#define STV090x_WIDTH_STOP_CLKPKDT2_FIELD 1
396#define STV090x_OFFST_STOP_CLKPKDT1_FIELD 5
397#define STV090x_WIDTH_STOP_CLKPKDT1_FIELD 1
398#define STV090x_OFFST_STOP_CLKFEC_FIELD 4
399#define STV090x_WIDTH_STOP_CLKFEC_FIELD 1
400#define STV090x_OFFST_STOP_CLKADCI2_FIELD 3
401#define STV090x_WIDTH_STOP_CLKADCI2_FIELD 1
402#define STV090x_OFFST_INV_CLKADCI2_FIELD 2
403#define STV090x_WIDTH_INV_CLKADCI2_FIELD 1
404#define STV090x_OFFST_STOP_CLKADCI1_FIELD 1
405#define STV090x_WIDTH_STOP_CLKADCI1_FIELD 1
406#define STV090x_OFFST_INV_CLKADCI1_FIELD 0
407#define STV090x_WIDTH_INV_CLKADCI1_FIELD 1
408
409#define STV090x_STOPCLK2 0xf1c3
410#define STV090x_OFFST_STOP_CLKSAMP2_FIELD 4
411#define STV090x_WIDTH_STOP_CLKSAMP2_FIELD 1
412#define STV090x_OFFST_STOP_CLKSAMP1_FIELD 3
413#define STV090x_WIDTH_STOP_CLKSAMP1_FIELD 1
414#define STV090x_OFFST_STOP_CLKVIT2_FIELD 2
415#define STV090x_WIDTH_STOP_CLKVIT2_FIELD 1
416#define STV090x_OFFST_STOP_CLKVIT1_FIELD 1
417#define STV090x_WIDTH_STOP_CLKVIT1_FIELD 1
418#define STV090x_OFFST_STOP_CLKTS_FIELD 0
419#define STV090x_WIDTH_STOP_CLKTS_FIELD 1
420
421#define STV090x_TSTTNR0 0xf1df
422#define STV090x_OFFST_SEL_FSK_FIELD 7
423#define STV090x_WIDTH_SEL_FSK_FIELD 1
424#define STV090x_OFFST_FSK_PON_FIELD 2
425#define STV090x_WIDTH_FSK_PON_FIELD 1
426
427#define STV090x_TSTTNR1 0xf1e0
428#define STV090x_OFFST_ADC1_PON_FIELD 1
429#define STV090x_WIDTH_ADC1_PON_FIELD 1
430#define STV090x_OFFST_ADC1_INMODE_FIELD 0
431#define STV090x_WIDTH_ADC1_INMODE_FIELD 1
432
433#define STV090x_TSTTNR2 0xf1e1
434#define STV090x_OFFST_DISEQC1_PON_FIELD 5
435#define STV090x_WIDTH_DISEQC1_PON_FIELD 1
436
437#define STV090x_TSTTNR3 0xf1e2
438#define STV090x_OFFST_ADC2_PON_FIELD 1
439#define STV090x_WIDTH_ADC2_PON_FIELD 1
440#define STV090x_OFFST_ADC2_INMODE_FIELD 0
441#define STV090x_WIDTH_ADC2_INMODE_FIELD 1
442
443#define STV090x_TSTTNR4 0xf1e3
444#define STV090x_OFFST_DISEQC2_PON_FIELD 5
445#define STV090x_WIDTH_DISEQC2_PON_FIELD 1
446
447#define STV090x_FSKTFC2 0xf170
448#define STV090x_OFFST_FSKT_KMOD_FIELD 2
449#define STV090x_WIDTH_FSKT_KMOD_FIELD 6
450#define STV090x_OFFST_FSKT_CAR_FIELD 0
451#define STV090x_WIDTH_FSKT_CAR_FIELD 2
452
453#define STV090x_FSKTFC1 0xf171
454#define STV090x_OFFST_FSKTC1_CAR_FIELD 0
455#define STV090x_WIDTH_FSKTC1_CAR_FIELD 8
456
457#define STV090x_FSKTFC0 0xf172
458#define STV090x_OFFST_FSKTC0_CAR_FIELD 0
459#define STV090x_WIDTH_FSKTC0_CAR_FIELD 8
460
461#define STV090x_FSKTDELTAF1 0xf173
462#define STV090x_OFFST_FSKTF1_DELTAF_FIELD 0
463#define STV090x_WIDTH_FSKTF1_DELTAF_FIELD 4
464
465#define STV090x_FSKTDELTAF0 0xf174
466#define STV090x_OFFST_FSKTF0_DELTAF_FIELD 0
467#define STV090x_WIDTH_FSKTF0_DELTAF_FIELD 8
468
469#define STV090x_FSKTCTRL 0xf175
470#define STV090x_OFFST_FSKT_EN_SGN_FIELD 6
471#define STV090x_WIDTH_FSKT_EN_SGN__FIELD 1
472#define STV090x_OFFST_FSKT_MOD_SGN_FIELD 5
473#define STV090x_WIDTH_FSKT_MOD_SGN_FIELD 1
474#define STV090x_OFFST_FSKT_MOD_EN_FIELD 2
475#define STV090x_WIDTH_FSKT_MOD_EN_FIELD 3
476#define STV090x_OFFST_FSKT_DACMODE_FIELD 0
477#define STV090x_WIDTH_FSKT_DACMODE_FIELD 2
478
479#define STV090x_FSKRFC2 0xf176
480#define STV090x_OFFST_FSKRC2_DETSGN_FIELD 6
481#define STV090x_WIDTH_FSKRC2_DETSGN_FIELD 1
482#define STV090x_OFFST_FSKRC2_OUTSGN_FIELD 5
483#define STV090x_WIDTH_FSKRC2_OUTSGN_FIELD 1
484#define STV090x_OFFST_FSKRC2_KAGC_FIELD 2
485#define STV090x_WIDTH_FSKRC2_KAGC_FIELD 3
486#define STV090x_OFFST_FSKRC2_CAR_FIELD 0
487#define STV090x_WIDTH_FSKRC2_CAR_FIELD 2
488
489#define STV090x_FSKRFC1 0xf177
490#define STV090x_OFFST_FSKRC1_CAR_FIELD 0
491#define STV090x_WIDTH_FSKRC1_CAR_FIELD 8
492
493#define STV090x_FSKRFC0 0xf178
494#define STV090x_OFFST_FSKRC0_CAR_FIELD 0
495#define STV090x_WIDTH_FSKRC0_CAR_FIELD 8
496
497#define STV090x_FSKRK1 0xf179
498#define STV090x_OFFST_FSKR_K1_EXP_FIELD 5
499#define STV090x_WIDTH_FSKR_K1_EXP_FIELD 3
500#define STV090x_OFFST_FSKR_K1_MANT_FIELD 0
501#define STV090x_WIDTH_FSKR_K1_MANT_FIELD 5
502
503#define STV090x_FSKRK2 0xf17a
504#define STV090x_OFFST_FSKR_K2_EXP_FIELD 5
505#define STV090x_WIDTH_FSKR_K2_EXP_FIELD 3
506#define STV090x_OFFST_FSKR_K2_MANT_FIELD 0
507#define STV090x_WIDTH_FSKR_K2_MANT_FIELD 5
508
509#define STV090x_FSKRAGCR 0xf17b
510#define STV090x_OFFST_FSKR_OUTCTL_FIELD 6
511#define STV090x_WIDTH_FSKR_OUTCTL_FIELD 2
512#define STV090x_OFFST_FSKR_AGC_REF_FIELD 0
513#define STV090x_WIDTH_FSKR_AGC_REF_FIELD 6
514
515#define STV090x_FSKRAGC 0xf17c
516#define STV090x_OFFST_FSKR_AGC_ACCU_FIELD 0
517#define STV090x_WIDTH_FSKR_AGC_ACCU_FIELD 8
518
519#define STV090x_FSKRALPHA 0xf17d
520#define STV090x_OFFST_FSKR_ALPHA_EXP_FIELD 2
521#define STV090x_WIDTH_FSKR_ALPHA_EXP_FIELD 3
522#define STV090x_OFFST_FSKR_ALPHA_M_FIELD 0
523#define STV090x_WIDTH_FSKR_ALPHA_M_FIELD 2
524
525#define STV090x_FSKRPLTH1 0xf17e
526#define STV090x_OFFST_FSKR_BETA_FIELD 4
527#define STV090x_WIDTH_FSKR_BETA_FIELD 4
528#define STV090x_OFFST_FSKR_PLL_TRESH1_FIELD 0
529#define STV090x_WIDTH_FSKR_PLL_TRESH1_FIELD 4
530
531#define STV090x_FSKRPLTH0 0xf17f
532#define STV090x_OFFST_FSKR_PLL_TRESH0_FIELD 0
533#define STV090x_WIDTH_FSKR_PLL_TRESH0_FIELD 8
534
535#define STV090x_FSKRDF1 0xf180
536#define STV090x_OFFST_FSKR_DELTAF1_FIELD 0
537#define STV090x_WIDTH_FSKR_DELTAF1_FIELD 5
538
539#define STV090x_FSKRDF0 0xf181
540#define STV090x_OFFST_FSKR_DELTAF0_FIELD 0
541#define STV090x_WIDTH_FSKR_DELTAF0_FIELD 8
542
543#define STV090x_FSKRSTEPP 0xf182
544#define STV090x_OFFST_FSKR_STEP_PLUS_FIELD 0
545#define STV090x_WIDTH_FSKR_STEP_PLUS_FIELD 8
546
547#define STV090x_FSKRSTEPM 0xf183
548#define STV090x_OFFST_FSKR_STEP_MINUS_FIELD 0
549#define STV090x_WIDTH_FSKR_STEP_MINUS_FIELD 8
550
551#define STV090x_FSKRDET1 0xf184
552#define STV090x_OFFST_FSKR_CARDET1_ACCU_FIELD 0
553#define STV090x_WIDTH_FSKR_CARDET1_ACCU_FIELD 4
554
555#define STV090x_FSKRDET0 0xf185
556#define STV090x_OFFST_FSKR_CARDET0_ACCU_FIELD 0
557#define STV090x_WIDTH_FSKR_CARDET0_ACCU_FIELD 8
558
559#define STV090x_FSKRDTH1 0xf186
560#define STV090x_OFFST_FSKR_CARLOSS_THRESH1_FIELD 4
561#define STV090x_WIDTH_FSKR_CARLOSS_THRESH1_FIELD 4
562#define STV090x_OFFST_FSKR_CARDET_THRESH1_FIELD 0
563#define STV090x_WIDTH_FSKR_CARDET_THRESH1_FIELD 4
564
565#define STV090x_FSKRDTH0 0xf187
566#define STV090x_OFFST_FSKR_CARDET_THRESH0_FIELD 0
567#define STV090x_WIDTH_FSKR_CARDET_THRESH0_FIELD 8
568
569#define STV090x_FSKRLOSS 0xf188
570#define STV090x_OFFST_FSKR_CARLOSS_THRESH_FIELD 0
571#define STV090x_WIDTH_FSKR_CARLOSS_THRESH_FIELD 8
572
573#define STV090x_Px_DISTXCTL(__x) (0xF1A0 - (__x - 1) * 0x10)
574#define STV090x_P1_DISTXCTL (1)
575#define STV090x_P2_DISTXCTL (2)
576#define STV090x_OFFST_Px_TIM_OFF_FIELD 7
577#define STV090x_WIDTH_Px_TIM_OFF_FIELD 1
578#define STV090x_OFFST_Px_DISEQC_RESET_FIELD 6
579#define STV090x_WIDTH_Px_DISEQC_RESET_FIELD 1
580#define STV090x_OFFST_Px_TIM_CMD_FIELD 4
581#define STV090x_WIDTH_Px_TIM_CMD_FIELD 2
582#define STV090x_OFFST_Px_DIS_PRECHARGE_FIELD 3
583#define STV090x_WIDTH_Px_DIS_PRECHARGE_FIELD 1
584#define STV090x_OFFST_Px_DISTX_MODE_FIELD 0
585#define STV090x_WIDTH_Px_DISTX_MODE_FIELD 3
586
587#define STV090x_Px_DISRXCTL(__x) (0xf1a1 - (__x - 1) * 0x10)
588#define STV090x_P1_DISRXCTL (1)
589#define STV090x_P2_DISRXCTL (2)
590#define STV090x_OFFST_Px_RECEIVER_ON_FIELD 7
591#define STV090x_WIDTH_Px_RECEIVER_ON_FIELD 1
592#define STV090x_OFFST_Px_IGNO_SHORT22K_FIELD 6
593#define STV090x_WIDTH_Px_IGNO_SHORT22K_FIELD 1
594#define STV090x_OFFST_Px_ONECHIP_TRX_FIELD 5
595#define STV090x_WIDTH_Px_ONECHIP_TRX_FIELD 1
596#define STV090x_OFFST_Px_EXT_ENVELOP_FIELD 4
597#define STV090x_WIDTH_Px_EXT_ENVELOP_FIELD 1
598#define STV090x_OFFST_Px_PIN_SELECT_FIELD 2
599#define STV090x_WIDTH_Px_PIN_SELECT_FIELD 2
600#define STV090x_OFFST_Px_IRQ_RXEND_FIELD 1
601#define STV090x_WIDTH_Px_IRQ_RXEND_FIELD 1
602#define STV090x_OFFST_Px_IRQ_4NBYTES_FIELD 0
603#define STV090x_WIDTH_Px_IRQ_4NBYTES_FIELD 1
604
605#define STV090x_Px_DISRX_ST0(__x) (0xf1a4 - (__x - 1) * 0x10)
606#define STV090x_P1_DISRX_ST0 (1)
607#define STV090x_P2_DISRX_ST0 (2)
608#define STV090x_OFFST_Px_RX_END_FIELD 7
609#define STV090x_WIDTH_Px_RX_END_FIELD 1
610#define STV090x_OFFST_Px_RX_ACTIVE_FIELD 6
611#define STV090x_WIDTH_Px_RX_ACTIVE_FIELD 1
612#define STV090x_OFFST_Px_SHORT_22KHZ_FIELD 5
613#define STV090x_WIDTH_Px_SHORT_22KHZ_FIELD 1
614#define STV090x_OFFST_Px_CONT_TONE_FIELD 4
615#define STV090x_WIDTH_Px_CONT_TONE_FIELD 1
616#define STV090x_OFFST_Px_FIFO_4BREADY_FIELD 3
617#define STV090x_WIDTH_Px_FIFO_4BREADYFIELD 2
618#define STV090x_OFFST_Px_FIFO_EMPTY_FIELD 2
619#define STV090x_WIDTH_Px_FIFO_EMPTY_FIELD 1
620#define STV090x_OFFST_Px_ABORT_DISRX_FIELD 0
621#define STV090x_WIDTH_Px_ABORT_DISRX_FIELD 1
622
623#define STV090x_Px_DISRX_ST1(__x) (0xf1a5 - (__x - 1) * 0x10)
624#define STV090x_P1_DISRX_ST1 (1)
625#define STV090x_P2_DISRX_ST1 (2)
626#define STV090x_OFFST_Px_RX_FAIL_FIELD 7
627#define STV090x_WIDTH_Px_RX_FAIL_FIELD 1
628#define STV090x_OFFST_Px_FIFO_PARITYFAIL_FIELD 6
629#define STV090x_WIDTH_Px_FIFO_PARITYFAIL_FIELD 1
630#define STV090x_OFFST_Px_RX_NONBYTE_FIELD 5
631#define STV090x_WIDTH_Px_RX_NONBYTE_FIELD 1
632#define STV090x_OFFST_Px_FIFO_OVERFLOW_FIELD 4
633#define STV090x_WIDTH_Px_FIFO_OVERFLOW_FIELD 1
634#define STV090x_OFFST_Px_FIFO_BYTENBR_FIELD 0
635#define STV090x_WIDTH_Px_FIFO_BYTENBR_FIELD 4
636
637#define STV090x_Px_DISRXDATA(__x) (0xf1a6 - (__x - 1) * 0x10)
638#define STV090x_P1_DISRXDATA (1)
639#define STV090x_P2_DISRXDATA (2)
640#define STV090x_OFFST_Px_DISRX_DATA_FIELD 0
641#define STV090x_WIDTH_Px_DISRX_DATA_FIELD 8
642
643#define STV090x_Px_DISTXDATA(__x) (0xf1a7 - (__x - 1) * 0x10)
644#define STV090x_P1_DISTXDATA (1)
645#define STV090x_P2_DISTXDATA (2)
646#define STV090x_OFFST_Px_DISEQC_FIFO_FIELD 0
647#define STV090x_WIDTH_Px_DISEQC_FIFO_FIELD 8
648
649#define STV090x_Px_DISTXSTATUS(__x) (0xf1a8 - (__x - 1) * 0x10)
650#define STV090x_P1_DISTXSTATUS (1)
651#define STV090x_P2_DISTXSTATUS (2)
652#define STV090x_OFFST_Px_TX_FAIL_FIELD 7
653#define STV090x_WIDTH_Px_TX_FAIL_FIELD 1
654#define STV090x_OFFST_Px_FIFO_FULL_FIELD 6
655#define STV090x_WIDTH_Px_FIFO_FULL_FIELD 1
656#define STV090x_OFFST_Px_TX_IDLE_FIELD 5
657#define STV090x_WIDTH_Px_TX_IDLE_FIELD 1
658#define STV090x_OFFST_Px_GAP_BURST_FIELD 4
659#define STV090x_WIDTH_Px_GAP_BURST_FIELD 1
660#define STV090x_OFFST_Px_TXFIFO_BYTES_FIELD 0
661#define STV090x_WIDTH_Px_TXFIFO_BYTES_FIELD 4
662
663#define STV090x_Px_F22TX(__x) (0xf1a9 - (__x - 1) * 0x10)
664#define STV090x_P1_F22TX (1)
665#define STV090x_P2_F22TX (2)
666#define STV090x_OFFST_Px_F22_REG_FIELD 0
667#define STV090x_WIDTH_Px_F22_REG_FIELD 8
668
669#define STV090x_Px_F22RX(__x) (0xf1aa - (__x - 1) * 0x10)
670#define STV090x_P1_F22RX (1)
671#define STV090x_P2_F22RX (2)
672#define STV090x_OFFST_Px_F22RX_REG_FIELD 0
673#define STV090x_WIDTH_Px_F22RX_REG_FIELD 8
674
675#define STV090x_Px_ACRPRESC(__x) (0xf1ac - (__x - 1) * 0x10)
676#define STV090x_P1_ACRPRESC (1)
677#define STV090x_P2_ACRPRESC (2)
678#define STV090x_OFFST_Px_ACR_PRESC_FIELD 0
679#define STV090x_WIDTH_Px_ACR_PRESC_FIELD 3
680
681#define STV090x_Px_ACRDIV(__x) (0xf1ad - (__x - 1) * 0x10)
682#define STV090x_P1_ACRDIV (1)
683#define STV090x_P2_ACRDIV (2)
684#define STV090x_OFFST_Px_ACR_DIV_FIELD 0
685#define STV090x_WIDTH_Px_ACR_DIV_FIELD 8
686
687#define STV090x_Px_IQCONST(__x) (0xF400 - (__x - 1) * 0x200)
688#define STV090x_P1_IQCONST STV090x_Px_IQCONST(1)
689#define STV090x_P2_IQCONST STV090x_Px_IQCONST(2)
690#define STV090x_OFFST_Px_CONSTEL_SELECT_FIELD 5
691#define STV090x_WIDTH_Px_CONSTEL_SELECT_FIELD 2
692
693#define STV090x_Px_NOSCFG(__x) (0xF401 - (__x - 1) * 0x200)
694#define STV090x_P1_NOSCFG STV090x_Px_NOSCFG(1)
695#define STV090x_P2_NOSCFG STV090x_Px_NOSCFG(2)
696#define STV090x_OFFST_Px_NOSPLH_BETA_FIELD 3
697#define STV090x_WIDTH_Px_NOSPLH_BETA_FIELD 2
698#define STV090x_OFFST_Px_NOSDATA_BETA_FIELD 0
699#define STV090x_WIDTH_Px_NOSDATA_BETA_FIELD 3
700
701#define STV090x_Px_ISYMB(__x) (0xF402 - (__x - 1) * 0x200)
702#define STV090x_P1_ISYMB STV090x_Px_ISYMB(1)
703#define STV090x_P2_ISYMB STV090x_Px_ISYMB(2)
704#define STV090x_OFFST_Px_I_SYMBOL_FIELD 0
705#define STV090x_WIDTH_Px_I_SYMBOL_FIELD 8
706
707#define STV090x_Px_QSYMB(__x) (0xF403 - (__x - 1) * 0x200)
708#define STV090x_P1_QSYMB STV090x_Px_QSYMB(1)
709#define STV090x_P2_QSYMB STV090x_Px_QSYMB(2)
710#define STV090x_OFFST_Px_Q_SYMBOL_FIELD 0
711#define STV090x_WIDTH_Px_Q_SYMBOL_FIELD 8
712
713#define STV090x_Px_AGC1CFG(__x) (0xF404 - (__x - 1) * 0x200)
714#define STV090x_P1_AGC1CFG STV090x_Px_AGC1CFG(1)
715#define STV090x_P2_AGC1CFG STV090x_Px_AGC1CFG(2)
716#define STV090x_OFFST_Px_DC_FROZEN_FIELD 7
717#define STV090x_WIDTH_Px_DC_FROZEN_FIELD 1
718#define STV090x_OFFST_Px_DC_CORRECT_FIELD 6
719#define STV090x_WIDTH_Px_DC_CORRECT_FIELD 1
720#define STV090x_OFFST_Px_AMM_FROZEN_FIELD 5
721#define STV090x_WIDTH_Px_AMM_FROZEN_FIELD 1
722#define STV090x_OFFST_Px_AMM_CORRECT_FIELD 4
723#define STV090x_WIDTH_Px_AMM_CORRECT_FIELD 1
724#define STV090x_OFFST_Px_QUAD_FROZEN_FIELD 3
725#define STV090x_WIDTH_Px_QUAD_FROZEN_FIELD 1
726#define STV090x_OFFST_Px_QUAD_CORRECT_FIELD 2
727#define STV090x_WIDTH_Px_QUAD_CORRECT_FIELD 1
728
729#define STV090x_Px_AGC1CN(__x) (0xF406 - (__x - 1) * 0x200)
730#define STV090x_P1_AGC1CN STV090x_Px_AGC1CN(1)
731#define STV090x_P2_AGC1CN STV090x_Px_AGC1CN(2)
732#define STV090x_WIDTH_Px_AGC1_LOCKED_FIELD 7
733#define STV090x_OFFST_Px_AGC1_LOCKED_FIELD 1
734#define STV090x_OFFST_Px_AGC1_MINPOWER_FIELD 4
735#define STV090x_WIDTH_Px_AGC1_MINPOWER_FIELD 1
736#define STV090x_OFFST_Px_AGCOUT_FAST_FIELD 3
737#define STV090x_WIDTH_Px_AGCOUT_FAST_FIELD 1
738#define STV090x_OFFST_Px_AGCIQ_BETA_FIELD 0
739#define STV090x_WIDTH_Px_AGCIQ_BETA_FIELD 3
740
741#define STV090x_Px_AGC1REF(__x) (0xF407 - (__x - 1) * 0x200)
742#define STV090x_P1_AGC1REF STV090x_Px_AGC1REF(1)
743#define STV090x_P2_AGC1REF STV090x_Px_AGC1REF(2)
744#define STV090x_OFFST_Px_AGCIQ_REF_FIELD 0
745#define STV090x_WIDTH_Px_AGCIQ_REF_FIELD 8
746
747#define STV090x_Px_IDCCOMP(__x) (0xF408 - (__x - 1) * 0x200)
748#define STV090x_P1_IDCCOMP STV090x_Px_IDCCOMP(1)
749#define STV090x_P2_IDCCOMP STV090x_Px_IDCCOMP(2)
750#define STV090x_OFFST_Px_IAVERAGE_ADJ_FIELD 0
751#define STV090x_WIDTH_Px_IAVERAGE_ADJ_FIELD 8
752
753#define STV090x_Px_QDCCOMP(__x) (0xF409 - (__x - 1) * 0x200)
754#define STV090x_P1_QDCCOMP STV090x_Px_QDCCOMP(1)
755#define STV090x_P2_QDCCOMP STV090x_Px_QDCCOMP(2)
756#define STV090x_OFFST_Px_QAVERAGE_ADJ_FIELD 0
757#define STV090x_WIDTH_Px_QAVERAGE_ADJ_FIELD 8
758
759#define STV090x_Px_POWERI(__x) (0xF40A - (__x - 1) * 0x200)
760#define STV090x_P1_POWERI STV090x_Px_POWERI(1)
761#define STV090x_P2_POWERI STV090x_Px_POWERI(2)
762#define STV090x_OFFST_Px_POWER_I_FIELD 0
763#define STV090x_WIDTH_Px_POWER_I_FIELD 8
764
765#define STV090x_Px_POWERQ(__x) (0xF40B - (__x - 1) * 0x200)
766#define STV090x_P1_POWERQ STV090x_Px_POWERQ(1)
767#define STV090x_P2_POWERQ STV090x_Px_POWERQ(2)
768#define STV090x_OFFST_Px_POWER_Q_FIELD 0
769#define STV090x_WIDTH_Px_POWER_Q_FIELD 8
770
771#define STV090x_Px_AGC1AMM(__x) (0xF40C - (__x - 1) * 0x200)
772#define STV090x_P1_AGC1AMM STV090x_Px_AGC1AMM(1)
773#define STV090x_P2_AGC1AMM STV090x_Px_AGC1AMM(2)
774#define STV090x_OFFST_Px_AMM_VALUE_FIELD 0
775#define STV090x_WIDTH_Px_AMM_VALUE_FIELD 8
776
777#define STV090x_Px_AGC1QUAD(__x) (0xF40D - (__x - 1) * 0x200)
778#define STV090x_P1_AGC1QUAD STV090x_Px_AGC1QUAD(1)
779#define STV090x_P2_AGC1QUAD STV090x_Px_AGC1QUAD(2)
780#define STV090x_OFFST_Px_QUAD_VALUE_FIELD 0
781#define STV090x_WIDTH_Px_QUAD_VALUE_FIELD 8
782
783#define STV090x_Px_AGCIQINy(__x, __y) (0xF40F - (__x-1) * 0x200 - __y * 0x1)
784#define STV090x_P1_AGCIQIN0 STV090x_Px_AGCIQINy(1, 0)
785#define STV090x_P1_AGCIQIN1 STV090x_Px_AGCIQINy(1, 1)
786#define STV090x_P2_AGCIQIN0 STV090x_Px_AGCIQINy(2, 0)
787#define STV090x_P2_AGCIQIN1 STV090x_Px_AGCIQINy(2, 1)
788#define STV090x_OFFST_Px_AGCIQ_VALUE_FIELD 0
789#define STV090x_WIDTH_Px_AGCIQ_VALUE_FIELD 8
790
791#define STV090x_Px_DEMOD(__x) (0xF410 - (__x - 1) * 0x200)
792#define STV090x_P1_DEMOD STV090x_Px_DEMOD(1)
793#define STV090x_P2_DEMOD STV090x_Px_DEMOD(2)
794#define STV090x_OFFST_Px_SPECINV_CONTROL_FIELD 4
795#define STV090x_WIDTH_Px_SPECINV_CONTROL_FIELD 2
796#define STV090x_OFFST_Px_MANUAL_ROLLOFF_FIELD 2
797#define STV090x_WIDTH_Px_MANUAL_ROLLOFF_FIELD 1
798#define STV090x_OFFST_Px_ROLLOFF_CONTROL_FIELD 0
799#define STV090x_WIDTH_Px_ROLLOFF_CONTROL_FIELD 2
800
801#define STV090x_Px_DMDMODCOD(__x) (0xF411 - (__x - 1) * 0x200)
802#define STV090x_P1_DMDMODCOD STV090x_Px_DMDMODCOD(1)
803#define STV090x_P2_DMDMODCOD STV090x_Px_DMDMODCOD(2)
804#define STV090x_OFFST_Px_MANUAL_MODCOD_FIELD 7
805#define STV090x_WIDTH_Px_MANUAL_MODCOD_FIELD 1
806#define STV090x_OFFST_Px_DEMOD_MODCOD_FIELD 2
807#define STV090x_WIDTH_Px_DEMOD_MODCOD_FIELD 5
808#define STV090x_OFFST_Px_DEMOD_TYPE_FIELD 0
809#define STV090x_WIDTH_Px_DEMOD_TYPE_FIELD 2
810
811#define STV090x_Px_DSTATUS(__x) (0xF412 - (__x - 1) * 0x200)
812#define STV090x_P1_DSTATUS STV090x_Px_DSTATUS(1)
813#define STV090x_P2_DSTATUS STV090x_Px_DSTATUS(2)
814#define STV090x_OFFST_Px_CAR_LOCK_FIELD 7
815#define STV090x_WIDTH_Px_CAR_LOCK_FIELD 1
816#define STV090x_OFFST_Px_TMGLOCK_QUALITY_FIELD 5
817#define STV090x_WIDTH_Px_TMGLOCK_QUALITY_FIELD 2
818#define STV090x_OFFST_Px_LOCK_DEFINITIF_FIELD 3
819#define STV090x_WIDTH_Px_LOCK_DEFINITIF_FIELD 1
820
821#define STV090x_Px_DSTATUS2(__x) (0xF413 - (__x - 1) * 0x200)
822#define STV090x_P1_DSTATUS2 STV090x_Px_DSTATUS2(1)
823#define STV090x_P2_DSTATUS2 STV090x_Px_DSTATUS2(2)
824#define STV090x_OFFST_Px_DEMOD_DELOCK_FIELD 7
825#define STV090x_WIDTH_Px_DEMOD_DELOCK_FIELD 1
826#define STV090x_OFFST_Px_AGC1_NOSIGNALACK_FIELD 3
827#define STV090x_WIDTH_Px_AGC1_NOSIGNALACK_FIELD 1
828#define STV090x_OFFST_Px_AGC2_OVERFLOW_FIELD 2
829#define STV090x_WIDTH_Px_AGC2_OVERFLOW_FIELD 1
830#define STV090x_OFFST_Px_CFR_OVERFLOW_FIELD 1
831#define STV090x_WIDTH_Px_CFR_OVERFLOW_FIELD 1
832#define STV090x_OFFST_Px_GAMMA_OVERUNDER_FIELD 0
833#define STV090x_WIDTH_Px_GAMMA_OVERUNDER_FIELD 1
834
835#define STV090x_Px_DMDCFGMD(__x) (0xF414 - (__x - 1) * 0x200)
836#define STV090x_P1_DMDCFGMD STV090x_Px_DMDCFGMD(1)
837#define STV090x_P2_DMDCFGMD STV090x_Px_DMDCFGMD(2)
838#define STV090x_OFFST_Px_DVBS2_ENABLE_FIELD 7
839#define STV090x_WIDTH_Px_DVBS2_ENABLE_FIELD 1
840#define STV090x_OFFST_Px_DVBS1_ENABLE_FIELD 6
841#define STV090x_WIDTH_Px_DVBS1_ENABLE_FIELD 1
842#define STV090x_OFFST_Px_CFR_AUTOSCAN_FIELD 5 /* check */
843#define STV090x_WIDTH_Px_CFR_AUTOSCAN_FIELD 1
844#define STV090x_OFFST_Px_SCAN_ENABLE_FIELD 4 /* check */
845#define STV090x_WIDTH_Px_SCAN_ENABLE_FIELD 1
846#define STV090x_OFFST_Px_TUN_AUTOSCAN_FIELD 3
847#define STV090x_WIDTH_Px_TUN_AUTOSCAN_FIELD 1
848#define STV090x_OFFST_Px_NOFORCE_RELOCK_FIELD 2
849#define STV090x_WIDTH_Px_NOFORCE_RELOCK_FIELD 1
850#define STV090x_OFFST_Px_TUN_RNG_FIELD 0
851#define STV090x_WIDTH_Px_TUN_RNG_FIELD 2
852
853#define STV090x_Px_DMDCFG2(__x) (0xF415 - (__x - 1) * 0x200)
854#define STV090x_P1_DMDCFG2 STV090x_Px_DMDCFG2(1)
855#define STV090x_P2_DMDCFG2 STV090x_Px_DMDCFG2(2)
856#define STV090x_OFFST_Px_S1S2_SEQUENTIAL_FIELD 6
857#define STV090x_WIDTH_Px_S1S2_SEQUENTIAL_FIELD 1
858
859#define STV090x_Px_DMDISTATE(__x) (0xF416 - (__x - 1) * 0x200)
860#define STV090x_P1_DMDISTATE STV090x_Px_DMDISTATE(1)
861#define STV090x_P2_DMDISTATE STV090x_Px_DMDISTATE(2)
862#define STV090x_OFFST_Px_I2C_DEMOD_MODE_FIELD 0
863#define STV090x_WIDTH_Px_I2C_DEMOD_MODE_FIELD 5
864
865#define STV090x_Px_DMDTOM(__x) (0xF417 - (__x - 1) * 0x200) /* check */
866#define STV090x_P1_DMDTOM STV090x_Px_DMDTOM(1)
867#define STV090x_P2_DMDTOM STV090x_Px_DMDTOM(2)
868
869#define STV090x_Px_DMDSTATE(__x) (0xF41B - (__x - 1) * 0x200)
870#define STV090x_P1_DMDSTATE STV090x_Px_DMDSTATE(1)
871#define STV090x_P2_DMDSTATE STV090x_Px_DMDSTATE(2)
872#define STV090x_OFFST_Px_HEADER_MODE_FIELD 5
873#define STV090x_WIDTH_Px_HEADER_MODE_FIELD 2
874
875#define STV090x_Px_DMDFLYW(__x) (0xF41C - (__x - 1) * 0x200)
876#define STV090x_P1_DMDFLYW STV090x_Px_DMDFLYW(1)
877#define STV090x_P2_DMDFLYW STV090x_Px_DMDFLYW(2)
878#define STV090x_OFFST_Px_I2C_IRQVAL_FIELD 4
879#define STV090x_WIDTH_Px_I2C_IRQVAL_FIELD 4
880#define STV090x_OFFST_Px_FLYWHEEL_CPT_FIELD 0 /* check */
881#define STV090x_WIDTH_Px_FLYWHEEL_CPT_FIELD 4
882
883#define STV090x_Px_DSTATUS3(__x) (0xF41D - (__x - 1) * 0x200)
884#define STV090x_P1_DSTATUS3 STV090x_Px_DSTATUS3(1)
885#define STV090x_P2_DSTATUS3 STV090x_Px_DSTATUS3(2)
886#define STV090x_OFFST_Px_DEMOD_CFGMODE_FIELD 5
887#define STV090x_WIDTH_Px_DEMOD_CFGMODE_FIELD 2
888
889#define STV090x_Px_DMDCFG3(__x) (0xF41E - (__x - 1) * 0x200)
890#define STV090x_P1_DMDCFG3 STV090x_Px_DMDCFG3(1)
891#define STV090x_P2_DMDCFG3 STV090x_Px_DMDCFG3(2)
892#define STV090x_OFFST_Px_NOSTOP_FIFOFULL_FIELD 3
893#define STV090x_WIDTH_Px_NOSTOP_FIFOFULL_FIELD 1
894
895#define STV090x_Px_CORRELMANT(__x) (0xF420 - (__x - 1) * 0x200)
896#define STV090x_P1_CORRELMANT STV090x_Px_CORRELMANT(1)
897#define STV090x_P2_CORRELMANT STV090x_Px_CORRELMANT(2)
898#define STV090x_OFFST_Px_CORREL_MANT_FIELD 0
899#define STV090x_WIDTH_Px_CORREL_MANT_FIELD 8
900
901#define STV090x_Px_CORRELABS(__x) (0xF421 - (__x - 1) * 0x200)
902#define STV090x_P1_CORRELABS STV090x_Px_CORRELABS(1)
903#define STV090x_P2_CORRELABS STV090x_Px_CORRELABS(2)
904#define STV090x_OFFST_Px_CORREL_ABS_FIELD 0
905#define STV090x_WIDTH_Px_CORREL_ABS_FIELD 8
906
907#define STV090x_Px_CORRELEXP(__x) (0xF422 - (__x - 1) * 0x200)
908#define STV090x_P1_CORRELEXP STV090x_Px_CORRELEXP(1)
909#define STV090x_P2_CORRELEXP STV090x_Px_CORRELEXP(2)
910#define STV090x_OFFST_Px_CORREL_ABSEXP_FIELD 4
911#define STV090x_WIDTH_Px_CORREL_ABSEXP_FIELD 4
912#define STV090x_OFFST_Px_CORREL_EXP_FIELD 0
913#define STV090x_WIDTH_Px_CORREL_EXP_FIELD 4
914
915#define STV090x_Px_PLHMODCOD(__x) (0xF424 - (__x - 1) * 0x200)
916#define STV090x_P1_PLHMODCOD STV090x_Px_PLHMODCOD(1)
917#define STV090x_P2_PLHMODCOD STV090x_Px_PLHMODCOD(2)
918#define STV090x_OFFST_Px_SPECINV_DEMOD_FIELD 7
919#define STV090x_WIDTH_Px_SPECINV_DEMOD_FIELD 1
920#define STV090x_OFFST_Px_PLH_MODCOD_FIELD 2
921#define STV090x_WIDTH_Px_PLH_MODCOD_FIELD 5
922#define STV090x_OFFST_Px_PLH_TYPE_FIELD 0
923#define STV090x_WIDTH_Px_PLH_TYPE_FIELD 2
924
925#define STV090x_Px_AGC2REF(__x) (0xF42D - (__x - 1) * 0x200)
926#define STV090x_P1_AGC2REF STV090x_Px_AGC2REF(1)
927#define STV090x_P2_AGC2REF STV090x_Px_AGC2REF(2)
928#define STV090x_OFFST_Px_AGC2_REF_FIELD 0
929#define STV090x_WIDTH_Px_AGC2_REF_FIELD 8
930
931#define STV090x_Px_AGC1ADJ(__x) (0xF42E - (__x - 1) * 0x200)
932#define STV090x_P1_AGC1ADJ STV090x_Px_AGC1ADJ(1)
933#define STV090x_P2_AGC1ADJ STV090x_Px_AGC1ADJ(2)
934#define STV090x_OFFST_Px_AGC1_ADJUSTED_FIELD 0
935#define STV090x_WIDTH_Px_AGC1_ADJUSTED_FIELD 7
936
937#define STV090x_Px_AGC2Iy(__x, __y) (0xF437 - (__x - 1) * 0x200 - __y * 0x1)
938#define STV090x_P1_AGC2I0 STV090x_Px_AGC2Iy(1, 0)
939#define STV090x_P1_AGC2I1 STV090x_Px_AGC2Iy(1, 1)
940#define STV090x_P2_AGC2I0 STV090x_Px_AGC2Iy(2, 0)
941#define STV090x_P2_AGC2I1 STV090x_Px_AGC2Iy(2, 1)
942#define STV090x_OFFST_Px_AGC2_INTEGRATOR_FIELD 0
943#define STV090x_WIDTH_Px_AGC2_INTEGRATOR_FIELD 8
944
945#define STV090x_Px_CARCFG(__x) (0xF438 - (__x - 1) * 0x200)
946#define STV090x_P1_CARCFG STV090x_Px_CARCFG(1)
947#define STV090x_P2_CARCFG STV090x_Px_CARCFG(2)
948#define STV090x_OFFST_Px_EN_CAR2CENTER_FIELD 5
949#define STV090x_WIDTH_Px_EN_CAR2CENTER_FIELD 1
950#define STV090x_OFFST_Px_ROTATON_FIELD 2
951#define STV090x_WIDTH_Px_ROTATON_FIELD 1
952#define STV090x_OFFST_Px_PH_DET_ALGO_FIELD 0
953#define STV090x_WIDTH_Px_PH_DET_ALGO_FIELD 2
954
955#define STV090x_Px_ACLC(__x) (0xF439 - (__x - 1) * 0x200)
956#define STV090x_P1_ACLC STV090x_Px_ACLC(1)
957#define STV090x_P2_ACLC STV090x_Px_ACLC(2)
958#define STV090x_OFFST_Px_CAR_ALPHA_MANT_FIELD 4
959#define STV090x_WIDTH_Px_CAR_ALPHA_MANT_FIELD 2
960#define STV090x_OFFST_Px_CAR_ALPHA_EXP_FIELD 0
961#define STV090x_WIDTH_Px_CAR_ALPHA_EXP_FIELD 4
962
963#define STV090x_Px_BCLC(__x) (0xF43A - (__x - 1) * 0x200)
964#define STV090x_P1_BCLC STV090x_Px_BCLC(1)
965#define STV090x_P2_BCLC STV090x_Px_BCLC(2)
966#define STV090x_OFFST_Px_CAR_BETA_MANT_FIELD 4
967#define STV090x_WIDTH_Px_CAR_BETA_MANT_FIELD 2
968#define STV090x_OFFST_Px_CAR_BETA_EXP_FIELD 0
969#define STV090x_WIDTH_Px_CAR_BETA_EXP_FIELD 4
970
971#define STV090x_Px_CARFREQ(__x) (0xF43D - (__x - 1) * 0x200)
972#define STV090x_P1_CARFREQ STV090x_Px_CARFREQ(1)
973#define STV090x_P2_CARFREQ STV090x_Px_CARFREQ(2)
974#define STV090x_OFFST_Px_KC_COARSE_EXP_FIELD 4
975#define STV090x_WIDTH_Px_KC_COARSE_EXP_FIELD 4
976#define STV090x_OFFST_Px_BETA_FREQ_FIELD 0
977#define STV090x_WIDTH_Px_BETA_FREQ_FIELD 4
978
979#define STV090x_Px_CARHDR(__x) (0xF43E - (__x - 1) * 0x200)
980#define STV090x_P1_CARHDR STV090x_Px_CARHDR(1)
981#define STV090x_P2_CARHDR STV090x_Px_CARHDR(2)
982#define STV090x_OFFST_Px_FREQ_HDR_FIELD 0
983#define STV090x_WIDTH_Px_FREQ_HDR_FIELD 8
984
985#define STV090x_Px_LDT(__x) (0xF43F - (__x - 1) * 0x200)
986#define STV090x_P1_LDT STV090x_Px_LDT(1)
987#define STV090x_P2_LDT STV090x_Px_LDT(2)
988#define STV090x_OFFST_Px_CARLOCK_THRES_FIELD 0
989#define STV090x_WIDTH_Px_CARLOCK_THRES_FIELD 8
990
991#define STV090x_Px_LDT2(__x) (0xF440 - (__x - 1) * 0x200)
992#define STV090x_P1_LDT2 STV090x_Px_LDT2(1)
993#define STV090x_P2_LDT2 STV090x_Px_LDT2(2)
994#define STV090x_OFFST_Px_CARLOCK_THRES2_FIELD 0
995#define STV090x_WIDTH_Px_CARLOCK_THRES2_FIELD 8
996
997#define STV090x_Px_CFRICFG(__x) (0xF441 - (__x - 1) * 0x200)
998#define STV090x_P1_CFRICFG STV090x_Px_CFRICFG(1)
999#define STV090x_P2_CFRICFG STV090x_Px_CFRICFG(2)
1000#define STV090x_OFFST_Px_NEG_CFRSTEP_FIELD 0
1001#define STV090x_WIDTH_Px_NEG_CFRSTEP_FIELD 1
1002
1003#define STV090x_Pn_CFRUPy(__x, __y) (0xF443 - (__x - 1) * 0x200 - __y * 0x1)
1004#define STV090x_P1_CFRUP0 STV090x_Pn_CFRUPy(1, 0)
1005#define STV090x_P1_CFRUP1 STV090x_Pn_CFRUPy(1, 1)
1006#define STV090x_P2_CFRUP0 STV090x_Pn_CFRUPy(2, 0)
1007#define STV090x_P2_CFRUP1 STV090x_Pn_CFRUPy(2, 1)
1008#define STV090x_OFFST_Px_CFR_UP_FIELD 0
1009#define STV090x_WIDTH_Px_CFR_UP_FIELD 8
1010
1011#define STV090x_Pn_CFRLOWy(__x, __y) (0xF447 - (__x - 1) * 0x200 - __y * 0x1)
1012#define STV090x_P1_CFRLOW0 STV090x_Pn_CFRLOWy(1, 0)
1013#define STV090x_P1_CFRLOW1 STV090x_Pn_CFRLOWy(1, 1)
1014#define STV090x_P2_CFRLOW0 STV090x_Pn_CFRLOWy(2, 0)
1015#define STV090x_P2_CFRLOW1 STV090x_Pn_CFRLOWy(2, 1)
1016#define STV090x_OFFST_Px_CFR_LOW_FIELD 0
1017#define STV090x_WIDTH_Px_CFR_LOW_FIELD 8
1018
1019#define STV090x_Pn_CFRINITy(__x, __y) (0xF449 - (__x - 1) * 0x200 - __y * 0x1)
1020#define STV090x_P1_CFRINIT0 STV090x_Pn_CFRINITy(1, 0)
1021#define STV090x_P1_CFRINIT1 STV090x_Pn_CFRINITy(1, 1)
1022#define STV090x_P2_CFRINIT0 STV090x_Pn_CFRINITy(2, 0)
1023#define STV090x_P2_CFRINIT1 STV090x_Pn_CFRINITy(2, 1)
1024#define STV090x_OFFST_Px_CFR_INIT_FIELD 0
1025#define STV090x_WIDTH_Px_CFR_INIT_FIELD 8
1026
1027#define STV090x_Px_CFRINC1(__x) (0xF44A - (__x - 1) * 0x200)
1028#define STV090x_P1_CFRINC1 STV090x_Px_CFRINC1(1)
1029#define STV090x_P2_CFRINC1 STV090x_Px_CFRINC1(2)
1030#define STV090x_OFFST_Px_CFR_INC1_FIELD 0
1031#define STV090x_WIDTH_Px_CFR_INC1_FIELD 7
1032
1033#define STV090x_Px_CFRINC0(__x) (0xF44B - (__x - 1) * 0x200)
1034#define STV090x_P1_CFRINC0 STV090x_Px_CFRINC0(1)
1035#define STV090x_P2_CFRINC0 STV090x_Px_CFRINC0(2)
1036#define STV090x_OFFST_Px_CFR_INC0_FIELD 4
1037#define STV090x_WIDTH_Px_CFR_INC0_FIELD 4
1038
1039#define STV090x_Pn_CFRy(__x, __y) (0xF44E - (__x - 1) * 0x200 - __y * 0x1)
1040#define STV090x_P1_CFR0 STV090x_Pn_CFRy(1, 0)
1041#define STV090x_P1_CFR1 STV090x_Pn_CFRy(1, 1)
1042#define STV090x_P1_CFR2 STV090x_Pn_CFRy(1, 2)
1043#define STV090x_P2_CFR0 STV090x_Pn_CFRy(2, 0)
1044#define STV090x_P2_CFR1 STV090x_Pn_CFRy(2, 1)
1045#define STV090x_P2_CFR2 STV090x_Pn_CFRy(2, 2)
1046#define STV090x_OFFST_Px_CAR_FREQ_FIELD 0
1047#define STV090x_WIDTH_Px_CAR_FREQ_FIELD 8
1048
1049#define STV090x_Px_LDI(__x) (0xF44F - (__x - 1) * 0x200)
1050#define STV090x_P1_LDI STV090x_Px_LDI(1)
1051#define STV090x_P2_LDI STV090x_Px_LDI(2)
1052#define STV090x_OFFST_Px_LOCK_DET_INTEGR_FIELD 0
1053#define STV090x_WIDTH_Px_LOCK_DET_INTEGR_FIELD 8
1054
1055#define STV090x_Px_TMGCFG(__x) (0xF450 - (__x - 1) * 0x200)
1056#define STV090x_P1_TMGCFG STV090x_Px_TMGCFG(1)
1057#define STV090x_P2_TMGCFG STV090x_Px_TMGCFG(2)
1058#define STV090x_OFFST_Px_TMGLOCK_BETA_FIELD 6
1059#define STV090x_WIDTH_Px_TMGLOCK_BETA_FIELD 2
1060#define STV090x_OFFST_Px_DO_TIMING_FIELD 4
1061#define STV090x_WIDTH_Px_DO_TIMING_FIELD 1
1062#define STV090x_OFFST_Px_TMG_MINFREQ_FIELD 0
1063#define STV090x_WIDTH_Px_TMG_MINFREQ_FIELD 2
1064
1065#define STV090x_Px_RTC(__x) (0xF451 - (__x - 1) * 0x200)
1066#define STV090x_P1_RTC STV090x_Px_RTC(1)
1067#define STV090x_P2_RTC STV090x_Px_RTC(2)
1068#define STV090x_OFFST_Px_TMGALPHA_EXP_FIELD 4
1069#define STV090x_WIDTH_Px_TMGALPHA_EXP_FIELD 4
1070#define STV090x_OFFST_Px_TMGBETA_EXP_FIELD 0
1071#define STV090x_WIDTH_Px_TMGBETA_EXP_FIELD 4
1072
1073#define STV090x_Px_RTCS2(__x) (0xF452 - (__x - 1) * 0x200)
1074#define STV090x_P1_RTCS2 STV090x_Px_RTCS2(1)
1075#define STV090x_P2_RTCS2 STV090x_Px_RTCS2(2)
1076#define STV090x_OFFST_Px_TMGALPHAS2_EXP_FIELD 4
1077#define STV090x_WIDTH_Px_TMGALPHAS2_EXP_FIELD 4
1078#define STV090x_OFFST_Px_TMGBETAS2_EXP_FIELD 0
1079#define STV090x_WIDTH_Px_TMGBETAS2_EXP_FIELD 4
1080
1081#define STV090x_Px_TMGTHRISE(__x) (0xF453 - (__x - 1) * 0x200)
1082#define STV090x_P1_TMGTHRISE STV090x_Px_TMGTHRISE(1)
1083#define STV090x_P2_TMGTHRISE STV090x_Px_TMGTHRISE(2)
1084#define STV090x_OFFST_Px_TMGLOCK_THRISE_FIELD 0
1085#define STV090x_WIDTH_Px_TMGLOCK_THRISE_FIELD 8
1086
1087#define STV090x_Px_TMGTHFALL(__x) (0xF454 - (__x - 1) * 0x200)
1088#define STV090x_P1_TMGTHFALL STV090x_Px_TMGTHFALL(1)
1089#define STV090x_P2_TMGTHFALL STV090x_Px_TMGTHFALL(2)
1090#define STV090x_OFFST_Px_TMGLOCK_THFALL_FIELD 0
1091#define STV090x_WIDTH_Px_TMGLOCK_THFALL_FIELD 8
1092
1093#define STV090x_Px_SFRUPRATIO(__x) (0xF455 - (__x - 1) * 0x200)
1094#define STV090x_P1_SFRUPRATIO STV090x_Px_SFRUPRATIO(1)
1095#define STV090x_P2_SFRUPRATIO STV090x_Px_SFRUPRATIO(2)
1096#define STV090x_OFFST_Px_SFR_UPRATIO_FIELD 0
1097#define STV090x_WIDTH_Px_SFR_UPRATIO_FIELD 8
1098
1099#define STV090x_Px_SFRLOWRATIO(__x) (0xF456 - (__x - 1) * 0x200)
1100#define STV090x_P1_SFRLOWRATIO STV090x_Px_SFRLOWRATIO(1)
1101#define STV090x_P2_SFRLOWRATIO STV090x_Px_SFRLOWRATIO(2)
1102#define STV090x_OFFST_Px_SFR_LOWRATIO_FIELD 0
1103#define STV090x_WIDTH_Px_SFR_LOWRATIO_FIELD 8
1104
1105#define STV090x_Px_KREFTMG(__x) (0xF458 - (__x - 1) * 0x200)
1106#define STV090x_P1_KREFTMG STV090x_Px_KREFTMG(1)
1107#define STV090x_P2_KREFTMG STV090x_Px_KREFTMG(2)
1108#define STV090x_OFFST_Px_KREF_TMG_FIELD 0
1109#define STV090x_WIDTH_Px_KREF_TMG_FIELD 8
1110
1111#define STV090x_Px_SFRSTEP(__x) (0xF459 - (__x - 1) * 0x200)
1112#define STV090x_P1_SFRSTEP STV090x_Px_SFRSTEP(1)
1113#define STV090x_P2_SFRSTEP STV090x_Px_SFRSTEP(2)
1114#define STV090x_OFFST_Px_SFR_SCANSTEP_FIELD 4
1115#define STV090x_WIDTH_Px_SFR_SCANSTEP_FIELD 4
1116#define STV090x_OFFST_Px_SFR_CENTERSTEP_FIELD 0
1117#define STV090x_WIDTH_Px_SFR_CENTERSTEP_FIELD 4
1118
1119#define STV090x_Px_TMGCFG2(__x) (0xF45A - (__x - 1) * 0x200)
1120#define STV090x_P1_TMGCFG2 STV090x_Px_TMGCFG2(1)
1121#define STV090x_P2_TMGCFG2 STV090x_Px_TMGCFG2(2)
1122#define STV090x_OFFST_Px_SFRRATIO_FINE_FIELD 0
1123#define STV090x_WIDTH_Px_SFRRATIO_FINE_FIELD 1
1124
1125#define STV090x_Px_SFRINIT1(__x) (0xF45E - (__x - 1) * 0x200)
1126#define STV090x_P1_SFRINIT1 STV090x_Px_SFRINIT1(1)
1127#define STV090x_P2_SFRINIT1 STV090x_Px_SFRINIT1(2)
1128#define STV090x_OFFST_Px_SFR_INIT_FIELD 0
1129#define STV090x_WIDTH_Px_SFR_INIT_FIELD 8
1130
1131#define STV090x_Px_SFRINIT0(__x) (0xF45F - (__x - 1) * 0x200)
1132#define STV090x_P1_SFRINIT0 STV090x_Px_SFRINIT0(1)
1133#define STV090x_P2_SFRINIT0 STV090x_Px_SFRINIT0(2)
1134#define STV090x_OFFST_Px_SFR_INIT_FIELD 0
1135#define STV090x_WIDTH_Px_SFR_INIT_FIELD 8
1136
1137#define STV090x_Px_SFRUP1(__x) (0xF460 - (__x - 1) * 0x200)
1138#define STV090x_P1_SFRUP1 STV090x_Px_SFRUP1(1)
1139#define STV090x_P2_SFRUP1 STV090x_Px_SFRUP1(2)
1140#define STV090x_OFFST_Px_SYMB_FREQ_UP1_FIELD 0
1141#define STV090x_WIDTH_Px_SYMB_FREQ_UP1_FIELD 7
1142
1143#define STV090x_Px_SFRUP0(__x) (0xF461 - (__x - 1) * 0x200)
1144#define STV090x_P1_SFRUP0 STV090x_Px_SFRUP0(1)
1145#define STV090x_P2_SFRUP0 STV090x_Px_SFRUP0(2)
1146#define STV090x_OFFST_Px_SYMB_FREQ_UP0_FIELD 0
1147#define STV090x_WIDTH_Px_SYMB_FREQ_UP0_FIELD 8
1148
1149#define STV090x_Px_SFRLOW1(__x) (0xF462 - (__x - 1) * 0x200)
1150#define STV090x_P1_SFRLOW1 STV090x_Px_SFRLOW1(1)
1151#define STV090x_P2_SFRLOW1 STV090x_Px_SFRLOW1(2)
1152#define STV090x_OFFST_Px_SYMB_FREQ_LOW1_FIELD 0
1153#define STV090x_WIDTH_Px_SYMB_FREQ_LOW1_FIELD 7
1154
1155#define STV090x_Px_SFRLOW0(__x) (0xF463 - (__x - 1) * 0x200)
1156#define STV090x_P1_SFRLOW0 STV090x_Px_SFRLOW0(1)
1157#define STV090x_P2_SFRLOW0 STV090x_Px_SFRLOW0(2)
1158#define STV090x_OFFST_Px_SYMB_FREQ_LOW0_FIELD 0
1159#define STV090x_WIDTH_Px_SYMB_FREQ_LOW0_FIELD 8
1160
1161#define STV090x_Px_SFRy(__x, __y) (0xF464 - (__x-1) * 0x200 + (3 - __y))
1162#define STV090x_P1_SFR0 STV090x_Px_SFRy(1, 0)
1163#define STV090x_P1_SFR1 STV090x_Px_SFRy(1, 1)
1164#define STV090x_P1_SFR2 STV090x_Px_SFRy(1, 2)
1165#define STV090x_P1_SFR3 STV090x_Px_SFRy(1, 3)
1166#define STV090x_P2_SFR0 STV090x_Px_SFRy(2, 0)
1167#define STV090x_P2_SFR1 STV090x_Px_SFRy(2, 1)
1168#define STV090x_P2_SFR2 STV090x_Px_SFRy(2, 2)
1169#define STV090x_P2_SFR3 STV090x_Px_SFRy(2, 3)
1170#define STV090x_OFFST_Px_SYMB_FREQ_FIELD 0
1171#define STV090x_WIDTH_Px_SYMB_FREQ_FIELD 32
1172
1173#define STV090x_Px_TMGREG2(__x) (0xF468 - (__x - 1) * 0x200)
1174#define STV090x_P1_TMGREG2 STV090x_Px_TMGREG2(1)
1175#define STV090x_P2_TMGREG2 STV090x_Px_TMGREG2(2)
1176#define STV090x_OFFST_Px_TMGREG_FIELD 0
1177#define STV090x_WIDTH_Px_TMGREG_FIELD 8
1178
1179#define STV090x_Px_TMGREG1(__x) (0xF469 - (__x - 1) * 0x200)
1180#define STV090x_P1_TMGREG1 STV090x_Px_TMGREG1(1)
1181#define STV090x_P2_TMGREG1 STV090x_Px_TMGREG1(2)
1182#define STV090x_OFFST_Px_TMGREG_FIELD 0
1183#define STV090x_WIDTH_Px_TMGREG_FIELD 8
1184
1185#define STV090x_Px_TMGREG0(__x) (0xF46A - (__x - 1) * 0x200)
1186#define STV090x_P1_TMGREG0 STV090x_Px_TMGREG0(1)
1187#define STV090x_P2_TMGREG0 STV090x_Px_TMGREG0(2)
1188#define STV090x_OFFST_Px_TMGREG_FIELD 0
1189#define STV090x_WIDTH_Px_TMGREG_FIELD 8
1190
1191#define STV090x_Px_TMGLOCKy(__x, __y) (0xF46C - (__x - 1) * 0x200 - __y * 0x1)
1192#define STV090x_P1_TMGLOCK0 STV090x_Px_TMGLOCKy(1, 0)
1193#define STV090x_P1_TMGLOCK1 STV090x_Px_TMGLOCKy(1, 1)
1194#define STV090x_P2_TMGLOCK0 STV090x_Px_TMGLOCKy(2, 0)
1195#define STV090x_P2_TMGLOCK1 STV090x_Px_TMGLOCKy(2, 1)
1196#define STV090x_OFFST_Px_TMGLOCK_LEVEL_FIELD 0
1197#define STV090x_WIDTH_Px_TMGLOCK_LEVEL_FIELD 8
1198
1199#define STV090x_Px_TMGOBS(__x) (0xF46D - (__x - 1) * 0x200)
1200#define STV090x_P1_TMGOBS STV090x_Px_TMGOBS(1)
1201#define STV090x_P2_TMGOBS STV090x_Px_TMGOBS(2)
1202#define STV090x_OFFST_Px_ROLLOFF_STATUS_FIELD 6
1203#define STV090x_WIDTH_Px_ROLLOFF_STATUS_FIELD 2
1204
1205#define STV090x_Px_EQUALCFG(__x) (0xF46F - (__x - 1) * 0x200)
1206#define STV090x_P1_EQUALCFG STV090x_Px_EQUALCFG(1)
1207#define STV090x_P2_EQUALCFG STV090x_Px_EQUALCFG(2)
1208#define STV090x_OFFST_Px_EQUAL_ON_FIELD 6
1209#define STV090x_WIDTH_Px_EQUAL_ON_FIELD 1
1210#define STV090x_OFFST_Px_MU_EQUALDFE_FIELD 0
1211#define STV090x_WIDTH_Px_MU_EQUALDFE_FIELD 3
1212
1213#define STV090x_Px_EQUAIy(__x, __y) (0xf470 - (__x - 1) * 0x200 + (__y - 1))
1214#define STV090x_P1_EQUAI1 STV090x_Px_EQUAIy(1, 1)
1215#define STV090x_P1_EQUAI2 STV090x_Px_EQUAIy(1, 2)
1216#define STV090x_P1_EQUAI3 STV090x_Px_EQUAIy(1, 3)
1217#define STV090x_P1_EQUAI4 STV090x_Px_EQUAIy(1, 4)
1218#define STV090x_P1_EQUAI5 STV090x_Px_EQUAIy(1, 5)
1219#define STV090x_P1_EQUAI6 STV090x_Px_EQUAIy(1, 6)
1220#define STV090x_P1_EQUAI7 STV090x_Px_EQUAIy(1, 7)
1221#define STV090x_P1_EQUAI8 STV090x_Px_EQUAIy(1, 8)
1222
1223#define STV090x_P2_EQUAI1 STV090x_Px_EQUAIy(2, 1)
1224#define STV090x_P2_EQUAI2 STV090x_Px_EQUAIy(2, 2)
1225#define STV090x_P2_EQUAI3 STV090x_Px_EQUAIy(2, 3)
1226#define STV090x_P2_EQUAI4 STV090x_Px_EQUAIy(2, 4)
1227#define STV090x_P2_EQUAI5 STV090x_Px_EQUAIy(2, 5)
1228#define STV090x_P2_EQUAI6 STV090x_Px_EQUAIy(2, 6)
1229#define STV090x_P2_EQUAI7 STV090x_Px_EQUAIy(2, 7)
1230#define STV090x_P2_EQUAI8 STV090x_Px_EQUAIy(2, 8)
1231#define STV090x_OFFST_Px_EQUA_ACCIy_FIELD 0
1232#define STV090x_WIDTH_Px_EQUA_ACCIy_FIELD 8
1233
1234#define STV090x_Px_EQUAQy(__x, __y) (0xf471 - (__x - 1) * 0x200 + (__y - 1))
1235#define STV090x_P1_EQUAQ1 STV090x_Px_EQUAQy(1, 1)
1236#define STV090x_P1_EQUAQ2 STV090x_Px_EQUAQy(1, 2)
1237#define STV090x_P1_EQUAQ3 STV090x_Px_EQUAQy(1, 3)
1238#define STV090x_P1_EQUAQ4 STV090x_Px_EQUAQy(1, 4)
1239#define STV090x_P1_EQUAQ5 STV090x_Px_EQUAQy(1, 5)
1240#define STV090x_P1_EQUAQ6 STV090x_Px_EQUAQy(1, 6)
1241#define STV090x_P1_EQUAQ7 STV090x_Px_EQUAQy(1, 7)
1242#define STV090x_P1_EQUAQ8 STV090x_Px_EQUAQy(1, 8)
1243
1244#define STV090x_P2_EQUAQ1 STV090x_Px_EQUAQy(2, 1)
1245#define STV090x_P2_EQUAQ2 STV090x_Px_EQUAQy(2, 2)
1246#define STV090x_P2_EQUAQ3 STV090x_Px_EQUAQy(2, 3)
1247#define STV090x_P2_EQUAQ4 STV090x_Px_EQUAQy(2, 4)
1248#define STV090x_P2_EQUAQ5 STV090x_Px_EQUAQy(2, 5)
1249#define STV090x_P2_EQUAQ6 STV090x_Px_EQUAQy(2, 6)
1250#define STV090x_P2_EQUAQ7 STV090x_Px_EQUAQy(2, 7)
1251#define STV090x_P2_EQUAQ8 STV090x_Px_EQUAQy(2, 8)
1252#define STV090x_OFFST_Px_EQUA_ACCQy_FIELD 0
1253#define STV090x_WIDTH_Px_EQUA_ACCQy_FIELD 8
1254
1255#define STV090x_Px_NNOSDATATy(__x, __y) (0xf481 - (__x - 1) * 0x200 - __y * 0x1)
1256#define STV090x_P1_NNOSDATAT0 STV090x_Px_NNOSDATATy(1, 0)
1257#define STV090x_P1_NNOSDATAT1 STV090x_Px_NNOSDATATy(1, 1)
1258#define STV090x_P2_NNOSDATAT0 STV090x_Px_NNOSDATATy(2, 0)
1259#define STV090x_P2_NNOSDATAT1 STV090x_Px_NNOSDATATy(2, 1)
1260#define STV090x_OFFST_Px_NOSDATAT_NORMED_FIELD 0
1261#define STV090x_WIDTH_Px_NOSDATAT_NORMED_FIELD 8
1262
1263#define STV090x_Px_NNOSDATAy(__x, __y) (0xf483 - (__x - 1) * 0x200 - __y * 0x1)
1264#define STV090x_P1_NNOSDATA0 STV090x_Px_NNOSDATAy(1, 0)
1265#define STV090x_P1_NNOSDATA1 STV090x_Px_NNOSDATAy(1, 1)
1266#define STV090x_P2_NNOSDATA0 STV090x_Px_NNOSDATAy(2, 0)
1267#define STV090x_P2_NNOSDATA1 STV090x_Px_NNOSDATAy(2, 1)
1268#define STV090x_OFFST_Px_NOSDATA_NORMED_FIELD 0
1269#define STV090x_WIDTH_Px_NOSDATA_NORMED_FIELD 8
1270
1271#define STV090x_Px_NNOSPLHTy(__x, __y) (0xf485 - (__x - 1) * 0x200 - __y * 0x1)
1272#define STV090x_P1_NNOSPLHT0 STV090x_Px_NNOSPLHTy(1, 0)
1273#define STV090x_P1_NNOSPLHT1 STV090x_Px_NNOSPLHTy(1, 1)
1274#define STV090x_P2_NNOSPLHT0 STV090x_Px_NNOSPLHTy(2, 0)
1275#define STV090x_P2_NNOSPLHT1 STV090x_Px_NNOSPLHTy(2, 1)
1276#define STV090x_OFFST_Px_NOSPLHT_NORMED_FIELD 0
1277#define STV090x_WIDTH_Px_NOSPLHT_NORMED_FIELD 8
1278
1279#define STV090x_Px_NNOSPLHy(__x, __y) (0xf487 - (__x - 1) * 0x200 - __y * 0x1)
1280#define STV090x_P1_NNOSPLH0 STV090x_Px_NNOSPLHy(1, 0)
1281#define STV090x_P1_NNOSPLH1 STV090x_Px_NNOSPLHy(1, 1)
1282#define STV090x_P2_NNOSPLH0 STV090x_Px_NNOSPLHy(2, 0)
1283#define STV090x_P2_NNOSPLH1 STV090x_Px_NNOSPLHy(2, 1)
1284#define STV090x_OFFST_Px_NOSPLH_NORMED_FIELD 0
1285#define STV090x_WIDTH_Px_NOSPLH_NORMED_FIELD 8
1286
1287#define STV090x_Px_NOSDATATy(__x, __y) (0xf489 - (__x - 1) * 0x200 - __y * 0x1)
1288#define STV090x_P1_NOSDATAT0 STV090x_Px_NOSDATATy(1, 0)
1289#define STV090x_P1_NOSDATAT1 STV090x_Px_NOSDATATy(1, 1)
1290#define STV090x_P2_NOSDATAT0 STV090x_Px_NOSDATATy(2, 0)
1291#define STV090x_P2_NOSDATAT1 STV090x_Px_NOSDATATy(2, 1)
1292#define STV090x_OFFST_Px_NOSDATAT_UNNORMED_FIELD 0
1293#define STV090x_WIDTH_Px_NOSDATAT_UNNORMED_FIELD 8
1294
1295#define STV090x_Px_NOSDATAy(__x, __y) (0xf48b - (__x - 1) * 0x200 - __y * 0x1)
1296#define STV090x_P1_NOSDATA0 STV090x_Px_NOSDATAy(1, 0)
1297#define STV090x_P1_NOSDATA1 STV090x_Px_NOSDATAy(1, 1)
1298#define STV090x_P2_NOSDATA0 STV090x_Px_NOSDATAy(2, 0)
1299#define STV090x_P2_NOSDATA1 STV090x_Px_NOSDATAy(2, 1)
1300#define STV090x_OFFST_Px_NOSDATA_UNNORMED_FIELD 0
1301#define STV090x_WIDTH_Px_NOSDATA_UNNORMED_FIELD 8
1302
1303#define STV090x_Px_NOSPLHTy(__x, __y) (0xf48d - (__x - 1) * 0x200 - __y * 0x1)
1304#define STV090x_P1_NOSPLHT0 STV090x_Px_NOSPLHTy(1, 0)
1305#define STV090x_P1_NOSPLHT1 STV090x_Px_NOSPLHTy(1, 1)
1306#define STV090x_P2_NOSPLHT0 STV090x_Px_NOSPLHTy(2, 0)
1307#define STV090x_P2_NOSPLHT1 STV090x_Px_NOSPLHTy(2, 1)
1308#define STV090x_OFFST_Px_NOSPLHT_UNNORMED_FIELD 0
1309#define STV090x_WIDTH_Px_NOSPLHT_UNNORMED_FIELD 8
1310
1311#define STV090x_Px_NOSPLHy(__x, __y) (0xf48f - (__x - 1) * 0x200 - __y * 0x1)
1312#define STv090x_P1_NOSPLH0 STV090x_Px_NOSPLHy(1, 0)
1313#define STv090x_P1_NOSPLH1 STV090x_Px_NOSPLHy(1, 1)
1314#define STv090x_P2_NOSPLH0 STV090x_Px_NOSPLHy(2, 0)
1315#define STv090x_P2_NOSPLH1 STV090x_Px_NOSPLHy(2, 1)
1316#define STV090x_OFFST_Px_NOSPLH_UNNORMED_FIELD 0
1317#define STV090x_WIDTH_Px_NOSPLH_UNNORMED_FIELD 8
1318
1319#define STV090x_Px_CAR2CFG(__x) (0xf490 - (__x - 1) * 0x200)
1320#define STV090x_P1_CAR2CFG STV090x_Px_CAR2CFG(1)
1321#define STV090x_P2_CAR2CFG STV090x_Px_CAR2CFG(2)
1322#define STV090x_OFFST_Px_PN4_SELECT_FIELD 6
1323#define STV090x_WIDTH_Px_PN4_SELECT_FIELD 1
1324#define STV090x_OFFST_Px_CFR2_STOPDVBS1_FIELD 5
1325#define STV090x_WIDTH_Px_CFR2_STOPDVBS1_FIELD 1
1326#define STV090x_OFFST_Px_ROTA2ON_FIELD 2
1327#define STV090x_WIDTH_Px_ROTA2ON_FIELD 1
1328#define STV090x_OFFST_Px_PH_DET_ALGO2_FIELD 0
1329#define STV090x_WIDTH_Px_PH_DET_ALGO2_FIELD 2
1330
1331#define STV090x_Px_ACLC2(__x) (0xf491 - (__x - 1) * 0x200)
1332#define STV090x_P1_ACLC2 STV090x_Px_ACLC2(1)
1333#define STV090x_P2_ACLC2 STV090x_Px_ACLC2(2)
1334#define STV090x_OFFST_Px_CAR2_ALPHA_MANT_FIELD 4
1335#define STV090x_WIDTH_Px_CAR2_ALPHA_MANT_FIELD 2
1336#define STV090x_OFFST_Px_CAR2_ALPHA_EXP_FIELD 0
1337#define STV090x_WIDTH_Px_CAR2_ALPHA_EXP_FIELD 4
1338
1339#define STV090x_Px_BCLC2(__x) (0xf492 - (__x - 1) * 0x200)
1340#define STV090x_P1_BCLC2 STV090x_Px_BCLC2(1)
1341#define STV090x_P2_BCLC2 STV090x_Px_BCLC2(2)
1342#define STV090x_OFFST_Px_CAR2_BETA_MANT_FIELD 4
1343#define STV090x_WIDTH_Px_CAR2_BETA_MANT_FIELD 2
1344#define STV090x_OFFST_Px_CAR2_BETA_EXP_FIELD 0
1345#define STV090x_WIDTH_Px_CAR2_BETA_EXP_FIELD 4
1346
1347#define STV090x_Px_ACLC2S2Q(__x) (0xf497 - (__x - 1) * 0x200)
1348#define STV090x_P1_ACLC2S2Q STV090x_Px_ACLC2S2Q(1)
1349#define STV090x_P2_ACLC2S2Q STV090x_Px_ACLC2S2Q(2)
1350#define STV090x_OFFST_Px_ENAB_SPSKSYMB_FIELD 7
1351#define STV090x_WIDTH_Px_ENAB_SPSKSYMB_FIELD 1
1352#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_M_FIELD 4
1353#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_M_FIELD 2
1354#define STV090x_OFFST_Px_CAR2S2_Q_ALPH_E_FIELD 0
1355#define STV090x_WIDTH_Px_CAR2S2_Q_ALPH_E_FIELD 4
1356
1357#define STV090x_Px_ACLC2S28(__x) (0xf498 - (__x - 1) * 0x200)
1358#define STV090x_P1_ACLC2S28 STV090x_Px_ACLC2S28(1)
1359#define STV090x_P2_ACLC2S28 STV090x_Px_ACLC2S28(2)
1360#define STV090x_OFFST_Px_CAR2S2_8_ALPH_M_FIELD 4
1361#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_M_FIELD 2
1362#define STV090x_OFFST_Px_CAR2S2_8_ALPH_E_FIELD 0
1363#define STV090x_WIDTH_Px_CAR2S2_8_ALPH_E_FIELD 4
1364
1365#define STV090x_Px_ACLC2S216A(__x) (0xf499 - (__x - 1) * 0x200)
1366#define STV090x_P1_ACLC2S216A STV090x_Px_ACLC2S216A(1)
1367#define STV090x_P2_ACLC2S216A STV090x_Px_ACLC2S216A(2)
1368#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_M_FIELD 4
1369#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_M_FIELD 2
1370#define STV090x_OFFST_Px_CAR2S2_16A_ALPH_E_FIELD 0
1371#define STV090x_WIDTH_Px_CAR2S2_16A_ALPH_E_FIELD 4
1372
1373#define STV090x_Px_ACLC2S232A(__x) (0xf499 - (__x - 1) * 0x200)
1374#define STV090x_P1_ACLC2S232A STV090x_Px_ACLC2S216A(1)
1375#define STV090x_P2_ACLC2S232A STV090x_Px_ACLC2S216A(2)
1376#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_M_FIELD 4
1377#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_M_FIELD 2
1378#define STV090x_OFFST_Px_CAR2S2_32A_ALPH_E_FIELD 0
1379#define STV090x_WIDTH_Px_CAR2S2_32A_ALPH_E_FIELD 4
1380
1381#define STV090x_Px_BCLC2S2Q(__x) (0xf49c - (__x - 1) * 0x200)
1382#define STV090x_P1_BCLC2S2Q STV090x_Px_BCLC2S2Q(1)
1383#define STV090x_P2_BCLC2S2Q STV090x_Px_BCLC2S2Q(2)
1384#define STV090x_OFFST_Px_CAR2S2_Q_BETA_M_FIELD 4
1385#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_M_FIELD 2
1386#define STV090x_OFFST_Px_CAR2S2_Q_BETA_E_FIELD 0
1387#define STV090x_WIDTH_Px_CAR2S2_Q_BETA_E_FIELD 4
1388
1389#define STV090x_Px_BCLC2S28(__x) (0xf49d - (__x - 1) * 0x200)
1390#define STV090x_P1_BCLC2S28 STV090x_Px_BCLC2S28(1)
1391#define STV090x_P2_BCLC2S28 STV090x_Px_BCLC2S28(1)
1392#define STV090x_OFFST_Px_CAR2S2_8_BETA_M_FIELD 4
1393#define STV090x_WIDTH_Px_CAR2S2_8_BETA_M_FIELD 2
1394#define STV090x_OFFST_Px_CAR2S2_8_BETA_E_FIELD 0
1395#define STV090x_WIDTH_Px_CAR2S2_8_BETA_E_FIELD 4
1396
1397#define STV090x_Px_BCLC2S216A(__x) (0xf49d - (__x - 1) * 0x200)
1398#define STV090x_P1_BCLC2S216A STV090x_Px_BCLC2S216A(1)
1399#define STV090x_P2_BCLC2S216A STV090x_Px_BCLC2S216A(1)
1400#define STV090x_OFFST_Px_CAR2S2_16A_BETA_M_FIELD 4
1401#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_M_FIELD 2
1402#define STV090x_OFFST_Px_CAR2S2_16A_BETA_E_FIELD 0
1403#define STV090x_WIDTH_Px_CAR2S2_16A_BETA_E_FIELD 4
1404
1405#define STV090x_Px_BCLC2S232A(__x) (0xf49d - (__x - 1) * 0x200)
1406#define STV090x_P1_BCLC2S232A STV090x_Px_BCLC2S232A(1)
1407#define STV090x_P2_BCLC2S232A STV090x_Px_BCLC2S232A(1)
1408#define STV090x_OFFST_Px_CAR2S2_32A_BETA_M_FIELD 4
1409#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_M_FIELD 2
1410#define STV090x_OFFST_Px_CAR2S2_32A_BETA_E_FIELD 0
1411#define STV090x_WIDTH_Px_CAR2S2_32A_BETA_E_FIELD 4
1412
1413#define STV090x_Px_PLROOT2(__x) (0xf4ac - (__x - 1) * 0x200)
1414#define STV090x_P1_PLROOT2 STV090x_Px_PLROOT2(1)
1415#define STV090x_P2_PLROOT2 STV090x_Px_PLROOT2(2)
1416#define STV090x_OFFST_Px_PLSCRAMB_MODE_FIELD 2
1417#define STV090x_WIDTH_Px_PLSCRAMB_MODE_FIELD 2
1418#define STV090x_OFFST_Px_PLSCRAMB_ROOT_FIELD 0
1419#define STV090x_WIDTH_Px_PLSCRAMB_ROOT_FIELD 2
1420
1421#define STV090x_Px_PLROOT1(__x) (0xf4ad - (__x - 1) * 0x200)
1422#define STV090x_P1_PLROOT1 STV090x_Px_PLROOT1(1)
1423#define STV090x_P2_PLROOT1 STV090x_Px_PLROOT1(2)
1424#define STV090x_OFFST_Px_PLSCRAMB_ROOT1_FIELD 0
1425#define STV090x_WIDTH_Px_PLSCRAMB_ROOT1_FIELD 8
1426
1427#define STV090x_Px_PLROOT0(__x) (0xf4ae - (__x - 1) * 0x200)
1428#define STV090x_P1_PLROOT0 STV090x_Px_PLROOT0(1)
1429#define STV090x_P2_PLROOT0 STV090x_Px_PLROOT0(2)
1430#define STV090x_OFFST_Px_PLSCRAMB_ROOT0_FIELD 0
1431#define STV090x_WIDTH_Px_PLSCRAMB_ROOT0_FIELD 8
1432
1433#define STV090x_Px_MODCODLST0(__x) (0xf4b0 - (__x - 1) * 0x200) /* check */
1434#define STV090x_P1_MODCODLST0 STV090x_Px_MODCODLST0(1)
1435#define STV090x_P2_MODCODLST0 STV090x_Px_MODCODLST0(2)
1436
1437#define STV090x_Px_MODCODLST1(__x) (0xf4b1 - (__x - 1) * 0x200)
1438#define STV090x_P1_MODCODLST1 STV090x_Px_MODCODLST1(1)
1439#define STV090x_P2_MODCODLST1 STV090x_Px_MODCODLST1(2)
1440#define STV090x_OFFST_Px_DIS_MODCOD29_FIELD 4
1441#define STV090x_WIDTH_Px_DIS_MODCOD29T_FIELD 4
1442#define STV090x_OFFST_Px_DIS_32PSK_9_10_FIELD 0
1443#define STV090x_WIDTH_Px_DIS_32PSK_9_10_FIELD 4
1444
1445#define STV090x_Px_MODCODLST2(__x) (0xf4b2 - (__x - 1) * 0x200)
1446#define STV090x_P1_MODCODLST2 STV090x_Px_MODCODLST2(1)
1447#define STV090x_P2_MODCODLST2 STV090x_Px_MODCODLST2(2)
1448#define STV090x_OFFST_Px_DIS_32PSK_8_9_FIELD 4
1449#define STV090x_WIDTH_Px_DIS_32PSK_8_9_FIELD 4
1450#define STV090x_OFFST_Px_DIS_32PSK_5_6_FIELD 0
1451#define STV090x_WIDTH_Px_DIS_32PSK_5_6_FIELD 4
1452
1453#define STV090x_Px_MODCODLST3(__x) (0xf4b3 - (__x - 1) * 0x200)
1454#define STV090x_P1_MODCODLST3 STV090x_Px_MODCODLST3(1)
1455#define STV090x_P2_MODCODLST3 STV090x_Px_MODCODLST3(2)
1456#define STV090x_OFFST_Px_DIS_32PSK_4_5_FIELD 4
1457#define STV090x_WIDTH_Px_DIS_32PSK_4_5_FIELD 4
1458#define STV090x_OFFST_Px_DIS_32PSK_3_4_FIELD 0
1459#define STV090x_WIDTH_Px_DIS_32PSK_3_4_FIELD 4
1460
1461#define STV090x_Px_MODCODLST4(__x) (0xf4b4 - (__x - 1) * 0x200)
1462#define STV090x_P1_MODCODLST4 STV090x_Px_MODCODLST4(1)
1463#define STV090x_P2_MODCODLST4 STV090x_Px_MODCODLST4(2)
1464#define STV090x_OFFST_Px_DIS_16PSK_9_10_FIELD 4
1465#define STV090x_WIDTH_Px_DIS_16PSK_9_10_FIELD 4
1466#define STV090x_OFFST_Px_DIS_16PSK_8_9_FIELD 0
1467#define STV090x_WIDTH_Px_DIS_16PSK_8_9_FIELD 4
1468
1469#define STV090x_Px_MODCODLST5(__x) (0xf4b5 - (__x - 1) * 0x200)
1470#define STV090x_P1_MODCODLST5 STV090x_Px_MODCODLST5(1)
1471#define STV090x_P2_MODCODLST5 STV090x_Px_MODCODLST5(2)
1472#define STV090x_OFFST_Px_DIS_16PSK_5_6_FIELD 4
1473#define STV090x_WIDTH_Px_DIS_16PSK_5_6_FIELD 4
1474#define STV090x_OFFST_Px_DIS_16PSK_4_5_FIELD 0
1475#define STV090x_WIDTH_Px_DIS_16PSK_4_5_FIELD 4
1476
1477#define STV090x_Px_MODCODLST6(__x) (0xf4b6 - (__x - 1) * 0x200)
1478#define STV090x_P1_MODCODLST6 STV090x_Px_MODCODLST6(1)
1479#define STV090x_P2_MODCODLST6 STV090x_Px_MODCODLST6(2)
1480#define STV090x_OFFST_Px_DIS_16PSK_3_4_FIELD 4
1481#define STV090x_WIDTH_Px_DIS_16PSK_3_4_FIELD 4
1482#define STV090x_OFFST_Px_DIS_16PSK_2_3_FIELD 0
1483#define STV090x_WIDTH_Px_DIS_16PSK_2_3_FIELD 4
1484
1485#define STV090x_Px_MODCODLST7(__x) (0xf4b7 - (__x - 1) * 0x200)
1486#define STV090x_P1_MODCODLST7 STV090x_Px_MODCODLST7(1)
1487#define STV090x_P2_MODCODLST7 STV090x_Px_MODCODLST7(2)
1488#define STV090x_OFFST_Px_DIS_8P_9_10_FIELD 4
1489#define STV090x_WIDTH_Px_DIS_8P_9_10_FIELD 4
1490#define STV090x_OFFST_Px_DIS_8P_8_9_FIELD 0
1491#define STV090x_WIDTH_Px_DIS_8P_8_9_FIELD 4
1492
1493#define STV090x_Px_MODCODLST8(__x) (0xf4b8 - (__x - 1) * 0x200)
1494#define STV090x_P1_MODCODLST8 STV090x_Px_MODCODLST8(1)
1495#define STV090x_P2_MODCODLST8 STV090x_Px_MODCODLST8(2)
1496#define STV090x_OFFST_Px_DIS_8P_5_6_FIELD 4
1497#define STV090x_WIDTH_Px_DIS_8P_5_6_FIELD 4
1498#define STV090x_OFFST_Px_DIS_8P_3_4_FIELD 0
1499#define STV090x_WIDTH_Px_DIS_8P_3_4_FIELD 4
1500
1501#define STV090x_Px_MODCODLST9(__x) (0xf4b9 - (__x - 1) * 0x200)
1502#define STV090x_P1_MODCODLST9 STV090x_Px_MODCODLST9(1)
1503#define STV090x_P2_MODCODLST9 STV090x_Px_MODCODLST9(2)
1504#define STV090x_OFFST_Px_DIS_8P_2_3_FIELD 4
1505#define STV090x_WIDTH_Px_DIS_8P_2_3_FIELD 4
1506#define STV090x_OFFST_Px_DIS_8P_3_5_FIELD 0
1507#define STV090x_WIDTH_Px_DIS_8P_3_5_FIELD 4
1508
1509#define STV090x_Px_MODCODLSTA(__x) (0xf4ba - (__x - 1) * 0x200)
1510#define STV090x_P1_MODCODLSTA STV090x_Px_MODCODLSTA(1)
1511#define STV090x_P2_MODCODLSTA STV090x_Px_MODCODLSTA(2)
1512#define STV090x_OFFST_Px_DIS_QP_9_10_FIELD 4
1513#define STV090x_WIDTH_Px_DIS_QP_9_10_FIELD 4
1514#define STV090x_OFFST_Px_DIS_QP_8_9_FIELD 0
1515#define STV090x_WIDTH_Px_DIS_QP_8_9_FIELD 4
1516
1517#define STV090x_Px_MODCODLSTB(__x) (0xf4bb - (__x - 1) * 0x200)
1518#define STV090x_P1_MODCODLSTB STV090x_Px_MODCODLSTB(1)
1519#define STV090x_P2_MODCODLSTB STV090x_Px_MODCODLSTB(2)
1520#define STV090x_OFFST_Px_DIS_QP_5_6_FIELD 4
1521#define STV090x_WIDTH_Px_DIS_QP_5_6_FIELD 4
1522#define STV090x_OFFST_Px_DIS_QP_4_5_FIELD 0
1523#define STV090x_WIDTH_Px_DIS_QP_4_5_FIELD 4
1524
1525#define STV090x_Px_MODCODLSTC(__x) (0xf4bc - (__x - 1) * 0x200)
1526#define STV090x_P1_MODCODLSTC STV090x_Px_MODCODLSTC(1)
1527#define STV090x_P2_MODCODLSTC STV090x_Px_MODCODLSTC(2)
1528#define STV090x_OFFST_Px_DIS_QP_3_4_FIELD 4
1529#define STV090x_WIDTH_Px_DIS_QP_3_4_FIELD 4
1530#define STV090x_OFFST_Px_DIS_QP_2_3_FIELD 0
1531#define STV090x_WIDTH_Px_DIS_QP_2_3_FIELD 4
1532
1533#define STV090x_Px_MODCODLSTD(__x) (0xf4bd - (__x - 1) * 0x200)
1534#define STV090x_P1_MODCODLSTD STV090x_Px_MODCODLSTD(1)
1535#define STV090x_P2_MODCODLSTD STV090x_Px_MODCODLSTD(2)
1536#define STV090x_OFFST_Px_DIS_QP_3_5_FIELD 4
1537#define STV090x_WIDTH_Px_DIS_QP_3_5_FIELD 4
1538#define STV090x_OFFST_Px_DIS_QP_1_2_FIELD 0
1539#define STV090x_WIDTH_Px_DIS_QP_1_2_FIELD 4
1540
1541#define STV090x_Px_MODCODLSTE(__x) (0xf4be - (__x - 1) * 0x200)
1542#define STV090x_P1_MODCODLSTE STV090x_Px_MODCODLSTE(1)
1543#define STV090x_P2_MODCODLSTE STV090x_Px_MODCODLSTE(2)
1544#define STV090x_OFFST_Px_DIS_QP_2_5_FIELD 4
1545#define STV090x_WIDTH_Px_DIS_QP_2_5_FIELD 4
1546#define STV090x_OFFST_Px_DIS_QP_1_3_FIELD 0
1547#define STV090x_WIDTH_Px_DIS_QP_1_3_FIELD 4
1548
1549#define STV090x_Px_MODCODLSTF(__x) (0xf4bf - (__x - 1) * 0x200)
1550#define STV090x_P1_MODCODLSTF STV090x_Px_MODCODLSTF(1)
1551#define STV090x_P2_MODCODLSTF STV090x_Px_MODCODLSTF(2)
1552#define STV090x_OFFST_Px_DIS_QP_1_4_FIELD 4
1553#define STV090x_WIDTH_Px_DIS_QP_1_4_FIELD 4
1554
1555#define STV090x_Px_DMDRESCFG(__x) (0xF4C6 - (__x - 1) * 0x200)
1556#define STV090x_P1_DMDRESCFG STV090x_Px_DMDRESCFG(1)
1557#define STV090x_P2_DMDRESCFG STV090x_Px_DMDRESCFG(2)
1558#define STV090x_OFFST_Px_DMDRES_RESET_FIELD 7
1559#define STV090x_WIDTH_Px_DMDRES_RESET_FIELD 1
1560
1561#define STV090x_Px_DMDRESADR(__x) (0xF4C7 - (__x - 1) * 0x200)
1562#define STV090x_P1_DMDRESADR STV090x_Px_DMDRESADR(1)
1563#define STV090x_P2_DMDRESADR STV090x_Px_DMDRESADR(2)
1564#define STV090x_OFFST_Px_DMDRES_RESNBR_FIELD 0
1565#define STV090x_WIDTH_Px_DMDRES_RESNBR_FIELD 4
1566
1567#define STV090x_Px_DMDRESDATAy(__x, __y) (0xF4C8 - (__x - 1) * 0x200 + (7 - __y))
1568#define STV090x_P1_DMDRESDATA0 STV090x_Px_DMDRESDATAy(1, 0)
1569#define STV090x_P1_DMDRESDATA1 STV090x_Px_DMDRESDATAy(1, 1)
1570#define STV090x_P1_DMDRESDATA2 STV090x_Px_DMDRESDATAy(1, 2)
1571#define STV090x_P1_DMDRESDATA3 STV090x_Px_DMDRESDATAy(1, 3)
1572#define STV090x_P1_DMDRESDATA4 STV090x_Px_DMDRESDATAy(1, 4)
1573#define STV090x_P1_DMDRESDATA5 STV090x_Px_DMDRESDATAy(1, 5)
1574#define STV090x_P1_DMDRESDATA6 STV090x_Px_DMDRESDATAy(1, 6)
1575#define STV090x_P1_DMDRESDATA7 STV090x_Px_DMDRESDATAy(1, 7)
1576#define STV090x_P2_DMDRESDATA0 STV090x_Px_DMDRESDATAy(2, 0)
1577#define STV090x_P2_DMDRESDATA1 STV090x_Px_DMDRESDATAy(2, 1)
1578#define STV090x_P2_DMDRESDATA2 STV090x_Px_DMDRESDATAy(2, 2)
1579#define STV090x_P2_DMDRESDATA3 STV090x_Px_DMDRESDATAy(2, 3)
1580#define STV090x_P2_DMDRESDATA4 STV090x_Px_DMDRESDATAy(2, 4)
1581#define STV090x_P2_DMDRESDATA5 STV090x_Px_DMDRESDATAy(2, 5)
1582#define STV090x_P2_DMDRESDATA6 STV090x_Px_DMDRESDATAy(2, 6)
1583#define STV090x_P2_DMDRESDATA7 STV090x_Px_DMDRESDATAy(2, 7)
1584#define STV090x_OFFST_Px_DMDRES_DATA_FIELD 0
1585#define STV090x_WIDTH_Px_DMDRES_DATA_FIELD 8
1586
1587#define STV090x_Px_FFEIy(__x, __y) (0xf4d0 - (__x - 1) * 0x200 + 0x2 * (__y - 1))
1588#define STV090x_P1_FFEI1 STV090x_Px_FFEIy(1, 1)
1589#define STV090x_P1_FFEI2 STV090x_Px_FFEIy(1, 2)
1590#define STV090x_P1_FFEI3 STV090x_Px_FFEIy(1, 3)
1591#define STV090x_P1_FFEI4 STV090x_Px_FFEIy(1, 4)
1592#define STV090x_P2_FFEI1 STV090x_Px_FFEIy(2, 1)
1593#define STV090x_P2_FFEI2 STV090x_Px_FFEIy(2, 2)
1594#define STV090x_P2_FFEI3 STV090x_Px_FFEIy(2, 3)
1595#define STV090x_P2_FFEI4 STV090x_Px_FFEIy(2, 4)
1596#define STV090x_OFFST_Px_FFE_ACCIy_FIELD 0
1597#define STV090x_WIDTH_Px_FFE_ACCIy_FIELD 8
1598
1599#define STV090x_Px_FFEQy(__x, __y) (0xf4d1 - (__x - 1) * 0x200 + 0x2 * (__y - 1))
1600#define STV090x_P1_FFEQ1 STV090x_Px_FFEQy(1, 1)
1601#define STV090x_P1_FFEQ2 STV090x_Px_FFEQy(1, 2)
1602#define STV090x_P1_FFEQ3 STV090x_Px_FFEQy(1, 3)
1603#define STV090x_P1_FFEQ4 STV090x_Px_FFEQy(1, 4)
1604#define STV090x_P2_FFEQ1 STV090x_Px_FFEQy(2, 1)
1605#define STV090x_P2_FFEQ2 STV090x_Px_FFEQy(2, 2)
1606#define STV090x_P2_FFEQ3 STV090x_Px_FFEQy(2, 3)
1607#define STV090x_P2_FFEQ4 STV090x_Px_FFEQy(2, 4)
1608#define STV090x_OFFST_Px_FFE_ACCQy_FIELD 0
1609#define STV090x_WIDTH_Px_FFE_ACCQy_FIELD 8
1610
1611#define STV090x_Px_FFECFG(__x) (0xf4d8 - (__x - 1) * 0x200)
1612#define STV090x_P1_FFECFG STV090x_Px_FFECFG(1)
1613#define STV090x_P2_FFECFG STV090x_Px_FFECFG(2)
1614#define STV090x_OFFST_Px_EQUALFFE_ON_FIELD 6
1615#define STV090x_WIDTH_Px_EQUALFFE_ON_FIELD 1
1616
1617#define STV090x_Px_SMAPCOEF7(__x) (0xf500 - (__x - 1) * 0x200)
1618#define STV090x_P1_SMAPCOEF7 STV090x_Px_SMAPCOEF7(1)
1619#define STV090x_P2_SMAPCOEF7 STV090x_Px_SMAPCOEF7(2)
1620#define STV090x_OFFST_Px_DIS_QSCALE_FIELD 7
1621#define STV090x_WIDTH_Px_DIS_QSCALE_FIELD 1
1622#define STV090x_OFFST_Px_SMAPCOEF_Q_LLR12_FIELD 0
1623#define STV090x_WIDTH_Px_SMAPCOEF_Q_LLR12_FIELD 7
1624
1625#define STV090x_Px_SMAPCOEF6(__x) (0xf501 - (__x - 1) * 0x200)
1626#define STV090x_P1_SMAPCOEF6 STV090x_Px_SMAPCOEF6(1)
1627#define STV090x_P2_SMAPCOEF6 STV090x_Px_SMAPCOEF6(2)
1628#define STV090x_OFFST_Px_ADJ_8PSKLLR1_FIELD 2
1629#define STV090x_WIDTH_Px_ADJ_8PSKLLR1_FIELD 1
1630#define STV090x_OFFST_Px_OLD_8PSKLLR1_FIELD 1
1631#define STV090x_WIDTH_Px_OLD_8PSKLLR1_FIELD 1
1632#define STV090x_OFFST_Px_DIS_AB8PSK_FIELD 0
1633#define STV090x_WIDTH_Px_DIS_AB8PSK_FIELD 1
1634
1635#define STV090x_Px_SMAPCOEF5(__x) (0xf502 - (__x - 1) * 0x200)
1636#define STV090x_P1_SMAPCOEF5 STV090x_Px_SMAPCOEF5(1)
1637#define STV090x_P2_SMAPCOEF5 STV090x_Px_SMAPCOEF5(2)
1638#define STV090x_OFFST_Px_DIS_8SCALE_FIELD 7
1639#define STV090x_WIDTH_Px_DIS_8SCALE_FIELD 1
1640#define STV090x_OFFST_Px_SMAPCOEF_8P_LLR23_FIELD 0
1641#define STV090x_WIDTH_Px_SMAPCOEF_8P_LLR23_FIELD 7
1642
1643#define STV090x_Px_DMDPLHSTAT(__x) (0xF520 - (__x - 1) * 0x200)
1644#define STV090x_P1_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(1)
1645#define STV090x_P2_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(2)
1646#define STV090x_OFFST_Px_PLH_STATISTIC_FIELD 0
1647#define STV090x_WIDTH_Px_PLH_STATISTIC_FIELD 8
1648
1649#define STV090x_Px_LOCKTIMEy(__x, __y) (0xF525 - (__x - 1) * 0x200 - __y * 0x1)
1650#define STV090x_P1_LOCKTIME0 STV090x_Px_LOCKTIMEy(1, 0)
1651#define STV090x_P1_LOCKTIME1 STV090x_Px_LOCKTIMEy(1, 1)
1652#define STV090x_P1_LOCKTIME2 STV090x_Px_LOCKTIMEy(1, 2)
1653#define STV090x_P1_LOCKTIME3 STV090x_Px_LOCKTIMEy(1, 3)
1654#define STV090x_P2_LOCKTIME0 STV090x_Px_LOCKTIMEy(2, 0)
1655#define STV090x_P2_LOCKTIME1 STV090x_Px_LOCKTIMEy(2, 1)
1656#define STV090x_P2_LOCKTIME2 STV090x_Px_LOCKTIMEy(2, 2)
1657#define STV090x_P2_LOCKTIME3 STV090x_Px_LOCKTIMEy(2, 3)
1658#define STV090x_OFFST_Px_DEMOD_LOCKTIME_FIELD 0
1659#define STV090x_WIDTH_Px_DEMOD_LOCKTIME_FIELD 8
1660
1661#define STV090x_Px_TNRCFG(__x) (0xf4e0 - (__x - 1) * 0x200) /* check */
1662#define STV090x_P1_TNRCFG STV090x_Px_TNRCFG(1)
1663#define STV090x_P2_TNRCFG STV090x_Px_TNRCFG(2)
1664
1665#define STV090x_Px_TNRCFG2(__x) (0xf4e1 - (__x - 1) * 0x200)
1666#define STV090x_P1_TNRCFG2 STV090x_Px_TNRCFG2(1)
1667#define STV090x_P2_TNRCFG2 STV090x_Px_TNRCFG2(2)
1668#define STV090x_OFFST_Px_TUN_IQSWAP_FIELD 7
1669#define STV090x_WIDTH_Px_TUN_IQSWAP_FIELD 1
1670
1671#define STV090x_Px_VITSCALE(__x) (0xf532 - (__x - 1) * 0x200)
1672#define STV090x_P1_VITSCALE STV090x_Px_VITSCALE(1)
1673#define STV090x_P2_VITSCALE STV090x_Px_VITSCALE(2)
1674#define STV090x_OFFST_Px_NVTH_NOSRANGE_FIELD 7
1675#define STV090x_WIDTH_Px_NVTH_NOSRANGE_FIELD 1
1676#define STV090x_OFFST_Px_VERROR_MAXMODE_FIELD 6
1677#define STV090x_WIDTH_Px_VERROR_MAXMODE_FIELD 1
1678#define STV090x_OFFST_Px_NSLOWSN_LOCKED_FIELD 3
1679#define STV090x_WIDTH_Px_NSLOWSN_LOCKED_FIELD 1
1680#define STV090x_OFFST_Px_DIS_RSFLOCK_FIELD 1
1681#define STV090x_WIDTH_Px_DIS_RSFLOCK_FIELD 1
1682
1683#define STV090x_Px_FECM(__x) (0xf533 - (__x - 1) * 0x200)
1684#define STV090x_P1_FECM STV090x_Px_FECM(1)
1685#define STV090x_P2_FECM STV090x_Px_FECM(2)
1686#define STV090x_OFFST_Px_DSS_DVB_FIELD 7
1687#define STV090x_WIDTH_Px_DSS_DVB_FIELD 1
1688#define STV090x_OFFST_Px_DSS_SRCH_FIELD 4
1689#define STV090x_WIDTH_Px_DSS_SRCH_FIELD 1
1690#define STV090x_OFFST_Px_SYNCVIT_FIELD 1
1691#define STV090x_WIDTH_Px_SYNCVIT_FIELD 1
1692#define STV090x_OFFST_Px_IQINV_FIELD 0
1693#define STV090x_WIDTH_Px_IQINV_FIELD 1
1694
1695#define STV090x_Px_VTH12(__x) (0xf534 - (__x - 1) * 0x200)
1696#define STV090x_P1_VTH12 STV090x_Px_VTH12(1)
1697#define STV090x_P2_VTH12 STV090x_Px_VTH12(2)
1698#define STV090x_OFFST_Px_VTH12_FIELD 0
1699#define STV090x_WIDTH_Px_VTH12_FIELD 8
1700
1701#define STV090x_Px_VTH23(__x) (0xf535 - (__x - 1) * 0x200)
1702#define STV090x_P1_VTH23 STV090x_Px_VTH23(1)
1703#define STV090x_P2_VTH23 STV090x_Px_VTH23(2)
1704#define STV090x_OFFST_Px_VTH23_FIELD 0
1705#define STV090x_WIDTH_Px_VTH23_FIELD 8
1706
1707#define STV090x_Px_VTH34(__x) (0xf536 - (__x - 1) * 0x200)
1708#define STV090x_P1_VTH34 STV090x_Px_VTH34(1)
1709 #define STV090x_P2_VTH34 STV090x_Px_VTH34(2)
1710#define STV090x_OFFST_Px_VTH34_FIELD 0
1711#define STV090x_WIDTH_Px_VTH34_FIELD 8
1712
1713#define STV090x_Px_VTH56(__x) (0xf537 - (__x - 1) * 0x200)
1714#define STV090x_P1_VTH56 STV090x_Px_VTH56(1)
1715#define STV090x_P2_VTH56 STV090x_Px_VTH56(2)
1716#define STV090x_OFFST_Px_VTH56_FIELD 0
1717#define STV090x_WIDTH_Px_VTH56_FIELD 8
1718
1719#define STV090x_Px_VTH67(__x) (0xf538 - (__x - 1) * 0x200)
1720#define STV090x_P1_VTH67 STV090x_Px_VTH67(1)
1721#define STV090x_P2_VTH67 STV090x_Px_VTH67(2)
1722#define STV090x_OFFST_Px_VTH67_FIELD 0
1723#define STV090x_WIDTH_Px_VTH67_FIELD 8
1724
1725#define STV090x_Px_VTH78(__x) (0xf539 - (__x - 1) * 0x200)
1726#define STV090x_P1_VTH78 STV090x_Px_VTH78(1)
1727#define STV090x_P2_VTH78 STV090x_Px_VTH78(2)
1728#define STV090x_OFFST_Px_VTH78_FIELD 0
1729#define STV090x_WIDTH_Px_VTH78_FIELD 8
1730
1731#define STV090x_Px_VITCURPUN(__x) (0xf53a - (__x - 1) * 0x200)
1732#define STV090x_P1_VITCURPUN STV090x_Px_VITCURPUN(1)
1733#define STV090x_P2_VITCURPUN STV090x_Px_VITCURPUN(2)
1734#define STV090x_OFFST_Px_VIT_CURPUN_FIELD 0
1735#define STV090x_WIDTH_Px_VIT_CURPUN_FIELD 5
1736
1737#define STV090x_Px_VERROR(__x) (0xf53b - (__x - 1) * 0x200)
1738#define STV090x_P1_VERROR STV090x_Px_VERROR(1)
1739#define STV090x_P2_VERROR STV090x_Px_VERROR(2)
1740#define STV090x_OFFST_Px_REGERR_VIT_FIELD 0
1741#define STV090x_WIDTH_Px_REGERR_VIT_FIELD 8
1742
1743#define STV090x_Px_PRVIT(__x) (0xf53c - (__x - 1) * 0x200)
1744#define STV090x_P1_PRVIT STV090x_Px_PRVIT(1)
1745#define STV090x_P2_PRVIT STV090x_Px_PRVIT(2)
1746#define STV090x_OFFST_Px_DIS_VTHLOCK_FIELD 6
1747#define STV090x_WIDTH_Px_DIS_VTHLOCK_FIELD 1
1748#define STV090x_OFFST_Px_E7_8VIT_FIELD 5
1749#define STV090x_WIDTH_Px_E7_8VIT_FIELD 1
1750#define STV090x_OFFST_Px_E6_7VIT_FIELD 4
1751#define STV090x_WIDTH_Px_E6_7VIT_FIELD 1
1752#define STV090x_OFFST_Px_E5_6VIT_FIELD_ 3
1753#define STV090x_WIDTH_Px_E5_6VIT_FIELD 1
1754#define STV090x_OFFST_Px_E3_4VIT_FIELD 2
1755#define STV090x_WIDTH_Px_E3_4VIT_FIELD 1
1756#define STV090x_OFFST_Px_E2_3VIT_FIELD 1
1757#define STV090x_WIDTH_Px_E2_3VIT_FIELD 1
1758#define STV090x_OFFST_Px_E1_2VIT_FIELD 0
1759#define STV090x_WIDTH_Px_E1_2VIT_FIELD 1
1760
1761#define STV090x_Px_VAVSRVIT(__x) (0xf53d - (__x - 1) * 0x200)
1762#define STV090x_P1_VAVSRVIT STV090x_Px_VAVSRVIT(1)
1763#define STV090x_P2_VAVSRVIT STV090x_Px_VAVSRVIT(2)
1764#define STV090x_OFFST_Px_SNVIT_FIELD 4
1765#define STV090x_WIDTH_Px_SNVIT_FIELD 2
1766#define STV090x_OFFST_Px_TOVVIT_FIELD 2
1767#define STV090x_WIDTH_Px_TOVVIT_FIELD 2
1768#define STV090x_OFFST_Px_HYPVIT_FIELD 0
1769#define STV090x_WIDTH_Px_HYPVIT_FIELD 2
1770
1771#define STV090x_Px_VSTATUSVIT(__x) (0xf53e - (__x - 1) * 0x200)
1772#define STV090x_P1_VSTATUSVIT STV090x_Px_VSTATUSVIT(1)
1773#define STV090x_P2_VSTATUSVIT STV090x_Px_VSTATUSVIT(2)
1774#define STV090x_OFFST_Px_PRFVIT_FIELD 4
1775#define STV090x_WIDTH_Px_PRFVIT_FIELD 1
1776#define STV090x_OFFST_Px_LOCKEDVIT_FIELD 3
1777#define STV090x_WIDTH_Px_LOCKEDVIT_FIELD 1
1778
1779#define STV090x_Px_VTHINUSE(__x) (0xf53f - (__x - 1) * 0x200)
1780#define STV090x_P1_VTHINUSE STV090x_Px_VTHINUSE(1)
1781#define STV090x_P2_VTHINUSE STV090x_Px_VTHINUSE(2)
1782#define STV090x_OFFST_Px_VIT_INUSE_FIELD 0
1783#define STV090x_WIDTH_Px_VIT_INUSE_FIELD 8
1784
1785#define STV090x_Px_KDIV12(__x) (0xf540 - (__x - 1) * 0x200)
1786#define STV090x_P1_KDIV12 STV090x_Px_KDIV12(1)
1787#define STV090x_P2_KDIV12 STV090x_Px_KDIV12(2)
1788#define STV090x_OFFST_Px_K_DIVIDER_12_FIELD 0
1789#define STV090x_WIDTH_Px_K_DIVIDER_12_FIELD 7
1790
1791#define STV090x_Px_KDIV23(__x) (0xf541 - (__x - 1) * 0x200)
1792#define STV090x_P1_KDIV23 STV090x_Px_KDIV23(1)
1793#define STV090x_P2_KDIV23 STV090x_Px_KDIV23(2)
1794#define STV090x_OFFST_Px_K_DIVIDER_23_FIELD 0
1795#define STV090x_WIDTH_Px_K_DIVIDER_23_FIELD 7
1796
1797#define STV090x_Px_KDIV34(__x) (0xf542 - (__x - 1) * 0x200)
1798#define STV090x_P1_KDIV34 STV090x_Px_KDIV34(1)
1799#define STV090x_P2_KDIV34 STV090x_Px_KDIV34(2)
1800#define STV090x_OFFST_Px_K_DIVIDER_34_FIELD 0
1801#define STV090x_WIDTH_Px_K_DIVIDER_34_FIELD 7
1802
1803#define STV090x_Px_KDIV56(__x) (0xf543 - (__x - 1) * 0x200)
1804#define STV090x_P1_KDIV56 STV090x_Px_KDIV56(1)
1805#define STV090x_P2_KDIV56 STV090x_Px_KDIV56(2)
1806#define STV090x_OFFST_Px_K_DIVIDER_56_FIELD 0
1807#define STV090x_WIDTH_Px_K_DIVIDER_56_FIELD 7
1808
1809#define STV090x_Px_KDIV67(__x) (0xf544 - (__x - 1) * 0x200)
1810#define STV090x_P1_KDIV67 STV090x_Px_KDIV67(1)
1811#define STV090x_P2_KDIV67 STV090x_Px_KDIV67(2)
1812#define STV090x_OFFST_Px_K_DIVIDER_67_FIELD 0
1813#define STV090x_WIDTH_Px_K_DIVIDER_67_FIELD 7
1814
1815#define STV090x_Px_KDIV78(__x) (0xf545 - (__x - 1) * 0x200)
1816#define STV090x_P1_KDIV78 STV090x_Px_KDIV78(1)
1817#define STV090x_P2_KDIV78 STV090x_Px_KDIV78(2)
1818#define STV090x_OFFST_Px_K_DIVIDER_78_FIELD 0
1819#define STV090x_WIDTH_Px_K_DIVIDER_78_FIELD 7
1820
1821#define STV090x_Px_PDELCTRL1(__x) (0xf550 - (__x - 1) * 0x200)
1822#define STV090x_P1_PDELCTRL1 STV090x_Px_PDELCTRL1(1)
1823#define STV090x_P2_PDELCTRL1 STV090x_Px_PDELCTRL1(2)
1824#define STV090x_OFFST_Px_INV_MISMASK_FIELD 7
1825#define STV090x_WIDTH_Px_INV_MISMASK_FIELD 1
1826#define STV090x_OFFST_Px_FILTER_EN_FIELD 5
1827#define STV090x_WIDTH_Px_FILTER_EN_FIELD 1
1828#define STV090x_OFFST_Px_EN_MIS00_FIELD 1
1829#define STV090x_WIDTH_Px_EN_MIS00_FIELD 1
1830#define STV090x_OFFST_Px_ALGOSWRST_FIELD 0
1831#define STV090x_WIDTH_Px_ALGOSWRST_FIELD 1
1832
1833#define STV090x_Px_PDELCTRL2(__x) (0xf551 - (__x - 1) * 0x200)
1834#define STV090x_P1_PDELCTRL2 STV090x_Px_PDELCTRL2(1)
1835#define STV090x_P2_PDELCTRL2 STV090x_Px_PDELCTRL2(2)
1836#define STV090x_OFFST_Px_FRAME_MODE_FIELD 1
1837#define STV090x_WIDTH_Px_FRAME_MODE_FIELD 1
1838
1839#define STV090x_Px_HYSTTHRESH(__x) (0xf554 - (__x - 1) * 0x200)
1840#define STV090x_P1_HYSTTHRESH STV090x_Px_HYSTTHRESH(1)
1841#define STV090x_P2_HYSTTHRESH STV090x_Px_HYSTTHRESH(2)
1842#define STV090x_OFFST_Px_UNLCK_THRESH_FIELD 4
1843#define STV090x_WIDTH_Px_UNLCK_THRESH_FIELD 4
1844#define STV090x_OFFST_Px_DELIN_LCK_THRESH_FIELD 0
1845#define STV090x_WIDTH_Px_DELIN_LCK_THRESH__FIELD 4
1846
1847#define STV090x_Px_ISIENTRY(__x) (0xf55e - (__x - 1) * 0x200)
1848#define STV090x_P1_ISIENTRY STV090x_Px_ISIENTRY(1)
1849#define STV090x_P2_ISIENTRY STV090x_Px_ISIENTRY(2)
1850#define STV090x_OFFST_Px_ISI_ENTRY_FIELD 0
1851#define STV090x_WIDTH_Px_ISI_ENTRY__FIELD 8
1852
1853#define STV090x_Px_ISIBITENA(__x) (0xf55f - (__x - 1) * 0x200)
1854#define STV090x_P1_ISIBITENA STV090x_Px_ISIBITENA(1)
1855#define STV090x_P2_ISIBITENA STV090x_Px_ISIBITENA(2)
1856#define STV090x_OFFST_Px_ISI_BIT_EN_FIELD 0
1857#define STV090x_WIDTH_Px_ISI_BIT_EN_FIELD 8
1858
1859#define STV090x_Px_MATSTRy(__x, __y) (0xf561 - (__x - 1) * 0x200 - __y * 0x1)
1860#define STV090x_P1_MATSTR0 STV090x_Px_MATSTRy(1, 0)
1861#define STV090x_P1_MATSTR1 STV090x_Px_MATSTRy(1, 1)
1862#define STV090x_P2_MATSTR0 STV090x_Px_MATSTRy(2, 0)
1863#define STV090x_P2_MATSTR1 STV090x_Px_MATSTRy(2, 1)
1864#define STV090x_OFFST_Px_MATYPE_CURRENT_FIELD 0
1865#define STV090x_WIDTH_Px_MATYPE_CURRENT_FIELD 8
1866
1867#define STV090x_Px_UPLSTRy(__x, __y) (0xf563 - (__x - 1) * 0x200 - __y * 0x1)
1868#define STV090x_P1_UPLSTR0 STV090x_Px_UPLSTRy(1, 0)
1869#define STV090x_P1_UPLSTR1 STV090x_Px_UPLSTRy(1, 1)
1870#define STV090x_P2_UPLSTR0 STV090x_Px_UPLSTRy(2, 0)
1871#define STV090x_P2_UPLSTR1 STV090x_Px_UPLSTRy(2, 1)
1872#define STV090x_OFFST_Px_UPL_CURRENT_FIELD 0
1873#define STV090x_WIDTH_Px_UPL_CURRENT_FIELD 8
1874
1875#define STV090x_Px_DFLSTRy(__x, __y) (0xf565 - (__x - 1) * 0x200 - __y * 0x1)
1876#define STV090x_P1_DFLSTR0 STV090x_Px_DFLSTRy(1, 0)
1877#define STV090x_P1_DFLSTR1 STV090x_Px_DFLSTRy(1, 1)
1878#define STV090x_P2_DFLSTR0 STV090x_Px_DFLSTRy(2, 0)
1879#define STV090x_P2_DFLSTR1 STV090x_Px_DFLSTRy(2, 1)
1880#define STV090x_OFFST_Px_DFL_CURRENT_FIELD 0
1881#define STV090x_WIDTH_Px_DFL_CURRENT_FIELD 8
1882
1883#define STV090x_Px_SYNCSTR(__x) (0xf566 - (__x - 1) * 0x200)
1884#define STV090x_P1_SYNCSTR STV090x_Px_SYNCSTR(1)
1885#define STV090x_P2_SYNCSTR STV090x_Px_SYNCSTR(2)
1886#define STV090x_OFFST_Px_SYNC_CURRENT_FIELD 0
1887#define STV090x_WIDTH_Px_SYNC_CURRENT_FIELD 8
1888
1889#define STV090x_Px_SYNCDSTRy(__x, __y) (0xf568 - (__x - 1) * 0x200 - __y * 0x1)
1890#define STV090x_P1_SYNCDSTR0 STV090x_Px_SYNCDSTRy(1, 0)
1891#define STV090x_P1_SYNCDSTR1 STV090x_Px_SYNCDSTRy(1, 1)
1892#define STV090x_P2_SYNCDSTR0 STV090x_Px_SYNCDSTRy(2, 0)
1893#define STV090x_P2_SYNCDSTR1 STV090x_Px_SYNCDSTRy(2, 1)
1894#define STV090x_OFFST_Px_SYNCD_CURRENT_FIELD 0
1895#define STV090x_WIDTH_Px_SYNCD_CURRENT_FIELD 8
1896
1897#define STV090x_Px_PDELSTATUS1(__x) (0xf569 - (__x - 1) * 0x200)
1898#define STV090x_P1_PDELSTATUS1 STV090x_Px_PDELSTATUS1(1)
1899#define STV090x_P2_PDELSTATUS1 STV090x_Px_PDELSTATUS1(2)
1900#define STV090x_OFFST_Px_PKTDELIN_LOCK_FIELD 1
1901#define STV090x_WIDTH_Px_PKTDELIN_LOCK_FIELD 1
1902#define STV090x_OFFST_Px_FIRST_LOCK_FIELD 0
1903#define STV090x_WIDTH_Px_FIRST_LOCK_FIELD 1
1904
1905#define STV090x_Px_PDELSTATUS2(__x) (0xf56a - (__x - 1) * 0x200)
1906#define STV090x_P1_PDELSTATUS2 STV090x_Px_PDELSTATUS2(1)
1907#define STV090x_P2_PDELSTATUS2 STV090x_Px_PDELSTATUS2(2)
1908#define STV090x_OFFST_Px_FRAME_MODCOD_FIELD 2
1909#define STV090x_WIDTH_Px_FRAME_MODCOD_FIELD 5
1910#define STV090x_OFFST_Px_FRAME_TYPE_FIELD 0
1911#define STV090x_WIDTH_Px_FRAME_TYPE_FIELD 2
1912
1913#define STV090x_Px_BBFCRCKO1(__x) (0xf56b - (__x - 1) * 0x200)
1914#define STV090x_P1_BBFCRCKO1 STV090x_Px_BBFCRCKO1(1)
1915#define STV090x_P2_BBFCRCKO1 STV090x_Px_BBFCRCKO1(2)
1916#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD 0
1917#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD 8
1918
1919#define STV090x_Px_BBFCRCKO0(__x) (0xf56c - (__x - 1) * 0x200)
1920#define STV090x_P1_BBFCRCKO0 STV090x_Px_BBFCRCKO0(1)
1921#define STV090x_P2_BBFCRCKO0 STV090x_Px_BBFCRCKO0(2)
1922#define STV090x_OFFST_Px_BBHCRC_KOCNT_FIELD 0
1923#define STV090x_WIDTH_Px_BBHCRC_KOCNT_FIELD 8
1924
1925#define STV090x_Px_UPCRCKO1(__x) (0xf56d - (__x - 1) * 0x200)
1926#define STV090x_P1_UPCRCKO1 STV090x_Px_UPCRCKO1(1)
1927#define STV090x_P2_UPCRCKO1 STV090x_Px_UPCRCKO1(2)
1928#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD 0
1929#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD 8
1930
1931#define STV090x_Px_UPCRCKO0(__x) (0xf56e - (__x - 1) * 0x200)
1932#define STV090x_P1_UPCRCKO0 STV090x_Px_UPCRCKO0(1)
1933#define STV090x_P2_UPCRCKO0 STV090x_Px_UPCRCKO0(2)
1934#define STV090x_OFFST_Px_PKTCRC_KOCNT_FIELD 0
1935#define STV090x_WIDTH_Px_PKTCRC_KOCNT_FIELD 8
1936
1937#define STV090x_NBITER_NFx(__x) (0xFA03 + (__x - 4) * 0x1)
1938#define STV090x_NBITER_NF4 STV090x_NBITER_NFx(4)
1939#define STV090x_NBITER_NF5 STV090x_NBITER_NFx(5)
1940#define STV090x_NBITER_NF6 STV090x_NBITER_NFx(6)
1941#define STV090x_NBITER_NF7 STV090x_NBITER_NFx(7)
1942#define STV090x_NBITER_NF8 STV090x_NBITER_NFx(8)
1943#define STV090x_NBITER_NF9 STV090x_NBITER_NFx(9)
1944#define STV090x_NBITER_NF10 STV090x_NBITER_NFx(10)
1945#define STV090x_NBITER_NF11 STV090x_NBITER_NFx(11)
1946#define STV090x_NBITER_NF12 STV090x_NBITER_NFx(12)
1947#define STV090x_NBITER_NF13 STV090x_NBITER_NFx(13)
1948#define STV090x_NBITER_NF14 STV090x_NBITER_NFx(14)
1949#define STV090x_NBITER_NF15 STV090x_NBITER_NFx(15)
1950#define STV090x_NBITER_NF16 STV090x_NBITER_NFx(16)
1951#define STV090x_NBITER_NF17 STV090x_NBITER_NFx(17)
1952
1953#define STV090x_NBITERNOERR 0xFA3F
1954#define STV090x_OFFST_NBITER_STOP_CRIT_FIELD 0
1955#define STV090x_WIDTH_NBITER_STOP_CRIT_FIELD 4
1956
1957#define STV090x_GAINLLR_NFx(__x) (0xFA43 + (__x - 4) * 0x1)
1958#define STV090x_GAINLLR_NF4 STV090x_GAINLLR_NFx(4)
1959#define STV090x_OFFST_GAINLLR_NF_QP_1_2_FIELD 0
1960#define STV090x_WIDTH_GAINLLR_NF_QP_1_2_FIELD 7
1961
1962#define STV090x_GAINLLR_NF5 STV090x_GAINLLR_NFx(5)
1963#define STV090x_OFFST_GAINLLR_NF_QP_3_5_FIELD 0
1964#define STV090x_WIDTH_GAINLLR_NF_QP_3_5_FIELD 7
1965
1966#define STV090x_GAINLLR_NF6 STV090x_GAINLLR_NFx(6)
1967#define STV090x_OFFST_GAINLLR_NF_QP_2_3_FIELD 0
1968#define STV090x_WIDTH_GAINLLR_NF_QP_2_3_FIELD 7
1969
1970#define STV090x_GAINLLR_NF7 STV090x_GAINLLR_NFx(7)
1971#define STV090x_OFFST_GAINLLR_NF_QP_3_4_FIELD 0
1972#define STV090x_WIDTH_GAINLLR_NF_QP_3_4_FIELD 7
1973
1974#define STV090x_GAINLLR_NF8 STV090x_GAINLLR_NFx(8)
1975#define STV090x_OFFST_GAINLLR_NF_QP_4_5_FIELD 0
1976#define STV090x_WIDTH_GAINLLR_NF_QP_4_5_FIELD 7
1977
1978#define STV090x_GAINLLR_NF9 STV090x_GAINLLR_NFx(9)
1979#define STV090x_OFFST_GAINLLR_NF_QP_5_6_FIELD 0
1980#define STV090x_WIDTH_GAINLLR_NF_QP_5_6_FIELD 7
1981
1982#define STV090x_GAINLLR_NF10 STV090x_GAINLLR_NFx(10)
1983#define STV090x_OFFST_GAINLLR_NF_QP_8_9_FIELD 0
1984#define STV090x_WIDTH_GAINLLR_NF_QP_8_9_FIELD 7
1985
1986#define STV090x_GAINLLR_NF11 STV090x_GAINLLR_NFx(11)
1987#define STV090x_OFFST_GAINLLR_NF_QP_9_10_FIELD 0
1988#define STV090x_WIDTH_GAINLLR_NF_QP_9_10IELD 7
1989
1990#define STV090x_GAINLLR_NF12 STV090x_GAINLLR_NFx(12)
1991#define STV090x_OFFST_GAINLLR_NF_8P_3_5_FIELD 0
1992#define STV090x_WIDTH_GAINLLR_NF_8P_3_5_FIELD 7
1993
1994#define STV090x_GAINLLR_NF13 STV090x_GAINLLR_NFx(13)
1995#define STV090x_OFFST_GAINLLR_NF_8P_2_3_FIELD 0
1996#define STV090x_WIDTH_GAINLLR_NF_8P_2_3_FIELD 7
1997
1998#define STV090x_GAINLLR_NF14 STV090x_GAINLLR_NFx(14)
1999#define STV090x_OFFST_GAINLLR_NF_8P_3_4_FIELD 0
2000#define STV090x_WIDTH_GAINLLR_NF_8P_3_4_FIELD 7
2001
2002#define STV090x_GAINLLR_NF15 STV090x_GAINLLR_NFx(15)
2003#define STV090x_OFFST_GAINLLR_NF_8P_5_6_FIELD 0
2004#define STV090x_WIDTH_GAINLLR_NF_8P_5_6_FIELD 7
2005
2006#define STV090x_GAINLLR_NF16 STV090x_GAINLLR_NFx(16)
2007#define STV090x_OFFST_GAINLLR_NF_8P_8_9_FIELD 0
2008#define STV090x_WIDTH_GAINLLR_NF_8P_8_9_FIELD 7
2009
2010#define STV090x_GAINLLR_NF17 STV090x_GAINLLR_NFx(17)
2011#define STV090x_OFFST_GAINLLR_NF_8P_9_10_FIELD 0
2012#define STV090x_WIDTH_GAINLLR_NF_8P_9_10_FIELD 7
2013
2014#define STV090x_GENCFG 0xFA86
2015#define STV090x_OFFST_BROADCAST_FIELD 4
2016#define STV090x_WIDTH_BROADCAST_FIELD 1
2017#define STV090x_OFFST_PRIORITY_FIELD 1
2018#define STV090x_WIDTH_PRIORITY_FIELD 1
2019#define STV090x_OFFST_DDEMOD_FIELD 0
2020#define STV090x_WIDTH_DDEMOD_FIELD 1
2021
2022#define STV090x_LDPCERRx(__x) (0xFA97 - (__x * 0x1))
2023#define STV090x_LDPCERR0 STV090x_LDPCERRx(0)
2024#define STV090x_LDPCERR1 STV090x_LDPCERRx(1)
2025#define STV090x_OFFST_Px_LDPC_ERRORS_COUNTER_FIELD 0
2026#define STV090x_WIDTH_Px_LDPC_ERRORS_COUNTER_FIELD 8
2027
2028#define STV090x_BCHERR 0xFA98
2029#define STV090x_OFFST_Px_ERRORFLAG_FIELD 4
2030#define STV090x_WIDTH_Px_ERRORFLAG_FIELD 1
2031#define STV090x_OFFST_Px_BCH_ERRORS_COUNTER_FIELD 0
2032#define STV090x_WIDTH_Px_BCH_ERRORS_COUNTER_FIELD 4
2033
2034#define STV090x_Px_TSSTATEM(__x) (0xF570 - (__x - 1) * 0x200)
2035#define STV090x_P1_TSSTATEM STV090x_Px_TSSTATEM(1)
2036#define STV090x_P2_TSSTATEM STV090x_Px_TSSTATEM(2)
2037#define STV090x_OFFST_Px_TSDIL_ON_FIELD 7
2038#define STV090x_WIDTH_Px_TSDIL_ON_FIELD 1
2039#define STV090x_OFFST_Px_TSRS_ON_FIELD 5
2040#define STV090x_WIDTH_Px_TSRS_ON_FIELD 1
2041
2042#define STV090x_Px_TSCFGH(__x) (0xF572 - (__x - 1) * 0x200)
2043#define STV090x_P1_TSCFGH STV090x_Px_TSCFGH(1)
2044#define STV090x_P2_TSCFGH STV090x_Px_TSCFGH(2)
2045#define STV090x_OFFST_Px_TSFIFO_DVBCI_FIELD 7
2046#define STV090x_WIDTH_Px_TSFIFO_DVBCI_FIELD 1
2047#define STV090x_OFFST_Px_TSFIFO_SERIAL_FIELD 6
2048#define STV090x_WIDTH_Px_TSFIFO_SERIAL_FIELD 1
2049#define STV090x_OFFST_Px_TSFIFO_TEIUPDATE_FIELD 5
2050#define STV090x_WIDTH_Px_TSFIFO_TEIUPDATE_FIELD 1
2051#define STV090x_OFFST_Px_TSFIFO_DUTY50_FIELD 4
2052#define STV090x_WIDTH_Px_TSFIFO_DUTY50_FIELD 1
2053#define STV090x_OFFST_Px_TSFIFO_HSGNLOUT_FIELD 3
2054#define STV090x_WIDTH_Px_TSFIFO_HSGNLOUT_FIELD 1
2055#define STV090x_OFFST_Px_TSFIFO_ERRORMODE_FIELD 1
2056#define STV090x_WIDTH_Px_TSFIFO_ERRORMODE_FIELD 2
2057#define STV090x_OFFST_Px_RST_HWARE_FIELD 0
2058#define STV090x_WIDTH_Px_RST_HWARE_FIELD 1
2059
2060#define STV090x_Px_TSCFGM(__x) (0xF573 - (__x - 1) * 0x200)
2061#define STV090x_P1_TSCFGM STV090x_Px_TSCFGM(1)
2062#define STV090x_P2_TSCFGM STV090x_Px_TSCFGM(2)
2063#define STV090x_OFFST_Px_TSFIFO_MANSPEED_FIELD 6
2064#define STV090x_WIDTH_Px_TSFIFO_MANSPEED_FIELD 2
2065#define STV090x_OFFST_Px_TSFIFO_PERMDATA_FIELD 5
2066#define STV090x_WIDTH_Px_TSFIFO_PERMDATA_FIELD 1
2067#define STV090x_OFFST_Px_TSFIFO_INVDATA_FIELD 0
2068#define STV090x_WIDTH_Px_TSFIFO_INVDATA__FIELD 1
2069
2070#define STV090x_Px_TSCFGL(__x) (0xF574 - (__x - 1) * 0x200)
2071#define STV090x_P1_TSCFGL STV090x_Px_TSCFGL(1)
2072#define STV090x_P2_TSCFGL STV090x_Px_TSCFGL(2)
2073#define STV090x_OFFST_Px_TSFIFO_BCLKDEL1CK_FIELD 6
2074#define STV090x_WIDTH_Px_TSFIFO_BCLKDEL1CK_FIELD 2
2075#define STV090x_OFFST_Px_BCHERROR_MODE_FIELD 4
2076#define STV090x_WIDTH_Px_BCHERROR_MODE_FIELD 2
2077#define STV090x_OFFST_Px_TSFIFO_NSGNL2DATA_FIELD 3
2078#define STV090x_WIDTH_Px_TSFIFO_NSGNL2DATA__FIELD 1
2079#define STV090x_OFFST_Px_TSFIFO_EMBINDVB_FIELD 2
2080#define STV090x_WIDTH_Px_TSFIFO_EMBINDVB_FIELD 1
2081#define STV090x_OFFST_Px_TSFIFO_DPUNACT_FIELD 1
2082#define STV090x_WIDTH_Px_TSFIFO_DPUNACT_FIELD 1
2083
2084#define STV090x_Px_TSINSDELH(__x) (0xF576 - (__x - 1) * 0x200)
2085#define STV090x_P1_TSINSDELH STV090x_Px_TSINSDELH(1)
2086#define STV090x_P2_TSINSDELH STV090x_Px_TSINSDELH(2)
2087#define STV090x_OFFST_Px_TSDEL_SYNCBYTE_FIELD 7
2088#define STV090x_WIDTH_Px_TSDEL_SYNCBYTE_FIELD 1
2089#define STV090x_OFFST_Px_TSDEL_XXHEADER_FIELD 6
2090#define STV090x_WIDTH_Px_TSDEL_XXHEADER_FIELD 1
2091
2092#define STV090x_Px_TSSPEED(__x) (0xF580 - (__x - 1) * 0x200)
2093#define STV090x_P1_TSSPEED STV090x_Px_TSSPEED(1)
2094#define STV090x_P2_TSSPEED STV090x_Px_TSSPEED(2)
2095#define STV090x_OFFST_Px_TSFIFO_OUTSPEED_FIELD 0
2096#define STV090x_WIDTH_Px_TSFIFO_OUTSPEED_FIELD 8
2097
2098#define STV090x_Px_TSSTATUS(__x) (0xF581 - (__x - 1) * 0x200)
2099#define STV090x_P1_TSSTATUS STV090x_Px_TSSTATUS(1)
2100#define STV090x_P2_TSSTATUS STV090x_Px_TSSTATUS(2)
2101#define STV090x_OFFST_Px_TSFIFO_LINEOK_FIELD 7
2102#define STV090x_WIDTH_Px_TSFIFO_LINEOK_FIELD 1
2103#define STV090x_OFFST_Px_TSFIFO_ERROR_FIELD 6
2104#define STV090x_WIDTH_Px_TSFIFO_ERROR_FIELD 1
2105
2106#define STV090x_Px_TSSTATUS2(__x) (0xF582 - (__x - 1) * 0x200)
2107#define STV090x_P1_TSSTATUS2 STV090x_Px_TSSTATUS2(1)
2108#define STV090x_P2_TSSTATUS2 STV090x_Px_TSSTATUS2(2)
2109#define STV090x_OFFST_Px_TSFIFO_DEMODSEL_FIELD 7
2110#define STV090x_WIDTH_Px_TSFIFO_DEMODSEL_FIELD 1
2111#define STV090x_OFFST_Px_TSFIFOSPEED_STORE_FIELD 6
2112#define STV090x_WIDTH_Px_TSFIFOSPEED_STORE_FIELD 1
2113#define STV090x_OFFST_Px_DILXX_RESET_FIELD 5
2114#define STV090x_WIDTH_Px_DILXX_RESET_FIELD 1
2115#define STV090x_OFFST_Px_TSSERIAL_IMPOS_FIELD 5
2116#define STV090x_WIDTH_Px_TSSERIAL_IMPOS_FIELD 1
2117#define STV090x_OFFST_Px_SCRAMBDETECT_FIELD 1
2118#define STV090x_WIDTH_Px_SCRAMBDETECT_FIELD 1
2119
2120#define STV090x_Px_TSBITRATEy(__x, __y) (0xF584 - (__x - 1) * 0x200 - __y * 0x1)
2121#define STV090x_P1_TSBITRATE0 STV090x_Px_TSBITRATEy(1, 0)
2122#define STV090x_P1_TSBITRATE1 STV090x_Px_TSBITRATEy(1, 1)
2123#define STV090x_P2_TSBITRATE0 STV090x_Px_TSBITRATEy(2, 0)
2124#define STV090x_P2_TSBITRATE1 STV090x_Px_TSBITRATEy(2, 1)
2125#define STV090x_OFFST_Px_TSFIFO_BITRATE_FIELD 7
2126#define STV090x_WIDTH_Px_TSFIFO_BITRATE_FIELD 8
2127
2128#define STV090x_Px_ERRCTRL1(__x) (0xF598 - (__x - 1) * 0x200)
2129#define STV090x_P1_ERRCTRL1 STV090x_Px_ERRCTRL1(1)
2130#define STV090x_P2_ERRCTRL1 STV090x_Px_ERRCTRL1(2)
2131#define STV090x_OFFST_Px_ERR_SOURCE_FIELD 4
2132#define STV090x_WIDTH_Px_ERR_SOURCE_FIELD 4
2133#define STV090x_OFFST_Px_NUM_EVENT_FIELD 0
2134#define STV090x_WIDTH_Px_NUM_EVENT_FIELD 3
2135
2136#define STV090x_Px_ERRCNT12(__x) (0xF599 - (__x - 1) * 0x200)
2137#define STV090x_P1_ERRCNT12 STV090x_Px_ERRCNT12(1)
2138#define STV090x_P2_ERRCNT12 STV090x_Px_ERRCNT12(2)
2139#define STV090x_OFFST_Px_ERRCNT1_OLDVALUE__FIELD 7
2140#define STV090x_WIDTH_Px_ERRCNT1_OLDVALUE_FIELD 1
2141#define STV090x_OFFST_Px_ERR_CNT12_FIELD 0
2142#define STV090x_WIDTH_Px_ERR_CNT12_FIELD 7
2143
2144#define STV090x_Px_ERRCNT11(__x) (0xF59A - (__x - 1) * 0x200)
2145#define STV090x_P1_ERRCNT11 STV090x_Px_ERRCNT11(1)
2146#define STV090x_P2_ERRCNT11 STV090x_Px_ERRCNT11(2)
2147#define STV090x_OFFST_Px_ERR_CNT11_FIELD 0
2148#define STV090x_WIDTH_Px_ERR_CNT11_FIELD 8
2149
2150#define STV090x_Px_ERRCNT10(__x) (0xF59B - (__x - 1) * 0x200)
2151#define STV090x_P1_ERRCNT10 STV090x_Px_ERRCNT10(1)
2152#define STV090x_P2_ERRCNT10 STV090x_Px_ERRCNT10(2)
2153#define STV090x_OFFST_Px_ERR_CNT10_FIELD 0
2154#define STV090x_WIDTH_Px_ERR_CNT10_FIELD 8
2155
2156#define STV090x_Px_ERRCTRL2(__x) (0xF59C - (__x - 1) * 0x200)
2157#define STV090x_P1_ERRCTRL2 STV090x_Px_ERRCTRL2(1)
2158#define STV090x_P2_ERRCTRL2 STV090x_Px_ERRCTRL2(2)
2159#define STV090x_OFFST_Px_ERR_SOURCE2_FIELD 4
2160#define STV090x_WIDTH_Px_ERR_SOURCE2_FIELD 4
2161#define STV090x_OFFST_Px_NUM_EVENT2_FIELD 0
2162#define STV090x_WIDTH_Px_NUM_EVENT2_FIELD 3
2163
2164#define STV090x_Px_ERRCNT22(__x) (0xF59D - (__x - 1) * 0x200)
2165#define STV090x_P1_ERRCNT22 STV090x_Px_ERRCNT22(1)
2166#define STV090x_P2_ERRCNT22 STV090x_Px_ERRCNT22(2)
2167#define STV090x_OFFST_Px_ERRCNT2_OLDVALUE_FIELD 7
2168#define STV090x_WIDTH_Px_ERRCNT2_OLDVALUE_FIELD 1
2169#define STV090x_OFFST_Px_ERR_CNT2_FIELD 0
2170#define STV090x_WIDTH_Px_ERR_CNT2_FIELD 7
2171
2172#define STV090x_Px_ERRCNT21(__x) (0xF59E - (__x - 1) * 0x200)
2173#define STV090x_P1_ERRCNT21 STV090x_Px_ERRCNT21(1)
2174#define STV090x_P2_ERRCNT21 STV090x_Px_ERRCNT21(2)
2175#define STV090x_OFFST_Px_ERR_CNT21_FIELD 0
2176#define STV090x_WIDTH_Px_ERR_CNT21_FIELD 8
2177
2178#define STV090x_Px_ERRCNT20(__x) (0xF59F - (__x - 1) * 0x200)
2179#define STV090x_P1_ERRCNT20 STV090x_Px_ERRCNT20(1)
2180#define STV090x_P2_ERRCNT20 STV090x_Px_ERRCNT20(2)
2181#define STV090x_OFFST_Px_ERR_CNT20_FIELD 0
2182#define STV090x_WIDTH_Px_ERR_CNT20_FIELD 8
2183
2184#define STV090x_Px_FECSPY(__x) (0xF5A0 - (__x - 1) * 0x200)
2185#define STV090x_P1_FECSPY STV090x_Px_FECSPY(1)
2186#define STV090x_P2_FECSPY STV090x_Px_FECSPY(2)
2187#define STV090x_OFFST_Px_SPY_ENABLE_FIELD 7
2188#define STV090x_WIDTH_Px_SPY_ENABLE_FIELD 1
2189#define STV090x_OFFST_Px_BERMETER_DATAMAODE_FIELD 2
2190#define STV090x_WIDTH_Px_BERMETER_DATAMAODE_FIELD 2
2191
2192#define STV090x_Px_FSPYCFG(__x) (0xF5A1 - (__x - 1) * 0x200)
2193#define STV090x_P1_FSPYCFG STV090x_Px_FSPYCFG(1)
2194#define STV090x_P2_FSPYCFG STV090x_Px_FSPYCFG(2)
2195#define STV090x_OFFST_Px_RST_ON_ERROR_FIELD 5
2196#define STV090x_WIDTH_Px_RST_ON_ERROR_FIELD 1
2197#define STV090x_OFFST_Px_ONE_SHOT_FIELD 4
2198#define STV090x_WIDTH_Px_ONE_SHOT_FIELD 1
2199#define STV090x_OFFST_Px_I2C_MODE_FIELD 2
2200#define STV090x_WIDTH_Px_I2C_MODE_FIELD 2
2201
2202#define STV090x_Px_FSPYDATA(__x) (0xF5A2 - (__x - 1) * 0x200)
2203#define STV090x_P1_FSPYDATA STV090x_Px_FSPYDATA(1)
2204#define STV090x_P2_FSPYDATA STV090x_Px_FSPYDATA(2)
2205#define STV090x_OFFST_Px_SPY_STUFFING_FIELD 7
2206#define STV090x_WIDTH_Px_SPY_STUFFING_FIELD 1
2207#define STV090x_OFFST_Px_SPY_CNULLPKT_FIELD 5
2208#define STV090x_WIDTH_Px_SPY_CNULLPKT_FIELD 1
2209#define STV090x_OFFST_Px_SPY_OUTDATA_MODE_FIELD 0
2210#define STV090x_WIDTH_Px_SPY_OUTDATA_MODE_FIELD 5
2211
2212#define STV090x_Px_FSPYOUT(__x) (0xF5A3 - (__x - 1) * 0x200)
2213#define STV090x_P1_FSPYOUT STV090x_Px_FSPYOUT(1)
2214#define STV090x_P2_FSPYOUT STV090x_Px_FSPYOUT(2)
2215#define STV090x_OFFST_Px_FSPY_DIRECT_FIELD 7
2216#define STV090x_WIDTH_Px_FSPY_DIRECT_FIELD 1
2217#define STV090x_OFFST_Px_STUFF_MODE_FIELD 0
2218#define STV090x_WIDTH_Px_STUFF_MODE_FIELD 3
2219
2220#define STV090x_Px_FSTATUS(__x) (0xF5A4 - (__x - 1) * 0x200)
2221#define STV090x_P1_FSTATUS STV090x_Px_FSTATUS(1)
2222#define STV090x_P2_FSTATUS STV090x_Px_FSTATUS(2)
2223#define STV090x_OFFST_Px_SPY_ENDSIM_FIELD 7
2224#define STV090x_WIDTH_Px_SPY_ENDSIM_FIELD 1
2225#define STV090x_OFFST_Px_VALID_SIM_FIELD 6
2226#define STV090x_WIDTH_Px_VALID_SIM_FIELD 1
2227#define STV090x_OFFST_Px_FOUND_SIGNAL_FIELD 5
2228#define STV090x_WIDTH_Px_FOUND_SIGNAL_FIELD 1
2229#define STV090x_OFFST_Px_DSS_SYNCBYTE_FIELD 4
2230#define STV090x_WIDTH_Px_DSS_SYNCBYTE_FIELD 1
2231#define STV090x_OFFST_Px_RESULT_STATE_FIELD 0
2232#define STV090x_WIDTH_Px_RESULT_STATE_FIELD 4
2233
2234#define STV090x_Px_FBERCPT4(__x) (0xF5A8 - (__x - 1) * 0x200)
2235#define STV090x_P1_FBERCPT4 STV090x_Px_FBERCPT4(1)
2236#define STV090x_P2_FBERCPT4 STV090x_Px_FBERCPT4(2)
2237#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0
2238#define STV090x_WIDTH_Px_BERMETER_CPT_FIELD 8
2239
2240#define STV090x_Px_FBERCPT3(__x) (0xF5A9 - (__x - 1) * 0x200)
2241#define STV090x_P1_FBERCPT3 STV090x_Px_FBERCPT3(1)
2242#define STV090x_P2_FBERCPT3 STV090x_Px_FBERCPT3(2)
2243#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0
2244#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8
2245
2246#define STV090x_Px_FBERCPT2(__x) (0xF5AA - (__x - 1) * 0x200)
2247#define STV090x_P1_FBERCPT2 STV090x_Px_FBERCPT2(1)
2248#define STV090x_P2_FBERCPT2 STV090x_Px_FBERCPT2(2)
2249#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0
2250#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8
2251
2252#define STV090x_Px_FBERCPT1(__x) (0xF5AB - (__x - 1) * 0x200)
2253#define STV090x_P1_FBERCPT1 STV090x_Px_FBERCPT1(1)
2254#define STV090x_P2_FBERCPT1 STV090x_Px_FBERCPT1(2)
2255#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0
2256#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8
2257
2258#define STV090x_Px_FBERCPT0(__x) (0xF5AC - (__x - 1) * 0x200)
2259#define STV090x_P1_FBERCPT0 STV090x_Px_FBERCPT0(1)
2260#define STV090x_P2_FBERCPT0 STV090x_Px_FBERCPT0(2)
2261#define STV090x_OFFST_Px_FBERMETER_CPT_FIELD 0
2262#define STV090x_WIDTH_Px_FBERMETER_CPT_FIELD 8
2263
2264#define STV090x_Px_FBERERRy(__x, __y) (0xF5AF - (__x - 1) * 0x200 - __y * 0x1)
2265#define STV090x_P1_FBERERR0 STV090x_Px_FBERERRy(1, 0)
2266#define STV090x_P1_FBERERR1 STV090x_Px_FBERERRy(1, 1)
2267#define STV090x_P1_FBERERR2 STV090x_Px_FBERERRy(1, 2)
2268#define STV090x_P2_FBERERR0 STV090x_Px_FBERERRy(2, 0)
2269#define STV090x_P2_FBERERR1 STV090x_Px_FBERERRy(2, 1)
2270#define STV090x_P2_FBERERR2 STV090x_Px_FBERERRy(2, 2)
2271#define STV090x_OFFST_Px_FBERMETER_CPT_ERR_FIELD 0
2272#define STV090x_WIDTH_Px_FBERMETER_CPT_ERR_FIELD 8
2273
2274#define STV090x_Px_FSPYBER(__x) (0xF5B2 - (__x - 1) * 0x200)
2275#define STV090x_P1_FSPYBER STV090x_Px_FSPYBER(1)
2276#define STV090x_P2_FSPYBER STV090x_Px_FSPYBER(2)
2277#define STV090x_OFFST_Px_FSPYBER_SYNCBYTE_FIELD 4
2278#define STV090x_WIDTH_Px_FSPYBER_SYNCBYTE_FIELD 1
2279#define STV090x_OFFST_Px_FSPYBER_UNSYNC_FIELD 3
2280#define STV090x_WIDTH_Px_FSPYBER_UNSYNC_FIELD 1
2281#define STV090x_OFFST_Px_FSPYBER_CTIME_FIELD 0
2282#define STV090x_WIDTH_Px_FSPYBER_CTIME_FIELD 3
2283
2284#define STV090x_TSGENERAL 0xF630
2285#define STV090x_OFFST_Px_MUXSTREAM_OUT_FIELD 3
2286#define STV090x_WIDTH_Px_MUXSTREAM_OUT_FIELD 1
2287#define STV090x_OFFST_Px_TSFIFO_PERMPARAL_FIELD 1
2288#define STV090x_WIDTH_Px_TSFIFO_PERMPARAL_FIELD 2
2289
2290#define STV090x_TSTRES0 0xFF11
2291#define STV090x_OFFST_FRESFEC_FIELD 7
2292#define STV090x_WIDTH_FRESFEC_FIELD 1
2293
2294#define STV090x_Px_TSTDISRX(__x) (0xFF67 - (__x - 1) * 0x2)
2295#define STV090x_P1_TSTDISRX STV090x_Px_TSTDISRX(1)
2296#define STV090x_P2_TSTDISRX STV090x_Px_TSTDISRX(2)
2297#define STV090x_OFFST_Px_TSTDISRX_SELECT_FIELD 3
2298#define STV090x_WIDTH_Px_TSTDISRX_SELECT_FIELD 1
2299
2300#endif /* __STV090x_REG_H */
diff --git a/drivers/media/dvb/frontends/stv6110x.c b/drivers/media/dvb/frontends/stv6110x.c
new file mode 100644
index 000000000000..738618133b16
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x.c
@@ -0,0 +1,372 @@
1/*
2 STV6110(A) Silicon tuner driver
3
4 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5
6 Copyright (C) ST Microelectronics
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/string.h>
27
28#include "dvb_frontend.h"
29
30#include "stv6110x_reg.h"
31#include "stv6110x.h"
32#include "stv6110x_priv.h"
33
34static unsigned int verbose;
35module_param(verbose, int, 0644);
36MODULE_PARM_DESC(verbose, "Set Verbosity level");
37
38static u8 stv6110x_regs[] = {0x07, 0x11, 0xdc, 0x85, 0x17, 0x01, 0xe6, 0x1e};
39
40static int stv6110x_read_reg(struct stv6110x_state *stv6110x, u8 reg, u8 *data)
41{
42 int ret;
43 const struct stv6110x_config *config = stv6110x->config;
44 u8 b0[] = { reg };
45 u8 b1[] = { 0 };
46 struct i2c_msg msg[] = {
47 { .addr = config->addr, .flags = 0, .buf = b0, .len = 1 },
48 { .addr = config->addr, .flags = I2C_M_RD, .buf = b1, .len = 1 }
49 };
50
51 ret = i2c_transfer(stv6110x->i2c, msg, 2);
52 if (ret != 2) {
53 dprintk(FE_ERROR, 1, "I/O Error");
54 return -EREMOTEIO;
55 }
56
57 return 0;
58}
59
60static int stv6110x_write_reg(struct stv6110x_state *stv6110x, u8 reg, u8 data)
61{
62 int ret;
63 const struct stv6110x_config *config = stv6110x->config;
64 u8 buf[] = { reg, data };
65 struct i2c_msg msg = { .addr = config->addr, .flags = 0, . buf = buf, .len = 2 };
66
67 ret = i2c_transfer(stv6110x->i2c, &msg, 1);
68 if (ret != 1) {
69 dprintk(FE_ERROR, 1, "I/O Error");
70 return -EREMOTEIO;
71 }
72
73 return 0;
74}
75
76static int stv6110x_init(struct dvb_frontend *fe)
77{
78 struct stv6110x_state *stv6110x = fe->tuner_priv;
79 int ret;
80 u8 i;
81
82 for (i = 0; i < ARRAY_SIZE(stv6110x_regs); i++) {
83 ret = stv6110x_write_reg(stv6110x, i, stv6110x_regs[i]);
84 if (ret < 0) {
85 dprintk(FE_ERROR, 1, "Initialization failed");
86 return -1;
87 }
88 }
89
90 return 0;
91}
92
93static int stv6110x_set_frequency(struct dvb_frontend *fe, u32 frequency)
94{
95 struct stv6110x_state *stv6110x = fe->tuner_priv;
96 u32 rDiv, divider;
97 s32 pVal, pCalc, rDivOpt = 0;
98 u8 i;
99
100 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_K, (REFCLOCK_MHz - 16));
101
102 if (frequency <= 1023000) {
103 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
104 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
105 pVal = 40;
106 } else if (frequency <= 1300000) {
107 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 1);
108 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
109 pVal = 40;
110 } else if (frequency <= 2046000) {
111 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
112 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 0);
113 pVal = 20;
114 } else {
115 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_DIV4SEL, 0);
116 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_PRESC32_ON, 1);
117 pVal = 20;
118 }
119
120 for (rDiv = 0; rDiv <= 3; rDiv++) {
121 pCalc = (REFCLOCK_kHz / 100) / R_DIV(rDiv);
122
123 if ((abs((s32)(pCalc - pVal))) < (abs((s32)(1000 - pVal))))
124 rDivOpt = rDiv;
125 }
126
127 divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
128 divider = (divider + 5) / 10;
129
130 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_R_DIV, rDivOpt);
131 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
132 STV6110x_SETFIELD(stv6110x_regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
133
134 /* VCO Auto calibration */
135 STV6110x_SETFIELD(stv6110x_regs[STV6110x_STAT1], STAT1_CALVCO_STRT, 1);
136
137 stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x_regs[STV6110x_CTRL1]);
138 stv6110x_write_reg(stv6110x, STV6110x_TNG1, stv6110x_regs[STV6110x_TNG1]);
139 stv6110x_write_reg(stv6110x, STV6110x_TNG0, stv6110x_regs[STV6110x_TNG0]);
140 stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x_regs[STV6110x_STAT1]);
141
142 for (i = 0; i < TRIALS; i++) {
143 stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
144 if (!STV6110x_GETFIELD(STAT1_CALVCO_STRT, stv6110x_regs[STV6110x_STAT1]))
145 break;
146 msleep(1);
147 }
148
149 return 0;
150}
151
152static int stv6110x_get_frequency(struct dvb_frontend *fe, u32 *frequency)
153{
154 struct stv6110x_state *stv6110x = fe->tuner_priv;
155
156 stv6110x_read_reg(stv6110x, STV6110x_TNG1, &stv6110x_regs[STV6110x_TNG1]);
157 stv6110x_read_reg(stv6110x, STV6110x_TNG0, &stv6110x_regs[STV6110x_TNG0]);
158
159 *frequency = (MAKEWORD16(STV6110x_GETFIELD(TNG1_N_DIV_11_8, stv6110x_regs[STV6110x_TNG1]),
160 STV6110x_GETFIELD(TNG0_N_DIV_7_0, stv6110x_regs[STV6110x_TNG0]))) * REFCLOCK_kHz;
161
162 *frequency /= (1 << (STV6110x_GETFIELD(TNG1_R_DIV, stv6110x_regs[STV6110x_TNG1]) +
163 STV6110x_GETFIELD(TNG1_DIV4SEL, stv6110x_regs[STV6110x_TNG1])));
164
165 *frequency >>= 2;
166
167 return 0;
168}
169
170static int stv6110x_set_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
171{
172 struct stv6110x_state *stv6110x = fe->tuner_priv;
173 u32 halfbw;
174 u8 i;
175
176 halfbw = bandwidth >> 1;
177
178 if (halfbw > 36000000)
179 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, 31); /* LPF */
180 else if (halfbw < 5000000)
181 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, 0); /* LPF */
182 else
183 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_CF, ((halfbw / 1000000) - 5)); /* LPF */
184
185
186 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x0); /* cal. clk activated */
187 STV6110x_SETFIELD(stv6110x_regs[STV6110x_STAT1], STAT1_CALRC_STRT, 0x1); /* LPF auto cal */
188
189 stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x_regs[STV6110x_CTRL3]);
190 stv6110x_write_reg(stv6110x, STV6110x_STAT1, stv6110x_regs[STV6110x_STAT1]);
191
192 for (i = 0; i < TRIALS; i++) {
193 stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
194 if (!STV6110x_GETFIELD(STAT1_CALRC_STRT, stv6110x_regs[STV6110x_STAT1]))
195 break;
196 msleep(1);
197 }
198 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL3], CTRL3_RCCLK_OFF, 0x1); /* cal. done */
199 stv6110x_write_reg(stv6110x, STV6110x_CTRL3, stv6110x_regs[STV6110x_CTRL3]);
200
201 return 0;
202}
203
204static int stv6110x_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
205{
206 struct stv6110x_state *stv6110x = fe->tuner_priv;
207
208 stv6110x_read_reg(stv6110x, STV6110x_CTRL3, &stv6110x_regs[STV6110x_CTRL3]);
209 *bandwidth = (STV6110x_GETFIELD(CTRL3_CF, stv6110x_regs[STV6110x_CTRL3]) + 5) * 2000000;
210
211 return 0;
212}
213
214static int stv6110x_set_refclock(struct dvb_frontend *fe, u32 refclock)
215{
216 struct stv6110x_state *stv6110x = fe->tuner_priv;
217
218 /* setup divider */
219 switch (refclock) {
220 default:
221 case 1:
222 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 0);
223 break;
224 case 2:
225 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 1);
226 break;
227 case 4:
228 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 2);
229 break;
230 case 8:
231 case 0:
232 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_CO_DIV, 3);
233 break;
234 }
235 stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x_regs[STV6110x_CTRL2]);
236
237 return 0;
238}
239
240static int stv6110x_get_bbgain(struct dvb_frontend *fe, u32 *gain)
241{
242 struct stv6110x_state *stv6110x = fe->tuner_priv;
243
244 stv6110x_read_reg(stv6110x, STV6110x_CTRL2, &stv6110x_regs[STV6110x_CTRL2]);
245 *gain = 2 * STV6110x_GETFIELD(CTRL2_BBGAIN, stv6110x_regs[STV6110x_CTRL2]);
246
247 return 0;
248}
249
250static int stv6110x_set_bbgain(struct dvb_frontend *fe, u32 gain)
251{
252 struct stv6110x_state *stv6110x = fe->tuner_priv;
253
254 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL2], CTRL2_BBGAIN, gain / 2);
255 stv6110x_write_reg(stv6110x, STV6110x_CTRL2, stv6110x_regs[STV6110x_CTRL2]);
256
257 return 0;
258}
259
260static int stv6110x_set_mode(struct dvb_frontend *fe, enum tuner_mode mode)
261{
262 struct stv6110x_state *stv6110x = fe->tuner_priv;
263 int ret;
264
265 switch (mode) {
266 case TUNER_SLEEP:
267 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_SYN, 0);
268 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_RX, 0);
269 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_LPT, 0);
270 break;
271
272 case TUNER_WAKE:
273 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_SYN, 1);
274 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_RX, 1);
275 STV6110x_SETFIELD(stv6110x_regs[STV6110x_CTRL1], CTRL1_LPT, 1);
276 break;
277 }
278
279 ret = stv6110x_write_reg(stv6110x, STV6110x_CTRL1, stv6110x_regs[STV6110x_CTRL1]);
280 if (ret < 0) {
281 dprintk(FE_ERROR, 1, "I/O Error");
282 return -EIO;
283 }
284
285 return 0;
286}
287
288static int stv6110x_sleep(struct dvb_frontend *fe)
289{
290 return stv6110x_set_mode(fe, TUNER_SLEEP);
291}
292
293static int stv6110x_get_status(struct dvb_frontend *fe, u32 *status)
294{
295 struct stv6110x_state *stv6110x = fe->tuner_priv;
296
297 stv6110x_read_reg(stv6110x, STV6110x_STAT1, &stv6110x_regs[STV6110x_STAT1]);
298
299 if (STV6110x_GETFIELD(STAT1_LOCK, stv6110x_regs[STV6110x_STAT1]))
300 *status = TUNER_PHASELOCKED;
301 else
302 *status = 0;
303
304 return 0;
305}
306
307
308static int stv6110x_release(struct dvb_frontend *fe)
309{
310 struct stv6110x_state *stv6110x = fe->tuner_priv;
311
312 fe->tuner_priv = NULL;
313 kfree(stv6110x);
314
315 return 0;
316}
317
318static struct dvb_tuner_ops stv6110x_ops = {
319 .info = {
320 .name = "STV6110(A) Silicon Tuner",
321 .frequency_min = 950000,
322 .frequency_max = 2150000,
323 .frequency_step = 0,
324 },
325
326 .init = stv6110x_init,
327 .sleep = stv6110x_sleep,
328 .release = stv6110x_release
329};
330
331static struct stv6110x_devctl stv6110x_ctl = {
332 .tuner_init = stv6110x_init,
333 .tuner_set_mode = stv6110x_set_mode,
334 .tuner_set_frequency = stv6110x_set_frequency,
335 .tuner_get_frequency = stv6110x_get_frequency,
336 .tuner_set_bandwidth = stv6110x_set_bandwidth,
337 .tuner_get_bandwidth = stv6110x_get_bandwidth,
338 .tuner_set_bbgain = stv6110x_set_bbgain,
339 .tuner_get_bbgain = stv6110x_get_bbgain,
340 .tuner_set_refclk = stv6110x_set_refclock,
341 .tuner_get_status = stv6110x_get_status,
342};
343
344struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
345 const struct stv6110x_config *config,
346 struct i2c_adapter *i2c)
347{
348 struct stv6110x_state *stv6110x;
349
350 stv6110x = kzalloc(sizeof (struct stv6110x_state), GFP_KERNEL);
351 if (stv6110x == NULL)
352 goto error;
353
354 stv6110x->i2c = i2c;
355 stv6110x->config = config;
356 stv6110x->devctl = &stv6110x_ctl;
357
358 fe->tuner_priv = stv6110x;
359 fe->ops.tuner_ops = stv6110x_ops;
360
361 printk("%s: Attaching STV6110x \n", __func__);
362 return stv6110x->devctl;
363
364error:
365 kfree(stv6110x);
366 return NULL;
367}
368EXPORT_SYMBOL(stv6110x_attach);
369
370MODULE_AUTHOR("Manu Abraham");
371MODULE_DESCRIPTION("STV6110x Silicon tuner");
372MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/stv6110x.h b/drivers/media/dvb/frontends/stv6110x.h
new file mode 100644
index 000000000000..a38257080e01
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x.h
@@ -0,0 +1,71 @@
1/*
2 STV6110(A) Silicon tuner driver
3
4 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5
6 Copyright (C) ST Microelectronics
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#ifndef __STV6110x_H
24#define __STV6110x_H
25
26struct stv6110x_config {
27 u8 addr;
28 u32 refclk;
29};
30
31enum tuner_mode {
32 TUNER_SLEEP = 1,
33 TUNER_WAKE,
34};
35
36enum tuner_status {
37 TUNER_PHASELOCKED = 1,
38};
39
40struct stv6110x_devctl {
41 int (*tuner_init) (struct dvb_frontend *fe);
42 int (*tuner_set_mode) (struct dvb_frontend *fe, enum tuner_mode mode);
43 int (*tuner_set_frequency) (struct dvb_frontend *fe, u32 frequency);
44 int (*tuner_get_frequency) (struct dvb_frontend *fe, u32 *frequency);
45 int (*tuner_set_bandwidth) (struct dvb_frontend *fe, u32 bandwidth);
46 int (*tuner_get_bandwidth) (struct dvb_frontend *fe, u32 *bandwidth);
47 int (*tuner_set_bbgain) (struct dvb_frontend *fe, u32 gain);
48 int (*tuner_get_bbgain) (struct dvb_frontend *fe, u32 *gain);
49 int (*tuner_set_refclk) (struct dvb_frontend *fe, u32 refclk);
50 int (*tuner_get_status) (struct dvb_frontend *fe, u32 *status);
51};
52
53
54#if defined(CONFIG_DVB_STV6110x) || (defined(CONFIG_DVB_STV6110x_MODULE) && defined(MODULE))
55
56extern struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
57 const struct stv6110x_config *config,
58 struct i2c_adapter *i2c);
59
60#else
61static inline struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe,
62 const struct stv6110x_config *config,
63 struct i2c_adapter *i2c)
64{
65 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
66 return NULL;
67}
68
69#endif /* CONFIG_DVB_STV6110x */
70
71#endif /* __STV6110x_H */
diff --git a/drivers/media/dvb/frontends/stv6110x_priv.h b/drivers/media/dvb/frontends/stv6110x_priv.h
new file mode 100644
index 000000000000..1295272fcff8
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x_priv.h
@@ -0,0 +1,77 @@
1/*
2 STV6110(A) Silicon tuner driver
3
4 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5
6 Copyright (C) ST Microelectronics
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#ifndef __STV6110x_PRIV_H
24#define __STV6110x_PRIV_H
25
26#define FE_ERROR 0
27#define FE_NOTICE 1
28#define FE_INFO 2
29#define FE_DEBUG 3
30#define FE_DEBUGREG 4
31
32#define dprintk(__y, __z, format, arg...) do { \
33 if (__z) { \
34 if ((verbose > FE_ERROR) && (verbose > __y)) \
35 printk(KERN_ERR "%s: " format "\n", __func__ , ##arg); \
36 else if ((verbose > FE_NOTICE) && (verbose > __y)) \
37 printk(KERN_NOTICE "%s: " format "\n", __func__ , ##arg); \
38 else if ((verbose > FE_INFO) && (verbose > __y)) \
39 printk(KERN_INFO "%s: " format "\n", __func__ , ##arg); \
40 else if ((verbose > FE_DEBUG) && (verbose > __y)) \
41 printk(KERN_DEBUG "%s: " format "\n", __func__ , ##arg); \
42 } else { \
43 if (verbose > __y) \
44 printk(format, ##arg); \
45 } \
46} while (0)
47
48
49#define STV6110x_SETFIELD(mask, bitf, val) \
50 (mask = (mask & (~(((1 << STV6110x_WIDTH_##bitf) - 1) << \
51 STV6110x_OFFST_##bitf))) | \
52 (val << STV6110x_OFFST_##bitf))
53
54#define STV6110x_GETFIELD(bitf, val) \
55 ((val >> STV6110x_OFFST_##bitf) & \
56 ((1 << STV6110x_WIDTH_##bitf) - 1))
57
58#define MAKEWORD16(a, b) (((a) << 8) | (b))
59
60#define LSB(x) ((x & 0xff))
61#define MSB(y) ((y >> 8) & 0xff)
62
63#define TRIALS 10
64#define R_DIV(__div) (1 << (__div + 1))
65#define REFCLOCK_kHz (stv6110x->reference / 1000)
66#define REFCLOCK_MHz (stv6110x->reference / 1000000)
67
68struct stv6110x_state {
69 struct i2c_adapter *i2c;
70 const struct stv6110x_config *config;
71
72 struct stv6110x_devctl *devctl;
73
74 u32 reference;
75};
76
77#endif /* __STV6110x_PRIV_H */
diff --git a/drivers/media/dvb/frontends/stv6110x_reg.h b/drivers/media/dvb/frontends/stv6110x_reg.h
new file mode 100644
index 000000000000..93e5c70e5fd8
--- /dev/null
+++ b/drivers/media/dvb/frontends/stv6110x_reg.h
@@ -0,0 +1,82 @@
1/*
2 STV6110(A) Silicon tuner driver
3
4 Copyright (C) Manu Abraham <abraham.manu@gmail.com>
5
6 Copyright (C) ST Microelectronics
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22
23#ifndef __STV6110x_REG_H
24#define __STV6110x_REG_H
25
26#define STV6110x_CTRL1 0x00
27#define STV6110x_OFFST_CTRL1_K 3
28#define STV6110x_WIDTH_CTRL1_K 5
29#define STV6110x_OFFST_CTRL1_LPT 2
30#define STV6110x_WIDTH_CTRL1_LPT 1
31#define STV6110x_OFFST_CTRL1_RX 1
32#define STV6110x_WIDTH_CTRL1_RX 1
33#define STV6110x_OFFST_CTRL1_SYN 0
34#define STV6110x_WIDTH_CTRL1_SYN 1
35
36#define STV6110x_CTRL2 0x01
37#define STV6110x_OFFST_CTRL2_CO_DIV 6
38#define STV6110x_WIDTH_CTRL2_CO_DIV 2
39#define STV6110x_OFFST_CTRL2_RSVD 5
40#define STV6110x_WIDTH_CTRL2_RSVD 1
41#define STV6110x_OFFST_CTRL2_REFOUT_SEL 4
42#define STV6110x_WIDTH_CTRL2_REFOUT_SEL 1
43#define STV6110x_OFFST_CTRL2_BBGAIN 0
44#define STV6110x_WIDTH_CTRL2_BBGAIN 4
45
46#define STV6110x_TNG0 0x02
47#define STV6110x_OFFST_TNG0_N_DIV_7_0 0
48#define STV6110x_WIDTH_TNG0_N_DIV_7_0 8
49
50#define STV6110x_TNG1 0x03
51#define STV6110x_OFFST_TNG1_R_DIV 6
52#define STV6110x_WIDTH_TNG1_R_DIV 2
53#define STV6110x_OFFST_TNG1_PRESC32_ON 5
54#define STV6110x_WIDTH_TNG1_PRESC32_ON 1
55#define STV6110x_OFFST_TNG1_DIV4SEL 4
56#define STV6110x_WIDTH_TNG1_DIV4SEL 1
57#define STV6110x_OFFST_TNG1_N_DIV_11_8 0
58#define STV6110x_WIDTH_TNG1_N_DIV_11_8 4
59
60
61#define STV6110x_CTRL3 0x04
62#define STV6110x_OFFST_CTRL3_DCLOOP_OFF 7
63#define STV6110x_WIDTH_CTRL3_DCLOOP_OFF 1
64#define STV6110x_OFFST_CTRL3_RCCLK_OFF 6
65#define STV6110x_WIDTH_CTRL3_RCCLK_OFF 1
66#define STV6110x_OFFST_CTRL3_ICP 5
67#define STV6110x_WIDTH_CTRL3_ICP 1
68#define STV6110x_OFFST_CTRL3_CF 0
69#define STV6110x_WIDTH_CTRL3_CF 5
70
71#define STV6110x_STAT1 0x05
72#define STV6110x_OFFST_STAT1_CALVCO_STRT 2
73#define STV6110x_WIDTH_STAT1_CALVCO_STRT 1
74#define STV6110x_OFFST_STAT1_CALRC_STRT 1
75#define STV6110x_WIDTH_STAT1_CALRC_STRT 1
76#define STV6110x_OFFST_STAT1_LOCK 0
77#define STV6110x_WIDTH_STAT1_LOCK 1
78
79#define STV6110x_STAT2 0x06
80#define STV6110x_STAT3 0x07
81
82#endif /* __STV6110x_REG_H */
diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c
index 371a71616810..2ee03206dc8c 100644
--- a/drivers/media/dvb/ttpci/budget-ci.c
+++ b/drivers/media/dvb/ttpci/budget-ci.c
@@ -53,6 +53,9 @@
53#include "bsru6.h" 53#include "bsru6.h"
54#include "tda1002x.h" 54#include "tda1002x.h"
55#include "tda827x.h" 55#include "tda827x.h"
56#include "stv6110x.h"
57#include "stv090x.h"
58#include "isl6423.h"
56 59
57/* 60/*
58 * Regarding DEBIADDR_IR: 61 * Regarding DEBIADDR_IR:
@@ -1346,6 +1349,41 @@ static struct stb6100_config tt3200_stb6100_config = {
1346 .refclock = 27000000, 1349 .refclock = 27000000,
1347}; 1350};
1348 1351
1352static struct stv090x_config tt1600_stv090x_config = {
1353 .device = STV0903,
1354 .demod_mode = STV090x_SINGLE,
1355 .clk_mode = STV090x_CLK_INT,
1356
1357 .xtal = 8000000,
1358 .address = 0x68,
1359 .ref_clk = 16000000,
1360
1361 .ts1_mode = STV090x_TSMODE_DVBCI,
1362 .ts2_mode = STV090x_TSMODE_DVBCI,
1363
1364 .tuner_init = NULL,
1365 .tuner_set_mode = NULL,
1366 .tuner_set_frequency = NULL,
1367 .tuner_get_frequency = NULL,
1368 .tuner_set_bandwidth = NULL,
1369 .tuner_get_bandwidth = NULL,
1370 .tuner_set_bbgain = NULL,
1371 .tuner_get_bbgain = NULL,
1372 .tuner_set_refclk = NULL,
1373 .tuner_get_status = NULL,
1374};
1375
1376static struct stv6110x_config tt1600_stv6110x_config = {
1377 .addr = 0x60,
1378 .refclk = 16000000,
1379};
1380
1381static struct isl6423_config tt1600_isl6423_config = {
1382 .current_max = SEC_CURRENT_800m,
1383 .curlim = SEC_CURRENT_LIM_ON,
1384 .addr = 0x08,
1385};
1386
1349static void frontend_init(struct budget_ci *budget_ci) 1387static void frontend_init(struct budget_ci *budget_ci)
1350{ 1388{
1351 switch (budget_ci->budget.dev->pci->subsystem_device) { 1389 switch (budget_ci->budget.dev->pci->subsystem_device) {
@@ -1465,6 +1503,49 @@ static void frontend_init(struct budget_ci *budget_ci)
1465 } 1503 }
1466 break; 1504 break;
1467 1505
1506 case 0x101c: { /* TT S2-1600 */
1507 struct stv6110x_devctl *ctl;
1508 /* TODO! must verify with Andreas */
1509 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO);
1510 msleep(50);
1511 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI);
1512 msleep(250);
1513
1514 budget_ci->budget.dvb_frontend = dvb_attach(stv090x_attach,
1515 &tt1600_stv090x_config,
1516 &budget_ci->budget.i2c_adap,
1517 STV090x_DEMODULATOR_0);
1518
1519 if (budget_ci->budget.dvb_frontend) {
1520
1521 ctl = dvb_attach(stv6110x_attach,
1522 budget_ci->budget.dvb_frontend,
1523 &tt1600_stv6110x_config,
1524 &budget_ci->budget.i2c_adap);
1525
1526 tt1600_stv090x_config.tuner_init = ctl->tuner_init;
1527 tt1600_stv090x_config.tuner_set_mode = ctl->tuner_set_mode;
1528 tt1600_stv090x_config.tuner_set_frequency = ctl->tuner_set_frequency;
1529 tt1600_stv090x_config.tuner_get_frequency = ctl->tuner_get_frequency;
1530 tt1600_stv090x_config.tuner_set_bandwidth = ctl->tuner_set_bandwidth;
1531 tt1600_stv090x_config.tuner_get_bandwidth = ctl->tuner_get_bandwidth;
1532 tt1600_stv090x_config.tuner_set_bbgain = ctl->tuner_set_bbgain;
1533 tt1600_stv090x_config.tuner_get_bbgain = ctl->tuner_get_bbgain;
1534 tt1600_stv090x_config.tuner_set_refclk = ctl->tuner_set_refclk;
1535 tt1600_stv090x_config.tuner_get_status = ctl->tuner_get_status;
1536
1537 dvb_attach(isl6423_attach,
1538 budget_ci->budget.dvb_frontend,
1539 &budget_ci->budget.i2c_adap,
1540 &tt1600_isl6423_config);
1541
1542 } else {
1543 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1544 budget_ci->budget.dvb_frontend = NULL;
1545 }
1546 }
1547 break;
1548
1468 } 1549 }
1469 1550
1470 if (budget_ci->budget.dvb_frontend == NULL) { 1551 if (budget_ci->budget.dvb_frontend == NULL) {
@@ -1556,6 +1637,7 @@ MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
1556MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT); 1637MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
1557MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT); 1638MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
1558MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT); 1639MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
1640MAKE_BUDGET_INFO(tt1600, "TT-Budget S2-1600 PCI", BUDGET_TT);
1559 1641
1560static struct pci_device_id pci_tbl[] = { 1642static struct pci_device_id pci_tbl[] = {
1561 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c), 1643 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
@@ -1566,6 +1648,7 @@ static struct pci_device_id pci_tbl[] = {
1566 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017), 1648 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
1567 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a), 1649 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
1568 MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019), 1650 MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
1651 MAKE_EXTENSION_PCI(tt1600, 0x13c2, 0x101c),
1569 { 1652 {
1570 .vendor = 0, 1653 .vendor = 0,
1571 } 1654 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 11:00:43 -0500