MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX

Make messages refer to all CN6XXX.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8941/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 8 insertions, 4 deletions

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 2d8a53100e41..6c51ef6d57c7 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -1041,7 +1041,7 @@ EXPORT_SYMBOL(prom_putchar);
 
 void prom_free_prom_memory(void)
 {
-        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
+        if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
                 /* Check for presence of Core-14449 fix.  */
                 u32 insn;
                 u32 *foo;
@@ -1063,8 +1063,9 @@ void prom_free_prom_memory(void)
                         panic("No PREF instruction at Core-14449 probe point.");
 
                 if (((insn >> 16) & 0x1f) != 28)
-                        panic("Core-14449 WAR not in place (%04x).\n"
-                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
+                        panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
+                              "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
+                              insn);
         }
 }
 
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index eb72b35cf04b..35c80be92207 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -22,4 +22,7 @@
 #define R10000_LLSC_WAR                 0
 #define MIPS34K_MISSED_ITLB_WAR         0
 
+#define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR       \
+        OCTEON_IS_MODEL(OCTEON_CN6XXX)
+
 #endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index f86d293463a6..319051c34343 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -341,7 +341,7 @@ I_u3u1u2(_ldx)
 void ISAFUNC(uasm_i_pref)(u32 **buf, unsigned int a, signed int b,
                             unsigned int c)
 {
-        if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
+        if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR && a <= 24 && a != 5)
                 /*
                  * As per erratum Core-14449, replace prefetches 0-4,
                  * 6-24 with 'pref 28'.