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authorLinus Walleij <linus.walleij@stericsson.com>2010-08-19 07:36:01 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-09-02 10:46:21 -0400
commite3726fcf263adf764a4f1b9428082837662a41c4 (patch)
tree080ffcc6a184e3afa723abcd901d305ba063e439
parent008f8a2f7ff4d63559b7ba7a6f7073efef9b1e08 (diff)
ARM: 6336/1: U8500 PRCMU driver
Add an initial driver for communicating with the Power, Reset and Clock Management Unit (PRCMU) firmware in U8500. This initial version supports AB8500 communication only. Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com> Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-ux500/Makefile2
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu-regs.h91
-rw-r--r--arch/arm/mach-ux500/include/mach/prcmu.h15
-rw-r--r--arch/arm/mach-ux500/prcmu.c231
5 files changed, 339 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 33903af98b24..009731864399 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -4,7 +4,7 @@
4 4
5obj-y := clock.o cpu.o devices.o 5obj-y := clock.o cpu.o devices.o
6obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o 6obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o
7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o
8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o 8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o
9obj-$(CONFIG_MACH_U5500) += board-u5500.o 9obj-$(CONFIG_MACH_U5500) += board-u5500.o
10obj-$(CONFIG_SMP) += platsmp.o headsmp.o 10obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 10385bdc2b77..0e7a2cec1994 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -41,6 +41,7 @@
41#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) 41#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
42#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) 42#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
43#define IRQ_AB4500 (IRQ_SHPI_START + 40) 43#define IRQ_AB4500 (IRQ_SHPI_START + 40)
44#define IRQ_PRCMU (IRQ_SHPI_START + 47)
44#define IRQ_DISP (IRQ_SHPI_START + 48) 45#define IRQ_DISP (IRQ_SHPI_START + 48)
45#define IRQ_SiPI3 (IRQ_SHPI_START + 49) 46#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
46#define IRQ_I2C4 (IRQ_SHPI_START + 51) 47#define IRQ_I2C4 (IRQ_SHPI_START + 51)
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
new file mode 100644
index 000000000000..8885f39a6421
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright (c) 2009 ST-Ericsson SA
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2
6 * as published by the Free Software Foundation.
7 */
8#ifndef __MACH_PRCMU_REGS_H
9#define __MACH_PRCMU_REGS_H
10
11#include <mach/hardware.h>
12
13#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
14
15#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
16#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
17#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
18#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
19#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
20#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
21#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
22#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
23
24/* ARM WFI Standby signal register */
25#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
26#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
27
28/* CPU mailbox registers */
29#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
30#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
31#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
32
33/* Dual A9 core interrupt management unit registers */
34#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
35#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
36#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
37#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
38#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
39#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
40#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
41#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
42#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
43#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
44#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
45
46#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
47#define ARM_WAKEUP_MODEM 0x1
48
49#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
50#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
51#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
52
53#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
54#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
55#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
56#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
57#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
58#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
59#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
60#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
61
62/* System reset register */
63#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
64
65/* Level shifter and clamp control registers */
66#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
67#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
68
69/* PRCMU clock/PLL/reset registers */
70#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
71#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
72#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
73#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
74#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
75#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
76#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
77#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
78#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
79#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
80
81/* ePOD and memory power signal control registers */
82#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
83#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
84
85/* Debug power control unit registers */
86#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
87
88/* Miscellaneous unit registers */
89#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
90
91#endif /* __MACH_PRCMU__REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
new file mode 100644
index 000000000000..549843ff6dbe
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 *
7 * PRCMU f/w APIs
8 */
9#ifndef __MACH_PRCMU_H
10#define __MACH_PRCMU_H
11
12int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
13int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
14
15#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
new file mode 100644
index 000000000000..293274d1342a
--- /dev/null
+++ b/arch/arm/mach-ux500/prcmu.c
@@ -0,0 +1,231 @@
1/*
2 * Copyright (C) ST Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
6 *
7 * U8500 PRCMU driver.
8 */
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/mutex.h>
15#include <linux/completion.h>
16#include <linux/jiffies.h>
17#include <linux/bitops.h>
18#include <linux/interrupt.h>
19
20#include <mach/hardware.h>
21#include <mach/prcmu-regs.h>
22
23#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE)
24
25#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44)
26#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4)
27
28#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
29#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
30#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
31#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
32
33#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
34#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
35
36#define I2C_WRITE(slave) ((slave) << 1)
37#define I2C_READ(slave) (((slave) << 1) | BIT(0))
38#define I2C_STOP_EN BIT(3)
39
40enum ack_mb5_status {
41 I2C_WR_OK = 0x01,
42 I2C_RD_OK = 0x02,
43};
44
45#define MBOX_BIT BIT
46#define NUM_MBOX 8
47
48static struct {
49 struct mutex lock;
50 struct completion work;
51 bool failed;
52 struct {
53 u8 status;
54 u8 value;
55 } ack;
56} mb5_transfer;
57
58/**
59 * prcmu_abb_read() - Read register value(s) from the ABB.
60 * @slave: The I2C slave address.
61 * @reg: The (start) register address.
62 * @value: The read out value(s).
63 * @size: The number of registers to read.
64 *
65 * Reads register value(s) from the ABB.
66 * @size has to be 1 for the current firmware version.
67 */
68int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
69{
70 int r;
71
72 if (size != 1)
73 return -EINVAL;
74
75 r = mutex_lock_interruptible(&mb5_transfer.lock);
76 if (r)
77 return r;
78
79 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
80 cpu_relax();
81
82 writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
83 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
84 writeb(reg, REQ_MB5_I2C_REG);
85
86 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
87 if (!wait_for_completion_timeout(&mb5_transfer.work,
88 msecs_to_jiffies(500))) {
89 pr_err("prcmu: prcmu_abb_read timed out.\n");
90 r = -EIO;
91 goto unlock_and_return;
92 }
93 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
94 if (!r)
95 *value = mb5_transfer.ack.value;
96
97unlock_and_return:
98 mutex_unlock(&mb5_transfer.lock);
99 return r;
100}
101EXPORT_SYMBOL(prcmu_abb_read);
102
103/**
104 * prcmu_abb_write() - Write register value(s) to the ABB.
105 * @slave: The I2C slave address.
106 * @reg: The (start) register address.
107 * @value: The value(s) to write.
108 * @size: The number of registers to write.
109 *
110 * Reads register value(s) from the ABB.
111 * @size has to be 1 for the current firmware version.
112 */
113int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
114{
115 int r;
116
117 if (size != 1)
118 return -EINVAL;
119
120 r = mutex_lock_interruptible(&mb5_transfer.lock);
121 if (r)
122 return r;
123
124
125 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
126 cpu_relax();
127
128 writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
129 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
130 writeb(reg, REQ_MB5_I2C_REG);
131 writeb(*value, REQ_MB5_I2C_VAL);
132
133 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
134 if (!wait_for_completion_timeout(&mb5_transfer.work,
135 msecs_to_jiffies(500))) {
136 pr_err("prcmu: prcmu_abb_write timed out.\n");
137 r = -EIO;
138 goto unlock_and_return;
139 }
140 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
141
142unlock_and_return:
143 mutex_unlock(&mb5_transfer.lock);
144 return r;
145}
146EXPORT_SYMBOL(prcmu_abb_write);
147
148static void read_mailbox_0(void)
149{
150 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
151}
152
153static void read_mailbox_1(void)
154{
155 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
156}
157
158static void read_mailbox_2(void)
159{
160 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
161}
162
163static void read_mailbox_3(void)
164{
165 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
166}
167
168static void read_mailbox_4(void)
169{
170 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
171}
172
173static void read_mailbox_5(void)
174{
175 mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
176 mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
177 complete(&mb5_transfer.work);
178 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
179}
180
181static void read_mailbox_6(void)
182{
183 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
184}
185
186static void read_mailbox_7(void)
187{
188 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
189}
190
191static void (* const read_mailbox[NUM_MBOX])(void) = {
192 read_mailbox_0,
193 read_mailbox_1,
194 read_mailbox_2,
195 read_mailbox_3,
196 read_mailbox_4,
197 read_mailbox_5,
198 read_mailbox_6,
199 read_mailbox_7
200};
201
202static irqreturn_t prcmu_irq_handler(int irq, void *data)
203{
204 u32 bits;
205 u8 n;
206
207 bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
208 if (unlikely(!bits))
209 return IRQ_NONE;
210
211 for (n = 0; bits; n++) {
212 if (bits & MBOX_BIT(n)) {
213 bits -= MBOX_BIT(n);
214 read_mailbox[n]();
215 }
216 }
217 return IRQ_HANDLED;
218}
219
220static int __init prcmu_init(void)
221{
222 mutex_init(&mb5_transfer.lock);
223 init_completion(&mb5_transfer.work);
224
225 /* Clean up the mailbox interrupts after pre-kernel code. */
226 writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
227
228 return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL);
229}
230
231arch_initcall(prcmu_init);