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authorRalf Baechle <ralf@linux-mips.org>2013-01-22 06:50:10 -0500
committerRalf Baechle <ralf@linux-mips.org>2013-02-01 04:00:21 -0500
commite33b0451e983734b20f423f3fd68016c34d5724d (patch)
tree06275d2d5cc82b9acfc56d0c240413dc32686008
parent9b73100911ac6886e1bbf54a4626d545f9ba6ddf (diff)
MIPS: PNX8550: Remove support for SOC and JBS and STB810 boards.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kbuild.platforms1
-rw-r--r--arch/mips/Kconfig23
-rw-r--r--arch/mips/configs/pnx8550_jbs_defconfig98
-rw-r--r--arch/mips/configs/pnx8550_stb810_defconfig92
-rw-r--r--arch/mips/include/asm/mach-pnx8550/cm.h43
-rw-r--r--arch/mips/include/asm/mach-pnx8550/glb.h86
-rw-r--r--arch/mips/include/asm/mach-pnx8550/int.h140
-rw-r--r--arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h262
-rw-r--r--arch/mips/include/asm/mach-pnx8550/nand.h121
-rw-r--r--arch/mips/include/asm/mach-pnx8550/pci.h185
-rw-r--r--arch/mips/include/asm/mach-pnx8550/uart.h30
-rw-r--r--arch/mips/include/asm/mach-pnx8550/usb.h32
-rw-r--r--arch/mips/include/asm/mach-pnx8550/war.h24
-rw-r--r--arch/mips/pci/Makefile1
-rw-r--r--arch/mips/pci/fixup-pnx8550.c57
-rw-r--r--arch/mips/pci/ops-pnx8550.c282
-rw-r--r--arch/mips/pnx8550/Makefile3
-rw-r--r--arch/mips/pnx8550/Platform7
-rw-r--r--arch/mips/pnx8550/common/Makefile26
-rw-r--r--arch/mips/pnx8550/common/int.c236
-rw-r--r--arch/mips/pnx8550/common/pci.c134
-rw-r--r--arch/mips/pnx8550/common/platform.c162
-rw-r--r--arch/mips/pnx8550/common/proc.c110
-rw-r--r--arch/mips/pnx8550/common/prom.c128
-rw-r--r--arch/mips/pnx8550/common/reset.c40
-rw-r--r--arch/mips/pnx8550/common/setup.c142
-rw-r--r--arch/mips/pnx8550/common/time.c151
-rw-r--r--arch/mips/pnx8550/jbs/Makefile4
-rw-r--r--arch/mips/pnx8550/jbs/board_setup.c56
-rw-r--r--arch/mips/pnx8550/jbs/init.c53
-rw-r--r--arch/mips/pnx8550/jbs/irqmap.c35
-rw-r--r--arch/mips/pnx8550/stb810/Makefile4
-rw-r--r--arch/mips/pnx8550/stb810/board_setup.c41
-rw-r--r--arch/mips/pnx8550/stb810/irqmap.c22
-rw-r--r--arch/mips/pnx8550/stb810/prom_init.c46
-rw-r--r--drivers/tty/serial/Kconfig10
36 files changed, 5 insertions, 2882 deletions
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 91b9d69f465c..c7ea3a08c729 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -20,7 +20,6 @@ platforms += mti-sead3
20platforms += netlogic 20platforms += netlogic
21platforms += pmc-sierra 21platforms += pmc-sierra
22platforms += pnx833x 22platforms += pnx833x
23platforms += pnx8550
24platforms += powertv 23platforms += powertv
25platforms += rb532 24platforms += rb532
26platforms += sgi-ip22 25platforms += sgi-ip22
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 1110cd718ff5..6b1c33b65d15 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -385,16 +385,6 @@ config NXP_STB225
385 help 385 help
386 Support for NXP Semiconductors STB225 Development Board. 386 Support for NXP Semiconductors STB225 Development Board.
387 387
388config PNX8550_JBS
389 bool "NXP PNX8550 based JBS board"
390 select PNX8550
391 select SYS_SUPPORTS_LITTLE_ENDIAN
392
393config PNX8550_STB810
394 bool "NXP PNX8550 based STB810 board"
395 select PNX8550
396 select SYS_SUPPORTS_LITTLE_ENDIAN
397
398config PMC_MSP 388config PMC_MSP
399 bool "PMC-Sierra MSP chipsets" 389 bool "PMC-Sierra MSP chipsets"
400 depends on EXPERIMENTAL 390 depends on EXPERIMENTAL
@@ -1113,19 +1103,6 @@ config SOC_PNX8335
1113 bool 1103 bool
1114 select SOC_PNX833X 1104 select SOC_PNX833X
1115 1105
1116config PNX8550
1117 bool
1118 select SOC_PNX8550
1119
1120config SOC_PNX8550
1121 bool
1122 select DMA_NONCOHERENT
1123 select HW_HAS_PCI
1124 select SYS_HAS_CPU_MIPS32_R1
1125 select SYS_HAS_EARLY_PRINTK
1126 select SYS_SUPPORTS_32BIT_KERNEL
1127 select GENERIC_GPIO
1128
1129config SWAP_IO_SPACE 1106config SWAP_IO_SPACE
1130 bool 1107 bool
1131 1108
diff --git a/arch/mips/configs/pnx8550_jbs_defconfig b/arch/mips/configs/pnx8550_jbs_defconfig
deleted file mode 100644
index 1d1f2067f3e6..000000000000
--- a/arch/mips/configs/pnx8550_jbs_defconfig
+++ /dev/null
@@ -1,98 +0,0 @@
1CONFIG_PNX8550_JBS=y
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_BLK_DEV_INITRD=y
8# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
9CONFIG_EXPERT=y
10# CONFIG_SYSCTL_SYSCALL is not set
11CONFIG_SLAB=y
12CONFIG_MODULES=y
13CONFIG_PCI=y
14CONFIG_PM=y
15CONFIG_PACKET=y
16CONFIG_UNIX=y
17CONFIG_XFRM_MIGRATE=y
18CONFIG_INET=y
19CONFIG_IP_PNP=y
20CONFIG_IP_PNP_DHCP=y
21CONFIG_IP_PNP_BOOTP=y
22CONFIG_TCP_MD5SIG=y
23# CONFIG_IPV6 is not set
24CONFIG_BLK_DEV_LOOP=y
25CONFIG_BLK_DEV_RAM=y
26CONFIG_BLK_DEV_RAM_SIZE=8192
27CONFIG_SGI_IOC4=m
28CONFIG_IDE=y
29CONFIG_BLK_DEV_IDECD=m
30CONFIG_IDE_GENERIC=y
31CONFIG_BLK_DEV_OFFBOARD=y
32CONFIG_BLK_DEV_GENERIC=y
33CONFIG_BLK_DEV_HPT366=y
34CONFIG_BLK_DEV_IT8213=m
35CONFIG_BLK_DEV_TC86C001=m
36CONFIG_SCSI=y
37CONFIG_SCSI_TGT=m
38CONFIG_BLK_DEV_SD=y
39CONFIG_SCSI_CONSTANTS=y
40CONFIG_SCSI_SCAN_ASYNC=y
41CONFIG_SCSI_FC_ATTRS=y
42CONFIG_ISCSI_TCP=m
43CONFIG_NETDEVICES=y
44CONFIG_NET_ETHERNET=y
45CONFIG_NET_PCI=y
46CONFIG_8139TOO=y
47# CONFIG_8139TOO_PIO is not set
48CONFIG_8139TOO_TUNE_TWISTER=y
49CONFIG_8139TOO_8129=y
50CONFIG_CHELSIO_T3=m
51CONFIG_NETXEN_NIC=m
52# CONFIG_INPUT_MOUSEDEV is not set
53# CONFIG_INPUT_KEYBOARD is not set
54# CONFIG_INPUT_MOUSE is not set
55# CONFIG_SERIO_I8042 is not set
56# CONFIG_SERIO_SERPORT is not set
57CONFIG_SERIO_LIBPS2=y
58CONFIG_SERIAL_PNX8XXX=y
59CONFIG_SERIAL_PNX8XXX_CONSOLE=y
60CONFIG_HW_RANDOM=y
61# CONFIG_VGA_CONSOLE is not set
62# CONFIG_HID is not set
63# CONFIG_USB_HID is not set
64CONFIG_USB=y
65CONFIG_USB_MON=y
66CONFIG_USB_OHCI_HCD=y
67CONFIG_USB_STORAGE=y
68CONFIG_USB_STORAGE_DATAFAB=y
69CONFIG_USB_STORAGE_FREECOM=y
70CONFIG_USB_STORAGE_ISD200=y
71CONFIG_USB_STORAGE_USBAT=y
72CONFIG_USB_STORAGE_SDDR09=y
73CONFIG_USB_STORAGE_SDDR55=y
74CONFIG_USB_STORAGE_JUMPSHOT=y
75CONFIG_EXT2_FS=y
76# CONFIG_DNOTIFY is not set
77CONFIG_MSDOS_FS=y
78CONFIG_VFAT_FS=y
79CONFIG_TMPFS=y
80CONFIG_NFS_FS=y
81CONFIG_NFS_V3=y
82CONFIG_ROOT_NFS=y
83CONFIG_NFSD=m
84CONFIG_DLM=m
85CONFIG_MAGIC_SYSRQ=y
86CONFIG_DEBUG_KERNEL=y
87CONFIG_DEBUG_SLAB=y
88CONFIG_DEBUG_MUTEXES=y
89CONFIG_CMDLINE_BOOL=y
90CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
91CONFIG_CRYPTO_CBC=m
92CONFIG_CRYPTO_ECB=m
93CONFIG_CRYPTO_LRW=m
94CONFIG_CRYPTO_PCBC=m
95CONFIG_CRYPTO_XCBC=m
96CONFIG_CRYPTO_CAMELLIA=m
97CONFIG_CRYPTO_FCRYPT=m
98CONFIG_CRC_CCITT=m
diff --git a/arch/mips/configs/pnx8550_stb810_defconfig b/arch/mips/configs/pnx8550_stb810_defconfig
deleted file mode 100644
index 15c66a571f99..000000000000
--- a/arch/mips/configs/pnx8550_stb810_defconfig
+++ /dev/null
@@ -1,92 +0,0 @@
1CONFIG_PNX8550_STB810=y
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=14
7CONFIG_BLK_DEV_INITRD=y
8# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
9CONFIG_EXPERT=y
10# CONFIG_SYSCTL_SYSCALL is not set
11# CONFIG_HOTPLUG is not set
12CONFIG_SLAB=y
13CONFIG_MODULES=y
14CONFIG_PCI=y
15CONFIG_PM=y
16CONFIG_NET=y
17CONFIG_PACKET=y
18CONFIG_UNIX=y
19CONFIG_XFRM_MIGRATE=y
20CONFIG_INET=y
21CONFIG_IP_PNP=y
22CONFIG_IP_PNP_DHCP=y
23CONFIG_IP_PNP_BOOTP=y
24# CONFIG_IPV6 is not set
25CONFIG_BLK_DEV_LOOP=y
26CONFIG_BLK_DEV_RAM=y
27CONFIG_BLK_DEV_RAM_SIZE=8192
28CONFIG_IDE=y
29CONFIG_BLK_DEV_IDECD=m
30CONFIG_IDE_GENERIC=y
31CONFIG_BLK_DEV_OFFBOARD=y
32CONFIG_BLK_DEV_GENERIC=y
33CONFIG_BLK_DEV_HPT366=y
34CONFIG_BLK_DEV_IT8213=m
35CONFIG_BLK_DEV_TC86C001=m
36CONFIG_SCSI=y
37CONFIG_SCSI_TGT=m
38CONFIG_BLK_DEV_SD=y
39CONFIG_SCSI_CONSTANTS=y
40CONFIG_SCSI_SCAN_ASYNC=y
41CONFIG_ISCSI_TCP=m
42CONFIG_NETDEVICES=y
43CONFIG_NET_ETHERNET=y
44CONFIG_MII=y
45CONFIG_NET_PCI=y
46CONFIG_NATSEMI=y
47CONFIG_CHELSIO_T3=m
48# CONFIG_INPUT_MOUSEDEV is not set
49# CONFIG_INPUT_KEYBOARD is not set
50# CONFIG_INPUT_MOUSE is not set
51# CONFIG_SERIO_I8042 is not set
52# CONFIG_SERIO_SERPORT is not set
53CONFIG_SERIO_LIBPS2=y
54CONFIG_HW_RANDOM=y
55# CONFIG_VGA_CONSOLE is not set
56# CONFIG_HID is not set
57# CONFIG_USB_HID is not set
58CONFIG_USB=y
59CONFIG_USB_MON=y
60CONFIG_USB_OHCI_HCD=y
61CONFIG_USB_STORAGE=y
62CONFIG_USB_STORAGE_DATAFAB=y
63CONFIG_USB_STORAGE_FREECOM=y
64CONFIG_USB_STORAGE_ISD200=y
65CONFIG_USB_STORAGE_USBAT=y
66CONFIG_USB_STORAGE_SDDR09=y
67CONFIG_USB_STORAGE_SDDR55=y
68CONFIG_USB_STORAGE_JUMPSHOT=y
69CONFIG_EXT2_FS=y
70# CONFIG_DNOTIFY is not set
71CONFIG_MSDOS_FS=y
72CONFIG_VFAT_FS=y
73CONFIG_TMPFS=y
74CONFIG_NFS_FS=y
75CONFIG_NFS_V3=y
76CONFIG_ROOT_NFS=y
77CONFIG_NFSD=m
78CONFIG_DLM=m
79CONFIG_MAGIC_SYSRQ=y
80CONFIG_HEADERS_CHECK=y
81CONFIG_DEBUG_KERNEL=y
82CONFIG_DEBUG_SLAB=y
83CONFIG_CMDLINE_BOOL=y
84CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
85CONFIG_CRYPTO_CBC=m
86CONFIG_CRYPTO_ECB=m
87CONFIG_CRYPTO_LRW=m
88CONFIG_CRYPTO_PCBC=m
89CONFIG_CRYPTO_XCBC=m
90CONFIG_CRYPTO_CAMELLIA=m
91CONFIG_CRYPTO_FCRYPT=m
92CONFIG_CRC_CCITT=m
diff --git a/arch/mips/include/asm/mach-pnx8550/cm.h b/arch/mips/include/asm/mach-pnx8550/cm.h
deleted file mode 100644
index bb0a56c7d011..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/cm.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Clock module specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_CM_H
23#define __PNX8550_CM_H
24
25#define PNX8550_CM_BASE 0xBBE47000
26
27#define PNX8550_CM_PLL0_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
28#define PNX8550_CM_PLL1_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
29#define PNX8550_CM_PLL2_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
30#define PNX8550_CM_PLL3_CTL *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
31
32// Table not complete.....
33
34#define PNX8550_CM_PLL_BLOCKED_MASK 0x80000000
35#define PNX8550_CM_PLL_LOCK_MASK 0x40000000
36#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
37#define PNX8550_CM_PLL_N_MASK 0x01ff0000
38#define PNX8550_CM_PLL_M_MASK 0x00003f00
39#define PNX8550_CM_PLL_P_MASK 0x0000000c
40#define PNX8550_CM_PLL_PD_MASK 0x00000002
41
42
43#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/glb.h b/arch/mips/include/asm/mach-pnx8550/glb.h
deleted file mode 100644
index 07aa85e609bc..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/glb.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PNX8550 global definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_GLB_H
23#define __PNX8550_GLB_H
24
25#define PNX8550_GLB1_BASE 0xBBE63000
26#define PNX8550_GLB2_BASE 0xBBE4d000
27#define PNX8550_RESET_BASE 0xBBE60000
28
29/* PCI Inta Output Enable Registers */
30#define PNX8550_GLB2_ENAB_INTA_O *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
31
32/* Bit 1:Enable DAC Powerdown
33 0:DACs are enabled and are working normally
34 1:DACs are powerdown
35*/
36#define PNX8550_GLB_DAC_PD 0x2
37/* Bit 0:Enable of PCI inta output
38 0 = Disable PCI inta output
39 1 = Enable PCI inta output
40*/
41#define PNX8550_GLB_ENABLE_INTA_O 0x1
42
43/* PCI Direct Mappings */
44#define PNX8550_PCIMEM 0x12000000
45#define PNX8550_PCIMEM_SIZE 0x08000000
46#define PNX8550_PCIIO 0x1c000000
47#define PNX8550_PCIIO_SIZE 0x02000000 /* 32M */
48
49#define PNX8550_PORT_BASE KSEG1
50
51// GPIO def
52#define PNX8550_GPIO_BASE 0x1Be00000
53
54#define PNX8550_GPIO_DIRQ0 (PNX8550_GPIO_BASE + 0x104500)
55#define PNX8550_GPIO_MC1 (PNX8550_GPIO_BASE + 0x104004)
56#define PNX8550_GPIO_MC_31_BIT 30
57#define PNX8550_GPIO_MC_30_BIT 28
58#define PNX8550_GPIO_MC_29_BIT 26
59#define PNX8550_GPIO_MC_28_BIT 24
60#define PNX8550_GPIO_MC_27_BIT 22
61#define PNX8550_GPIO_MC_26_BIT 20
62#define PNX8550_GPIO_MC_25_BIT 18
63#define PNX8550_GPIO_MC_24_BIT 16
64#define PNX8550_GPIO_MC_23_BIT 14
65#define PNX8550_GPIO_MC_22_BIT 12
66#define PNX8550_GPIO_MC_21_BIT 10
67#define PNX8550_GPIO_MC_20_BIT 8
68#define PNX8550_GPIO_MC_19_BIT 6
69#define PNX8550_GPIO_MC_18_BIT 4
70#define PNX8550_GPIO_MC_17_BIT 2
71#define PNX8550_GPIO_MC_16_BIT 0
72
73#define PNX8550_GPIO_MODE_PRIMOP 0x1
74#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
75#define PNX8550_GPIO_MODE_OPENDR 0x3
76
77// RESET module
78#define PNX8550_RST_CTL *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
79#define PNX8550_RST_CAUSE *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
80#define PNX8550_RST_EN_WATCHDOG *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
81
82#define PNX8550_RST_REL_MIPS_RST_N 0x8
83#define PNX8550_RST_DO_SW_RST 0x4
84#define PNX8550_RST_REL_SYS_RST_OUT 0x2
85#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
86#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/int.h b/arch/mips/include/asm/mach-pnx8550/int.h
deleted file mode 100644
index 0e0668b524f4..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/int.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Interrupt specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_INT_H
23#define __PNX8550_INT_H
24
25#define PNX8550_GIC_BASE 0xBBE3E000
26
27#define PNX8550_GIC_PRIMASK_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
28#define PNX8550_GIC_PRIMASK_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
29#define PNX8550_GIC_VECTOR_0 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
30#define PNX8550_GIC_VECTOR_1 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
31#define PNX8550_GIC_PEND_1_31 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
32#define PNX8550_GIC_PEND_32_63 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
33#define PNX8550_GIC_PEND_64_70 *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
34#define PNX8550_GIC_FEATURES *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
35#define PNX8550_GIC_REQ(x) *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
36#define PNX8550_GIC_MOD_ID *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
37
38// cp0 is two software + six hw exceptions
39#define PNX8550_INT_CP0_TOTINT 8
40#define PNX8550_INT_CP0_MIN 0
41#define PNX8550_INT_CP0_MAX (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
42
43#define MIPS_CPU_GIC_IRQ 2
44#define MIPS_CPU_TIMER_IRQ 7
45
46// GIC are 71 exceptions connected to cp0's first hardware exception
47#define PNX8550_INT_GIC_TOTINT 71
48#define PNX8550_INT_GIC_MIN (PNX8550_INT_CP0_MAX+1)
49#define PNX8550_INT_GIC_MAX (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
50
51#define PNX8550_INT_UNDEF (PNX8550_INT_GIC_MIN+0)
52#define PNX8550_INT_IPC_TARGET0_MIPS (PNX8550_INT_GIC_MIN+1)
53#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
54#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
55#define PNX8550_INT_RESERVED_4 (PNX8550_INT_GIC_MIN+4)
56#define PNX8550_INT_USB (PNX8550_INT_GIC_MIN+5)
57#define PNX8550_INT_GPIO_EQ1 (PNX8550_INT_GIC_MIN+6)
58#define PNX8550_INT_GPIO_EQ2 (PNX8550_INT_GIC_MIN+7)
59#define PNX8550_INT_GPIO_EQ3 (PNX8550_INT_GIC_MIN+8)
60#define PNX8550_INT_GPIO_EQ4 (PNX8550_INT_GIC_MIN+9)
61
62#define PNX8550_INT_GPIO_EQ5 (PNX8550_INT_GIC_MIN+10)
63#define PNX8550_INT_GPIO_EQ6 (PNX8550_INT_GIC_MIN+11)
64#define PNX8550_INT_RESERVED_12 (PNX8550_INT_GIC_MIN+12)
65#define PNX8550_INT_QVCP1 (PNX8550_INT_GIC_MIN+13)
66#define PNX8550_INT_QVCP2 (PNX8550_INT_GIC_MIN+14)
67#define PNX8550_INT_I2C1 (PNX8550_INT_GIC_MIN+15)
68#define PNX8550_INT_I2C2 (PNX8550_INT_GIC_MIN+16)
69#define PNX8550_INT_ISO_UART1 (PNX8550_INT_GIC_MIN+17)
70#define PNX8550_INT_ISO_UART2 (PNX8550_INT_GIC_MIN+18)
71#define PNX8550_INT_UART1 (PNX8550_INT_GIC_MIN+19)
72
73#define PNX8550_INT_UART2 (PNX8550_INT_GIC_MIN+20)
74#define PNX8550_INT_QNTR (PNX8550_INT_GIC_MIN+21)
75#define PNX8550_INT_RESERVED22 (PNX8550_INT_GIC_MIN+22)
76#define PNX8550_INT_T_DSC (PNX8550_INT_GIC_MIN+23)
77#define PNX8550_INT_M_DSC (PNX8550_INT_GIC_MIN+24)
78#define PNX8550_INT_RESERVED25 (PNX8550_INT_GIC_MIN+25)
79#define PNX8550_INT_2D_DRAW_ENG (PNX8550_INT_GIC_MIN+26)
80#define PNX8550_INT_MEM_BASED_SCALAR1 (PNX8550_INT_GIC_MIN+27)
81#define PNX8550_INT_VIDEO_MPEG (PNX8550_INT_GIC_MIN+28)
82#define PNX8550_INT_VIDEO_INPUT_P1 (PNX8550_INT_GIC_MIN+29)
83
84#define PNX8550_INT_VIDEO_INPUT_P2 (PNX8550_INT_GIC_MIN+30)
85#define PNX8550_INT_SPDI1 (PNX8550_INT_GIC_MIN+31)
86#define PNX8550_INT_SPDO (PNX8550_INT_GIC_MIN+32)
87#define PNX8550_INT_AUDIO_INPUT1 (PNX8550_INT_GIC_MIN+33)
88#define PNX8550_INT_AUDIO_OUTPUT1 (PNX8550_INT_GIC_MIN+34)
89#define PNX8550_INT_AUDIO_INPUT2 (PNX8550_INT_GIC_MIN+35)
90#define PNX8550_INT_AUDIO_OUTPUT2 (PNX8550_INT_GIC_MIN+36)
91#define PNX8550_INT_MEMBASED_SCALAR2 (PNX8550_INT_GIC_MIN+37)
92#define PNX8550_INT_VPK (PNX8550_INT_GIC_MIN+38)
93#define PNX8550_INT_MPEG1_MIPS (PNX8550_INT_GIC_MIN+39)
94
95#define PNX8550_INT_MPEG1_TM (PNX8550_INT_GIC_MIN+40)
96#define PNX8550_INT_MPEG2_MIPS (PNX8550_INT_GIC_MIN+41)
97#define PNX8550_INT_MPEG2_TM (PNX8550_INT_GIC_MIN+42)
98#define PNX8550_INT_TS_DMA (PNX8550_INT_GIC_MIN+43)
99#define PNX8550_INT_EDMA (PNX8550_INT_GIC_MIN+44)
100#define PNX8550_INT_TM_DEBUG1 (PNX8550_INT_GIC_MIN+45)
101#define PNX8550_INT_TM_DEBUG2 (PNX8550_INT_GIC_MIN+46)
102#define PNX8550_INT_PCI_INTA (PNX8550_INT_GIC_MIN+47)
103#define PNX8550_INT_CLOCK_MODULE (PNX8550_INT_GIC_MIN+48)
104#define PNX8550_INT_PCI_XIO_INTA_PCI (PNX8550_INT_GIC_MIN+49)
105
106#define PNX8550_INT_PCI_XIO_INTB_DMA (PNX8550_INT_GIC_MIN+50)
107#define PNX8550_INT_PCI_XIO_INTC_GPPM (PNX8550_INT_GIC_MIN+51)
108#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
109#define PNX8550_INT_DVD_CSS (PNX8550_INT_GIC_MIN+53)
110#define PNX8550_INT_VLD (PNX8550_INT_GIC_MIN+54)
111#define PNX8550_INT_GPIO_TSU_7_0 (PNX8550_INT_GIC_MIN+55)
112#define PNX8550_INT_GPIO_TSU_15_8 (PNX8550_INT_GIC_MIN+56)
113#define PNX8550_INT_GPIO_CTU_IR (PNX8550_INT_GIC_MIN+57)
114#define PNX8550_INT_GPIO0 (PNX8550_INT_GIC_MIN+58)
115#define PNX8550_INT_GPIO1 (PNX8550_INT_GIC_MIN+59)
116
117#define PNX8550_INT_GPIO2 (PNX8550_INT_GIC_MIN+60)
118#define PNX8550_INT_GPIO3 (PNX8550_INT_GIC_MIN+61)
119#define PNX8550_INT_GPIO4 (PNX8550_INT_GIC_MIN+62)
120#define PNX8550_INT_GPIO5 (PNX8550_INT_GIC_MIN+63)
121#define PNX8550_INT_GPIO6 (PNX8550_INT_GIC_MIN+64)
122#define PNX8550_INT_GPIO7 (PNX8550_INT_GIC_MIN+65)
123#define PNX8550_INT_PMAN_SECURITY (PNX8550_INT_GIC_MIN+66)
124#define PNX8550_INT_I2C3 (PNX8550_INT_GIC_MIN+67)
125#define PNX8550_INT_RESERVED_68 (PNX8550_INT_GIC_MIN+68)
126#define PNX8550_INT_SPDI2 (PNX8550_INT_GIC_MIN+69)
127
128#define PNX8550_INT_I2C4 (PNX8550_INT_GIC_MIN+70)
129
130// Timer are 3 exceptions connected to cp0's 7th hardware exception
131#define PNX8550_INT_TIMER_TOTINT 3
132#define PNX8550_INT_TIMER_MIN (PNX8550_INT_GIC_MAX+1)
133#define PNX8550_INT_TIMER_MAX (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
134
135#define PNX8550_INT_TIMER1 (PNX8550_INT_TIMER_MIN+0)
136#define PNX8550_INT_TIMER2 (PNX8550_INT_TIMER_MIN+1)
137#define PNX8550_INT_TIMER3 (PNX8550_INT_TIMER_MIN+2)
138#define PNX8550_INT_WATCHDOG PNX8550_INT_TIMER3
139
140#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h b/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
deleted file mode 100644
index bdde00c9199b..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/kernel-entry-init.h
+++ /dev/null
@@ -1,262 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005 Embedded Alley Solutions, Inc
7 */
8#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
9#define __ASM_MACH_KERNEL_ENTRY_INIT_H
10
11#include <asm/cacheops.h>
12#include <asm/addrspace.h>
13
14#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
15#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
16#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
17#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
18#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
19
20#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
21#define DCACHE_SET_COUNT 128 /* Data cache set count */
22
23#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
24#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
25
26 .macro kernel_entry_setup
27 .set push
28 .set noreorder
29 /*
30 * PNX8550 entry point, when running a non compressed
31 * kernel. When loading a zImage, the head.S code in
32 * arch/mips/zboot/pnx8550 will init the caches and,
33 * decompress the kernel, and branch to kernel_entry.
34 */
35cache_begin: li t0, (1<<28)
36 mtc0 t0, CP0_STATUS /* cp0 usable */
37 HAZARD_CP0
38
39 mtc0 zero, CP0_CAUSE
40 HAZARD_CP0
41
42
43 /* Set static virtual to phys address translation and TLB disabled */
44 mfc0 t0, CP0_CONFIG, 7
45 HAZARD_CP0
46
47 and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
48 mtc0 t0, CP0_CONFIG, 7
49 HAZARD_CP0
50
51 /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
52
53 init_icache
54 nop
55 init_dcache
56 nop
57
58 cachePr4450ICReset
59 nop
60
61 cachePr4450DCReset
62 nop
63
64 /* read ConfigPR into t0 */
65 mfc0 t0, CP0_CONFIG, 7
66 HAZARD_CP0
67
68 /* enable the TLB */
69 or t0, (1<<19)
70
71 /* disable the ICACHE: at least 10x slower */
72 /* or t0, (1<<26) */
73
74 /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
75 /* or t0, (1<<27) */
76
77 and t0, CO_CONFIGPR_VALID
78
79 /* enable TLB. */
80 mtc0 t0, CP0_CONFIG, 7
81 HAZARD_CP0
82cache_end:
83 /* Setup CMEM_0 to MMIO address space, 2MB */
84 lui t0, 0x1BE0
85 addi t0, t0, 0x3
86 mtc0 $8, $22, 4
87 nop
88
89 /* Setup CMEM_1, 128MB */
90 lui t0, 0x1000
91 addi t0, t0, 0xf
92 mtc0 $8, $22, 5
93 nop
94
95
96 /* Setup CMEM_2, 32MB */
97 lui t0, 0x1C00
98 addi t0, t0, 0xb
99 mtc0 $8, $22, 6
100 nop
101
102 /* Setup CMEM_3, 0MB */
103 lui t0, 0x0
104 addi t0, t0, 0x0
105 mtc0 $8, $22, 7
106 nop
107
108 /* Enable cache */
109 mfc0 t0, CP0_CONFIG
110 HAZARD_CP0
111 and t0, t0, 0xFFFFFFF8
112 or t0, t0, 3
113 mtc0 t0, CP0_CONFIG
114 HAZARD_CP0
115 .set pop
116 .endm
117
118 .macro init_icache
119 .set push
120 .set noreorder
121
122 /* Get Cache Configuration */
123 mfc0 t3, CP0_CONFIG, 1
124 HAZARD_CP0
125
126 /* get cache Line size */
127
128 srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
129 andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
130 beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
131 nop
132 addiu t0, t1, 1
133 ori t1, zero, 1
134 sllv t1, t1, t0
135
136 /* get max cache Index */
137 srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
138 andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
139 addiu t0, t2, 6
140 ori t2, zero, 1
141 sllv t2, t2, t0
142
143 /* get max cache way */
144 srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
145 andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
146 addiu t3, t3, 1
147
148 /* total no of cache lines */
149 multu t2, t3 /* max index * max way */
150 mflo t2
151 addiu t2, t2, -1
152
153 move t0, zero
154pr4450_next_instruction_cache_set:
155 cache Index_Invalidate_I, 0(t0)
156 addu t0, t0, t1 /* add bytes in a line */
157 bne t2, zero, pr4450_next_instruction_cache_set
158 addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
159pr4450_instr_cache_invalidated:
160 .set pop
161 .endm
162
163 .macro init_dcache
164 .set push
165 .set noreorder
166 move t1, zero
167
168 /* Store Tag Information */
169 mtc0 zero, CP0_TAGLO, 0
170 HAZARD_CP0
171
172 mtc0 zero, CP0_TAGHI, 0
173 HAZARD_CP0
174
175 /* Cache size is 16384 = 512 lines x 32 bytes per line */
176 or t2, zero, (128*4)-1 /* 512 lines */
177 /* Invalidate all lines */
1782:
179 cache Index_Store_Tag_D, 0(t1)
180 addiu t2, t2, -1
181 bne t2, zero, 2b
182 addiu t1, t1, 32 /* 32 bytes in a line */
183 .set pop
184 .endm
185
186 .macro cachePr4450ICReset
187 .set push
188 .set noreorder
189
190 /* Save CP0 status reg on entry; */
191 /* disable interrupts during cache reset */
192 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
193 HAZARD_CP0
194
195 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
196 HAZARD_CP0
197
198 or t1, zero, zero /* T1 = starting cache index (0) */
199 ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
200
201 icache_invd_loop:
202 /* 9 == register t1 */
203 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
204 (0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
205 .word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
206 (1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
207
208 addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
209 bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
210 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
211
212 /* Initialize the latches in the instruction cache tag */
213 /* that drive the way selection tri-state bus drivers, by doing a */
214 /* dummy load while the instruction cache is still disabled. */
215 /* TODO: Is this needed ? */
216 la t1, KSEG0 /* T1 = cached memory base address */
217 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
218
219 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
220 HAZARD_CP0
221 .set pop
222 .endm
223
224 .macro cachePr4450DCReset
225 .set push
226 .set noreorder
227 mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
228 HAZARD_CP0
229 mtc0 zero, CP0_STATUS /* disable CPU interrupts */
230 HAZARD_CP0
231
232 /* Writeback/invalidate entire data cache sets/ways/lines */
233 or t1, zero, zero /* T1 = starting cache index (0) */
234 ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
235
236 dcache_wbinvd_loop:
237 /* 9 == register t1 */
238 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
239 (0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
240 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
241 (1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
242 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
243 (2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
244 .word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
245 (3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
246
247 addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
248 bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
249 addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
250
251 /* Initialize the latches in the data cache tag that drive the way
252 selection tri-state bus drivers, by doing a dummy load while the
253 data cache is still in the disabled mode. TODO: Is this needed ? */
254 la t1, KSEG0 /* T1 = cached memory base address */
255 lw zero, 0x0000(t1) /* (dummy read of first memory word) */
256
257 mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
258 HAZARD_CP0
259 .set pop
260 .endm
261
262#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/arch/mips/include/asm/mach-pnx8550/nand.h b/arch/mips/include/asm/mach-pnx8550/nand.h
deleted file mode 100644
index aefbc514ab09..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/nand.h
+++ /dev/null
@@ -1,121 +0,0 @@
1#ifndef __PNX8550_NAND_H
2#define __PNX8550_NAND_H
3
4#define PNX8550_NAND_BASE_ADDR 0x10000000
5#define PNX8550_PCIXIO_BASE 0xBBE40000
6
7#define PNX8550_DMA_EXT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
8#define PNX8550_DMA_INT_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
9#define PNX8550_DMA_TRANS_SIZE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
10#define PNX8550_DMA_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
11#define PNX8550_XIO_SEL0 *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
12#define PNX8550_GPXIO_ADDR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
13#define PNX8550_GPXIO_WR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
14#define PNX8550_GPXIO_RD *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
15#define PNX8550_GPXIO_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
16#define PNX8550_XIO_FLASH_CTRL *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
17#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
18#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
19#define PNX8550_GPXIO_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
20#define PNX8550_DMA_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
21#define PNX8550_DMA_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
22#define PNX8550_DMA_INT_CLEAR *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
23
24#define PNX8550_XIO_SEL0_EN_16BIT 0x00800000
25#define PNX8550_XIO_SEL0_USE_ACK 0x00400000
26#define PNX8550_XIO_SEL0_REN_HIGH 0x00100000
27#define PNX8550_XIO_SEL0_REN_LOW 0x00040000
28#define PNX8550_XIO_SEL0_WEN_HIGH 0x00010000
29#define PNX8550_XIO_SEL0_WEN_LOW 0x00004000
30#define PNX8550_XIO_SEL0_WAIT 0x00000200
31#define PNX8550_XIO_SEL0_OFFSET 0x00000020
32#define PNX8550_XIO_SEL0_TYPE_68360 0x00000000
33#define PNX8550_XIO_SEL0_TYPE_NOR 0x00000008
34#define PNX8550_XIO_SEL0_TYPE_NAND 0x00000010
35#define PNX8550_XIO_SEL0_TYPE_IDE 0x00000018
36#define PNX8550_XIO_SEL0_SIZE_8MB 0x00000000
37#define PNX8550_XIO_SEL0_SIZE_16MB 0x00000002
38#define PNX8550_XIO_SEL0_SIZE_32MB 0x00000004
39#define PNX8550_XIO_SEL0_SIZE_64MB 0x00000006
40#define PNX8550_XIO_SEL0_ENAB 0x00000001
41
42#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT) | \
43 (PNX8550_XIO_SEL0_REN_HIGH*0)| \
44 (PNX8550_XIO_SEL0_REN_LOW*2) | \
45 (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
46 (PNX8550_XIO_SEL0_WEN_LOW*2) | \
47 (PNX8550_XIO_SEL0_WAIT*4) | \
48 (PNX8550_XIO_SEL0_OFFSET*0) | \
49 (PNX8550_XIO_SEL0_TYPE_NAND) | \
50 (PNX8550_XIO_SEL0_SIZE_32MB) | \
51 (PNX8550_XIO_SEL0_ENAB))
52
53#define PNX8550_GPXIO_PENDING 0x00000200
54#define PNX8550_GPXIO_DONE 0x00000100
55#define PNX8550_GPXIO_CLR_DONE 0x00000080
56#define PNX8550_GPXIO_INIT 0x00000040
57#define PNX8550_GPXIO_READ_CMD 0x00000010
58#define PNX8550_GPXIO_BEN 0x0000000F
59
60#define PNX8550_XIO_FLASH_64MB 0x00200000
61#define PNX8550_XIO_FLASH_INC_DATA 0x00100000
62#define PNX8550_XIO_FLASH_CMD_PH 0x000C0000
63#define PNX8550_XIO_FLASH_CMD_PH2 0x00080000
64#define PNX8550_XIO_FLASH_CMD_PH1 0x00040000
65#define PNX8550_XIO_FLASH_CMD_PH0 0x00000000
66#define PNX8550_XIO_FLASH_ADR_PH 0x00030000
67#define PNX8550_XIO_FLASH_ADR_PH3 0x00030000
68#define PNX8550_XIO_FLASH_ADR_PH2 0x00020000
69#define PNX8550_XIO_FLASH_ADR_PH1 0x00010000
70#define PNX8550_XIO_FLASH_ADR_PH0 0x00000000
71#define PNX8550_XIO_FLASH_CMD_B(x) ((x<<8) & 0x0000FF00)
72#define PNX8550_XIO_FLASH_CMD_A(x) (x & 0x000000FF)
73
74#define PNX8550_XIO_INT_ACK 0x00004000
75#define PNX8550_XIO_INT_COMPL 0x00002000
76#define PNX8550_XIO_INT_NONSUP 0x00000200
77#define PNX8550_XIO_INT_ABORT 0x00000004
78
79#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
80#define PNX8550_DMA_CTRL_SND2XIO 0x00000200
81#define PNX8550_DMA_CTRL_FIX_ADDR 0x00000100
82#define PNX8550_DMA_CTRL_BURST_8 0x00000000
83#define PNX8550_DMA_CTRL_BURST_16 0x00000020
84#define PNX8550_DMA_CTRL_BURST_32 0x00000040
85#define PNX8550_DMA_CTRL_BURST_64 0x00000060
86#define PNX8550_DMA_CTRL_BURST_128 0x00000080
87#define PNX8550_DMA_CTRL_BURST_256 0x000000A0
88#define PNX8550_DMA_CTRL_BURST_512 0x000000C0
89#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
90#define PNX8550_DMA_CTRL_INIT_DMA 0x00000010
91#define PNX8550_DMA_CTRL_CMD_TYPE 0x0000000F
92
93/* see PCI system arch, page 100 for the full list: */
94#define PNX8550_DMA_CTRL_PCI_CMD_READ 0x00000006
95#define PNX8550_DMA_CTRL_PCI_CMD_WRITE 0x00000007
96
97#define PNX8550_DMA_INT_STAT_ACK_DONE (1<<14)
98#define PNX8550_DMA_INT_STAT_DMA_DONE (1<<12)
99#define PNX8550_DMA_INT_STAT_DMA_ERR (1<<9)
100#define PNX8550_DMA_INT_STAT_PERR5 (1<<5)
101#define PNX8550_DMA_INT_STAT_PERR4 (1<<4)
102#define PNX8550_DMA_INT_STAT_M_ABORT (1<<2)
103#define PNX8550_DMA_INT_STAT_T_ABORT (1<<1)
104
105#define PNX8550_DMA_INT_EN_ACK_DONE (1<<14)
106#define PNX8550_DMA_INT_EN_DMA_DONE (1<<12)
107#define PNX8550_DMA_INT_EN_DMA_ERR (1<<9)
108#define PNX8550_DMA_INT_EN_PERR5 (1<<5)
109#define PNX8550_DMA_INT_EN_PERR4 (1<<4)
110#define PNX8550_DMA_INT_EN_M_ABORT (1<<2)
111#define PNX8550_DMA_INT_EN_T_ABORT (1<<1)
112
113#define PNX8550_DMA_INT_CLR_ACK_DONE (1<<14)
114#define PNX8550_DMA_INT_CLR_DMA_DONE (1<<12)
115#define PNX8550_DMA_INT_CLR_DMA_ERR (1<<9)
116#define PNX8550_DMA_INT_CLR_PERR5 (1<<5)
117#define PNX8550_DMA_INT_CLR_PERR4 (1<<4)
118#define PNX8550_DMA_INT_CLR_M_ABORT (1<<2)
119#define PNX8550_DMA_INT_CLR_T_ABORT (1<<1)
120
121#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/pci.h b/arch/mips/include/asm/mach-pnx8550/pci.h
deleted file mode 100644
index b921508d701b..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/pci.h
+++ /dev/null
@@ -1,185 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_PCI_H
23#define __PNX8550_PCI_H
24
25#include <linux/types.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/init.h>
29
30#define PCI_ACCESS_READ 0
31#define PCI_ACCESS_WRITE 1
32
33#define PCI_CMD_IOR 0x20
34#define PCI_CMD_IOW 0x30
35#define PCI_CMD_CONFIG_READ 0xa0
36#define PCI_CMD_CONFIG_WRITE 0xb0
37
38#define PCI_IO_TIMEOUT 1000
39#define PCI_IO_RETRY 5
40/* Timeout for IO and CFG accesses.
41 This is in 1/1024 th of a jiffie(=10ms)
42 i.e. approx 10us */
43#define PCI_IO_JIFFIES_TIMEOUT 40
44#define PCI_IO_JIFFIES_SHIFT 10
45
46#define PCI_BYTE_ENABLE_MASK 0x0000000f
47#define PCI_CFG_BUS_SHIFT 16
48#define PCI_CFG_FUNC_SHIFT 8
49#define PCI_CFG_REG_SHIFT 2
50
51#define PCI_BASE 0x1be00000
52#define PCI_SETUP 0x00040010
53#define PCI_DIS_REQGNT (1<<30)
54#define PCI_DIS_REQGNTA (1<<29)
55#define PCI_DIS_REQGNTB (1<<28)
56#define PCI_D2_SUPPORT (1<<27)
57#define PCI_D1_SUPPORT (1<<26)
58#define PCI_EN_TA (1<<24)
59#define PCI_EN_PCI2MMI (1<<23)
60#define PCI_EN_XIO (1<<22)
61#define PCI_BASE18_PREF (1<<21)
62#define SIZE_16M 0x3
63#define SIZE_32M 0x4
64#define SIZE_64M 0x5
65#define SIZE_128M 0x6
66#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
67#define PCI_SETUP_BASE18_EN (1<<17)
68#define PCI_SETUP_BASE14_PREF (1<<16)
69#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
70#define PCI_SETUP_BASE14_EN (1<<11)
71#define PCI_SETUP_BASE10_PREF (1<<10)
72#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
73#define PCI_SETUP_CFGMANAGE_EN (1<<1)
74#define PCI_SETUP_PCIARB_EN (1<<0)
75
76#define PCI_CTRL 0x040014
77#define PCI_SWPB_DCS_PCI (1<<16)
78#define PCI_SWPB_PCI_PCI (1<<15)
79#define PCI_SWPB_PCI_DCS (1<<14)
80#define PCI_REG_WR_POST (1<<13)
81#define PCI_XIO_WR_POST (1<<12)
82#define PCI_PCI2_WR_POST (1<<13)
83#define PCI_PCI1_WR_POST (1<<12)
84#define PCI_SERR_SEEN (1<<11)
85#define PCI_B10_SPEC_RD (1<<6)
86#define PCI_B14_SPEC_RD (1<<5)
87#define PCI_B18_SPEC_RD (1<<4)
88#define PCI_B10_NOSUBWORD (1<<3)
89#define PCI_B14_NOSUBWORD (1<<2)
90#define PCI_B18_NOSUBWORD (1<<1)
91#define PCI_RETRY_TMREN (1<<0)
92
93#define PCI_BASE1_LO 0x040018
94#define PCI_BASE1_HI 0x04001C
95#define PCI_BASE2_LO 0x040020
96#define PCI_BASE2_HI 0x040024
97#define PCI_RDLIFETIM 0x040028
98#define PCI_GPPM_ADDR 0x04002C
99#define PCI_GPPM_WDAT 0x040030
100#define PCI_GPPM_RDAT 0x040034
101#define PCI_GPPM_CTRL 0x040038
102#define GPPM_DONE (1<<10)
103#define INIT_PCI_CYCLE (1<<9)
104#define GPPM_CMD(X) (((X)&0xf)<<4)
105#define GPPM_BYTEEN(X) ((X)&0xf)
106#define PCI_UNLOCKREG 0x04003C
107#define UNLOCK_SSID(X) (((X)&0xff)<<8)
108#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
109#define UNLOCK_MAGIC 0xCA
110#define PCI_DEV_VEND_ID 0x040040
111#define DEVICE_ID(X) (((X)>>16)&0xffff)
112#define VENDOR_ID(X) (((X)&0xffff))
113#define PCI_CFG_CMDSTAT 0x040044
114#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
115#define PCI_CFG_COMMAND(X) ((X)&0xffff)
116#define PCI_CLASS_REV 0x040048
117#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
118#define PCI_REVID(X) ((X)&0xff)
119#define PCI_LAT_TMR 0x04004c
120#define PCI_BASE10 0x040050
121#define PCI_BASE14 0x040054
122#define PCI_BASE18 0x040058
123#define PCI_SUBSYS_ID 0x04006c
124#define PCI_CAP_PTR 0x040074
125#define PCI_CFG_MISC 0x04007c
126#define PCI_PMC 0x040080
127#define PCI_PWR_STATE 0x040084
128#define PCI_IO 0x040088
129#define PCI_SLVTUNING 0x04008C
130#define PCI_DMATUNING 0x040090
131#define PCI_DMAEADDR 0x040800
132#define PCI_DMAIADDR 0x040804
133#define PCI_DMALEN 0x040808
134#define PCI_DMACTRL 0x04080C
135#define PCI_XIOCTRL 0x040810
136#define PCI_SEL0PROF 0x040814
137#define PCI_SEL1PROF 0x040818
138#define PCI_SEL2PROF 0x04081C
139#define PCI_GPXIOADDR 0x040820
140#define PCI_NANDCTRLS 0x400830
141#define PCI_SEL3PROF 0x040834
142#define PCI_SEL4PROF 0x040838
143#define PCI_GPXIO_STAT 0x040FB0
144#define PCI_GPXIO_IMASK 0x040FB4
145#define PCI_GPXIO_ICLR 0x040FB8
146#define PCI_GPXIO_ISET 0x040FBC
147#define PCI_GPPM_STATUS 0x040FC0
148#define GPPM_DONE (1<<10)
149#define GPPM_ERR (1<<9)
150#define GPPM_MPAR_ERR (1<<8)
151#define GPPM_PAR_ERR (1<<7)
152#define GPPM_R_MABORT (1<<2)
153#define GPPM_R_TABORT (1<<1)
154#define PCI_GPPM_IMASK 0x040FC4
155#define PCI_GPPM_ICLR 0x040FC8
156#define PCI_GPPM_ISET 0x040FCC
157#define PCI_DMA_STATUS 0x040FD0
158#define PCI_DMA_IMASK 0x040FD4
159#define PCI_DMA_ICLR 0x040FD8
160#define PCI_DMA_ISET 0x040FDC
161#define PCI_ISTATUS 0x040FE0
162#define PCI_IMASK 0x040FE4
163#define PCI_ICLR 0x040FE8
164#define PCI_ISET 0x040FEC
165#define PCI_MOD_ID 0x040FFC
166
167/*
168 * PCI configuration cycle AD bus definition
169 */
170/* Type 0 */
171#define PCI_CFG_TYPE0_REG_SHF 0
172#define PCI_CFG_TYPE0_FUNC_SHF 8
173
174/* Type 1 */
175#define PCI_CFG_TYPE1_REG_SHF 0
176#define PCI_CFG_TYPE1_FUNC_SHF 8
177#define PCI_CFG_TYPE1_DEV_SHF 11
178#define PCI_CFG_TYPE1_BUS_SHF 16
179
180/*
181 * Ethernet device DP83816 definition
182 */
183#define DP83816_IRQ_ETHER 66
184
185#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/uart.h b/arch/mips/include/asm/mach-pnx8550/uart.h
deleted file mode 100644
index ad7608d44874..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/uart.h
+++ /dev/null
@@ -1,30 +0,0 @@
1#ifndef __IP3106_UART_H
2#define __IP3106_UART_H
3
4#include <int.h>
5
6/* early macros for kgdb use. fixme: clean this up */
7
8#define UART_BASE 0xbbe4a000 /* PNX8550 */
9
10#define PNX8550_UART_PORT0 (UART_BASE)
11#define PNX8550_UART_PORT1 (UART_BASE + 0x1000)
12
13#define PNX8550_UART_INT(x) (PNX8550_INT_GIC_MIN+19+x)
14#define IRQ_TO_UART(x) (x-PNX8550_INT_GIC_MIN-19)
15
16/* early macros needed for prom/kgdb */
17
18#define ip3106_lcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x000)
19#define ip3106_mcr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x004)
20#define ip3106_baud(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x008)
21#define ip3106_cfg(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x00C)
22#define ip3106_fifo(base, port) *(volatile u32 *)(base+(port*0x1000) + 0x028)
23#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
24#define ip3106_ien(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
25#define ip3106_iclr(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
26#define ip3106_iset(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
27#define ip3106_pd(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
28#define ip3106_mid(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
29
30#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/usb.h b/arch/mips/include/asm/mach-pnx8550/usb.h
deleted file mode 100644
index 483b7fc65d41..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/usb.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * USB specific definitions
5 *
6 * Author: source@mvista.com
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21
22#ifndef __PNX8550_USB_H
23#define __PNX8550_USB_H
24
25/*
26 * USB Host controller
27 */
28
29#define PNX8550_USB_OHCI_OP_BASE 0x1be48000
30#define PNX8550_USB_OHCI_OP_LEN 0x1000
31
32#endif
diff --git a/arch/mips/include/asm/mach-pnx8550/war.h b/arch/mips/include/asm/mach-pnx8550/war.h
deleted file mode 100644
index de8894c46686..000000000000
--- a/arch/mips/include/asm/mach-pnx8550/war.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
9#define __ASM_MIPS_MACH_PNX8550_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0
23
24#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index ce995d3d9440..998554f37a17 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_PCI_AR724X) += pci-ar724x.o
27# 27#
28obj-$(CONFIG_LASAT) += pci-lasat.o 28obj-$(CONFIG_LASAT) += pci-lasat.o
29obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 29obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o 30obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
32obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o 31obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
33obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c
deleted file mode 100644
index 96857ac63bf5..000000000000
--- a/arch/mips/pci/fixup-pnx8550.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * Philips PNX8550 pci fixups.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <asm/mach-pnx8550/pci.h>
26#include <asm/mach-pnx8550/int.h>
27
28
29#undef DEBUG
30#ifdef DEBUG
31#define DBG(x...) printk(x)
32#else
33#define DBG(x...)
34#endif
35
36extern char pnx8550_irq_tab[][5];
37
38void __init pcibios_fixup_resources(struct pci_dev *dev)
39{
40 /* no need to fixup IO resources */
41}
42
43void __init pcibios_fixup(void)
44{
45 /* nothing to do here */
46}
47
48int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
49{
50 return pnx8550_irq_tab[slot][pin];
51}
52
53/* Do platform specific device initialization at pci_enable_device() time */
54int pcibios_plat_dev_init(struct pci_dev *dev)
55{
56 return 0;
57}
diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c
deleted file mode 100644
index 1e6213fa7bdb..000000000000
--- a/arch/mips/pci/ops-pnx8550.c
+++ /dev/null
@@ -1,282 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * 2.6 port, Embedded Alley Solutions, Inc
6 *
7 * Based on:
8 * Author: source@mvista.com
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 */
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/vmalloc.h>
28#include <linux/delay.h>
29
30#include <asm/mach-pnx8550/pci.h>
31#include <asm/mach-pnx8550/glb.h>
32
33static inline void clear_status(void)
34{
35 unsigned long pci_stat;
36
37 pci_stat = inl(PCI_BASE | PCI_GPPM_STATUS);
38 outl(pci_stat, PCI_BASE | PCI_GPPM_ICLR);
39}
40
41static inline unsigned int
42calc_cfg_addr(struct pci_bus *bus, unsigned int devfn, int where)
43{
44 unsigned int addr;
45
46 addr = ((bus->number > 0) ? (((bus->number & 0xff) << PCI_CFG_BUS_SHIFT) | 1) : 0);
47 addr |= ((devfn & 0xff) << PCI_CFG_FUNC_SHIFT) | (where & 0xfc);
48
49 return addr;
50}
51
52static int
53config_access(unsigned int pci_cmd, struct pci_bus *bus, unsigned int devfn, int where, unsigned int pci_mode, unsigned int *val)
54{
55 unsigned int flags;
56 unsigned long loops = 0;
57 unsigned long ioaddr = calc_cfg_addr(bus, devfn, where);
58
59 local_irq_save(flags);
60 /*Clear pending interrupt status */
61 if (inl(PCI_BASE | PCI_GPPM_STATUS)) {
62 clear_status();
63 while (!(inl(PCI_BASE | PCI_GPPM_STATUS) == 0)) ;
64 }
65
66 outl(ioaddr, PCI_BASE | PCI_GPPM_ADDR);
67
68 if ((pci_cmd == PCI_CMD_IOW) || (pci_cmd == PCI_CMD_CONFIG_WRITE))
69 outl(*val, PCI_BASE | PCI_GPPM_WDAT);
70
71 outl(INIT_PCI_CYCLE | pci_cmd | (pci_mode & PCI_BYTE_ENABLE_MASK),
72 PCI_BASE | PCI_GPPM_CTRL);
73
74 loops =
75 ((loops_per_jiffy *
76 PCI_IO_JIFFIES_TIMEOUT) >> (PCI_IO_JIFFIES_SHIFT));
77 while (1) {
78 if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_DONE) {
79 if ((pci_cmd == PCI_CMD_IOR) ||
80 (pci_cmd == PCI_CMD_CONFIG_READ))
81 *val = inl(PCI_BASE | PCI_GPPM_RDAT);
82 clear_status();
83 local_irq_restore(flags);
84 return PCIBIOS_SUCCESSFUL;
85 } else if (inl(PCI_BASE | PCI_GPPM_STATUS) & GPPM_R_MABORT) {
86 break;
87 }
88
89 loops--;
90 if (loops == 0) {
91 printk("%s : Arbiter Locked.\n", __func__);
92 }
93 }
94
95 clear_status();
96 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_IOW)) {
97 printk("%s timeout (GPPM_CTRL=%X) ioaddr %lX pci_cmd %X\n",
98 __func__, inl(PCI_BASE | PCI_GPPM_CTRL), ioaddr,
99 pci_cmd);
100 }
101
102 if ((pci_cmd == PCI_CMD_IOR) || (pci_cmd == PCI_CMD_CONFIG_READ))
103 *val = 0xffffffff;
104 local_irq_restore(flags);
105 return PCIBIOS_DEVICE_NOT_FOUND;
106}
107
108/*
109 * We can't address 8 and 16 bit words directly. Instead we have to
110 * read/write a 32bit word and mask/modify the data we actually want.
111 */
112static int
113read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
114{
115 unsigned int data = 0;
116 int err;
117
118 if (bus == NULL)
119 return -1;
120
121 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data);
122 switch (where & 0x03) {
123 case 0:
124 *val = (unsigned char)(data & 0x000000ff);
125 break;
126 case 1:
127 *val = (unsigned char)((data & 0x0000ff00) >> 8);
128 break;
129 case 2:
130 *val = (unsigned char)((data & 0x00ff0000) >> 16);
131 break;
132 case 3:
133 *val = (unsigned char)((data & 0xff000000) >> 24);
134 break;
135 }
136
137 return err;
138}
139
140static int
141read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
142{
143 unsigned int data = 0;
144 int err;
145
146 if (bus == NULL)
147 return -1;
148
149 if (where & 0x01)
150 return PCIBIOS_BAD_REGISTER_NUMBER;
151
152 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(3 << (where & 3)), &data);
153 switch (where & 0x02) {
154 case 0:
155 *val = (unsigned short)(data & 0x0000ffff);
156 break;
157 case 2:
158 *val = (unsigned short)((data & 0xffff0000) >> 16);
159 break;
160 }
161
162 return err;
163}
164
165static int
166read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
167{
168 int err;
169 if (bus == NULL)
170 return -1;
171
172 if (where & 0x03)
173 return PCIBIOS_BAD_REGISTER_NUMBER;
174
175 err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, 0, val);
176
177 return err;
178}
179
180static int
181write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
182{
183 unsigned int data = (unsigned int)val;
184 int err;
185
186 if (bus == NULL)
187 return -1;
188
189 switch (where & 0x03) {
190 case 1:
191 data = (data << 8);
192 break;
193 case 2:
194 data = (data << 16);
195 break;
196 case 3:
197 data = (data << 24);
198 break;
199 default:
200 break;
201 }
202
203 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(1 << (where & 3)), &data);
204
205 return err;
206}
207
208static int
209write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
210{
211 unsigned int data = (unsigned int)val;
212 int err;
213
214 if (bus == NULL)
215 return -1;
216
217 if (where & 0x01)
218 return PCIBIOS_BAD_REGISTER_NUMBER;
219
220 switch (where & 0x02) {
221 case 2:
222 data = (data << 16);
223 break;
224 default:
225 break;
226 }
227 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, ~(3 << (where & 3)), &data);
228
229 return err;
230}
231
232static int
233write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
234{
235 int err;
236 if (bus == NULL)
237 return -1;
238
239 if (where & 0x03)
240 return PCIBIOS_BAD_REGISTER_NUMBER;
241
242 err = config_access(PCI_CMD_CONFIG_WRITE, bus, devfn, where, 0, &val);
243
244 return err;
245}
246
247static int config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
248{
249 switch (size) {
250 case 1: {
251 u8 _val;
252 int rc = read_config_byte(bus, devfn, where, &_val);
253 *val = _val;
254 return rc;
255 }
256 case 2: {
257 u16 _val;
258 int rc = read_config_word(bus, devfn, where, &_val);
259 *val = _val;
260 return rc;
261 }
262 default:
263 return read_config_dword(bus, devfn, where, val);
264 }
265}
266
267static int config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
268{
269 switch (size) {
270 case 1:
271 return write_config_byte(bus, devfn, where, (u8) val);
272 case 2:
273 return write_config_word(bus, devfn, where, (u16) val);
274 default:
275 return write_config_dword(bus, devfn, where, val);
276 }
277}
278
279struct pci_ops pnx8550_pci_ops = {
280 config_read,
281 config_write
282};
diff --git a/arch/mips/pnx8550/Makefile b/arch/mips/pnx8550/Makefile
deleted file mode 100644
index 3f7e8561437b..000000000000
--- a/arch/mips/pnx8550/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1obj-$(CONFIG_SOC_PNX8550) += common/
2obj-$(CONFIG_PNX8550_JBS) += jbs/
3obj-$(CONFIG_PNX8550_STB810) += stb810/
diff --git a/arch/mips/pnx8550/Platform b/arch/mips/pnx8550/Platform
deleted file mode 100644
index 0e7fbde768d5..000000000000
--- a/arch/mips/pnx8550/Platform
+++ /dev/null
@@ -1,7 +0,0 @@
1platform-$(CONFIG_SOC_PNX8550) += pnx8550/
2
3cflags-$(CONFIG_SOC_PNX8550) += \
4 -I$(srctree)/arch/mips/include/asm/mach-pnx8550
5
6load-$(CONFIG_PNX8550_JBS) += 0xffffffff80060000
7load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000
diff --git a/arch/mips/pnx8550/common/Makefile b/arch/mips/pnx8550/common/Makefile
deleted file mode 100644
index f8ce695dc54f..000000000000
--- a/arch/mips/pnx8550/common/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
1#
2# Per Hallsmark, per.hallsmark@mvista.com
3#
4# ########################################################################
5#
6# This program is free software; you can distribute it and/or modify it
7# under the terms of the GNU General Public License (Version 2) as
8# published by the Free Software Foundation.
9#
10# This program is distributed in the hope it will be useful, but WITHOUT
11# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13# for more details.
14#
15# You should have received a copy of the GNU General Public License along
16# with this program; if not, write to the Free Software Foundation, Inc.,
17# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18#
19# #######################################################################
20#
21# Makefile for the PNX8550 specific kernel interface routines
22# under Linux.
23#
24
25obj-y := setup.o prom.o int.o reset.o time.o proc.o platform.o
26obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
deleted file mode 100644
index ec684b8c3f79..000000000000
--- a/arch/mips/pnx8550/common/int.c
+++ /dev/null
@@ -1,236 +0,0 @@
1/*
2 *
3 * Copyright (C) 2005 Embedded Alley Solutions, Inc
4 * Ported to 2.6.
5 *
6 * Per Hallsmark, per.hallsmark@mvista.com
7 * Copyright (C) 2000, 2001 MIPS Technologies, Inc.
8 * Copyright (C) 2001 Ralf Baechle
9 *
10 * Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 * for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 *
25 */
26#include <linux/compiler.h>
27#include <linux/init.h>
28#include <linux/irq.h>
29#include <linux/sched.h>
30#include <linux/interrupt.h>
31#include <linux/kernel_stat.h>
32#include <linux/random.h>
33#include <linux/module.h>
34
35#include <asm/io.h>
36#include <int.h>
37#include <uart.h>
38
39/* default prio for interrupts */
40/* first one is a no-no so therefore always prio 0 (disabled) */
41static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
42 0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9
43 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19
44 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29
45 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39
46 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49
47 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59
48 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69
49 1 // 70
50};
51
52static void hw0_irqdispatch(int irq)
53{
54 /* find out which interrupt */
55 irq = PNX8550_GIC_VECTOR_0 >> 3;
56
57 if (irq == 0) {
58 printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
59 return;
60 }
61 do_IRQ(PNX8550_INT_GIC_MIN + irq);
62}
63
64
65static void timer_irqdispatch(int irq)
66{
67 irq = (0x01c0 & read_c0_config7()) >> 6;
68
69 if (unlikely(irq == 0)) {
70 printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
71 return;
72 }
73
74 if (irq & 0x1)
75 do_IRQ(PNX8550_INT_TIMER1);
76 if (irq & 0x2)
77 do_IRQ(PNX8550_INT_TIMER2);
78 if (irq & 0x4)
79 do_IRQ(PNX8550_INT_TIMER3);
80}
81
82asmlinkage void plat_irq_dispatch(void)
83{
84 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
85
86 if (pending & STATUSF_IP2)
87 hw0_irqdispatch(2);
88 else if (pending & STATUSF_IP7) {
89 if (read_c0_config7() & 0x01c0)
90 timer_irqdispatch(7);
91 } else
92 spurious_interrupt();
93}
94
95static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
96{
97 unsigned long status = read_c0_status();
98
99 status &= ~((clr_mask & 0xFF) << 8);
100 status |= (set_mask & 0xFF) << 8;
101
102 write_c0_status(status);
103}
104
105static inline void mask_gic_int(unsigned int irq_nr)
106{
107 /* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
108 PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
109}
110
111static inline void unmask_gic_int(unsigned int irq_nr)
112{
113 /* set prio mask to lower four bits and enable interrupt */
114 PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
115}
116
117static inline void mask_irq(struct irq_data *d)
118{
119 unsigned int irq_nr = d->irq;
120
121 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
122 modify_cp0_intmask(1 << irq_nr, 0);
123 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
124 (irq_nr <= PNX8550_INT_GIC_MAX)) {
125 mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
126 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
127 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
128 modify_cp0_intmask(1 << 7, 0);
129 } else {
130 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
131 }
132}
133
134static inline void unmask_irq(struct irq_data *d)
135{
136 unsigned int irq_nr = d->irq;
137
138 if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
139 modify_cp0_intmask(0, 1 << irq_nr);
140 } else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
141 (irq_nr <= PNX8550_INT_GIC_MAX)) {
142 unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
143 } else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
144 (irq_nr <= PNX8550_INT_TIMER_MAX)) {
145 modify_cp0_intmask(0, 1 << 7);
146 } else {
147 printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
148 }
149}
150
151int pnx8550_set_gic_priority(int irq, int priority)
152{
153 int gic_irq = irq-PNX8550_INT_GIC_MIN;
154 int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
155
156 gic_prio[gic_irq] = priority;
157 PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
158
159 return prev_priority;
160}
161
162static struct irq_chip level_irq_type = {
163 .name = "PNX Level IRQ",
164 .irq_mask = mask_irq,
165 .irq_unmask = unmask_irq,
166};
167
168static struct irqaction gic_action = {
169 .handler = no_action,
170 .flags = IRQF_NO_THREAD,
171 .name = "GIC",
172};
173
174static struct irqaction timer_action = {
175 .handler = no_action,
176 .flags = IRQF_TIMER,
177 .name = "Timer",
178};
179
180void __init arch_init_irq(void)
181{
182 int i;
183 int configPR;
184
185 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
186 irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
187
188 /* init of GIC/IPC interrupts */
189 /* should be done before cp0 since cp0 init enables the GIC int */
190 for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
191 int gic_int_line = i - PNX8550_INT_GIC_MIN;
192 if (gic_int_line == 0 )
193 continue; // don't fiddle with int 0
194 /*
195 * enable change of TARGET, ENABLE and ACTIVE_LOW bits
196 * set TARGET 0 to route through hw0 interrupt
197 * set ACTIVE_LOW 0 active high (correct?)
198 *
199 * We really should setup an interrupt description table
200 * to do this nicely.
201 * Note, PCI INTA is active low on the bus, but inverted
202 * in the GIC, so to us it's active high.
203 */
204 PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
205
206 /* mask/priority is still 0 so we will not get any
207 * interrupts until it is unmasked */
208
209 irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
210 }
211
212 /* Priority level 0 */
213 PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
214
215 /* Set int vector table address */
216 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
217
218 irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
219 handle_level_irq);
220 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
221
222 /* init of Timer interrupts */
223 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
224 irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
225
226 /* Stop Timer 1-3 */
227 configPR = read_c0_config7();
228 configPR |= 0x00000038;
229 write_c0_config7(configPR);
230
231 irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
232 handle_level_irq);
233 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
234}
235
236EXPORT_SYMBOL(pnx8550_set_gic_priority);
diff --git a/arch/mips/pnx8550/common/pci.c b/arch/mips/pnx8550/common/pci.c
deleted file mode 100644
index 98e86ddb86cc..000000000000
--- a/arch/mips/pnx8550/common/pci.c
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 *
5 * Author: source@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/types.h>
21#include <linux/pci.h>
22#include <linux/kernel.h>
23#include <linux/init.h>
24
25#include <pci.h>
26#include <glb.h>
27#include <nand.h>
28
29static struct resource pci_io_resource = {
30 .start = PNX8550_PCIIO + 0x1000, /* reserve regacy I/O space */
31 .end = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
32 .name = "pci IO space",
33 .flags = IORESOURCE_IO
34};
35
36static struct resource pci_mem_resource = {
37 .start = PNX8550_PCIMEM,
38 .end = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
39 .name = "pci memory space",
40 .flags = IORESOURCE_MEM
41};
42
43extern struct pci_ops pnx8550_pci_ops;
44
45static struct pci_controller pnx8550_controller = {
46 .pci_ops = &pnx8550_pci_ops,
47 .io_map_base = PNX8550_PORT_BASE,
48 .io_resource = &pci_io_resource,
49 .mem_resource = &pci_mem_resource,
50};
51
52/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
53static inline unsigned long get_system_mem_size(void)
54{
55 /* Read IP2031_RANK0_ADDR_LO */
56 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
57 /* Read IP2031_RANK1_ADDR_HI */
58 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
59
60 return dram_r1_hi - dram_r0_lo + 1;
61}
62
63static int __init pnx8550_pci_setup(void)
64{
65 int pci_mem_code;
66 int mem_size = get_system_mem_size() >> 20;
67
68 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
69 Bit 1:Enable DAC Powerdown
70 -> 0:DACs are enabled and are working normally
71 1:DACs are powerdown
72 Bit 0:Enable of PCI inta output
73 -> 0 = Disable PCI inta output
74 1 = Enable PCI inta output
75 */
76 PNX8550_GLB2_ENAB_INTA_O = 0;
77
78 /* Calc the PCI mem size code */
79 if (mem_size >= 128)
80 pci_mem_code = SIZE_128M;
81 else if (mem_size >= 64)
82 pci_mem_code = SIZE_64M;
83 else if (mem_size >= 32)
84 pci_mem_code = SIZE_32M;
85 else
86 pci_mem_code = SIZE_16M;
87
88 /* Set PCI_XIO registers */
89 outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
90 outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
91 outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
92 outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
93
94 /* Send memory transaction via PCI_BASE2 */
95 outl(0x00000001, PCI_BASE | PCI_IO);
96
97 /* Unlock the setup register */
98 outl(0xca, PCI_BASE | PCI_UNLOCKREG);
99
100 /*
101 * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
102 * to work, and in order for bus_to_baddr to work without any
103 * hacks.
104 */
105 outl(0x00000000, PCI_BASE | PCI_BASE10);
106
107 /*
108 *These two bars are set by default or the boot code.
109 * However, it's safer to set them here so we're not boot
110 * code dependent.
111 */
112 outl(0x1be00000, PCI_BASE | PCI_BASE14); /* PNX MMIO */
113 outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18); /* XIO */
114
115 outl(PCI_EN_TA |
116 PCI_EN_PCI2MMI |
117 PCI_EN_XIO |
118 PCI_SETUP_BASE18_SIZE(SIZE_32M) |
119 PCI_SETUP_BASE18_EN |
120 PCI_SETUP_BASE14_EN |
121 PCI_SETUP_BASE10_PREF |
122 PCI_SETUP_BASE10_SIZE(pci_mem_code) |
123 PCI_SETUP_CFGMANAGE_EN |
124 PCI_SETUP_PCIARB_EN,
125 PCI_BASE |
126 PCI_SETUP); /* PCI_SETUP */
127 outl(0x00000000, PCI_BASE | PCI_CTRL); /* PCI_CONTROL */
128
129 register_pci_controller(&pnx8550_controller);
130
131 return 0;
132}
133
134arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/pnx8550/common/platform.c b/arch/mips/pnx8550/common/platform.c
deleted file mode 100644
index 0a8faeaa7b70..000000000000
--- a/arch/mips/pnx8550/common/platform.c
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * Platform device support for NXP PNX8550 SoCs
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * Based on arch/mips/au1000/common/platform.c
7 * Platform device support for Au1x00 SoCs.
8 *
9 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15#include <linux/device.h>
16#include <linux/dma-mapping.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/resource.h>
20#include <linux/serial.h>
21#include <linux/serial_pnx8xxx.h>
22#include <linux/platform_device.h>
23#include <linux/usb/ohci_pdriver.h>
24
25#include <int.h>
26#include <usb.h>
27#include <uart.h>
28
29static struct resource pnx8550_usb_ohci_resources[] = {
30 [0] = {
31 .start = PNX8550_USB_OHCI_OP_BASE,
32 .end = PNX8550_USB_OHCI_OP_BASE +
33 PNX8550_USB_OHCI_OP_LEN,
34 .flags = IORESOURCE_MEM,
35 },
36 [1] = {
37 .start = PNX8550_INT_USB,
38 .end = PNX8550_INT_USB,
39 .flags = IORESOURCE_IRQ,
40 },
41};
42
43static struct resource pnx8550_uart_resources[] = {
44 [0] = {
45 .start = PNX8550_UART_PORT0,
46 .end = PNX8550_UART_PORT0 + 0xfff,
47 .flags = IORESOURCE_MEM,
48 },
49 [1] = {
50 .start = PNX8550_UART_INT(0),
51 .end = PNX8550_UART_INT(0),
52 .flags = IORESOURCE_IRQ,
53 },
54 [2] = {
55 .start = PNX8550_UART_PORT1,
56 .end = PNX8550_UART_PORT1 + 0xfff,
57 .flags = IORESOURCE_MEM,
58 },
59 [3] = {
60 .start = PNX8550_UART_INT(1),
61 .end = PNX8550_UART_INT(1),
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66struct pnx8xxx_port pnx8xxx_ports[] = {
67 [0] = {
68 .port = {
69 .type = PORT_PNX8XXX,
70 .iotype = UPIO_MEM,
71 .membase = (void __iomem *)PNX8550_UART_PORT0,
72 .mapbase = PNX8550_UART_PORT0,
73 .irq = PNX8550_UART_INT(0),
74 .uartclk = 3692300,
75 .fifosize = 16,
76 .flags = UPF_BOOT_AUTOCONF,
77 .line = 0,
78 },
79 },
80 [1] = {
81 .port = {
82 .type = PORT_PNX8XXX,
83 .iotype = UPIO_MEM,
84 .membase = (void __iomem *)PNX8550_UART_PORT1,
85 .mapbase = PNX8550_UART_PORT1,
86 .irq = PNX8550_UART_INT(1),
87 .uartclk = 3692300,
88 .fifosize = 16,
89 .flags = UPF_BOOT_AUTOCONF,
90 .line = 1,
91 },
92 },
93};
94
95/* The dmamask must be set for OHCI to work */
96static u64 ohci_dmamask = DMA_BIT_MASK(32);
97
98static u64 uart_dmamask = DMA_BIT_MASK(32);
99
100static int pnx8550_usb_ohci_power_on(struct platform_device *pdev)
101{
102 /*
103 * Set register CLK48CTL to enable and 48MHz
104 */
105 outl(0x00000003, PCI_BASE | 0x0004770c);
106
107 /*
108 * Set register CLK12CTL to enable and 48MHz
109 */
110 outl(0x00000003, PCI_BASE | 0x00047710);
111
112 udelay(100);
113
114 return 0;
115}
116
117static void pnx8550_usb_ohci_power_off(struct platform_device *pdev)
118{
119 udelay(10);
120}
121
122static struct usb_ohci_pdata pnx8550_usb_ohci_pdata = {
123 .power_on = pnx8550_usb_ohci_power_on,
124 .power_off = pnx8550_usb_ohci_power_off,
125};
126
127static struct platform_device pnx8550_usb_ohci_device = {
128 .name = "ohci-platform",
129 .id = -1,
130 .dev = {
131 .dma_mask = &ohci_dmamask,
132 .coherent_dma_mask = DMA_BIT_MASK(32),
133 .platform_data = &pnx8550_usb_ohci_pdata,
134 },
135 .num_resources = ARRAY_SIZE(pnx8550_usb_ohci_resources),
136 .resource = pnx8550_usb_ohci_resources,
137};
138
139static struct platform_device pnx8550_uart_device = {
140 .name = "pnx8xxx-uart",
141 .id = -1,
142 .dev = {
143 .dma_mask = &uart_dmamask,
144 .coherent_dma_mask = DMA_BIT_MASK(32),
145 .platform_data = pnx8xxx_ports,
146 },
147 .num_resources = ARRAY_SIZE(pnx8550_uart_resources),
148 .resource = pnx8550_uart_resources,
149};
150
151static struct platform_device *pnx8550_platform_devices[] __initdata = {
152 &pnx8550_usb_ohci_device,
153 &pnx8550_uart_device,
154};
155
156static int __init pnx8550_platform_init(void)
157{
158 return platform_add_devices(pnx8550_platform_devices,
159 ARRAY_SIZE(pnx8550_platform_devices));
160}
161
162arch_initcall(pnx8550_platform_init);
diff --git a/arch/mips/pnx8550/common/proc.c b/arch/mips/pnx8550/common/proc.c
deleted file mode 100644
index 3bba5ec828e8..000000000000
--- a/arch/mips/pnx8550/common/proc.c
+++ /dev/null
@@ -1,110 +0,0 @@
1/*
2 * This program is free software; you can distribute it and/or modify it
3 * under the terms of the GNU General Public License (Version 2) as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
9 * for more details.
10 *
11 * You should have received a copy of the GNU General Public License along
12 * with this program; if not, write to the Free Software Foundation, Inc.,
13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14 */
15#include <linux/init.h>
16#include <linux/proc_fs.h>
17#include <linux/irq.h>
18#include <linux/sched.h>
19#include <linux/interrupt.h>
20#include <linux/kernel_stat.h>
21#include <linux/random.h>
22
23#include <asm/io.h>
24#include <int.h>
25#include <uart.h>
26
27
28static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
29{
30 int len = 0;
31 int configPR = read_c0_config7();
32
33 if (offset==0) {
34 len += sprintf(&page[len], "Timer: count, compare, tc, status\n");
35 len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n",
36 read_c0_count(), read_c0_compare(),
37 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
38 len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n",
39 read_c0_count2(), read_c0_compare2(),
40 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
41 len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n",
42 read_c0_count3(), read_c0_compare3(),
43 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
44 }
45
46 return len;
47}
48
49static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
50{
51 int len = 0;
52
53 if (offset==0) {
54 len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1());
55 len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2());
56 len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3());
57 len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7());
58 len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status());
59 len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause());
60 len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count());
61 len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2());
62 len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3());
63 len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare());
64 len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2());
65 len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3());
66 }
67
68 return len;
69}
70
71static struct proc_dir_entry* pnx8550_dir;
72static struct proc_dir_entry* pnx8550_timers;
73static struct proc_dir_entry* pnx8550_registers;
74
75static int pnx8550_proc_init( void )
76{
77
78 // Create /proc/pnx8550
79 pnx8550_dir = proc_mkdir("pnx8550", NULL);
80 if (!pnx8550_dir) {
81 printk(KERN_ERR "Can't create pnx8550 proc dir\n");
82 return -1;
83 }
84
85 // Create /proc/pnx8550/timers
86 pnx8550_timers = create_proc_read_entry(
87 "timers",
88 0,
89 pnx8550_dir,
90 pnx8550_timers_read,
91 NULL);
92
93 if (!pnx8550_timers)
94 printk(KERN_ERR "Can't create pnx8550 timers proc file\n");
95
96 // Create /proc/pnx8550/registers
97 pnx8550_registers = create_proc_read_entry(
98 "registers",
99 0,
100 pnx8550_dir,
101 pnx8550_registers_read,
102 NULL);
103
104 if (!pnx8550_registers)
105 printk(KERN_ERR "Can't create pnx8550 registers proc file\n");
106
107 return 0;
108}
109
110__initcall(pnx8550_proc_init);
diff --git a/arch/mips/pnx8550/common/prom.c b/arch/mips/pnx8550/common/prom.c
deleted file mode 100644
index 49639e8120d8..000000000000
--- a/arch/mips/pnx8550/common/prom.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/*
2 *
3 * Per Hallsmark, per.hallsmark@mvista.com
4 *
5 * Based on jmr3927/common/prom.c
6 *
7 * 2004 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/string.h>
16#include <linux/serial_pnx8xxx.h>
17
18#include <asm/bootinfo.h>
19#include <uart.h>
20
21/* #define DEBUG_CMDLINE */
22
23extern int prom_argc;
24extern char **prom_argv, **prom_envp;
25
26typedef struct
27{
28 char *name;
29/* char *val; */
30}t_env_var;
31
32
33char * __init prom_getcmdline(void)
34{
35 return &(arcs_cmdline[0]);
36}
37
38void __init prom_init_cmdline(void)
39{
40 int i;
41
42 arcs_cmdline[0] = '\0';
43 for (i = 0; i < prom_argc; i++) {
44 strcat(arcs_cmdline, prom_argv[i]);
45 strcat(arcs_cmdline, " ");
46 }
47}
48
49char *prom_getenv(char *envname)
50{
51 /*
52 * Return a pointer to the given environment variable.
53 * Environment variables are stored in the form of "memsize=64".
54 */
55
56 t_env_var *env = (t_env_var *)prom_envp;
57 int i;
58
59 i = strlen(envname);
60
61 while(env->name) {
62 if(strncmp(envname, env->name, i) == 0) {
63 return(env->name + strlen(envname) + 1);
64 }
65 env++;
66 }
67 return(NULL);
68}
69
70inline unsigned char str2hexnum(unsigned char c)
71{
72 if(c >= '0' && c <= '9')
73 return c - '0';
74 if(c >= 'a' && c <= 'f')
75 return c - 'a' + 10;
76 if(c >= 'A' && c <= 'F')
77 return c - 'A' + 10;
78 return 0; /* foo */
79}
80
81inline void str2eaddr(unsigned char *ea, unsigned char *str)
82{
83 int i;
84
85 for(i = 0; i < 6; i++) {
86 unsigned char num;
87
88 if((*str == '.') || (*str == ':'))
89 str++;
90 num = str2hexnum(*str++) << 4;
91 num |= (str2hexnum(*str++));
92 ea[i] = num;
93 }
94}
95
96int get_ethernet_addr(char *ethernet_addr)
97{
98 char *ethaddr_str;
99
100 ethaddr_str = prom_getenv("ethaddr");
101 if (!ethaddr_str) {
102 printk("ethaddr not set in boot prom\n");
103 return -1;
104 }
105 str2eaddr(ethernet_addr, ethaddr_str);
106 return 0;
107}
108
109void __init prom_free_prom_memory(void)
110{
111}
112
113extern int pnx8550_console_port;
114
115/* used by early printk */
116void prom_putchar(char c)
117{
118 if (pnx8550_console_port != -1) {
119 /* Wait until FIFO not full */
120 while( ((ip3106_fifo(UART_BASE, pnx8550_console_port) & PNX8XXX_UART_FIFO_TXFIFO) >> 16) >= 16)
121 ;
122 /* Send one char */
123 ip3106_fifo(UART_BASE, pnx8550_console_port) = c;
124 }
125}
126
127EXPORT_SYMBOL(get_ethernet_addr);
128EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/pnx8550/common/reset.c b/arch/mips/pnx8550/common/reset.c
deleted file mode 100644
index e7a12ff304b9..000000000000
--- a/arch/mips/pnx8550/common/reset.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*.
2 *
3 * ########################################################################
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * ########################################################################
19 *
20 * Reset the PNX8550 board.
21 *
22 */
23#include <linux/kernel.h>
24
25#include <asm/processor.h>
26#include <asm/reboot.h>
27#include <glb.h>
28
29void pnx8550_machine_restart(char *command)
30{
31 PNX8550_RST_CTL = PNX8550_RST_DO_SW_RST;
32}
33
34void pnx8550_machine_halt(void)
35{
36 while (1) {
37 if (cpu_wait)
38 cpu_wait();
39 }
40}
diff --git a/arch/mips/pnx8550/common/setup.c b/arch/mips/pnx8550/common/setup.c
deleted file mode 100644
index fccd6b0c6d3f..000000000000
--- a/arch/mips/pnx8550/common/setup.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 *
3 * 2.6 port, Embedded Alley Solutions, Inc
4 *
5 * Based on Per Hallsmark, per.hallsmark@mvista.com
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 */
20#include <linux/init.h>
21#include <linux/sched.h>
22#include <linux/ioport.h>
23#include <linux/irq.h>
24#include <linux/mm.h>
25#include <linux/delay.h>
26#include <linux/interrupt.h>
27#include <linux/serial_pnx8xxx.h>
28#include <linux/pm.h>
29
30#include <asm/cpu.h>
31#include <asm/bootinfo.h>
32#include <asm/irq.h>
33#include <asm/mipsregs.h>
34#include <asm/reboot.h>
35#include <asm/pgtable.h>
36#include <asm/time.h>
37
38#include <glb.h>
39#include <int.h>
40#include <pci.h>
41#include <uart.h>
42#include <nand.h>
43
44extern void __init board_setup(void);
45extern void pnx8550_machine_restart(char *);
46extern void pnx8550_machine_halt(void);
47extern struct resource ioport_resource;
48extern struct resource iomem_resource;
49extern char *prom_getcmdline(void);
50
51struct resource standard_io_resources[] = {
52 {
53 .start = 0x00,
54 .end = 0x1f,
55 .name = "dma1",
56 .flags = IORESOURCE_BUSY
57 }, {
58 .start = 0x40,
59 .end = 0x5f,
60 .name = "timer",
61 .flags = IORESOURCE_BUSY
62 }, {
63 .start = 0x80,
64 .end = 0x8f,
65 .name = "dma page reg",
66 .flags = IORESOURCE_BUSY
67 }, {
68 .start = 0xc0,
69 .end = 0xdf,
70 .name = "dma2",
71 .flags = IORESOURCE_BUSY
72 },
73};
74
75#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
76
77extern struct resource pci_io_resource;
78extern struct resource pci_mem_resource;
79
80/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
81unsigned long get_system_mem_size(void)
82{
83 /* Read IP2031_RANK0_ADDR_LO */
84 unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
85 /* Read IP2031_RANK1_ADDR_HI */
86 unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
87
88 return dram_r1_hi - dram_r0_lo + 1;
89}
90
91int pnx8550_console_port = -1;
92
93void __init plat_mem_setup(void)
94{
95 int i;
96 char* argptr;
97
98 board_setup(); /* board specific setup */
99
100 _machine_restart = pnx8550_machine_restart;
101 _machine_halt = pnx8550_machine_halt;
102 pm_power_off = pnx8550_machine_halt;
103
104 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
105 Bit 1:Enable DAC Powerdown
106 -> 0:DACs are enabled and are working normally
107 1:DACs are powerdown
108 Bit 0:Enable of PCI inta output
109 -> 0 = Disable PCI inta output
110 1 = Enable PCI inta output
111 */
112 PNX8550_GLB2_ENAB_INTA_O = 0;
113
114 /* IO/MEM resources. */
115 set_io_port_base(PNX8550_PORT_BASE);
116 ioport_resource.start = 0;
117 ioport_resource.end = ~0;
118 iomem_resource.start = 0;
119 iomem_resource.end = ~0;
120
121 /* Request I/O space for devices on this board */
122 for (i = 0; i < STANDARD_IO_RESOURCES; i++)
123 request_resource(&ioport_resource, standard_io_resources + i);
124
125 /* Place the Mode Control bit for GPIO pin 16 in primary function */
126 /* Pin 16 is used by UART1, UA1_TX */
127 outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
128 (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
129 PNX8550_GPIO_MC1);
130
131 argptr = prom_getcmdline();
132 if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
133 argptr += strlen("console=ttyS");
134 pnx8550_console_port = *argptr == '0' ? 0 : 1;
135
136 /* We must initialize the UART (console) before early printk */
137 /* Set LCR to 8-bit and BAUD to 38400 (no 5) */
138 ip3106_lcr(UART_BASE, pnx8550_console_port) =
139 PNX8XXX_UART_LCR_8BIT;
140 ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
141 }
142}
diff --git a/arch/mips/pnx8550/common/time.c b/arch/mips/pnx8550/common/time.c
deleted file mode 100644
index 831d6b369e9c..000000000000
--- a/arch/mips/pnx8550/common/time.c
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
5 *
6 * Common time service routines for MIPS machines. See
7 * Documents/MIPS/README.txt.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sched.h>
18#include <linux/param.h>
19#include <linux/time.h>
20#include <linux/timer.h>
21#include <linux/smp.h>
22#include <linux/kernel_stat.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25
26#include <asm/bootinfo.h>
27#include <asm/cpu.h>
28#include <asm/time.h>
29#include <asm/hardirq.h>
30#include <asm/div64.h>
31#include <asm/debug.h>
32
33#include <int.h>
34#include <cm.h>
35
36static unsigned long cpj;
37
38static cycle_t hpt_read(struct clocksource *cs)
39{
40 return read_c0_count2();
41}
42
43static struct clocksource pnx_clocksource = {
44 .name = "pnx8xxx",
45 .rating = 200,
46 .read = hpt_read,
47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
48};
49
50static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id)
51{
52 struct clock_event_device *c = dev_id;
53
54 /* clear MATCH, signal the event */
55 c->event_handler(c);
56
57 return IRQ_HANDLED;
58}
59
60static struct irqaction pnx8xxx_timer_irq = {
61 .handler = pnx8xxx_timer_interrupt,
62 .flags = IRQF_PERCPU | IRQF_TIMER,
63 .name = "pnx8xxx_timer",
64};
65
66static irqreturn_t monotonic_interrupt(int irq, void *dev_id)
67{
68 /* Timer 2 clear interrupt */
69 write_c0_compare2(-1);
70 return IRQ_HANDLED;
71}
72
73static struct irqaction monotonic_irqaction = {
74 .handler = monotonic_interrupt,
75 .flags = IRQF_TIMER,
76 .name = "Monotonic timer",
77};
78
79static int pnx8xxx_set_next_event(unsigned long delta,
80 struct clock_event_device *evt)
81{
82 write_c0_compare(delta);
83 return 0;
84}
85
86static struct clock_event_device pnx8xxx_clockevent = {
87 .name = "pnx8xxx_clockevent",
88 .features = CLOCK_EVT_FEAT_ONESHOT,
89 .set_next_event = pnx8xxx_set_next_event,
90};
91
92static inline void timer_ack(void)
93{
94 write_c0_compare(cpj);
95}
96
97__init void plat_time_init(void)
98{
99 unsigned int configPR;
100 unsigned int n;
101 unsigned int m;
102 unsigned int p;
103 unsigned int pow2p;
104
105 pnx8xxx_clockevent.cpumask = cpu_none_mask;
106 clockevents_register_device(&pnx8xxx_clockevent);
107 clocksource_register(&pnx_clocksource);
108
109 /* Timer 1 start */
110 configPR = read_c0_config7();
111 configPR &= ~0x00000008;
112 write_c0_config7(configPR);
113
114 /* Timer 2 start */
115 configPR = read_c0_config7();
116 configPR &= ~0x00000010;
117 write_c0_config7(configPR);
118
119 /* Timer 3 stop */
120 configPR = read_c0_config7();
121 configPR |= 0x00000020;
122 write_c0_config7(configPR);
123
124
125 /* PLL0 sets MIPS clock (PLL1 <=> TM1, PLL6 <=> TM2, PLL5 <=> mem) */
126 /* (but only if CLK_MIPS_CTL select value [bits 3:1] is 1: FIXME) */
127
128 n = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_N_MASK) >> 16;
129 m = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_M_MASK) >> 8;
130 p = (PNX8550_CM_PLL0_CTL & PNX8550_CM_PLL_P_MASK) >> 2;
131 pow2p = (1 << p);
132
133 db_assert(m != 0 && pow2p != 0);
134
135 /*
136 * Compute the frequency as in the PNX8550 User Manual 1.0, p.186
137 * (a.k.a. 8-10). Divide by HZ for a timer offset that results in
138 * HZ timer interrupts per second.
139 */
140 mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p));
141 cpj = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ);
142 write_c0_count(0);
143 timer_ack();
144
145 /* Setup Timer 2 */
146 write_c0_count2(0);
147 write_c0_compare2(0xffffffff);
148
149 setup_irq(PNX8550_INT_TIMER1, &pnx8xxx_timer_irq);
150 setup_irq(PNX8550_INT_TIMER2, &monotonic_irqaction);
151}
diff --git a/arch/mips/pnx8550/jbs/Makefile b/arch/mips/pnx8550/jbs/Makefile
deleted file mode 100644
index c4dc3d53eb5c..000000000000
--- a/arch/mips/pnx8550/jbs/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
1
2# Makefile for the NXP JBS Board.
3
4obj-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/pnx8550/jbs/board_setup.c b/arch/mips/pnx8550/jbs/board_setup.c
deleted file mode 100644
index 57dd903ca408..000000000000
--- a/arch/mips/pnx8550/jbs/board_setup.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * JBS Specific board startup routines.
3 *
4 * Copyright 2005, Embedded Alley Solutions, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26#include <linux/init.h>
27#include <linux/sched.h>
28#include <linux/ioport.h>
29#include <linux/mm.h>
30#include <linux/console.h>
31#include <linux/mc146818rtc.h>
32#include <linux/delay.h>
33
34#include <asm/cpu.h>
35#include <asm/bootinfo.h>
36#include <asm/irq.h>
37#include <asm/mipsregs.h>
38#include <asm/reboot.h>
39#include <asm/pgtable.h>
40
41#include <glb.h>
42
43/* CP0 hazard avoidance. */
44#define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
45 "nop; nop; nop; nop; nop; nop;\n\t" \
46 ".set reorder\n\t")
47
48void __init board_setup(void)
49{
50 unsigned long configpr;
51
52 configpr = read_c0_config7();
53 configpr |= (1<<19); /* enable tlb */
54 write_c0_config7(configpr);
55 BARRIER;
56}
diff --git a/arch/mips/pnx8550/jbs/init.c b/arch/mips/pnx8550/jbs/init.c
deleted file mode 100644
index d59b4a4e5e8b..000000000000
--- a/arch/mips/pnx8550/jbs/init.c
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 *
3 * Copyright 2005 Embedded Alley Solutions, Inc
4 * source@embeddedalley.com
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/mm.h>
29#include <linux/sched.h>
30#include <linux/bootmem.h>
31#include <asm/addrspace.h>
32#include <asm/bootinfo.h>
33#include <linux/string.h>
34#include <linux/kernel.h>
35
36int prom_argc;
37char **prom_argv, **prom_envp;
38extern void __init prom_init_cmdline(void);
39extern char *prom_getenv(char *envname);
40
41const char *get_system_type(void)
42{
43 return "NXP PNX8550/JBS";
44}
45
46void __init prom_init(void)
47{
48 unsigned long memsize;
49
50 //memsize = 0x02800000; /* Trimedia uses memory above */
51 memsize = 0x08000000; /* Trimedia uses memory above */
52 add_memory_region(0, memsize, BOOT_MEM_RAM);
53}
diff --git a/arch/mips/pnx8550/jbs/irqmap.c b/arch/mips/pnx8550/jbs/irqmap.c
deleted file mode 100644
index 7fc89842002c..000000000000
--- a/arch/mips/pnx8550/jbs/irqmap.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * NXP JBS board irqmap.
3 *
4 * Copyright 2005 Embedded Alley Solutions, Inc
5 * source@embeddealley.com
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/init.h>
29#include <int.h>
30
31char pnx8550_irq_tab[][5] __initdata = {
32 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
33 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
34 [17] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
35};
diff --git a/arch/mips/pnx8550/stb810/Makefile b/arch/mips/pnx8550/stb810/Makefile
deleted file mode 100644
index cb4ff022f1fb..000000000000
--- a/arch/mips/pnx8550/stb810/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
1
2# Makefile for the NXP STB810 Board.
3
4obj-y := prom_init.o board_setup.o irqmap.o
diff --git a/arch/mips/pnx8550/stb810/board_setup.c b/arch/mips/pnx8550/stb810/board_setup.c
deleted file mode 100644
index af2a55e0b4e9..000000000000
--- a/arch/mips/pnx8550/stb810/board_setup.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * STB810 specific board startup routines.
3 *
4 * Based on the arch/mips/nxp/pnx8550/jbs/board_setup.c
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * Copyright 2005 MontaVista Software Inc.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17#include <linux/init.h>
18#include <linux/sched.h>
19#include <linux/ioport.h>
20#include <linux/mm.h>
21#include <linux/console.h>
22#include <linux/mc146818rtc.h>
23#include <linux/delay.h>
24
25#include <asm/cpu.h>
26#include <asm/bootinfo.h>
27#include <asm/irq.h>
28#include <asm/mipsregs.h>
29#include <asm/reboot.h>
30#include <asm/pgtable.h>
31
32#include <glb.h>
33
34void __init board_setup(void)
35{
36 unsigned long configpr;
37
38 configpr = read_c0_config7();
39 configpr |= (1<<19); /* enable tlb */
40 write_c0_config7(configpr);
41}
diff --git a/arch/mips/pnx8550/stb810/irqmap.c b/arch/mips/pnx8550/stb810/irqmap.c
deleted file mode 100644
index 8c034963ddcd..000000000000
--- a/arch/mips/pnx8550/stb810/irqmap.c
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * NXP STB810 board irqmap.
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16#include <int.h>
17
18char pnx8550_irq_tab[][5] __initdata = {
19 [8] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
20 [9] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
21 [10] = { -1, PNX8550_INT_PCI_INTA, 0xff, 0xff, 0xff},
22};
diff --git a/arch/mips/pnx8550/stb810/prom_init.c b/arch/mips/pnx8550/stb810/prom_init.c
deleted file mode 100644
index ca7f4ada0640..000000000000
--- a/arch/mips/pnx8550/stb810/prom_init.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * STB810 specific prom routines
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15#include <linux/init.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/bootmem.h>
19#include <asm/addrspace.h>
20#include <asm/bootinfo.h>
21#include <linux/string.h>
22#include <linux/kernel.h>
23
24int prom_argc;
25char **prom_argv, **prom_envp;
26extern void __init prom_init_cmdline(void);
27extern char *prom_getenv(char *envname);
28
29const char *get_system_type(void)
30{
31 return "NXP PNX8950/STB810";
32}
33
34void __init prom_init(void)
35{
36 unsigned long memsize;
37
38 prom_argc = (int) fw_arg0;
39 prom_argv = (char **) fw_arg1;
40 prom_envp = (char **) fw_arg2;
41
42 prom_init_cmdline();
43
44 memsize = 0x08000000; /* Trimedia uses memory above */
45 add_memory_region(0, memsize, BOOT_MEM_RAM);
46}
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 59c23d038106..250df4d9f347 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -716,19 +716,19 @@ config SERIAL_SH_SCI_DMA
716 716
717config SERIAL_PNX8XXX 717config SERIAL_PNX8XXX
718 bool "Enable PNX8XXX SoCs' UART Support" 718 bool "Enable PNX8XXX SoCs' UART Support"
719 depends on SOC_PNX8550 || SOC_PNX833X 719 depends on SOC_PNX833X
720 select SERIAL_CORE 720 select SERIAL_CORE
721 help 721 help
722 If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 722 If you have a MIPS-based Philips SoC such as PNX8330 and you want
723 and you want to use serial ports, say Y. Otherwise, say N. 723 to use serial ports, say Y. Otherwise, say N.
724 724
725config SERIAL_PNX8XXX_CONSOLE 725config SERIAL_PNX8XXX_CONSOLE
726 bool "Enable PNX8XX0 serial console" 726 bool "Enable PNX8XX0 serial console"
727 depends on SERIAL_PNX8XXX 727 depends on SERIAL_PNX8XXX
728 select SERIAL_CORE_CONSOLE 728 select SERIAL_CORE_CONSOLE
729 help 729 help
730 If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 730 If you have a MIPS-based Philips SoC such as PNX8330 and you want
731 and you want to use serial console, say Y. Otherwise, say N. 731 to use serial console, say Y. Otherwise, say N.
732 732
733config SERIAL_HS_LPC32XX 733config SERIAL_HS_LPC32XX
734 tristate "LPC32XX high speed serial port support" 734 tristate "LPC32XX high speed serial port support"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 18:21:45 -0500