diff options
author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2015-03-09 10:48:45 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2015-03-09 14:11:13 -0400 |
commit | e31abce778bc05b94d406e8cbebd9953d12e84b8 (patch) | |
tree | a91c08786ebba08a6f443a2e731f09311a8aa8c1 | |
parent | 0365fbd4bbc0b8f3fd3c78c16a8020ea83b3afcf (diff) |
spi: dw-mid: convert value of dma_width to enum dma_slave_buswidth
DMAEngine has a specific type to be used for bus width. This patch converts the
code to use the values of the specific type when configure DMA transfer.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | drivers/spi/spi-dw-mid.c | 13 | ||||
-rw-r--r-- | drivers/spi/spi-dw.c | 12 |
2 files changed, 19 insertions, 6 deletions
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index c8416ef01f9a..25c8fa7d073f 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c | |||
@@ -100,6 +100,15 @@ static void mid_spi_dma_exit(struct dw_spi *dws) | |||
100 | dma_release_channel(dws->rxchan); | 100 | dma_release_channel(dws->rxchan); |
101 | } | 101 | } |
102 | 102 | ||
103 | static enum dma_slave_buswidth convert_dma_width(u32 dma_width) { | ||
104 | if (dma_width == 1) | ||
105 | return DMA_SLAVE_BUSWIDTH_1_BYTE; | ||
106 | else if (dma_width == 2) | ||
107 | return DMA_SLAVE_BUSWIDTH_2_BYTES; | ||
108 | |||
109 | return DMA_SLAVE_BUSWIDTH_UNDEFINED; | ||
110 | } | ||
111 | |||
103 | /* | 112 | /* |
104 | * dws->dma_chan_busy is set before the dma transfer starts, callback for tx | 113 | * dws->dma_chan_busy is set before the dma transfer starts, callback for tx |
105 | * channel will clear a corresponding bit. | 114 | * channel will clear a corresponding bit. |
@@ -126,7 +135,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws) | |||
126 | txconf.dst_addr = dws->dma_addr; | 135 | txconf.dst_addr = dws->dma_addr; |
127 | txconf.dst_maxburst = LNW_DMA_MSIZE_16; | 136 | txconf.dst_maxburst = LNW_DMA_MSIZE_16; |
128 | txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | 137 | txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
129 | txconf.dst_addr_width = dws->dma_width; | 138 | txconf.dst_addr_width = convert_dma_width(dws->dma_width); |
130 | txconf.device_fc = false; | 139 | txconf.device_fc = false; |
131 | 140 | ||
132 | dmaengine_slave_config(dws->txchan, &txconf); | 141 | dmaengine_slave_config(dws->txchan, &txconf); |
@@ -175,7 +184,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws) | |||
175 | rxconf.src_addr = dws->dma_addr; | 184 | rxconf.src_addr = dws->dma_addr; |
176 | rxconf.src_maxburst = LNW_DMA_MSIZE_16; | 185 | rxconf.src_maxburst = LNW_DMA_MSIZE_16; |
177 | rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | 186 | rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
178 | rxconf.src_addr_width = dws->dma_width; | 187 | rxconf.src_addr_width = convert_dma_width(dws->dma_width); |
179 | rxconf.device_fc = false; | 188 | rxconf.device_fc = false; |
180 | 189 | ||
181 | dmaengine_slave_config(dws->rxchan, &rxconf); | 190 | dmaengine_slave_config(dws->rxchan, &rxconf); |
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c index 950bc50361b3..f3e4092cd8dc 100644 --- a/drivers/spi/spi-dw.c +++ b/drivers/spi/spi-dw.c | |||
@@ -315,7 +315,6 @@ static int dw_spi_transfer_one(struct spi_master *master, | |||
315 | { | 315 | { |
316 | struct dw_spi *dws = spi_master_get_devdata(master); | 316 | struct dw_spi *dws = spi_master_get_devdata(master); |
317 | struct chip_data *chip = spi_get_ctldata(spi); | 317 | struct chip_data *chip = spi_get_ctldata(spi); |
318 | u8 bits = 0; | ||
319 | u8 imask = 0; | 318 | u8 imask = 0; |
320 | u8 cs_change = 0; | 319 | u8 cs_change = 0; |
321 | u16 txlevel = 0; | 320 | u16 txlevel = 0; |
@@ -357,9 +356,14 @@ static int dw_spi_transfer_one(struct spi_master *master, | |||
357 | } | 356 | } |
358 | } | 357 | } |
359 | if (transfer->bits_per_word) { | 358 | if (transfer->bits_per_word) { |
360 | bits = transfer->bits_per_word; | 359 | if (transfer->bits_per_word == 8) { |
361 | dws->n_bytes = dws->dma_width = bits >> 3; | 360 | dws->n_bytes = 1; |
362 | cr0 = (bits - 1) | 361 | dws->dma_width = 1; |
362 | } else if (transfer->bits_per_word == 16) { | ||
363 | dws->n_bytes = 2; | ||
364 | dws->dma_width = 2; | ||
365 | } | ||
366 | cr0 = (transfer->bits_per_word - 1) | ||
363 | | (chip->type << SPI_FRF_OFFSET) | 367 | | (chip->type << SPI_FRF_OFFSET) |
364 | | (spi->mode << SPI_MODE_OFFSET) | 368 | | (spi->mode << SPI_MODE_OFFSET) |
365 | | (chip->tmode << SPI_TMOD_OFFSET); | 369 | | (chip->tmode << SPI_TMOD_OFFSET); |