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authordmitry pervushin <dpervushin@embeddedalley.com>2009-04-22 18:55:23 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-04-27 05:28:07 -0400
commite317872ac532fd845c597e55ceb5a9bceee878c1 (patch)
treed3cb40d75229448563dc5b5ea93c35d5717b7996
parent07d9714365bcab286389d679f73512e35796847c (diff)
[ARM] 5466/1: Freescale STMP platform support [5/10]
Shared (platform) headers Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/clkdev.h18
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/cputype.h33
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/debug-macro.S42
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/dma.h155
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpio.h28
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/hardware.h32
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/io.h25
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/memory.h22
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pinmux.h158
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pins.h30
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/platform.h47
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h34
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h195
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/system.h47
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/timex.h20
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/uncompress.h53
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/vmalloc.h12
17 files changed, 951 insertions, 0 deletions
diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
new file mode 100644
index 000000000000..f9c39772d7c5
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#ifndef __ASM_MACH_CLKDEV_H
13#define __ASM_MACH_CLKDEV_H
14
15#define __clk_get(clk) ({ 1; })
16#define __clk_put(clk) do { } while (0)
17
18#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
new file mode 100644
index 000000000000..b4e205b95f2c
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
@@ -0,0 +1,33 @@
1/*
2 * Freescale STMP37XX/STMP378X CPU type detection
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_CPU_H
19#define __ASM_PLAT_CPU_H
20
21#ifdef CONFIG_ARCH_STMP37XX
22#define cpu_is_stmp37xx() (1)
23#else
24#define cpu_is_stmp37xx() (0)
25#endif
26
27#ifdef CONFIG_ARCH_STMP378X
28#define cpu_is_stmp378x() (1)
29#else
30#define cpu_is_stmp378x() (0)
31#endif
32
33#endif /* __ASM_PLAT_CPU_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..fb3b969bf0a2
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
@@ -0,0 +1,42 @@
1/*
2 * Debugging macro include header
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro addruart,rx
20 mrc p15, 0, \rx, c1, c0
21 tst \rx, #1 @ MMU enabled?
22 moveq \rx, #0x80000000 @ physical base address
23 addeq \rx, \rx, #0x00070000
24 movne \rx, #0xf0000000 @ virtual base
25 addne \rx, \rx, #0x00070000
26 .endm
27
28 .macro senduart,rd,rx
29 strb \rd, [\rx, #0] @ data register at 0
30 .endm
31
32 .macro waituart,rd,rx
331001: ldr \rd, [\rx, #0x18] @ UARTFLG
34 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
35 bne 1001b
36 .endm
37
38 .macro busyuart,rd,rx
391001: ldr \rd, [\rx, #0x18] @ UARTFLG
40 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
41 bne 1001b
42 .endm
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
new file mode 100644
index 000000000000..1e305b2bfe73
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/dma.h
@@ -0,0 +1,155 @@
1/*
2 * Freescale STMP37XX/STMP378X DMA helper interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_DMA_H
19#define __ASM_PLAT_STMP3XXX_DMA_H
20
21#include <linux/platform_device.h>
22#include <linux/dmapool.h>
23
24#if !defined(MAX_PIO_WORDS)
25#define MAX_PIO_WORDS (15)
26#endif
27
28#define STMP3XXX_BUS_APBH 0
29#define STMP3XXX_BUS_APBX 1
30#define STMP3XXX_DMA_MAX_CHANNEL 16
31
32
33#define STMP3xxx_DMA(channel, bus) ((bus) * 16 + (channel))
34
35#define MAX_DMA_ADDRESS 0xffffffff
36
37#define MAX_DMA_CHANNELS 32
38
39struct stmp3xxx_dma_command {
40 u32 next;
41 u32 cmd;
42 union {
43 u32 buf_ptr;
44 u32 alternate;
45 };
46 u32 pio_words[MAX_PIO_WORDS];
47};
48
49struct stmp3xxx_dma_descriptor {
50 struct stmp3xxx_dma_command *command;
51 dma_addr_t handle;
52
53 /* The virtual address of the buffer pointer */
54 void *virtual_buf_ptr;
55 /* The next descriptor in a the DMA chain (optional) */
56 struct stmp3xxx_dma_descriptor *next_descr;
57};
58
59struct stmp37xx_circ_dma_chain {
60 unsigned total_count;
61 struct stmp3xxx_dma_descriptor *chain;
62
63 unsigned free_index;
64 unsigned free_count;
65 unsigned active_index;
66 unsigned active_count;
67 unsigned cooked_index;
68 unsigned cooked_count;
69
70 int bus;
71 unsigned channel;
72};
73
74static inline struct stmp3xxx_dma_descriptor
75 *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
76{
77 return &(chain->chain[chain->free_index]);
78}
79
80static inline struct stmp3xxx_dma_descriptor
81 *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
82{
83 return &(chain->chain[chain->cooked_index]);
84}
85
86int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
87int stmp3xxx_dma_release(int ch);
88int stmp3xxx_dma_allocate_command(int ch,
89 struct stmp3xxx_dma_descriptor *descriptor);
90int stmp3xxx_dma_free_command(int ch,
91 struct stmp3xxx_dma_descriptor *descriptor);
92void stmp3xxx_dma_continue(int channel, u32 semaphore);
93void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
94 u32 semaphore);
95int stmp3xxx_dma_running(int ch);
96int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
97 struct stmp3xxx_dma_descriptor descriptors[],
98 unsigned items);
99void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
100void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
101void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
102 unsigned count);
103void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
104 unsigned count);
105unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
106int stmp3xxx_dma_read_semaphore(int ch);
107void stmp3xxx_dma_init(void);
108void stmp3xxx_dma_set_alt_target(int ch, int target);
109void stmp3xxx_dma_suspend(void);
110void stmp3xxx_dma_resume(void);
111
112/*
113 * STMP37xx and STMP378x have different DMA control
114 * registers layout
115 */
116
117void stmp3xxx_arch_dma_freeze(int ch);
118void stmp3xxx_arch_dma_unfreeze(int ch);
119void stmp3xxx_arch_dma_reset_channel(int ch);
120void stmp3xxx_arch_dma_enable_interrupt(int ch);
121void stmp3xxx_arch_dma_clear_interrupt(int ch);
122int stmp3xxx_arch_dma_is_interrupt(int ch);
123
124static inline void stmp3xxx_dma_reset_channel(int ch)
125{
126 stmp3xxx_arch_dma_reset_channel(ch);
127}
128
129
130static inline void stmp3xxx_dma_freeze(int ch)
131{
132 stmp3xxx_arch_dma_freeze(ch);
133}
134
135static inline void stmp3xxx_dma_unfreeze(int ch)
136{
137 stmp3xxx_arch_dma_unfreeze(ch);
138}
139
140static inline void stmp3xxx_dma_enable_interrupt(int ch)
141{
142 stmp3xxx_arch_dma_enable_interrupt(ch);
143}
144
145static inline void stmp3xxx_dma_clear_interrupt(int ch)
146{
147 stmp3xxx_arch_dma_clear_interrupt(ch);
148}
149
150static inline int stmp3xxx_dma_is_interrupt(int ch)
151{
152 return stmp3xxx_arch_dma_is_interrupt(ch);
153}
154
155#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
new file mode 100644
index 000000000000..a8b579256170
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
@@ -0,0 +1,28 @@
1/*
2 * Freescale STMP37XX/STMP378X GPIO interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_GPIO_H
19#define __ASM_PLAT_GPIO_H
20
21#define ARCH_NR_GPIOS (32 * 3)
22#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
23#define gpio_get_value(gpio) __gpio_get_value(gpio)
24#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
25
26#include <asm-generic/gpio.h>
27
28#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
new file mode 100644
index 000000000000..47b8978405bc
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
@@ -0,0 +1,32 @@
1/*
2 * This file contains the hardware definitions of the Freescale STMP3XXX
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_HARDWARE_H
19#define __ASM_ARCH_HARDWARE_H
20
21/*
22 * Where in virtual memory the IO devices (timers, system controllers
23 * and so on)
24 */
25#define IO_BASE 0xF0000000 /* VA of IO */
26#define IO_SIZE 0x00100000 /* How much? */
27#define IO_START 0x80000000 /* PA of IO */
28
29/* macro to get at IO space when running virtually */
30#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
31
32#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
new file mode 100644
index 000000000000..d08b1b7f3d1c
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19#define IO_SPACE_LIMIT 0xffffffff
20
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23#define __mem_isa(a) (a)
24
25#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
new file mode 100644
index 000000000000..7b875a07a1a7
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/memory.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET UL(0x40000000)
21
22#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
new file mode 100644
index 000000000000..526c068d7c44
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
@@ -0,0 +1,158 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __PINMUX_H
19#define __PINMUX_H
20
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <asm-generic/gpio.h>
25
26/* Pin definitions */
27#include "pins.h"
28#include <mach/pins.h>
29
30/*
31 * Each pin may be routed up to four different HW interfaces
32 * including GPIO
33 */
34enum pin_fun {
35 PIN_FUN1 = 0,
36 PIN_FUN2,
37 PIN_FUN3,
38 PIN_GPIO,
39};
40
41/*
42 * Each pin may have different output drive strength in range from
43 * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
44 */
45enum pin_strength {
46 PIN_4MA = 0,
47 PIN_8MA,
48 PIN_12MA,
49 PIN_16MA,
50 PIN_20MA,
51};
52
53/*
54 * Each pin can be programmed for 1.8V or 3.3V
55 */
56enum pin_voltage {
57 PIN_1_8V = 0,
58 PIN_3_3V,
59};
60
61/*
62 * Structure to define a group of pins and their parameters
63 */
64struct pin_desc {
65 unsigned id;
66 enum pin_fun fun;
67 enum pin_strength strength;
68 enum pin_voltage voltage;
69 unsigned pullup:1;
70};
71
72struct pin_group {
73 struct pin_desc *pins;
74 int nr_pins;
75};
76
77/* Set pin drive strength */
78void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
79 const char *label);
80
81/* Set pin voltage */
82void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
83 const char *label);
84
85/* Enable pull-up resistor for a pin */
86void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
87
88/*
89 * Request a pin ownership, only one module (identified by @label)
90 * may own a pin.
91 */
92int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
93
94/* Release pin */
95void stmp3xxx_release_pin(unsigned id, const char *label);
96
97void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
98
99/*
100 * Each bank is associated with a number of registers to control
101 * pin function, drive strength, voltage and pull-up reigster. The
102 * number of registers of a given type depends on the number of bits
103 * describin particular pin.
104 */
105#define HW_MUXSEL_NUM 2 /* registers per bank */
106#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
107#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
108#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
109#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
110
111#define HW_DRIVE_NUM 4 /* registers per bank */
112#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
113#define HW_DRIVE_PIN_NUM 8 /* pins per register */
114#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
115#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
116#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
117
118
119struct stmp3xxx_pinmux_bank {
120 struct gpio_chip chip;
121
122 /* Pins allocation map */
123 unsigned long pin_map;
124
125 /* Pin owner names */
126 const char *pin_labels[32];
127
128 /* Bank registers */
129 void __iomem *hw_muxsel[HW_MUXSEL_NUM];
130 void __iomem *hw_drive[HW_DRIVE_NUM];
131 void __iomem *hw_pull;
132
133 void __iomem *pin2irq,
134 *irqlevel,
135 *irqpolarity,
136 *irqen,
137 *irqstat;
138
139 /* HW MUXSEL register function bit values */
140 u8 functions[HW_MUXSEL_PINFUN_NUM];
141
142 /*
143 * HW DRIVE register strength bit values:
144 * 0xff - requested strength is not supported for this bank
145 */
146 u8 strengths[HW_DRIVE_PINDRV_NUM];
147
148 /* GPIO things */
149 void __iomem *hw_gpio_read,
150 *hw_gpio_set,
151 *hw_gpio_clr,
152 *hw_gpio_doe;
153 int irq, virq;
154};
155
156int __init stmp3xxx_pinmux_init(int virtual_irq_start);
157
158#endif /* __PINMUX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h
new file mode 100644
index 000000000000..c573318e1caa
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/pins.h
@@ -0,0 +1,30 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_PINS_H
19#define __ASM_PLAT_PINS_H
20
21#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
22#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
23#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
24
25/*
26 * Special invalid pin identificator to show a pin doesn't exist
27 */
28#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
29
30#endif /* __ASM_PLAT_PINS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
new file mode 100644
index 000000000000..525c41379bbe
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/platform.h
@@ -0,0 +1,47 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_PLAT_PLATFORM_H
15#define __ASM_PLAT_PLATFORM_H
16
17#include <asm/sizes.h>
18
19/* Virtual address where registers are mapped */
20#define STMP3XXX_REGS_PHBASE 0x80000000
21#ifdef __ASSEMBLER__
22#define STMP3XXX_REGS_BASE 0xF0000000
23#else
24#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
25#endif
26#define STMP3XXX_REGS_SIZE SZ_1M
27
28/* Virtual address where OCRAM is mapped */
29#define STMP3XXX_OCRAM_PHBASE 0x00000000
30#ifdef __ASSEMBLER__
31#define STMP3XXX_OCRAM_BASE 0xf1000000
32#else
33#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
34#endif
35#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
36
37#ifdef CONFIG_ARCH_STMP37XX
38#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
39#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
40#endif
41
42#ifdef CONFIG_ARCH_STMP378X
43#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
44#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
45#endif
46
47#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
new file mode 100644
index 000000000000..78cf1be75519
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
@@ -0,0 +1,34 @@
1/*
2 * Freescale STMP37XX/STMP378X core structure and function declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_H
19#define __ASM_PLAT_STMP3XXX_H
20
21#include <linux/irq.h>
22
23extern struct sys_timer stmp3xxx_timer;
24
25void stmp3xxx_init_irq(struct irq_chip *chip);
26void stmp3xxx_init(void);
27int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
28extern struct platform_device stmp3xxx_dbguart;
29
30struct pin_group;
31void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
32int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
33
34#endif /* __ASM_PLAT_STMP3XXX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h
new file mode 100644
index 000000000000..47797b2b36af
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx_regs.h
@@ -0,0 +1,195 @@
1/*
2 * Freescale STMP37XX/STMP378X SoC register access interfaces
3 *
4 * The SoC registers may be accessed via:
5 *
6 * - single 32 bit address, or
7 * - four 32 bit addresses - general purpose, set, clear and toggle bits
8 *
9 * Multiple IP blocks (e.g. SSP, UART) provide identical register sets per
10 * each module
11 *
12 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
13 *
14 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
15 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
16 */
17
18/*
19 * The code contained herein is licensed under the GNU General Public
20 * License. You may obtain a copy of the GNU General Public License
21 * Version 2 or later at the following locations:
22 *
23 * http://www.opensource.org/licenses/gpl-license.html
24 * http://www.gnu.org/copyleft/gpl.html
25 */
26#ifndef __ASM_PLAT_STMP3XXX_REGS_H
27#define __ASM_PLAT_STMP3XXX_REGS_H
28
29#ifndef __ASSEMBLER__
30#include <linux/io.h>
31#endif
32
33#include "platform.h"
34
35#define REGS_BASE STMP3XXX_REGS_BASE
36
37#define HW_STMP3xxx_SET 0x04
38#define HW_STMP3xxx_CLR 0x08
39#define HW_STMP3xxx_TOG 0x0c
40
41#ifndef __ASSEMBLER__
42#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr) \
43 static const u32 id##_OFFSET = offset; \
44 static inline u32 id##_RD_NB(const void __iomem *regbase) { \
45 if (!rd) \
46 printk(KERN_ERR"%s: cannot READ at %p+%x\n", \
47 #id, regbase, offset); \
48 return __raw_readl(regbase + offset); \
49 } \
50 static inline void id##_WR_NB(void __iomem *regbase, u32 v) { \
51 if (!wr) \
52 printk(KERN_ERR"%s: cannot WRITE at %p+%x\n", \
53 #id, regbase, offset); \
54 __raw_writel(v, regbase + offset); \
55 } \
56 static inline void id##_SET_NB(void __iomem *regbase, u32 v) { \
57 if (!wr) \
58 printk(KERN_ERR"%s: cannot SET at %p+%x\n", \
59 #id, regbase, offset); \
60 if (regset) \
61 __raw_writel(v, regbase + \
62 offset + HW_STMP3xxx_SET); \
63 else \
64 __raw_writel(v | __raw_readl(regbase + offset), \
65 regbase + offset); \
66 } \
67 static inline void id##_CLR_NB(void __iomem *regbase, u32 v) { \
68 if (!wr) \
69 printk(KERN_ERR"%s: cannot CLR at %p+%x\n", \
70 #id, regbase, offset); \
71 if (regset) \
72 __raw_writel(v, regbase + \
73 offset + HW_STMP3xxx_CLR); \
74 else \
75 __raw_writel( \
76 ~v & __raw_readl(regbase + offset), \
77 regbase + offset); \
78 } \
79 static inline void id##_TOG_NB(void __iomem *regbase, u32 v) { \
80 if (!wr) \
81 printk(KERN_ERR"%s: cannot TOG at %p+%x\n", \
82 #id, regbase, offset); \
83 if (regset) \
84 __raw_writel(v, regbase + \
85 offset + HW_STMP3xxx_TOG); \
86 else \
87 __raw_writel(v ^ __raw_readl(regbase + offset), \
88 regbase + offset); \
89 } \
90 static inline u32 id##_RD(void) { return id##_RD_NB(base); } \
91 static inline void id##_WR(u32 v) { id##_WR_NB(base, v); } \
92 static inline void id##_SET(u32 v) { id##_SET_NB(base, v); } \
93 static inline void id##_CLR(u32 v) { id##_CLR_NB(base, v); } \
94 static inline void id##_TOG(u32 v) { id##_TOG_NB(base, v); }
95
96#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)\
97 static inline u32 id##_OFFSET(int i) { \
98 return offset + i * step; \
99 } \
100 static inline u32 id##_RD_NB(const void __iomem *regbase, int i) {\
101 if (!rd) \
102 printk(KERN_ERR"%s(%d): can't READ at %p+%x\n", \
103 #id, i, regbase, offset + i * step); \
104 return __raw_readl(regbase + offset + i * step); \
105 } \
106 static inline void id##_WR_NB(void __iomem *regbase, int i, u32 v) {\
107 if (!wr) \
108 printk(KERN_ERR"%s(%d): can't WRITE at %p+%x\n",\
109 #id, i, regbase, offset + i * step); \
110 __raw_writel(v, regbase + offset + i * step); \
111 } \
112 static inline void id##_SET_NB(void __iomem *regbase, int i, u32 v) {\
113 if (!wr) \
114 printk(KERN_ERR"%s(%d): can't SET at %p+%x\n", \
115 #id, i, regbase, offset + i * step); \
116 if (regset) \
117 __raw_writel(v, regbase + offset + \
118 i * step + HW_STMP3xxx_SET); \
119 else \
120 __raw_writel(v | __raw_readl(regbase + \
121 offset + i * step), \
122 regbase + offset + i * step); \
123 } \
124 static inline void id##_CLR_NB(void __iomem *regbase, int i, u32 v) {\
125 if (!wr) \
126 printk(KERN_ERR"%s(%d): cannot CLR at %p+%x\n", \
127 #id, i, regbase, offset + i * step); \
128 if (regset) \
129 __raw_writel(v, regbase + offset + \
130 i * step + HW_STMP3xxx_CLR); \
131 else \
132 __raw_writel(~v & __raw_readl(regbase + \
133 offset + i * step), \
134 regbase + offset + i * step); \
135 } \
136 static inline void id##_TOG_NB(void __iomem *regbase, int i, u32 v) {\
137 if (!wr) \
138 printk(KERN_ERR"%s(%d): cannot TOG at %p+%x\n", \
139 #id, i, regbase, offset + i * step); \
140 if (regset) \
141 __raw_writel(v, regbase + offset + \
142 i * step + HW_STMP3xxx_TOG); \
143 else \
144 __raw_writel(v ^ __raw_readl(regbase + offset \
145 + i * step), \
146 regbase + offset + i * step); \
147 } \
148 static inline u32 id##_RD(int i) \
149 { \
150 return id##_RD_NB(base, i); \
151 } \
152 static inline void id##_WR(int i, u32 v) \
153 { \
154 id##_WR_NB(base, i, v); \
155 } \
156 static inline void id##_SET(int i, u32 v) \
157 { \
158 id##_SET_NB(base, i, v); \
159 } \
160 static inline void id##_CLR(int i, u32 v) \
161 { \
162 id##_CLR_NB(base, i, v); \
163 } \
164 static inline void id##_TOG(int i, u32 v) \
165 { \
166 id##_TOG_NB(base, i, v); \
167 }
168
169#define HW_REGISTER_WO(id, base, offset)\
170 HW_REGISTER_FUNCS(id, base, offset, 1, 0, 1)
171#define HW_REGISTER_RO(id, base, offset)\
172 HW_REGISTER_FUNCS(id, base, offset, 1, 1, 0)
173#define HW_REGISTER(id, base, offset) \
174 HW_REGISTER_FUNCS(id, base, offset, 1, 1, 1)
175#define HW_REGISTER_0(id, base, offset) \
176 HW_REGISTER_FUNCS(id, base, offset, 0, 1, 1)
177#define HW_REGISTER_INDEXED(id, base, offset, step) \
178 HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 1, step)
179#define HW_REGISTER_RO_INDEXED(id, base, offset, step) \
180 HW_REGISTER_FUNCS_INDEXED(id, base, offset, 1, 1, 0, step)
181#define HW_REGISTER_0_INDEXED(id, base, offset, step) \
182 HW_REGISTER_FUNCS_INDEXED(id, base, offset, 0, 1, 1, step)
183#else /* __ASSEMBLER__ */
184#define HW_REGISTER_FUNCS(id, base, offset, regset, rd, wr)
185#define HW_REGISTER_FUNCS_INDEXED(id, base, offset, regset, rd, wr, step)
186#define HW_REGISTER_WO(id, base, offset)
187#define HW_REGISTER_RO(id, base, offset)
188#define HW_REGISTER(id, base, offset)
189#define HW_REGISTER_0(id, base, offset)
190#define HW_REGISTER_INDEXED(id, base, offset, step)
191#define HW_REGISTER_RO_INDEXED(id, base, offset, step)
192#define HW_REGISTER_0_INDEXED(id, base, offset, step)
193#endif /* __ASSEMBLER__ */
194
195#endif /* __ASM_PLAT_STMP3XXX_REGS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
new file mode 100644
index 000000000000..dac48d267148
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/system.h
@@ -0,0 +1,47 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARCH_SYSTEM_H
17#define __ASM_ARCH_SYSTEM_H
18
19#include <asm/proc-fns.h>
20#include <mach/regs-clkctrl.h>
21#include <mach/regs-power.h>
22
23static inline void arch_idle(void)
24{
25 /*
26 * This should do all the clock switching
27 * and wait for interrupt tricks
28 */
29
30 cpu_do_idle();
31}
32
33static inline void arch_reset(char mode, const char *cmd)
34{
35 /* Set BATTCHRG to default value */
36 HW_POWER_CHARGE_WR(0x00010000);
37
38 /* Set MINPWR to default value */
39 HW_POWER_MINPWR_WR(0);
40
41 /* Reset digital side of chip (but not power or RTC) */
42 HW_CLKCTRL_RESET_WR(BM_CLKCTRL_RESET_DIG);
43
44 /* Should not return */
45}
46
47#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h
new file mode 100644
index 000000000000..3373985d7a8e
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/timex.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17/*
18 * System time clock is sourced from the 32k clock
19 */
20#define CLOCK_TICK_RATE (32768)
diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
new file mode 100644
index 000000000000..f79f5ee56cd4
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
@@ -0,0 +1,53 @@
1/*
2 *
3 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 */
6
7/*
8 * The code contained herein is licensed under the GNU General Public
9 * License. You may obtain a copy of the GNU General Public License
10 * Version 2 or later at the following locations:
11 *
12 * http://www.opensource.org/licenses/gpl-license.html
13 * http://www.gnu.org/copyleft/gpl.html
14 */
15#ifndef __ASM_PLAT_UNCOMPRESS_H
16#define __ASM_PLAT_UNCOMPRESS_H
17
18/*
19 * Register includes are for when the MMU enabled; we need to define our
20 * own stuff here for pre-MMU use
21 */
22#define UARTDBG_BASE 0x80070000
23#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
24
25/*
26 * This does not append a newline
27 */
28static void putc(char c)
29{
30 /* Wait for TX fifo empty */
31 while ((UART(6) & (1<<7)) == 0)
32 continue;
33
34 /* Write byte */
35 UART(0) = c;
36
37 /* Wait for last bit to exit the UART */
38 while (UART(6) & (1<<3))
39 continue;
40}
41
42static void flush(void)
43{
44}
45
46/*
47 * nothing to do
48 */
49#define arch_decomp_setup()
50
51#define arch_decomp_wdog()
52
53#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..541b880c1863
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
@@ -0,0 +1,12 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#define VMALLOC_END (0xF0000000)
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-20 17:40:33 -0400