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authorStephen Warren <swarren@nvidia.com>2014-03-03 16:51:15 -0500
committerStephen Warren <swarren@nvidia.com>2014-03-05 15:29:13 -0500
commite30cb2388ab68de68142120ab9fca5ae6e377682 (patch)
tree74daa407671bb5b33abc0b882b8dd95ae3297647
parentfdc44f9491cda0607b9c4b2ddb95bd742418635e (diff)
ARM: tegra: use 2 address cells for Tegra124 DT
Tegra124 can support 4GB of RAM. With that much RAM (plus some memory- mapped IO peripherals), more than 32-bits of physical address space is required. Hence, convert all Tegra124 DTs to use 2 DT cells for address space. (I think this was suggested by Olof Johansson, but I'm not 100% sure) Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts54
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi215
2 files changed, 137 insertions, 132 deletions
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 1ad686154286..86536d919ed2 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -8,29 +8,29 @@
8 compatible = "nvidia,venice2", "nvidia,tegra124"; 8 compatible = "nvidia,venice2", "nvidia,tegra124";
9 9
10 aliases { 10 aliases {
11 rtc0 = "/i2c@7000d000/pmic@40"; 11 rtc0 = "/i2c@0,7000d000/pmic@40";
12 rtc1 = "/rtc@7000e000"; 12 rtc1 = "/rtc@0,7000e000";
13 }; 13 };
14 14
15 memory { 15 memory {
16 reg = <0x80000000 0x80000000>; 16 reg = <0x0 0x80000000 0x0 0x80000000>;
17 }; 17 };
18 18
19 host1x@50000000 { 19 host1x@0,50000000 {
20 sor@54540000 { 20 sor@0,54540000 {
21 status = "okay"; 21 status = "okay";
22 22
23 nvidia,dpaux = <&dpaux>; 23 nvidia,dpaux = <&dpaux>;
24 nvidia,panel = <&panel>; 24 nvidia,panel = <&panel>;
25 }; 25 };
26 26
27 dpaux: dpaux@545c0000 { 27 dpaux: dpaux@0,545c0000 {
28 vdd-supply = <&vdd_3v3_panel>; 28 vdd-supply = <&vdd_3v3_panel>;
29 status = "okay"; 29 status = "okay";
30 }; 30 };
31 }; 31 };
32 32
33 pinmux: pinmux@70000868 { 33 pinmux: pinmux@0,70000868 {
34 pinctrl-names = "default"; 34 pinctrl-names = "default";
35 pinctrl-0 = <&pinmux_default>; 35 pinctrl-0 = <&pinmux_default>;
36 36
@@ -578,15 +578,15 @@
578 }; 578 };
579 }; 579 };
580 580
581 serial@70006000 { 581 serial@0,70006000 {
582 status = "okay"; 582 status = "okay";
583 }; 583 };
584 584
585 pwm: pwm@7000a000 { 585 pwm: pwm@0,7000a000 {
586 status = "okay"; 586 status = "okay";
587 }; 587 };
588 588
589 i2c@7000c000 { 589 i2c@0,7000c000 {
590 status = "okay"; 590 status = "okay";
591 clock-frequency = <100000>; 591 clock-frequency = <100000>;
592 592
@@ -598,22 +598,22 @@
598 }; 598 };
599 }; 599 };
600 600
601 i2c@7000c400 { 601 i2c@0,7000c400 {
602 status = "okay"; 602 status = "okay";
603 clock-frequency = <100000>; 603 clock-frequency = <100000>;
604 }; 604 };
605 605
606 i2c@7000c500 { 606 i2c@0,7000c500 {
607 status = "okay"; 607 status = "okay";
608 clock-frequency = <100000>; 608 clock-frequency = <100000>;
609 }; 609 };
610 610
611 i2c@7000c700 { 611 i2c@0,7000c700 {
612 status = "okay"; 612 status = "okay";
613 clock-frequency = <100000>; 613 clock-frequency = <100000>;
614 }; 614 };
615 615
616 i2c@7000d000 { 616 i2c@0,7000d000 {
617 status = "okay"; 617 status = "okay";
618 clock-frequency = <400000>; 618 clock-frequency = <400000>;
619 619
@@ -808,7 +808,7 @@
808 }; 808 };
809 }; 809 };
810 810
811 spi@7000d400 { 811 spi@0,7000d400 {
812 status = "okay"; 812 status = "okay";
813 813
814 cros-ec@0 { 814 cros-ec@0 {
@@ -914,7 +914,7 @@
914 }; 914 };
915 }; 915 };
916 916
917 spi@7000da00 { 917 spi@0,7000da00 {
918 status = "okay"; 918 status = "okay";
919 spi-max-frequency = <25000000>; 919 spi-max-frequency = <25000000>;
920 spi-flash@0 { 920 spi-flash@0 {
@@ -924,7 +924,7 @@
924 }; 924 };
925 }; 925 };
926 926
927 pmc@7000e400 { 927 pmc@0,7000e400 {
928 nvidia,invert-interrupt; 928 nvidia,invert-interrupt;
929 nvidia,suspend-mode = <1>; 929 nvidia,suspend-mode = <1>;
930 nvidia,cpu-pwr-good-time = <500>; 930 nvidia,cpu-pwr-good-time = <500>;
@@ -935,7 +935,7 @@
935 nvidia,sys-clock-req-active-high; 935 nvidia,sys-clock-req-active-high;
936 }; 936 };
937 937
938 sdhci@700b0400 { 938 sdhci@0,700b0400 {
939 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 939 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
940 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 940 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
941 status = "okay"; 941 status = "okay";
@@ -943,40 +943,40 @@
943 vmmc-supply = <&vddio_sdmmc3>; 943 vmmc-supply = <&vddio_sdmmc3>;
944 }; 944 };
945 945
946 sdhci@700b0600 { 946 sdhci@0,700b0600 {
947 status = "okay"; 947 status = "okay";
948 bus-width = <8>; 948 bus-width = <8>;
949 }; 949 };
950 950
951 ahub@70300000 { 951 ahub@0,70300000 {
952 i2s@70301100 { 952 i2s@0,70301100 {
953 status = "okay"; 953 status = "okay";
954 }; 954 };
955 }; 955 };
956 956
957 usb@7d000000 { 957 usb@0,7d000000 {
958 status = "okay"; 958 status = "okay";
959 }; 959 };
960 960
961 usb-phy@7d000000 { 961 usb-phy@0,7d000000 {
962 status = "okay"; 962 status = "okay";
963 vbus-supply = <&vdd_usb1_vbus>; 963 vbus-supply = <&vdd_usb1_vbus>;
964 }; 964 };
965 965
966 usb@7d004000 { 966 usb@0,7d004000 {
967 status = "okay"; 967 status = "okay";
968 }; 968 };
969 969
970 usb-phy@7d004000 { 970 usb-phy@0,7d004000 {
971 status = "okay"; 971 status = "okay";
972 vbus-supply = <&vdd_run_cam>; 972 vbus-supply = <&vdd_run_cam>;
973 }; 973 };
974 974
975 usb@7d008000 { 975 usb@0,7d008000 {
976 status = "okay"; 976 status = "okay";
977 }; 977 };
978 978
979 usb-phy@7d008000 { 979 usb-phy@0,7d008000 {
980 status = "okay"; 980 status = "okay";
981 vbus-supply = <&vdd_usb3_vbus>; 981 vbus-supply = <&vdd_usb3_vbus>;
982 }; 982 };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index b1459844ef09..cf45a1a39483 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -8,24 +8,26 @@
8/ { 8/ {
9 compatible = "nvidia,tegra124"; 9 compatible = "nvidia,tegra124";
10 interrupt-parent = <&gic>; 10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
11 13
12 host1x@50000000 { 14 host1x@0,50000000 {
13 compatible = "nvidia,tegra124-host1x", "simple-bus"; 15 compatible = "nvidia,tegra124-host1x", "simple-bus";
14 reg = <0x50000000 0x00034000>; 16 reg = <0x0 0x50000000 0x0 0x00034000>;
15 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 17 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
16 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 18 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
17 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 19 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
18 resets = <&tegra_car 28>; 20 resets = <&tegra_car 28>;
19 reset-names = "host1x"; 21 reset-names = "host1x";
20 22
21 #address-cells = <1>; 23 #address-cells = <2>;
22 #size-cells = <1>; 24 #size-cells = <2>;
23 25
24 ranges = <0x54000000 0x54000000 0x01000000>; 26 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
25 27
26 dc@54200000 { 28 dc@0,54200000 {
27 compatible = "nvidia,tegra124-dc"; 29 compatible = "nvidia,tegra124-dc";
28 reg = <0x54200000 0x00040000>; 30 reg = <0x0 0x54200000 0x0 0x00040000>;
29 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 31 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
30 clocks = <&tegra_car TEGRA124_CLK_DISP1>, 32 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
31 <&tegra_car TEGRA124_CLK_PLL_P>; 33 <&tegra_car TEGRA124_CLK_PLL_P>;
@@ -36,9 +38,9 @@
36 nvidia,head = <0>; 38 nvidia,head = <0>;
37 }; 39 };
38 40
39 dc@54240000 { 41 dc@0,54240000 {
40 compatible = "nvidia,tegra124-dc"; 42 compatible = "nvidia,tegra124-dc";
41 reg = <0x54240000 0x00040000>; 43 reg = <0x0 0x54240000 0x0 0x00040000>;
42 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 44 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
43 clocks = <&tegra_car TEGRA124_CLK_DISP2>, 45 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
44 <&tegra_car TEGRA124_CLK_PLL_P>; 46 <&tegra_car TEGRA124_CLK_PLL_P>;
@@ -49,9 +51,9 @@
49 nvidia,head = <1>; 51 nvidia,head = <1>;
50 }; 52 };
51 53
52 sor@54540000 { 54 sor@0,54540000 {
53 compatible = "nvidia,tegra124-sor"; 55 compatible = "nvidia,tegra124-sor";
54 reg = <0x54540000 0x00040000>; 56 reg = <0x0 0x54540000 0x0 0x00040000>;
55 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 57 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
56 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 58 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
57 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 59 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
@@ -63,9 +65,9 @@
63 status = "disabled"; 65 status = "disabled";
64 }; 66 };
65 67
66 dpaux@545c0000 { 68 dpaux@0,545c0000 {
67 compatible = "nvidia,tegra124-dpaux"; 69 compatible = "nvidia,tegra124-dpaux";
68 reg = <0x545c0000 0x00040000>; 70 reg = <0x0 0x545c0000 0x0 0x00040000>;
69 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 71 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
70 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 72 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
71 <&tegra_car TEGRA124_CLK_PLL_DP>; 73 <&tegra_car TEGRA124_CLK_PLL_DP>;
@@ -76,21 +78,21 @@
76 }; 78 };
77 }; 79 };
78 80
79 gic: interrupt-controller@50041000 { 81 gic: interrupt-controller@0,50041000 {
80 compatible = "arm,cortex-a15-gic"; 82 compatible = "arm,cortex-a15-gic";
81 #interrupt-cells = <3>; 83 #interrupt-cells = <3>;
82 interrupt-controller; 84 interrupt-controller;
83 reg = <0x50041000 0x1000>, 85 reg = <0x0 0x50041000 0x0 0x1000>,
84 <0x50042000 0x1000>, 86 <0x0 0x50042000 0x0 0x1000>,
85 <0x50044000 0x2000>, 87 <0x0 0x50044000 0x0 0x2000>,
86 <0x50046000 0x2000>; 88 <0x0 0x50046000 0x0 0x2000>;
87 interrupts = <GIC_PPI 9 89 interrupts = <GIC_PPI 9
88 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 90 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
89 }; 91 };
90 92
91 timer@60005000 { 93 timer@0,60005000 {
92 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 94 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
93 reg = <0x60005000 0x400>; 95 reg = <0x0 0x60005000 0x0 0x400>;
94 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 96 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -100,16 +102,16 @@
100 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 102 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
101 }; 103 };
102 104
103 tegra_car: clock@60006000 { 105 tegra_car: clock@0,60006000 {
104 compatible = "nvidia,tegra124-car"; 106 compatible = "nvidia,tegra124-car";
105 reg = <0x60006000 0x1000>; 107 reg = <0x0 0x60006000 0x0 0x1000>;
106 #clock-cells = <1>; 108 #clock-cells = <1>;
107 #reset-cells = <1>; 109 #reset-cells = <1>;
108 }; 110 };
109 111
110 gpio: gpio@6000d000 { 112 gpio: gpio@0,6000d000 {
111 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 113 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
112 reg = <0x6000d000 0x1000>; 114 reg = <0x0 0x6000d000 0x0 0x1000>;
113 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 115 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
@@ -124,9 +126,9 @@
124 interrupt-controller; 126 interrupt-controller;
125 }; 127 };
126 128
127 apbdma: dma@60020000 { 129 apbdma: dma@0,60020000 {
128 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 130 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
129 reg = <0x60020000 0x1400>; 131 reg = <0x0 0x60020000 0x0 0x1400>;
130 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 132 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
@@ -165,10 +167,10 @@
165 #dma-cells = <1>; 167 #dma-cells = <1>;
166 }; 168 };
167 169
168 pinmux: pinmux@70000868 { 170 pinmux: pinmux@0,70000868 {
169 compatible = "nvidia,tegra124-pinmux"; 171 compatible = "nvidia,tegra124-pinmux";
170 reg = <0x70000868 0x164>, /* Pad control registers */ 172 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
171 <0x70003000 0x434>; /* Mux registers */ 173 <0x0 0x70003000 0x0 0x434>; /* Mux registers */
172 }; 174 };
173 175
174 /* 176 /*
@@ -179,9 +181,9 @@
179 * the APB DMA based serial driver, the comptible is 181 * the APB DMA based serial driver, the comptible is
180 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 182 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
181 */ 183 */
182 serial@70006000 { 184 serial@0,70006000 {
183 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 185 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
184 reg = <0x70006000 0x40>; 186 reg = <0x0 0x70006000 0x0 0x40>;
185 reg-shift = <2>; 187 reg-shift = <2>;
186 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 188 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 189 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
@@ -192,9 +194,9 @@
192 status = "disabled"; 194 status = "disabled";
193 }; 195 };
194 196
195 serial@70006040 { 197 serial@0,70006040 {
196 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 198 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
197 reg = <0x70006040 0x40>; 199 reg = <0x0 0x70006040 0x0 0x40>;
198 reg-shift = <2>; 200 reg-shift = <2>;
199 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 201 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 202 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
@@ -205,9 +207,9 @@
205 status = "disabled"; 207 status = "disabled";
206 }; 208 };
207 209
208 serial@70006200 { 210 serial@0,70006200 {
209 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 211 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
210 reg = <0x70006200 0x40>; 212 reg = <0x0 0x70006200 0x0 0x40>;
211 reg-shift = <2>; 213 reg-shift = <2>;
212 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 214 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 215 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
@@ -218,9 +220,9 @@
218 status = "disabled"; 220 status = "disabled";
219 }; 221 };
220 222
221 serial@70006300 { 223 serial@0,70006300 {
222 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 224 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
223 reg = <0x70006300 0x40>; 225 reg = <0x0 0x70006300 0x0 0x40>;
224 reg-shift = <2>; 226 reg-shift = <2>;
225 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 227 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 228 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
@@ -231,9 +233,9 @@
231 status = "disabled"; 233 status = "disabled";
232 }; 234 };
233 235
234 serial@70006400 { 236 serial@0,70006400 {
235 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 237 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
236 reg = <0x70006400 0x40>; 238 reg = <0x0 0x70006400 0x0 0x40>;
237 reg-shift = <2>; 239 reg-shift = <2>;
238 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 240 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&tegra_car TEGRA124_CLK_UARTE>; 241 clocks = <&tegra_car TEGRA124_CLK_UARTE>;
@@ -244,9 +246,9 @@
244 status = "disabled"; 246 status = "disabled";
245 }; 247 };
246 248
247 pwm@7000a000 { 249 pwm@0,7000a000 {
248 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 250 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
249 reg = <0x7000a000 0x100>; 251 reg = <0x0 0x7000a000 0x0 0x100>;
250 #pwm-cells = <2>; 252 #pwm-cells = <2>;
251 clocks = <&tegra_car TEGRA124_CLK_PWM>; 253 clocks = <&tegra_car TEGRA124_CLK_PWM>;
252 resets = <&tegra_car 17>; 254 resets = <&tegra_car 17>;
@@ -254,9 +256,9 @@
254 status = "disabled"; 256 status = "disabled";
255 }; 257 };
256 258
257 i2c@7000c000 { 259 i2c@0,7000c000 {
258 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 260 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
259 reg = <0x7000c000 0x100>; 261 reg = <0x0 0x7000c000 0x0 0x100>;
260 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
261 #address-cells = <1>; 263 #address-cells = <1>;
262 #size-cells = <0>; 264 #size-cells = <0>;
@@ -269,9 +271,9 @@
269 status = "disabled"; 271 status = "disabled";
270 }; 272 };
271 273
272 i2c@7000c400 { 274 i2c@0,7000c400 {
273 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 275 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
274 reg = <0x7000c400 0x100>; 276 reg = <0x0 0x7000c400 0x0 0x100>;
275 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 277 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>; 278 #address-cells = <1>;
277 #size-cells = <0>; 279 #size-cells = <0>;
@@ -284,9 +286,9 @@
284 status = "disabled"; 286 status = "disabled";
285 }; 287 };
286 288
287 i2c@7000c500 { 289 i2c@0,7000c500 {
288 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 290 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
289 reg = <0x7000c500 0x100>; 291 reg = <0x0 0x7000c500 0x0 0x100>;
290 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 292 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
291 #address-cells = <1>; 293 #address-cells = <1>;
292 #size-cells = <0>; 294 #size-cells = <0>;
@@ -299,9 +301,9 @@
299 status = "disabled"; 301 status = "disabled";
300 }; 302 };
301 303
302 i2c@7000c700 { 304 i2c@0,7000c700 {
303 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 305 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
304 reg = <0x7000c700 0x100>; 306 reg = <0x0 0x7000c700 0x0 0x100>;
305 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
306 #address-cells = <1>; 308 #address-cells = <1>;
307 #size-cells = <0>; 309 #size-cells = <0>;
@@ -314,9 +316,9 @@
314 status = "disabled"; 316 status = "disabled";
315 }; 317 };
316 318
317 i2c@7000d000 { 319 i2c@0,7000d000 {
318 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 320 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
319 reg = <0x7000d000 0x100>; 321 reg = <0x0 0x7000d000 0x0 0x100>;
320 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
321 #address-cells = <1>; 323 #address-cells = <1>;
322 #size-cells = <0>; 324 #size-cells = <0>;
@@ -329,9 +331,9 @@
329 status = "disabled"; 331 status = "disabled";
330 }; 332 };
331 333
332 i2c@7000d100 { 334 i2c@0,7000d100 {
333 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c"; 335 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
334 reg = <0x7000d100 0x100>; 336 reg = <0x0 0x7000d100 0x0 0x100>;
335 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 337 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>; 338 #address-cells = <1>;
337 #size-cells = <0>; 339 #size-cells = <0>;
@@ -344,9 +346,9 @@
344 status = "disabled"; 346 status = "disabled";
345 }; 347 };
346 348
347 spi@7000d400 { 349 spi@0,7000d400 {
348 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 350 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
349 reg = <0x7000d400 0x200>; 351 reg = <0x0 0x7000d400 0x0 0x200>;
350 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>; 353 #address-cells = <1>;
352 #size-cells = <0>; 354 #size-cells = <0>;
@@ -359,9 +361,9 @@
359 status = "disabled"; 361 status = "disabled";
360 }; 362 };
361 363
362 spi@7000d600 { 364 spi@0,7000d600 {
363 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 365 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
364 reg = <0x7000d600 0x200>; 366 reg = <0x0 0x7000d600 0x0 0x200>;
365 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
366 #address-cells = <1>; 368 #address-cells = <1>;
367 #size-cells = <0>; 369 #size-cells = <0>;
@@ -374,9 +376,9 @@
374 status = "disabled"; 376 status = "disabled";
375 }; 377 };
376 378
377 spi@7000d800 { 379 spi@0,7000d800 {
378 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 380 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
379 reg = <0x7000d800 0x200>; 381 reg = <0x0 0x7000d800 0x0 0x200>;
380 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 382 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
381 #address-cells = <1>; 383 #address-cells = <1>;
382 #size-cells = <0>; 384 #size-cells = <0>;
@@ -389,9 +391,9 @@
389 status = "disabled"; 391 status = "disabled";
390 }; 392 };
391 393
392 spi@7000da00 { 394 spi@0,7000da00 {
393 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 395 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
394 reg = <0x7000da00 0x200>; 396 reg = <0x0 0x7000da00 0x0 0x200>;
395 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>; 398 #address-cells = <1>;
397 #size-cells = <0>; 399 #size-cells = <0>;
@@ -404,9 +406,9 @@
404 status = "disabled"; 406 status = "disabled";
405 }; 407 };
406 408
407 spi@7000dc00 { 409 spi@0,7000dc00 {
408 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 410 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
409 reg = <0x7000dc00 0x200>; 411 reg = <0x0 0x7000dc00 0x0 0x200>;
410 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 412 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
411 #address-cells = <1>; 413 #address-cells = <1>;
412 #size-cells = <0>; 414 #size-cells = <0>;
@@ -419,9 +421,9 @@
419 status = "disabled"; 421 status = "disabled";
420 }; 422 };
421 423
422 spi@7000de00 { 424 spi@0,7000de00 {
423 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 425 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
424 reg = <0x7000de00 0x200>; 426 reg = <0x0 0x7000de00 0x0 0x200>;
425 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 427 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>; 428 #address-cells = <1>;
427 #size-cells = <0>; 429 #size-cells = <0>;
@@ -434,23 +436,23 @@
434 status = "disabled"; 436 status = "disabled";
435 }; 437 };
436 438
437 rtc@7000e000 { 439 rtc@0,7000e000 {
438 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 440 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
439 reg = <0x7000e000 0x100>; 441 reg = <0x0 0x7000e000 0x0 0x100>;
440 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 442 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&tegra_car TEGRA124_CLK_RTC>; 443 clocks = <&tegra_car TEGRA124_CLK_RTC>;
442 }; 444 };
443 445
444 pmc@7000e400 { 446 pmc@0,7000e400 {
445 compatible = "nvidia,tegra124-pmc"; 447 compatible = "nvidia,tegra124-pmc";
446 reg = <0x7000e400 0x400>; 448 reg = <0x0 0x7000e400 0x0 0x400>;
447 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 449 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
448 clock-names = "pclk", "clk32k_in"; 450 clock-names = "pclk", "clk32k_in";
449 }; 451 };
450 452
451 sdhci@700b0000 { 453 sdhci@0,700b0000 {
452 compatible = "nvidia,tegra124-sdhci"; 454 compatible = "nvidia,tegra124-sdhci";
453 reg = <0x700b0000 0x200>; 455 reg = <0x0 0x700b0000 0x0 0x200>;
454 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 456 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 457 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
456 resets = <&tegra_car 14>; 458 resets = <&tegra_car 14>;
@@ -458,9 +460,9 @@
458 status = "disabled"; 460 status = "disabled";
459 }; 461 };
460 462
461 sdhci@700b0200 { 463 sdhci@0,700b0200 {
462 compatible = "nvidia,tegra124-sdhci"; 464 compatible = "nvidia,tegra124-sdhci";
463 reg = <0x700b0200 0x200>; 465 reg = <0x0 0x700b0200 0x0 0x200>;
464 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 466 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
465 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 467 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
466 resets = <&tegra_car 9>; 468 resets = <&tegra_car 9>;
@@ -468,9 +470,9 @@
468 status = "disabled"; 470 status = "disabled";
469 }; 471 };
470 472
471 sdhci@700b0400 { 473 sdhci@0,700b0400 {
472 compatible = "nvidia,tegra124-sdhci"; 474 compatible = "nvidia,tegra124-sdhci";
473 reg = <0x700b0400 0x200>; 475 reg = <0x0 0x700b0400 0x0 0x200>;
474 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 476 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 477 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
476 resets = <&tegra_car 69>; 478 resets = <&tegra_car 69>;
@@ -478,9 +480,9 @@
478 status = "disabled"; 480 status = "disabled";
479 }; 481 };
480 482
481 sdhci@700b0600 { 483 sdhci@0,700b0600 {
482 compatible = "nvidia,tegra124-sdhci"; 484 compatible = "nvidia,tegra124-sdhci";
483 reg = <0x700b0600 0x200>; 485 reg = <0x0 0x700b0600 0x0 0x200>;
484 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 486 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 487 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
486 resets = <&tegra_car 15>; 488 resets = <&tegra_car 15>;
@@ -488,11 +490,11 @@
488 status = "disabled"; 490 status = "disabled";
489 }; 491 };
490 492
491 ahub@70300000 { 493 ahub@0,70300000 {
492 compatible = "nvidia,tegra124-ahub"; 494 compatible = "nvidia,tegra124-ahub";
493 reg = <0x70300000 0x200>, 495 reg = <0x0 0x70300000 0x0 0x200>,
494 <0x70300800 0x800>, 496 <0x0 0x70300800 0x0 0x800>,
495 <0x70300200 0x600>; 497 <0x0 0x70300200 0x0 0x600>;
496 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 498 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 499 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
498 <&tegra_car TEGRA124_CLK_APBIF>; 500 <&tegra_car TEGRA124_CLK_APBIF>;
@@ -537,12 +539,12 @@
537 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 539 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
538 "rx9", "tx9"; 540 "rx9", "tx9";
539 ranges; 541 ranges;
540 #address-cells = <1>; 542 #address-cells = <2>;
541 #size-cells = <1>; 543 #size-cells = <2>;
542 544
543 tegra_i2s0: i2s@70301000 { 545 tegra_i2s0: i2s@0,70301000 {
544 compatible = "nvidia,tegra124-i2s"; 546 compatible = "nvidia,tegra124-i2s";
545 reg = <0x70301000 0x100>; 547 reg = <0x0 0x70301000 0x0 0x100>;
546 nvidia,ahub-cif-ids = <4 4>; 548 nvidia,ahub-cif-ids = <4 4>;
547 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 549 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
548 resets = <&tegra_car 30>; 550 resets = <&tegra_car 30>;
@@ -550,9 +552,9 @@
550 status = "disabled"; 552 status = "disabled";
551 }; 553 };
552 554
553 tegra_i2s1: i2s@70301100 { 555 tegra_i2s1: i2s@0,70301100 {
554 compatible = "nvidia,tegra124-i2s"; 556 compatible = "nvidia,tegra124-i2s";
555 reg = <0x70301100 0x100>; 557 reg = <0x0 0x70301100 0x0 0x100>;
556 nvidia,ahub-cif-ids = <5 5>; 558 nvidia,ahub-cif-ids = <5 5>;
557 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 559 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
558 resets = <&tegra_car 11>; 560 resets = <&tegra_car 11>;
@@ -560,9 +562,9 @@
560 status = "disabled"; 562 status = "disabled";
561 }; 563 };
562 564
563 tegra_i2s2: i2s@70301200 { 565 tegra_i2s2: i2s@0,70301200 {
564 compatible = "nvidia,tegra124-i2s"; 566 compatible = "nvidia,tegra124-i2s";
565 reg = <0x70301200 0x100>; 567 reg = <0x0 0x70301200 0x0 0x100>;
566 nvidia,ahub-cif-ids = <6 6>; 568 nvidia,ahub-cif-ids = <6 6>;
567 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 569 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
568 resets = <&tegra_car 18>; 570 resets = <&tegra_car 18>;
@@ -570,9 +572,9 @@
570 status = "disabled"; 572 status = "disabled";
571 }; 573 };
572 574
573 tegra_i2s3: i2s@70301300 { 575 tegra_i2s3: i2s@0,70301300 {
574 compatible = "nvidia,tegra124-i2s"; 576 compatible = "nvidia,tegra124-i2s";
575 reg = <0x70301300 0x100>; 577 reg = <0x0 0x70301300 0x0 0x100>;
576 nvidia,ahub-cif-ids = <7 7>; 578 nvidia,ahub-cif-ids = <7 7>;
577 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 579 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
578 resets = <&tegra_car 101>; 580 resets = <&tegra_car 101>;
@@ -580,9 +582,9 @@
580 status = "disabled"; 582 status = "disabled";
581 }; 583 };
582 584
583 tegra_i2s4: i2s@70301400 { 585 tegra_i2s4: i2s@0,70301400 {
584 compatible = "nvidia,tegra124-i2s"; 586 compatible = "nvidia,tegra124-i2s";
585 reg = <0x70301400 0x100>; 587 reg = <0x0 0x70301400 0x0 0x100>;
586 nvidia,ahub-cif-ids = <8 8>; 588 nvidia,ahub-cif-ids = <8 8>;
587 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 589 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
588 resets = <&tegra_car 102>; 590 resets = <&tegra_car 102>;
@@ -591,9 +593,9 @@
591 }; 593 };
592 }; 594 };
593 595
594 usb@7d000000 { 596 usb@0,7d000000 {
595 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 597 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
596 reg = <0x7d000000 0x4000>; 598 reg = <0x0 0x7d000000 0x0 0x4000>;
597 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 599 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
598 phy_type = "utmi"; 600 phy_type = "utmi";
599 clocks = <&tegra_car TEGRA124_CLK_USBD>; 601 clocks = <&tegra_car TEGRA124_CLK_USBD>;
@@ -603,9 +605,10 @@
603 status = "disabled"; 605 status = "disabled";
604 }; 606 };
605 607
606 phy1: usb-phy@7d000000 { 608 phy1: usb-phy@0,7d000000 {
607 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 609 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
608 reg = <0x7d000000 0x4000 0x7d000000 0x4000>; 610 reg = <0x0 0x7d000000 0x0 0x4000>,
611 <0x0 0x7d000000 0x0 0x4000>;
609 phy_type = "utmi"; 612 phy_type = "utmi";
610 clocks = <&tegra_car TEGRA124_CLK_USBD>, 613 clocks = <&tegra_car TEGRA124_CLK_USBD>,
611 <&tegra_car TEGRA124_CLK_PLL_U>, 614 <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -624,9 +627,9 @@
624 status = "disabled"; 627 status = "disabled";
625 }; 628 };
626 629
627 usb@7d004000 { 630 usb@0,7d004000 {
628 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 631 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
629 reg = <0x7d004000 0x4000>; 632 reg = <0x0 0x7d004000 0x0 0x4000>;
630 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 633 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
631 phy_type = "utmi"; 634 phy_type = "utmi";
632 clocks = <&tegra_car TEGRA124_CLK_USB2>; 635 clocks = <&tegra_car TEGRA124_CLK_USB2>;
@@ -636,9 +639,10 @@
636 status = "disabled"; 639 status = "disabled";
637 }; 640 };
638 641
639 phy2: usb-phy@7d004000 { 642 phy2: usb-phy@0,7d004000 {
640 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 643 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
641 reg = <0x7d004000 0x4000 0x7d000000 0x4000>; 644 reg = <0x0 0x7d004000 0x0 0x4000>,
645 <0x0 0x7d000000 0x0 0x4000>;
642 phy_type = "utmi"; 646 phy_type = "utmi";
643 clocks = <&tegra_car TEGRA124_CLK_USB2>, 647 clocks = <&tegra_car TEGRA124_CLK_USB2>,
644 <&tegra_car TEGRA124_CLK_PLL_U>, 648 <&tegra_car TEGRA124_CLK_PLL_U>,
@@ -657,9 +661,9 @@
657 status = "disabled"; 661 status = "disabled";
658 }; 662 };
659 663
660 usb@7d008000 { 664 usb@0,7d008000 {
661 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 665 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
662 reg = <0x7d008000 0x4000>; 666 reg = <0x0 0x7d008000 0x0 0x4000>;
663 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 667 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
664 phy_type = "utmi"; 668 phy_type = "utmi";
665 clocks = <&tegra_car TEGRA124_CLK_USB3>; 669 clocks = <&tegra_car TEGRA124_CLK_USB3>;
@@ -669,9 +673,10 @@
669 status = "disabled"; 673 status = "disabled";
670 }; 674 };
671 675
672 phy3: usb-phy@7d008000 { 676 phy3: usb-phy@0,7d008000 {
673 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 677 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
674 reg = <0x7d008000 0x4000 0x7d000000 0x4000>; 678 reg = <0x0 0x7d008000 0x0 0x4000>,
679 <0x0 0x7d000000 0x0 0x4000>;
675 phy_type = "utmi"; 680 phy_type = "utmi";
676 clocks = <&tegra_car TEGRA124_CLK_USB3>, 681 clocks = <&tegra_car TEGRA124_CLK_USB3>,
677 <&tegra_car TEGRA124_CLK_PLL_U>, 682 <&tegra_car TEGRA124_CLK_PLL_U>,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 13:14:07 -0500