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authorKamil Debski <k.debski@samsung.com>2014-09-11 09:27:20 -0400
committerMauro Carvalho Chehab <mchehab@osg.samsung.com>2014-09-26 05:47:46 -0400
commite2c3be2aff3358e485ed307cc3ad11a9c58c086f (patch)
tree346851ef1bce754b1a632462ad8e5cd39c03673c
parent9aee8b80a8facefb29ad0077fdbcca116f25f6e6 (diff)
[media] s5p-mfc: Fix sparse errors in the MFC driver
The following error: "error: incompatible types in conditional expression (different base types)" was reported multiple times for the s5p-mfc driver. This error was caused by two macro definitions - s5p_mfc_hw_call (in s5p_mfc_common.h) and WRITEL (in s5p_mfc_opr_v6.c). In the former case the macro assumed that all ops return a value, but some ops return void. The solution to this problem was the addition of a s5p_mfc_hw_call_void macro. In the latter case the macro used the ?: construction to check whether the address is non zero. This is not necessary after the driver left the development and debugging cycle, so the READL and WRITEL macros were removed. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc.c46
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_common.h6
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c16
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_dec.c20
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_enc.c26
-rw-r--r--drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c471
6 files changed, 293 insertions, 292 deletions
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc.c b/drivers/media/platform/s5p-mfc/s5p_mfc.c
index d180440ac43e..01e17f47b590 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc.c
@@ -150,10 +150,10 @@ static void s5p_mfc_watchdog_worker(struct work_struct *work)
150 if (!ctx) 150 if (!ctx)
151 continue; 151 continue;
152 ctx->state = MFCINST_ERROR; 152 ctx->state = MFCINST_ERROR;
153 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 153 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
154 &ctx->vq_dst); 154 &ctx->dst_queue, &ctx->vq_dst);
155 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 155 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
156 &ctx->vq_src); 156 &ctx->src_queue, &ctx->vq_src);
157 clear_work_bit(ctx); 157 clear_work_bit(ctx);
158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0); 158 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
159 } 159 }
@@ -327,12 +327,12 @@ static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
327 if (res_change == S5P_FIMV_RES_INCREASE || 327 if (res_change == S5P_FIMV_RES_INCREASE ||
328 res_change == S5P_FIMV_RES_DECREASE) { 328 res_change == S5P_FIMV_RES_DECREASE) {
329 ctx->state = MFCINST_RES_CHANGE_INIT; 329 ctx->state = MFCINST_RES_CHANGE_INIT;
330 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 330 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
331 wake_up_ctx(ctx, reason, err); 331 wake_up_ctx(ctx, reason, err);
332 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 332 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
333 BUG(); 333 BUG();
334 s5p_mfc_clock_off(); 334 s5p_mfc_clock_off();
335 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 335 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
336 return; 336 return;
337 } 337 }
338 if (ctx->dpb_flush_flag) 338 if (ctx->dpb_flush_flag)
@@ -400,7 +400,7 @@ leave_handle_frame:
400 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING) 400 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
401 || ctx->dst_queue_cnt < ctx->pb_count) 401 || ctx->dst_queue_cnt < ctx->pb_count)
402 clear_work_bit(ctx); 402 clear_work_bit(ctx);
403 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 403 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
404 wake_up_ctx(ctx, reason, err); 404 wake_up_ctx(ctx, reason, err);
405 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 405 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
406 BUG(); 406 BUG();
@@ -409,7 +409,7 @@ leave_handle_frame:
409 if (test_bit(0, &dev->enter_suspend)) 409 if (test_bit(0, &dev->enter_suspend))
410 wake_up_dev(dev, reason, err); 410 wake_up_dev(dev, reason, err);
411 else 411 else
412 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 412 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
413} 413}
414 414
415/* Error handling for interrupt */ 415/* Error handling for interrupt */
@@ -435,10 +435,10 @@ static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
435 ctx->state = MFCINST_ERROR; 435 ctx->state = MFCINST_ERROR;
436 /* Mark all dst buffers as having an error */ 436 /* Mark all dst buffers as having an error */
437 spin_lock_irqsave(&dev->irqlock, flags); 437 spin_lock_irqsave(&dev->irqlock, flags);
438 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 438 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
439 &ctx->dst_queue, &ctx->vq_dst); 439 &ctx->dst_queue, &ctx->vq_dst);
440 /* Mark all src buffers as having an error */ 440 /* Mark all src buffers as having an error */
441 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, 441 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
442 &ctx->src_queue, &ctx->vq_src); 442 &ctx->src_queue, &ctx->vq_src);
443 spin_unlock_irqrestore(&dev->irqlock, flags); 443 spin_unlock_irqrestore(&dev->irqlock, flags);
444 wake_up_ctx(ctx, reason, err); 444 wake_up_ctx(ctx, reason, err);
@@ -452,7 +452,7 @@ static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
452 } 452 }
453 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 453 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
454 BUG(); 454 BUG();
455 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 455 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
456 s5p_mfc_clock_off(); 456 s5p_mfc_clock_off();
457 wake_up_dev(dev, reason, err); 457 wake_up_dev(dev, reason, err);
458 return; 458 return;
@@ -476,7 +476,7 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
476 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height, 476 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
477 dev); 477 dev);
478 478
479 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx); 479 s5p_mfc_hw_call_void(dev->mfc_ops, dec_calc_dpb_size, ctx);
480 480
481 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count, 481 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
482 dev); 482 dev);
@@ -503,12 +503,12 @@ static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
503 ctx->head_processed = 1; 503 ctx->head_processed = 1;
504 } 504 }
505 } 505 }
506 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 506 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
507 clear_work_bit(ctx); 507 clear_work_bit(ctx);
508 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 508 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
509 BUG(); 509 BUG();
510 s5p_mfc_clock_off(); 510 s5p_mfc_clock_off();
511 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 511 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
512 wake_up_ctx(ctx, reason, err); 512 wake_up_ctx(ctx, reason, err);
513} 513}
514 514
@@ -523,7 +523,7 @@ static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
523 if (ctx == NULL) 523 if (ctx == NULL)
524 return; 524 return;
525 dev = ctx->dev; 525 dev = ctx->dev;
526 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 526 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
527 ctx->int_type = reason; 527 ctx->int_type = reason;
528 ctx->int_err = err; 528 ctx->int_err = err;
529 ctx->int_cond = 1; 529 ctx->int_cond = 1;
@@ -550,7 +550,7 @@ static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
550 s5p_mfc_clock_off(); 550 s5p_mfc_clock_off();
551 551
552 wake_up(&ctx->queue); 552 wake_up(&ctx->queue);
553 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 553 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
554 } else { 554 } else {
555 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 555 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
556 BUG(); 556 BUG();
@@ -591,7 +591,7 @@ static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx,
591 591
592 s5p_mfc_clock_off(); 592 s5p_mfc_clock_off();
593 wake_up(&ctx->queue); 593 wake_up(&ctx->queue);
594 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 594 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
595} 595}
596 596
597/* Interrupt processing */ 597/* Interrupt processing */
@@ -628,12 +628,12 @@ static irqreturn_t s5p_mfc_irq(int irq, void *priv)
628 if (ctx->c_ops->post_frame_start) { 628 if (ctx->c_ops->post_frame_start) {
629 if (ctx->c_ops->post_frame_start(ctx)) 629 if (ctx->c_ops->post_frame_start(ctx))
630 mfc_err("post_frame_start() failed\n"); 630 mfc_err("post_frame_start() failed\n");
631 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 631 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
632 wake_up_ctx(ctx, reason, err); 632 wake_up_ctx(ctx, reason, err);
633 if (test_and_clear_bit(0, &dev->hw_lock) == 0) 633 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
634 BUG(); 634 BUG();
635 s5p_mfc_clock_off(); 635 s5p_mfc_clock_off();
636 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 636 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
637 } else { 637 } else {
638 s5p_mfc_handle_frame(ctx, reason, err); 638 s5p_mfc_handle_frame(ctx, reason, err);
639 } 639 }
@@ -663,7 +663,7 @@ static irqreturn_t s5p_mfc_irq(int irq, void *priv)
663 case S5P_MFC_R2H_CMD_WAKEUP_RET: 663 case S5P_MFC_R2H_CMD_WAKEUP_RET:
664 if (ctx) 664 if (ctx)
665 clear_work_bit(ctx); 665 clear_work_bit(ctx);
666 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 666 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
667 wake_up_dev(dev, reason, err); 667 wake_up_dev(dev, reason, err);
668 clear_bit(0, &dev->hw_lock); 668 clear_bit(0, &dev->hw_lock);
669 clear_bit(0, &dev->enter_suspend); 669 clear_bit(0, &dev->enter_suspend);
@@ -685,12 +685,12 @@ static irqreturn_t s5p_mfc_irq(int irq, void *priv)
685 685
686 default: 686 default:
687 mfc_debug(2, "Unknown int reason\n"); 687 mfc_debug(2, "Unknown int reason\n");
688 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 688 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
689 } 689 }
690 mfc_debug_leave(); 690 mfc_debug_leave();
691 return IRQ_HANDLED; 691 return IRQ_HANDLED;
692irq_cleanup_hw: 692irq_cleanup_hw:
693 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev); 693 s5p_mfc_hw_call_void(dev->mfc_ops, clear_int_flags, dev);
694 ctx->int_type = reason; 694 ctx->int_type = reason;
695 ctx->int_err = err; 695 ctx->int_err = err;
696 ctx->int_cond = 1; 696 ctx->int_cond = 1;
@@ -699,7 +699,7 @@ irq_cleanup_hw:
699 699
700 s5p_mfc_clock_off(); 700 s5p_mfc_clock_off();
701 701
702 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 702 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
703 mfc_debug(2, "Exit via irq_cleanup_hw\n"); 703 mfc_debug(2, "Exit via irq_cleanup_hw\n");
704 return IRQ_HANDLED; 704 return IRQ_HANDLED;
705} 705}
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
index 01816ffb384b..3e41ca1293ed 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_common.h
@@ -698,6 +698,12 @@ struct mfc_control {
698#define s5p_mfc_hw_call(f, op, args...) \ 698#define s5p_mfc_hw_call(f, op, args...) \
699 ((f && f->op) ? f->op(args) : -ENODEV) 699 ((f && f->op) ? f->op(args) : -ENODEV)
700 700
701#define s5p_mfc_hw_call_void(f, op, args...) \
702do { \
703 if (f && f->op) \
704 f->op(args); \
705} while (0)
706
701#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh) 707#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
702#define ctrl_to_ctx(__ctrl) \ 708#define ctrl_to_ctx(__ctrl) \
703 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler) 709 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
index 23d247d535a0..3c10e31d017b 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
@@ -294,7 +294,7 @@ void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
294 s5p_mfc_clock_on(); 294 s5p_mfc_clock_on();
295 295
296 s5p_mfc_reset(dev); 296 s5p_mfc_reset(dev);
297 s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev); 297 s5p_mfc_hw_call_void(dev->mfc_ops, release_dev_context_buffer, dev);
298 298
299 s5p_mfc_clock_off(); 299 s5p_mfc_clock_off();
300} 300}
@@ -397,7 +397,7 @@ int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
397 397
398 set_work_bit_irqsave(ctx); 398 set_work_bit_irqsave(ctx);
399 s5p_mfc_clean_ctx_int_flags(ctx); 399 s5p_mfc_clean_ctx_int_flags(ctx);
400 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 400 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
401 if (s5p_mfc_wait_for_done_ctx(ctx, 401 if (s5p_mfc_wait_for_done_ctx(ctx,
402 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) { 402 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
403 /* Error or timeout */ 403 /* Error or timeout */
@@ -411,9 +411,9 @@ int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
411 411
412err_free_desc_buf: 412err_free_desc_buf:
413 if (ctx->type == MFCINST_DECODER) 413 if (ctx->type == MFCINST_DECODER)
414 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx); 414 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);
415err_free_inst_buf: 415err_free_inst_buf:
416 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 416 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
417err: 417err:
418 return ret; 418 return ret;
419} 419}
@@ -423,17 +423,17 @@ void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
423 ctx->state = MFCINST_RETURN_INST; 423 ctx->state = MFCINST_RETURN_INST;
424 set_work_bit_irqsave(ctx); 424 set_work_bit_irqsave(ctx);
425 s5p_mfc_clean_ctx_int_flags(ctx); 425 s5p_mfc_clean_ctx_int_flags(ctx);
426 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 426 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
427 /* Wait until instance is returned or timeout occurred */ 427 /* Wait until instance is returned or timeout occurred */
428 if (s5p_mfc_wait_for_done_ctx(ctx, 428 if (s5p_mfc_wait_for_done_ctx(ctx,
429 S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0)) 429 S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
430 mfc_err("Err returning instance\n"); 430 mfc_err("Err returning instance\n");
431 431
432 /* Free resources */ 432 /* Free resources */
433 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 433 s5p_mfc_hw_call_void(dev->mfc_ops, release_codec_buffers, ctx);
434 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx); 434 s5p_mfc_hw_call_void(dev->mfc_ops, release_instance_buffer, ctx);
435 if (ctx->type == MFCINST_DECODER) 435 if (ctx->type == MFCINST_DECODER)
436 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx); 436 s5p_mfc_hw_call_void(dev->mfc_ops, release_dec_desc_buffer, ctx);
437 437
438 ctx->inst_no = MFC_NO_INSTANCE_SET; 438 ctx->inst_no = MFC_NO_INSTANCE_SET;
439 ctx->state = MFCINST_FREE; 439 ctx->state = MFCINST_FREE;
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
index 9e47b969853b..7bfbc38dc20a 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_dec.c
@@ -543,7 +543,7 @@ static int reqbufs_capture(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx,
543 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs); 543 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
544 if (ret) 544 if (ret)
545 goto out; 545 goto out;
546 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx); 546 s5p_mfc_hw_call_void(dev->mfc_ops, release_codec_buffers, ctx);
547 ctx->dst_bufs_cnt = 0; 547 ctx->dst_bufs_cnt = 0;
548 } else if (ctx->capture_state == QUEUE_FREE) { 548 } else if (ctx->capture_state == QUEUE_FREE) {
549 WARN_ON(ctx->dst_bufs_cnt != 0); 549 WARN_ON(ctx->dst_bufs_cnt != 0);
@@ -571,7 +571,7 @@ static int reqbufs_capture(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx,
571 571
572 if (s5p_mfc_ctx_ready(ctx)) 572 if (s5p_mfc_ctx_ready(ctx))
573 set_work_bit_irqsave(ctx); 573 set_work_bit_irqsave(ctx);
574 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 574 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
575 s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_INIT_BUFFERS_RET, 575 s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_INIT_BUFFERS_RET,
576 0); 576 0);
577 } else { 577 } else {
@@ -846,7 +846,7 @@ static int vidioc_decoder_cmd(struct file *file, void *priv,
846 if (s5p_mfc_ctx_ready(ctx)) 846 if (s5p_mfc_ctx_ready(ctx))
847 set_work_bit_irqsave(ctx); 847 set_work_bit_irqsave(ctx);
848 spin_unlock_irqrestore(&dev->irqlock, flags); 848 spin_unlock_irqrestore(&dev->irqlock, flags);
849 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 849 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
850 } else { 850 } else {
851 mfc_err("EOS: marking last buffer of stream"); 851 mfc_err("EOS: marking last buffer of stream");
852 buf = list_entry(ctx->src_queue.prev, 852 buf = list_entry(ctx->src_queue.prev,
@@ -1044,7 +1044,7 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count)
1044 /* If context is ready then dev = work->data;schedule it to run */ 1044 /* If context is ready then dev = work->data;schedule it to run */
1045 if (s5p_mfc_ctx_ready(ctx)) 1045 if (s5p_mfc_ctx_ready(ctx))
1046 set_work_bit_irqsave(ctx); 1046 set_work_bit_irqsave(ctx);
1047 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 1047 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
1048 return 0; 1048 return 0;
1049} 1049}
1050 1050
@@ -1065,8 +1065,8 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q)
1065 } 1065 }
1066 if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { 1066 if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1067 spin_lock_irqsave(&dev->irqlock, flags); 1067 spin_lock_irqsave(&dev->irqlock, flags);
1068 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 1068 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
1069 &ctx->vq_dst); 1069 &ctx->dst_queue, &ctx->vq_dst);
1070 INIT_LIST_HEAD(&ctx->dst_queue); 1070 INIT_LIST_HEAD(&ctx->dst_queue);
1071 ctx->dst_queue_cnt = 0; 1071 ctx->dst_queue_cnt = 0;
1072 ctx->dpb_flush_flag = 1; 1072 ctx->dpb_flush_flag = 1;
@@ -1076,7 +1076,7 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q)
1076 ctx->state = MFCINST_FLUSH; 1076 ctx->state = MFCINST_FLUSH;
1077 set_work_bit_irqsave(ctx); 1077 set_work_bit_irqsave(ctx);
1078 s5p_mfc_clean_ctx_int_flags(ctx); 1078 s5p_mfc_clean_ctx_int_flags(ctx);
1079 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 1079 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
1080 if (s5p_mfc_wait_for_done_ctx(ctx, 1080 if (s5p_mfc_wait_for_done_ctx(ctx,
1081 S5P_MFC_R2H_CMD_DPB_FLUSH_RET, 0)) 1081 S5P_MFC_R2H_CMD_DPB_FLUSH_RET, 0))
1082 mfc_err("Err flushing buffers\n"); 1082 mfc_err("Err flushing buffers\n");
@@ -1084,8 +1084,8 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q)
1084 } 1084 }
1085 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 1085 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1086 spin_lock_irqsave(&dev->irqlock, flags); 1086 spin_lock_irqsave(&dev->irqlock, flags);
1087 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 1087 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
1088 &ctx->vq_src); 1088 &ctx->src_queue, &ctx->vq_src);
1089 INIT_LIST_HEAD(&ctx->src_queue); 1089 INIT_LIST_HEAD(&ctx->src_queue);
1090 ctx->src_queue_cnt = 0; 1090 ctx->src_queue_cnt = 0;
1091 spin_unlock_irqrestore(&dev->irqlock, flags); 1091 spin_unlock_irqrestore(&dev->irqlock, flags);
@@ -1124,7 +1124,7 @@ static void s5p_mfc_buf_queue(struct vb2_buffer *vb)
1124 } 1124 }
1125 if (s5p_mfc_ctx_ready(ctx)) 1125 if (s5p_mfc_ctx_ready(ctx))
1126 set_work_bit_irqsave(ctx); 1126 set_work_bit_irqsave(ctx);
1127 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 1127 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
1128} 1128}
1129 1129
1130static struct vb2_ops s5p_mfc_dec_qops = { 1130static struct vb2_ops s5p_mfc_dec_qops = {
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
index 41f3b7f512fa..4ebfcd647b72 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_enc.c
@@ -767,7 +767,7 @@ static int enc_pre_seq_start(struct s5p_mfc_ctx *ctx)
767 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 767 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
768 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 768 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
769 dst_size = vb2_plane_size(dst_mb->b, 0); 769 dst_size = vb2_plane_size(dst_mb->b, 0);
770 s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr, 770 s5p_mfc_hw_call_void(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
771 dst_size); 771 dst_size);
772 spin_unlock_irqrestore(&dev->irqlock, flags); 772 spin_unlock_irqrestore(&dev->irqlock, flags);
773 return 0; 773 return 0;
@@ -800,7 +800,7 @@ static int enc_post_seq_start(struct s5p_mfc_ctx *ctx)
800 ctx->state = MFCINST_RUNNING; 800 ctx->state = MFCINST_RUNNING;
801 if (s5p_mfc_ctx_ready(ctx)) 801 if (s5p_mfc_ctx_ready(ctx))
802 set_work_bit_irqsave(ctx); 802 set_work_bit_irqsave(ctx);
803 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 803 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
804 } else { 804 } else {
805 enc_pb_count = s5p_mfc_hw_call(dev->mfc_ops, 805 enc_pb_count = s5p_mfc_hw_call(dev->mfc_ops,
806 get_enc_dpb_count, dev); 806 get_enc_dpb_count, dev);
@@ -825,15 +825,15 @@ static int enc_pre_frame_start(struct s5p_mfc_ctx *ctx)
825 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); 825 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
826 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0); 826 src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 0);
827 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1); 827 src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, 1);
828 s5p_mfc_hw_call(dev->mfc_ops, set_enc_frame_buffer, ctx, src_y_addr, 828 s5p_mfc_hw_call_void(dev->mfc_ops, set_enc_frame_buffer, ctx,
829 src_c_addr); 829 src_y_addr, src_c_addr);
830 spin_unlock_irqrestore(&dev->irqlock, flags); 830 spin_unlock_irqrestore(&dev->irqlock, flags);
831 831
832 spin_lock_irqsave(&dev->irqlock, flags); 832 spin_lock_irqsave(&dev->irqlock, flags);
833 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); 833 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
834 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); 834 dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0);
835 dst_size = vb2_plane_size(dst_mb->b, 0); 835 dst_size = vb2_plane_size(dst_mb->b, 0);
836 s5p_mfc_hw_call(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr, 836 s5p_mfc_hw_call_void(dev->mfc_ops, set_enc_stream_buffer, ctx, dst_addr,
837 dst_size); 837 dst_size);
838 spin_unlock_irqrestore(&dev->irqlock, flags); 838 spin_unlock_irqrestore(&dev->irqlock, flags);
839 839
@@ -858,7 +858,7 @@ static int enc_post_frame_start(struct s5p_mfc_ctx *ctx)
858 mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT)); 858 mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT));
859 spin_lock_irqsave(&dev->irqlock, flags); 859 spin_lock_irqsave(&dev->irqlock, flags);
860 if (slice_type >= 0) { 860 if (slice_type >= 0) {
861 s5p_mfc_hw_call(dev->mfc_ops, get_enc_frame_buffer, ctx, 861 s5p_mfc_hw_call_void(dev->mfc_ops, get_enc_frame_buffer, ctx,
862 &enc_y_addr, &enc_c_addr); 862 &enc_y_addr, &enc_c_addr);
863 list_for_each_entry(mb_entry, &ctx->src_queue, list) { 863 list_for_each_entry(mb_entry, &ctx->src_queue, list) {
864 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0); 864 mb_y_addr = vb2_dma_contig_plane_dma_addr(mb_entry->b, 0);
@@ -1124,7 +1124,7 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1124 pix_fmt_mp->width, pix_fmt_mp->height, 1124 pix_fmt_mp->width, pix_fmt_mp->height,
1125 ctx->img_width, ctx->img_height); 1125 ctx->img_width, ctx->img_height);
1126 1126
1127 s5p_mfc_hw_call(dev->mfc_ops, enc_calc_src_size, ctx); 1127 s5p_mfc_hw_call_void(dev->mfc_ops, enc_calc_src_size, ctx);
1128 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size; 1128 pix_fmt_mp->plane_fmt[0].sizeimage = ctx->luma_size;
1129 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width; 1129 pix_fmt_mp->plane_fmt[0].bytesperline = ctx->buf_width;
1130 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size; 1130 pix_fmt_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
@@ -1701,7 +1701,7 @@ static int vidioc_encoder_cmd(struct file *file, void *priv,
1701 if (s5p_mfc_ctx_ready(ctx)) 1701 if (s5p_mfc_ctx_ready(ctx))
1702 set_work_bit_irqsave(ctx); 1702 set_work_bit_irqsave(ctx);
1703 spin_unlock_irqrestore(&dev->irqlock, flags); 1703 spin_unlock_irqrestore(&dev->irqlock, flags);
1704 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 1704 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
1705 } else { 1705 } else {
1706 mfc_debug(2, "EOS: marking last buffer of stream\n"); 1706 mfc_debug(2, "EOS: marking last buffer of stream\n");
1707 buf = list_entry(ctx->src_queue.prev, 1707 buf = list_entry(ctx->src_queue.prev,
@@ -1945,7 +1945,7 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count)
1945 /* If context is ready then dev = work->data;schedule it to run */ 1945 /* If context is ready then dev = work->data;schedule it to run */
1946 if (s5p_mfc_ctx_ready(ctx)) 1946 if (s5p_mfc_ctx_ready(ctx))
1947 set_work_bit_irqsave(ctx); 1947 set_work_bit_irqsave(ctx);
1948 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 1948 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
1949 1949
1950 return 0; 1950 return 0;
1951} 1951}
@@ -1966,14 +1966,14 @@ static void s5p_mfc_stop_streaming(struct vb2_queue *q)
1966 ctx->state = MFCINST_FINISHED; 1966 ctx->state = MFCINST_FINISHED;
1967 spin_lock_irqsave(&dev->irqlock, flags); 1967 spin_lock_irqsave(&dev->irqlock, flags);
1968 if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { 1968 if (q->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
1969 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->dst_queue, 1969 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue,
1970 &ctx->vq_dst); 1970 &ctx->dst_queue, &ctx->vq_dst);
1971 INIT_LIST_HEAD(&ctx->dst_queue); 1971 INIT_LIST_HEAD(&ctx->dst_queue);
1972 ctx->dst_queue_cnt = 0; 1972 ctx->dst_queue_cnt = 0;
1973 } 1973 }
1974 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 1974 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1975 cleanup_ref_queue(ctx); 1975 cleanup_ref_queue(ctx);
1976 s5p_mfc_hw_call(dev->mfc_ops, cleanup_queue, &ctx->src_queue, 1976 s5p_mfc_hw_call_void(dev->mfc_ops, cleanup_queue, &ctx->src_queue,
1977 &ctx->vq_src); 1977 &ctx->vq_src);
1978 INIT_LIST_HEAD(&ctx->src_queue); 1978 INIT_LIST_HEAD(&ctx->src_queue);
1979 ctx->src_queue_cnt = 0; 1979 ctx->src_queue_cnt = 0;
@@ -2014,7 +2014,7 @@ static void s5p_mfc_buf_queue(struct vb2_buffer *vb)
2014 } 2014 }
2015 if (s5p_mfc_ctx_ready(ctx)) 2015 if (s5p_mfc_ctx_ready(ctx))
2016 set_work_bit_irqsave(ctx); 2016 set_work_bit_irqsave(ctx);
2017 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev); 2017 s5p_mfc_hw_call_void(dev->mfc_ops, try_run, dev);
2018} 2018}
2019 2019
2020static struct vb2_ops s5p_mfc_enc_qops = { 2020static struct vb2_ops s5p_mfc_enc_qops = {
diff --git a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
index c1c12f8d8f68..e9d1eaf72682 100644
--- a/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
+++ b/drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
@@ -43,11 +43,6 @@
43 } while (0) 43 } while (0)
44#endif /* S5P_MFC_DEBUG_REGWRITE */ 44#endif /* S5P_MFC_DEBUG_REGWRITE */
45 45
46#define READL(reg) \
47 (WARN_ON_ONCE(!(reg)) ? 0 : readl(reg))
48#define WRITEL(data, reg) \
49 (WARN_ON_ONCE(!(reg)) ? 0 : writel((data), (reg)))
50
51#define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2) 46#define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
52 47
53/* Allocate temporary buffers for decoding */ 48/* Allocate temporary buffers for decoding */
@@ -416,10 +411,10 @@ static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
416 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n" 411 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
417 "buf_size: 0x%08x (%d)\n", 412 "buf_size: 0x%08x (%d)\n",
418 ctx->inst_no, buf_addr, strm_size, strm_size); 413 ctx->inst_no, buf_addr, strm_size, strm_size);
419 WRITEL(strm_size, mfc_regs->d_stream_data_size); 414 writel(strm_size, mfc_regs->d_stream_data_size);
420 WRITEL(buf_addr, mfc_regs->d_cpb_buffer_addr); 415 writel(buf_addr, mfc_regs->d_cpb_buffer_addr);
421 WRITEL(buf_size->cpb, mfc_regs->d_cpb_buffer_size); 416 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
422 WRITEL(start_num_byte, mfc_regs->d_cpb_buffer_offset); 417 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset);
423 418
424 mfc_debug_leave(); 419 mfc_debug_leave();
425 return 0; 420 return 0;
@@ -443,17 +438,17 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
443 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count); 438 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
444 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay); 439 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
445 440
446 WRITEL(ctx->total_dpb_count, mfc_regs->d_num_dpb); 441 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
447 WRITEL(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); 442 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
448 WRITEL(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); 443 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
449 444
450 WRITEL(buf_addr1, mfc_regs->d_scratch_buffer_addr); 445 writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
451 WRITEL(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size); 446 writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
452 447
453 if (IS_MFCV8(dev)) { 448 if (IS_MFCV8(dev)) {
454 WRITEL(ctx->img_width, 449 writel(ctx->img_width,
455 mfc_regs->d_first_plane_dpb_stride_size); 450 mfc_regs->d_first_plane_dpb_stride_size);
456 WRITEL(ctx->img_width, 451 writel(ctx->img_width,
457 mfc_regs->d_second_plane_dpb_stride_size); 452 mfc_regs->d_second_plane_dpb_stride_size);
458 } 453 }
459 454
@@ -462,8 +457,8 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
462 457
463 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC || 458 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
464 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){ 459 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC){
465 WRITEL(ctx->mv_size, mfc_regs->d_mv_buffer_size); 460 writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
466 WRITEL(ctx->mv_count, mfc_regs->d_num_mv); 461 writel(ctx->mv_count, mfc_regs->d_num_mv);
467 } 462 }
468 463
469 frame_size = ctx->luma_size; 464 frame_size = ctx->luma_size;
@@ -476,11 +471,11 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
476 /* Bank2 */ 471 /* Bank2 */
477 mfc_debug(2, "Luma %d: %x\n", i, 472 mfc_debug(2, "Luma %d: %x\n", i,
478 ctx->dst_bufs[i].cookie.raw.luma); 473 ctx->dst_bufs[i].cookie.raw.luma);
479 WRITEL(ctx->dst_bufs[i].cookie.raw.luma, 474 writel(ctx->dst_bufs[i].cookie.raw.luma,
480 mfc_regs->d_first_plane_dpb + i * 4); 475 mfc_regs->d_first_plane_dpb + i * 4);
481 mfc_debug(2, "\tChroma %d: %x\n", i, 476 mfc_debug(2, "\tChroma %d: %x\n", i,
482 ctx->dst_bufs[i].cookie.raw.chroma); 477 ctx->dst_bufs[i].cookie.raw.chroma);
483 WRITEL(ctx->dst_bufs[i].cookie.raw.chroma, 478 writel(ctx->dst_bufs[i].cookie.raw.chroma,
484 mfc_regs->d_second_plane_dpb + i * 4); 479 mfc_regs->d_second_plane_dpb + i * 4);
485 } 480 }
486 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || 481 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
@@ -494,7 +489,7 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
494 489
495 mfc_debug(2, "\tBuf1: %x, size: %d\n", 490 mfc_debug(2, "\tBuf1: %x, size: %d\n",
496 buf_addr1, buf_size1); 491 buf_addr1, buf_size1);
497 WRITEL(buf_addr1, mfc_regs->d_mv_buffer + i * 4); 492 writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
498 buf_addr1 += frame_size_mv; 493 buf_addr1 += frame_size_mv;
499 buf_size1 -= frame_size_mv; 494 buf_size1 -= frame_size_mv;
500 } 495 }
@@ -507,8 +502,8 @@ static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
507 return -ENOMEM; 502 return -ENOMEM;
508 } 503 }
509 504
510 WRITEL(ctx->inst_no, mfc_regs->instance_id); 505 writel(ctx->inst_no, mfc_regs->instance_id);
511 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 506 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
512 S5P_FIMV_CH_INIT_BUFS_V6, NULL); 507 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
513 508
514 mfc_debug(2, "After setting buffers.\n"); 509 mfc_debug(2, "After setting buffers.\n");
@@ -522,8 +517,8 @@ static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
522 struct s5p_mfc_dev *dev = ctx->dev; 517 struct s5p_mfc_dev *dev = ctx->dev;
523 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 518 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
524 519
525 WRITEL(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */ 520 writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
526 WRITEL(size, mfc_regs->e_stream_buffer_size); 521 writel(size, mfc_regs->e_stream_buffer_size);
527 522
528 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n", 523 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%d\n",
529 addr, size); 524 addr, size);
@@ -537,8 +532,8 @@ static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
537 struct s5p_mfc_dev *dev = ctx->dev; 532 struct s5p_mfc_dev *dev = ctx->dev;
538 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 533 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
539 534
540 WRITEL(y_addr, mfc_regs->e_source_first_plane_addr); 535 writel(y_addr, mfc_regs->e_source_first_plane_addr);
541 WRITEL(c_addr, mfc_regs->e_source_second_plane_addr); 536 writel(c_addr, mfc_regs->e_source_second_plane_addr);
542 537
543 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr); 538 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
544 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr); 539 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
@@ -551,11 +546,11 @@ static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
551 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 546 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
552 unsigned long enc_recon_y_addr, enc_recon_c_addr; 547 unsigned long enc_recon_y_addr, enc_recon_c_addr;
553 548
554 *y_addr = READL(mfc_regs->e_encoded_source_first_plane_addr); 549 *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr);
555 *c_addr = READL(mfc_regs->e_encoded_source_second_plane_addr); 550 *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr);
556 551
557 enc_recon_y_addr = READL(mfc_regs->e_recon_luma_dpb_addr); 552 enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr);
558 enc_recon_c_addr = READL(mfc_regs->e_recon_chroma_dpb_addr); 553 enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr);
559 554
560 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr); 555 mfc_debug(2, "recon y addr: 0x%08lx\n", enc_recon_y_addr);
561 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr); 556 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
@@ -577,24 +572,24 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
577 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); 572 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
578 573
579 for (i = 0; i < ctx->pb_count; i++) { 574 for (i = 0; i < ctx->pb_count; i++) {
580 WRITEL(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); 575 writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
581 buf_addr1 += ctx->luma_dpb_size; 576 buf_addr1 += ctx->luma_dpb_size;
582 WRITEL(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); 577 writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
583 buf_addr1 += ctx->chroma_dpb_size; 578 buf_addr1 += ctx->chroma_dpb_size;
584 WRITEL(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); 579 writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
585 buf_addr1 += ctx->me_buffer_size; 580 buf_addr1 += ctx->me_buffer_size;
586 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size + 581 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size +
587 ctx->me_buffer_size); 582 ctx->me_buffer_size);
588 } 583 }
589 584
590 WRITEL(buf_addr1, mfc_regs->e_scratch_buffer_addr); 585 writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
591 WRITEL(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size); 586 writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
592 buf_addr1 += ctx->scratch_buf_size; 587 buf_addr1 += ctx->scratch_buf_size;
593 buf_size1 -= ctx->scratch_buf_size; 588 buf_size1 -= ctx->scratch_buf_size;
594 589
595 WRITEL(buf_addr1, mfc_regs->e_tmv_buffer0); 590 writel(buf_addr1, mfc_regs->e_tmv_buffer0);
596 buf_addr1 += ctx->tmv_buffer_size >> 1; 591 buf_addr1 += ctx->tmv_buffer_size >> 1;
597 WRITEL(buf_addr1, mfc_regs->e_tmv_buffer1); 592 writel(buf_addr1, mfc_regs->e_tmv_buffer1);
598 buf_addr1 += ctx->tmv_buffer_size >> 1; 593 buf_addr1 += ctx->tmv_buffer_size >> 1;
599 buf_size1 -= ctx->tmv_buffer_size; 594 buf_size1 -= ctx->tmv_buffer_size;
600 595
@@ -605,8 +600,8 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
605 return -ENOMEM; 600 return -ENOMEM;
606 } 601 }
607 602
608 WRITEL(ctx->inst_no, mfc_regs->instance_id); 603 writel(ctx->inst_no, mfc_regs->instance_id);
609 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 604 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
610 S5P_FIMV_CH_INIT_BUFS_V6, NULL); 605 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
611 606
612 mfc_debug_leave(); 607 mfc_debug_leave();
@@ -621,15 +616,15 @@ static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
621 616
622 /* multi-slice control */ 617 /* multi-slice control */
623 /* multi-slice MB number or bit size */ 618 /* multi-slice MB number or bit size */
624 WRITEL(ctx->slice_mode, mfc_regs->e_mslice_mode); 619 writel(ctx->slice_mode, mfc_regs->e_mslice_mode);
625 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 620 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
626 WRITEL(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb); 621 writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
627 } else if (ctx->slice_mode == 622 } else if (ctx->slice_mode ==
628 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 623 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
629 WRITEL(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits); 624 writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
630 } else { 625 } else {
631 WRITEL(0x0, mfc_regs->e_mslice_size_mb); 626 writel(0x0, mfc_regs->e_mslice_size_mb);
632 WRITEL(0x0, mfc_regs->e_mslice_size_bits); 627 writel(0x0, mfc_regs->e_mslice_size_bits);
633 } 628 }
634 629
635 return 0; 630 return 0;
@@ -645,21 +640,21 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
645 mfc_debug_enter(); 640 mfc_debug_enter();
646 641
647 /* width */ 642 /* width */
648 WRITEL(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */ 643 writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
649 /* height */ 644 /* height */
650 WRITEL(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */ 645 writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
651 646
652 /* cropped width */ 647 /* cropped width */
653 WRITEL(ctx->img_width, mfc_regs->e_cropped_frame_width); 648 writel(ctx->img_width, mfc_regs->e_cropped_frame_width);
654 /* cropped height */ 649 /* cropped height */
655 WRITEL(ctx->img_height, mfc_regs->e_cropped_frame_height); 650 writel(ctx->img_height, mfc_regs->e_cropped_frame_height);
656 /* cropped offset */ 651 /* cropped offset */
657 WRITEL(0x0, mfc_regs->e_frame_crop_offset); 652 writel(0x0, mfc_regs->e_frame_crop_offset);
658 653
659 /* pictype : IDR period */ 654 /* pictype : IDR period */
660 reg = 0; 655 reg = 0;
661 reg |= p->gop_size & 0xFFFF; 656 reg |= p->gop_size & 0xFFFF;
662 WRITEL(reg, mfc_regs->e_gop_config); 657 writel(reg, mfc_regs->e_gop_config);
663 658
664 /* multi-slice control */ 659 /* multi-slice control */
665 /* multi-slice MB number or bit size */ 660 /* multi-slice MB number or bit size */
@@ -667,65 +662,65 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
667 reg = 0; 662 reg = 0;
668 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { 663 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
669 reg |= (0x1 << 3); 664 reg |= (0x1 << 3);
670 WRITEL(reg, mfc_regs->e_enc_options); 665 writel(reg, mfc_regs->e_enc_options);
671 ctx->slice_size.mb = p->slice_mb; 666 ctx->slice_size.mb = p->slice_mb;
672 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { 667 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
673 reg |= (0x1 << 3); 668 reg |= (0x1 << 3);
674 WRITEL(reg, mfc_regs->e_enc_options); 669 writel(reg, mfc_regs->e_enc_options);
675 ctx->slice_size.bits = p->slice_bit; 670 ctx->slice_size.bits = p->slice_bit;
676 } else { 671 } else {
677 reg &= ~(0x1 << 3); 672 reg &= ~(0x1 << 3);
678 WRITEL(reg, mfc_regs->e_enc_options); 673 writel(reg, mfc_regs->e_enc_options);
679 } 674 }
680 675
681 s5p_mfc_set_slice_mode(ctx); 676 s5p_mfc_set_slice_mode(ctx);
682 677
683 /* cyclic intra refresh */ 678 /* cyclic intra refresh */
684 WRITEL(p->intra_refresh_mb, mfc_regs->e_ir_size); 679 writel(p->intra_refresh_mb, mfc_regs->e_ir_size);
685 reg = READL(mfc_regs->e_enc_options); 680 reg = readl(mfc_regs->e_enc_options);
686 if (p->intra_refresh_mb == 0) 681 if (p->intra_refresh_mb == 0)
687 reg &= ~(0x1 << 4); 682 reg &= ~(0x1 << 4);
688 else 683 else
689 reg |= (0x1 << 4); 684 reg |= (0x1 << 4);
690 WRITEL(reg, mfc_regs->e_enc_options); 685 writel(reg, mfc_regs->e_enc_options);
691 686
692 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */ 687 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
693 reg = READL(mfc_regs->e_enc_options); 688 reg = readl(mfc_regs->e_enc_options);
694 reg &= ~(0x1 << 9); 689 reg &= ~(0x1 << 9);
695 WRITEL(reg, mfc_regs->e_enc_options); 690 writel(reg, mfc_regs->e_enc_options);
696 691
697 /* memory structure cur. frame */ 692 /* memory structure cur. frame */
698 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { 693 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
699 /* 0: Linear, 1: 2D tiled*/ 694 /* 0: Linear, 1: 2D tiled*/
700 reg = READL(mfc_regs->e_enc_options); 695 reg = readl(mfc_regs->e_enc_options);
701 reg &= ~(0x1 << 7); 696 reg &= ~(0x1 << 7);
702 WRITEL(reg, mfc_regs->e_enc_options); 697 writel(reg, mfc_regs->e_enc_options);
703 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 698 /* 0: NV12(CbCr), 1: NV21(CrCb) */
704 WRITEL(0x0, mfc_regs->pixel_format); 699 writel(0x0, mfc_regs->pixel_format);
705 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) { 700 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
706 /* 0: Linear, 1: 2D tiled*/ 701 /* 0: Linear, 1: 2D tiled*/
707 reg = READL(mfc_regs->e_enc_options); 702 reg = readl(mfc_regs->e_enc_options);
708 reg &= ~(0x1 << 7); 703 reg &= ~(0x1 << 7);
709 WRITEL(reg, mfc_regs->e_enc_options); 704 writel(reg, mfc_regs->e_enc_options);
710 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 705 /* 0: NV12(CbCr), 1: NV21(CrCb) */
711 WRITEL(0x1, mfc_regs->pixel_format); 706 writel(0x1, mfc_regs->pixel_format);
712 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) { 707 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
713 /* 0: Linear, 1: 2D tiled*/ 708 /* 0: Linear, 1: 2D tiled*/
714 reg = READL(mfc_regs->e_enc_options); 709 reg = readl(mfc_regs->e_enc_options);
715 reg |= (0x1 << 7); 710 reg |= (0x1 << 7);
716 WRITEL(reg, mfc_regs->e_enc_options); 711 writel(reg, mfc_regs->e_enc_options);
717 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 712 /* 0: NV12(CbCr), 1: NV21(CrCb) */
718 WRITEL(0x0, mfc_regs->pixel_format); 713 writel(0x0, mfc_regs->pixel_format);
719 } 714 }
720 715
721 /* memory structure recon. frame */ 716 /* memory structure recon. frame */
722 /* 0: Linear, 1: 2D tiled */ 717 /* 0: Linear, 1: 2D tiled */
723 reg = READL(mfc_regs->e_enc_options); 718 reg = readl(mfc_regs->e_enc_options);
724 reg |= (0x1 << 8); 719 reg |= (0x1 << 8);
725 WRITEL(reg, mfc_regs->e_enc_options); 720 writel(reg, mfc_regs->e_enc_options);
726 721
727 /* padding control & value */ 722 /* padding control & value */
728 WRITEL(0x0, mfc_regs->e_padding_ctrl); 723 writel(0x0, mfc_regs->e_padding_ctrl);
729 if (p->pad) { 724 if (p->pad) {
730 reg = 0; 725 reg = 0;
731 /** enable */ 726 /** enable */
@@ -736,64 +731,64 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
736 reg |= ((p->pad_cb & 0xFF) << 8); 731 reg |= ((p->pad_cb & 0xFF) << 8);
737 /** y value */ 732 /** y value */
738 reg |= p->pad_luma & 0xFF; 733 reg |= p->pad_luma & 0xFF;
739 WRITEL(reg, mfc_regs->e_padding_ctrl); 734 writel(reg, mfc_regs->e_padding_ctrl);
740 } 735 }
741 736
742 /* rate control config. */ 737 /* rate control config. */
743 reg = 0; 738 reg = 0;
744 /* frame-level rate control */ 739 /* frame-level rate control */
745 reg |= ((p->rc_frame & 0x1) << 9); 740 reg |= ((p->rc_frame & 0x1) << 9);
746 WRITEL(reg, mfc_regs->e_rc_config); 741 writel(reg, mfc_regs->e_rc_config);
747 742
748 /* bit rate */ 743 /* bit rate */
749 if (p->rc_frame) 744 if (p->rc_frame)
750 WRITEL(p->rc_bitrate, 745 writel(p->rc_bitrate,
751 mfc_regs->e_rc_bit_rate); 746 mfc_regs->e_rc_bit_rate);
752 else 747 else
753 WRITEL(1, mfc_regs->e_rc_bit_rate); 748 writel(1, mfc_regs->e_rc_bit_rate);
754 749
755 /* reaction coefficient */ 750 /* reaction coefficient */
756 if (p->rc_frame) { 751 if (p->rc_frame) {
757 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */ 752 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
758 WRITEL(1, mfc_regs->e_rc_mode); 753 writel(1, mfc_regs->e_rc_mode);
759 else /* loose CBR */ 754 else /* loose CBR */
760 WRITEL(2, mfc_regs->e_rc_mode); 755 writel(2, mfc_regs->e_rc_mode);
761 } 756 }
762 757
763 /* seq header ctrl */ 758 /* seq header ctrl */
764 reg = READL(mfc_regs->e_enc_options); 759 reg = readl(mfc_regs->e_enc_options);
765 reg &= ~(0x1 << 2); 760 reg &= ~(0x1 << 2);
766 reg |= ((p->seq_hdr_mode & 0x1) << 2); 761 reg |= ((p->seq_hdr_mode & 0x1) << 2);
767 762
768 /* frame skip mode */ 763 /* frame skip mode */
769 reg &= ~(0x3); 764 reg &= ~(0x3);
770 reg |= (p->frame_skip_mode & 0x3); 765 reg |= (p->frame_skip_mode & 0x3);
771 WRITEL(reg, mfc_regs->e_enc_options); 766 writel(reg, mfc_regs->e_enc_options);
772 767
773 /* 'DROP_CONTROL_ENABLE', disable */ 768 /* 'DROP_CONTROL_ENABLE', disable */
774 reg = READL(mfc_regs->e_rc_config); 769 reg = readl(mfc_regs->e_rc_config);
775 reg &= ~(0x1 << 10); 770 reg &= ~(0x1 << 10);
776 WRITEL(reg, mfc_regs->e_rc_config); 771 writel(reg, mfc_regs->e_rc_config);
777 772
778 /* setting for MV range [16, 256] */ 773 /* setting for MV range [16, 256] */
779 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK); 774 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
780 WRITEL(reg, mfc_regs->e_mv_hor_range); 775 writel(reg, mfc_regs->e_mv_hor_range);
781 776
782 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK); 777 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
783 WRITEL(reg, mfc_regs->e_mv_ver_range); 778 writel(reg, mfc_regs->e_mv_ver_range);
784 779
785 WRITEL(0x0, mfc_regs->e_frame_insertion); 780 writel(0x0, mfc_regs->e_frame_insertion);
786 WRITEL(0x0, mfc_regs->e_roi_buffer_addr); 781 writel(0x0, mfc_regs->e_roi_buffer_addr);
787 WRITEL(0x0, mfc_regs->e_param_change); 782 writel(0x0, mfc_regs->e_param_change);
788 WRITEL(0x0, mfc_regs->e_rc_roi_ctrl); 783 writel(0x0, mfc_regs->e_rc_roi_ctrl);
789 WRITEL(0x0, mfc_regs->e_picture_tag); 784 writel(0x0, mfc_regs->e_picture_tag);
790 785
791 WRITEL(0x0, mfc_regs->e_bit_count_enable); 786 writel(0x0, mfc_regs->e_bit_count_enable);
792 WRITEL(0x0, mfc_regs->e_max_bit_count); 787 writel(0x0, mfc_regs->e_max_bit_count);
793 WRITEL(0x0, mfc_regs->e_min_bit_count); 788 writel(0x0, mfc_regs->e_min_bit_count);
794 789
795 WRITEL(0x0, mfc_regs->e_metadata_buffer_addr); 790 writel(0x0, mfc_regs->e_metadata_buffer_addr);
796 WRITEL(0x0, mfc_regs->e_metadata_buffer_size); 791 writel(0x0, mfc_regs->e_metadata_buffer_size);
797 792
798 mfc_debug_leave(); 793 mfc_debug_leave();
799 794
@@ -814,10 +809,10 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
814 s5p_mfc_set_enc_params(ctx); 809 s5p_mfc_set_enc_params(ctx);
815 810
816 /* pictype : number of B */ 811 /* pictype : number of B */
817 reg = READL(mfc_regs->e_gop_config); 812 reg = readl(mfc_regs->e_gop_config);
818 reg &= ~(0x3 << 16); 813 reg &= ~(0x3 << 16);
819 reg |= ((p->num_b_frame & 0x3) << 16); 814 reg |= ((p->num_b_frame & 0x3) << 16);
820 WRITEL(reg, mfc_regs->e_gop_config); 815 writel(reg, mfc_regs->e_gop_config);
821 816
822 /* profile & level */ 817 /* profile & level */
823 reg = 0; 818 reg = 0;
@@ -825,19 +820,19 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
825 reg |= ((p_h264->level & 0xFF) << 8); 820 reg |= ((p_h264->level & 0xFF) << 8);
826 /** profile - 0 ~ 3 */ 821 /** profile - 0 ~ 3 */
827 reg |= p_h264->profile & 0x3F; 822 reg |= p_h264->profile & 0x3F;
828 WRITEL(reg, mfc_regs->e_picture_profile); 823 writel(reg, mfc_regs->e_picture_profile);
829 824
830 /* rate control config. */ 825 /* rate control config. */
831 reg = READL(mfc_regs->e_rc_config); 826 reg = readl(mfc_regs->e_rc_config);
832 /** macroblock level rate control */ 827 /** macroblock level rate control */
833 reg &= ~(0x1 << 8); 828 reg &= ~(0x1 << 8);
834 reg |= ((p->rc_mb & 0x1) << 8); 829 reg |= ((p->rc_mb & 0x1) << 8);
835 WRITEL(reg, mfc_regs->e_rc_config); 830 writel(reg, mfc_regs->e_rc_config);
836 831
837 /** frame QP */ 832 /** frame QP */
838 reg &= ~(0x3F); 833 reg &= ~(0x3F);
839 reg |= p_h264->rc_frame_qp & 0x3F; 834 reg |= p_h264->rc_frame_qp & 0x3F;
840 WRITEL(reg, mfc_regs->e_rc_config); 835 writel(reg, mfc_regs->e_rc_config);
841 836
842 /* max & min value of QP */ 837 /* max & min value of QP */
843 reg = 0; 838 reg = 0;
@@ -845,16 +840,16 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
845 reg |= ((p_h264->rc_max_qp & 0x3F) << 8); 840 reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
846 /** min QP */ 841 /** min QP */
847 reg |= p_h264->rc_min_qp & 0x3F; 842 reg |= p_h264->rc_min_qp & 0x3F;
848 WRITEL(reg, mfc_regs->e_rc_qp_bound); 843 writel(reg, mfc_regs->e_rc_qp_bound);
849 844
850 /* other QPs */ 845 /* other QPs */
851 WRITEL(0x0, mfc_regs->e_fixed_picture_qp); 846 writel(0x0, mfc_regs->e_fixed_picture_qp);
852 if (!p->rc_frame && !p->rc_mb) { 847 if (!p->rc_frame && !p->rc_mb) {
853 reg = 0; 848 reg = 0;
854 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16); 849 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
855 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8); 850 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
856 reg |= p_h264->rc_frame_qp & 0x3F; 851 reg |= p_h264->rc_frame_qp & 0x3F;
857 WRITEL(reg, mfc_regs->e_fixed_picture_qp); 852 writel(reg, mfc_regs->e_fixed_picture_qp);
858 } 853 }
859 854
860 /* frame rate */ 855 /* frame rate */
@@ -862,38 +857,38 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
862 reg = 0; 857 reg = 0;
863 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 858 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
864 reg |= p->rc_framerate_denom & 0xFFFF; 859 reg |= p->rc_framerate_denom & 0xFFFF;
865 WRITEL(reg, mfc_regs->e_rc_frame_rate); 860 writel(reg, mfc_regs->e_rc_frame_rate);
866 } 861 }
867 862
868 /* vbv buffer size */ 863 /* vbv buffer size */
869 if (p->frame_skip_mode == 864 if (p->frame_skip_mode ==
870 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 865 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
871 WRITEL(p_h264->cpb_size & 0xFFFF, 866 writel(p_h264->cpb_size & 0xFFFF,
872 mfc_regs->e_vbv_buffer_size); 867 mfc_regs->e_vbv_buffer_size);
873 868
874 if (p->rc_frame) 869 if (p->rc_frame)
875 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); 870 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
876 } 871 }
877 872
878 /* interlace */ 873 /* interlace */
879 reg = 0; 874 reg = 0;
880 reg |= ((p_h264->interlace & 0x1) << 3); 875 reg |= ((p_h264->interlace & 0x1) << 3);
881 WRITEL(reg, mfc_regs->e_h264_options); 876 writel(reg, mfc_regs->e_h264_options);
882 877
883 /* height */ 878 /* height */
884 if (p_h264->interlace) { 879 if (p_h264->interlace) {
885 WRITEL(ctx->img_height >> 1, 880 writel(ctx->img_height >> 1,
886 mfc_regs->e_frame_height); /* 32 align */ 881 mfc_regs->e_frame_height); /* 32 align */
887 /* cropped height */ 882 /* cropped height */
888 WRITEL(ctx->img_height >> 1, 883 writel(ctx->img_height >> 1,
889 mfc_regs->e_cropped_frame_height); 884 mfc_regs->e_cropped_frame_height);
890 } 885 }
891 886
892 /* loop filter ctrl */ 887 /* loop filter ctrl */
893 reg = READL(mfc_regs->e_h264_options); 888 reg = readl(mfc_regs->e_h264_options);
894 reg &= ~(0x3 << 1); 889 reg &= ~(0x3 << 1);
895 reg |= ((p_h264->loop_filter_mode & 0x3) << 1); 890 reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
896 WRITEL(reg, mfc_regs->e_h264_options); 891 writel(reg, mfc_regs->e_h264_options);
897 892
898 /* loopfilter alpha offset */ 893 /* loopfilter alpha offset */
899 if (p_h264->loop_filter_alpha < 0) { 894 if (p_h264->loop_filter_alpha < 0) {
@@ -903,7 +898,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
903 reg = 0x00; 898 reg = 0x00;
904 reg |= (p_h264->loop_filter_alpha & 0xF); 899 reg |= (p_h264->loop_filter_alpha & 0xF);
905 } 900 }
906 WRITEL(reg, mfc_regs->e_h264_lf_alpha_offset); 901 writel(reg, mfc_regs->e_h264_lf_alpha_offset);
907 902
908 /* loopfilter beta offset */ 903 /* loopfilter beta offset */
909 if (p_h264->loop_filter_beta < 0) { 904 if (p_h264->loop_filter_beta < 0) {
@@ -913,28 +908,28 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
913 reg = 0x00; 908 reg = 0x00;
914 reg |= (p_h264->loop_filter_beta & 0xF); 909 reg |= (p_h264->loop_filter_beta & 0xF);
915 } 910 }
916 WRITEL(reg, mfc_regs->e_h264_lf_beta_offset); 911 writel(reg, mfc_regs->e_h264_lf_beta_offset);
917 912
918 /* entropy coding mode */ 913 /* entropy coding mode */
919 reg = READL(mfc_regs->e_h264_options); 914 reg = readl(mfc_regs->e_h264_options);
920 reg &= ~(0x1); 915 reg &= ~(0x1);
921 reg |= p_h264->entropy_mode & 0x1; 916 reg |= p_h264->entropy_mode & 0x1;
922 WRITEL(reg, mfc_regs->e_h264_options); 917 writel(reg, mfc_regs->e_h264_options);
923 918
924 /* number of ref. picture */ 919 /* number of ref. picture */
925 reg = READL(mfc_regs->e_h264_options); 920 reg = readl(mfc_regs->e_h264_options);
926 reg &= ~(0x1 << 7); 921 reg &= ~(0x1 << 7);
927 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7); 922 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
928 WRITEL(reg, mfc_regs->e_h264_options); 923 writel(reg, mfc_regs->e_h264_options);
929 924
930 /* 8x8 transform enable */ 925 /* 8x8 transform enable */
931 reg = READL(mfc_regs->e_h264_options); 926 reg = readl(mfc_regs->e_h264_options);
932 reg &= ~(0x3 << 12); 927 reg &= ~(0x3 << 12);
933 reg |= ((p_h264->_8x8_transform & 0x3) << 12); 928 reg |= ((p_h264->_8x8_transform & 0x3) << 12);
934 WRITEL(reg, mfc_regs->e_h264_options); 929 writel(reg, mfc_regs->e_h264_options);
935 930
936 /* macroblock adaptive scaling features */ 931 /* macroblock adaptive scaling features */
937 WRITEL(0x0, mfc_regs->e_mb_rc_config); 932 writel(0x0, mfc_regs->e_mb_rc_config);
938 if (p->rc_mb) { 933 if (p->rc_mb) {
939 reg = 0; 934 reg = 0;
940 /** dark region */ 935 /** dark region */
@@ -945,95 +940,95 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
945 reg |= ((p_h264->rc_mb_static & 0x1) << 1); 940 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
946 /** high activity region */ 941 /** high activity region */
947 reg |= p_h264->rc_mb_activity & 0x1; 942 reg |= p_h264->rc_mb_activity & 0x1;
948 WRITEL(reg, mfc_regs->e_mb_rc_config); 943 writel(reg, mfc_regs->e_mb_rc_config);
949 } 944 }
950 945
951 /* aspect ratio VUI */ 946 /* aspect ratio VUI */
952 READL(mfc_regs->e_h264_options); 947 readl(mfc_regs->e_h264_options);
953 reg &= ~(0x1 << 5); 948 reg &= ~(0x1 << 5);
954 reg |= ((p_h264->vui_sar & 0x1) << 5); 949 reg |= ((p_h264->vui_sar & 0x1) << 5);
955 WRITEL(reg, mfc_regs->e_h264_options); 950 writel(reg, mfc_regs->e_h264_options);
956 951
957 WRITEL(0x0, mfc_regs->e_aspect_ratio); 952 writel(0x0, mfc_regs->e_aspect_ratio);
958 WRITEL(0x0, mfc_regs->e_extended_sar); 953 writel(0x0, mfc_regs->e_extended_sar);
959 if (p_h264->vui_sar) { 954 if (p_h264->vui_sar) {
960 /* aspect ration IDC */ 955 /* aspect ration IDC */
961 reg = 0; 956 reg = 0;
962 reg |= p_h264->vui_sar_idc & 0xFF; 957 reg |= p_h264->vui_sar_idc & 0xFF;
963 WRITEL(reg, mfc_regs->e_aspect_ratio); 958 writel(reg, mfc_regs->e_aspect_ratio);
964 if (p_h264->vui_sar_idc == 0xFF) { 959 if (p_h264->vui_sar_idc == 0xFF) {
965 /* extended SAR */ 960 /* extended SAR */
966 reg = 0; 961 reg = 0;
967 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16; 962 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
968 reg |= p_h264->vui_ext_sar_height & 0xFFFF; 963 reg |= p_h264->vui_ext_sar_height & 0xFFFF;
969 WRITEL(reg, mfc_regs->e_extended_sar); 964 writel(reg, mfc_regs->e_extended_sar);
970 } 965 }
971 } 966 }
972 967
973 /* intra picture period for H.264 open GOP */ 968 /* intra picture period for H.264 open GOP */
974 /* control */ 969 /* control */
975 READL(mfc_regs->e_h264_options); 970 readl(mfc_regs->e_h264_options);
976 reg &= ~(0x1 << 4); 971 reg &= ~(0x1 << 4);
977 reg |= ((p_h264->open_gop & 0x1) << 4); 972 reg |= ((p_h264->open_gop & 0x1) << 4);
978 WRITEL(reg, mfc_regs->e_h264_options); 973 writel(reg, mfc_regs->e_h264_options);
979 974
980 /* value */ 975 /* value */
981 WRITEL(0x0, mfc_regs->e_h264_i_period); 976 writel(0x0, mfc_regs->e_h264_i_period);
982 if (p_h264->open_gop) { 977 if (p_h264->open_gop) {
983 reg = 0; 978 reg = 0;
984 reg |= p_h264->open_gop_size & 0xFFFF; 979 reg |= p_h264->open_gop_size & 0xFFFF;
985 WRITEL(reg, mfc_regs->e_h264_i_period); 980 writel(reg, mfc_regs->e_h264_i_period);
986 } 981 }
987 982
988 /* 'WEIGHTED_BI_PREDICTION' for B is disable */ 983 /* 'WEIGHTED_BI_PREDICTION' for B is disable */
989 READL(mfc_regs->e_h264_options); 984 readl(mfc_regs->e_h264_options);
990 reg &= ~(0x3 << 9); 985 reg &= ~(0x3 << 9);
991 WRITEL(reg, mfc_regs->e_h264_options); 986 writel(reg, mfc_regs->e_h264_options);
992 987
993 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */ 988 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
994 READL(mfc_regs->e_h264_options); 989 readl(mfc_regs->e_h264_options);
995 reg &= ~(0x1 << 14); 990 reg &= ~(0x1 << 14);
996 WRITEL(reg, mfc_regs->e_h264_options); 991 writel(reg, mfc_regs->e_h264_options);
997 992
998 /* ASO */ 993 /* ASO */
999 READL(mfc_regs->e_h264_options); 994 readl(mfc_regs->e_h264_options);
1000 reg &= ~(0x1 << 6); 995 reg &= ~(0x1 << 6);
1001 reg |= ((p_h264->aso & 0x1) << 6); 996 reg |= ((p_h264->aso & 0x1) << 6);
1002 WRITEL(reg, mfc_regs->e_h264_options); 997 writel(reg, mfc_regs->e_h264_options);
1003 998
1004 /* hier qp enable */ 999 /* hier qp enable */
1005 READL(mfc_regs->e_h264_options); 1000 readl(mfc_regs->e_h264_options);
1006 reg &= ~(0x1 << 8); 1001 reg &= ~(0x1 << 8);
1007 reg |= ((p_h264->open_gop & 0x1) << 8); 1002 reg |= ((p_h264->open_gop & 0x1) << 8);
1008 WRITEL(reg, mfc_regs->e_h264_options); 1003 writel(reg, mfc_regs->e_h264_options);
1009 reg = 0; 1004 reg = 0;
1010 if (p_h264->hier_qp && p_h264->hier_qp_layer) { 1005 if (p_h264->hier_qp && p_h264->hier_qp_layer) {
1011 reg |= (p_h264->hier_qp_type & 0x1) << 0x3; 1006 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
1012 reg |= p_h264->hier_qp_layer & 0x7; 1007 reg |= p_h264->hier_qp_layer & 0x7;
1013 WRITEL(reg, mfc_regs->e_h264_num_t_layer); 1008 writel(reg, mfc_regs->e_h264_num_t_layer);
1014 /* QP value for each layer */ 1009 /* QP value for each layer */
1015 for (i = 0; i < p_h264->hier_qp_layer && 1010 for (i = 0; i < p_h264->hier_qp_layer &&
1016 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) { 1011 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
1017 WRITEL(p_h264->hier_qp_layer_qp[i], 1012 writel(p_h264->hier_qp_layer_qp[i],
1018 mfc_regs->e_h264_hierarchical_qp_layer0 1013 mfc_regs->e_h264_hierarchical_qp_layer0
1019 + i * 4); 1014 + i * 4);
1020 } 1015 }
1021 } 1016 }
1022 /* number of coding layer should be zero when hierarchical is disable */ 1017 /* number of coding layer should be zero when hierarchical is disable */
1023 WRITEL(reg, mfc_regs->e_h264_num_t_layer); 1018 writel(reg, mfc_regs->e_h264_num_t_layer);
1024 1019
1025 /* frame packing SEI generation */ 1020 /* frame packing SEI generation */
1026 READL(mfc_regs->e_h264_options); 1021 readl(mfc_regs->e_h264_options);
1027 reg &= ~(0x1 << 25); 1022 reg &= ~(0x1 << 25);
1028 reg |= ((p_h264->sei_frame_packing & 0x1) << 25); 1023 reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
1029 WRITEL(reg, mfc_regs->e_h264_options); 1024 writel(reg, mfc_regs->e_h264_options);
1030 if (p_h264->sei_frame_packing) { 1025 if (p_h264->sei_frame_packing) {
1031 reg = 0; 1026 reg = 0;
1032 /** current frame0 flag */ 1027 /** current frame0 flag */
1033 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2); 1028 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
1034 /** arrangement type */ 1029 /** arrangement type */
1035 reg |= p_h264->sei_fp_arrangement_type & 0x3; 1030 reg |= p_h264->sei_fp_arrangement_type & 0x3;
1036 WRITEL(reg, mfc_regs->e_h264_frame_packing_sei_info); 1031 writel(reg, mfc_regs->e_h264_frame_packing_sei_info);
1037 } 1032 }
1038 1033
1039 if (p_h264->fmo) { 1034 if (p_h264->fmo) {
@@ -1042,7 +1037,7 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1042 if (p_h264->fmo_slice_grp > 4) 1037 if (p_h264->fmo_slice_grp > 4)
1043 p_h264->fmo_slice_grp = 4; 1038 p_h264->fmo_slice_grp = 4;
1044 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++) 1039 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
1045 WRITEL(p_h264->fmo_run_len[i] - 1, 1040 writel(p_h264->fmo_run_len[i] - 1,
1046 mfc_regs->e_h264_fmo_run_length_minus1_0 1041 mfc_regs->e_h264_fmo_run_length_minus1_0
1047 + i * 4); 1042 + i * 4);
1048 break; 1043 break;
@@ -1054,10 +1049,10 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1054 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN: 1049 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1055 if (p_h264->fmo_slice_grp > 2) 1050 if (p_h264->fmo_slice_grp > 2)
1056 p_h264->fmo_slice_grp = 2; 1051 p_h264->fmo_slice_grp = 2;
1057 WRITEL(p_h264->fmo_chg_dir & 0x1, 1052 writel(p_h264->fmo_chg_dir & 0x1,
1058 mfc_regs->e_h264_fmo_slice_grp_change_dir); 1053 mfc_regs->e_h264_fmo_slice_grp_change_dir);
1059 /* the valid range is 0 ~ number of macroblocks -1 */ 1054 /* the valid range is 0 ~ number of macroblocks -1 */
1060 WRITEL(p_h264->fmo_chg_rate, 1055 writel(p_h264->fmo_chg_rate,
1061 mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1); 1056 mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1062 break; 1057 break;
1063 default: 1058 default:
@@ -1068,12 +1063,12 @@ static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1068 break; 1063 break;
1069 } 1064 }
1070 1065
1071 WRITEL(p_h264->fmo_map_type, 1066 writel(p_h264->fmo_map_type,
1072 mfc_regs->e_h264_fmo_slice_grp_map_type); 1067 mfc_regs->e_h264_fmo_slice_grp_map_type);
1073 WRITEL(p_h264->fmo_slice_grp - 1, 1068 writel(p_h264->fmo_slice_grp - 1,
1074 mfc_regs->e_h264_fmo_num_slice_grp_minus1); 1069 mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1075 } else { 1070 } else {
1076 WRITEL(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1); 1071 writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1077 } 1072 }
1078 1073
1079 mfc_debug_leave(); 1074 mfc_debug_leave();
@@ -1094,10 +1089,10 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1094 s5p_mfc_set_enc_params(ctx); 1089 s5p_mfc_set_enc_params(ctx);
1095 1090
1096 /* pictype : number of B */ 1091 /* pictype : number of B */
1097 reg = READL(mfc_regs->e_gop_config); 1092 reg = readl(mfc_regs->e_gop_config);
1098 reg &= ~(0x3 << 16); 1093 reg &= ~(0x3 << 16);
1099 reg |= ((p->num_b_frame & 0x3) << 16); 1094 reg |= ((p->num_b_frame & 0x3) << 16);
1100 WRITEL(reg, mfc_regs->e_gop_config); 1095 writel(reg, mfc_regs->e_gop_config);
1101 1096
1102 /* profile & level */ 1097 /* profile & level */
1103 reg = 0; 1098 reg = 0;
@@ -1105,19 +1100,19 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1105 reg |= ((p_mpeg4->level & 0xFF) << 8); 1100 reg |= ((p_mpeg4->level & 0xFF) << 8);
1106 /** profile - 0 ~ 1 */ 1101 /** profile - 0 ~ 1 */
1107 reg |= p_mpeg4->profile & 0x3F; 1102 reg |= p_mpeg4->profile & 0x3F;
1108 WRITEL(reg, mfc_regs->e_picture_profile); 1103 writel(reg, mfc_regs->e_picture_profile);
1109 1104
1110 /* rate control config. */ 1105 /* rate control config. */
1111 reg = READL(mfc_regs->e_rc_config); 1106 reg = readl(mfc_regs->e_rc_config);
1112 /** macroblock level rate control */ 1107 /** macroblock level rate control */
1113 reg &= ~(0x1 << 8); 1108 reg &= ~(0x1 << 8);
1114 reg |= ((p->rc_mb & 0x1) << 8); 1109 reg |= ((p->rc_mb & 0x1) << 8);
1115 WRITEL(reg, mfc_regs->e_rc_config); 1110 writel(reg, mfc_regs->e_rc_config);
1116 1111
1117 /** frame QP */ 1112 /** frame QP */
1118 reg &= ~(0x3F); 1113 reg &= ~(0x3F);
1119 reg |= p_mpeg4->rc_frame_qp & 0x3F; 1114 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1120 WRITEL(reg, mfc_regs->e_rc_config); 1115 writel(reg, mfc_regs->e_rc_config);
1121 1116
1122 /* max & min value of QP */ 1117 /* max & min value of QP */
1123 reg = 0; 1118 reg = 0;
@@ -1125,16 +1120,16 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1125 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8); 1120 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1126 /** min QP */ 1121 /** min QP */
1127 reg |= p_mpeg4->rc_min_qp & 0x3F; 1122 reg |= p_mpeg4->rc_min_qp & 0x3F;
1128 WRITEL(reg, mfc_regs->e_rc_qp_bound); 1123 writel(reg, mfc_regs->e_rc_qp_bound);
1129 1124
1130 /* other QPs */ 1125 /* other QPs */
1131 WRITEL(0x0, mfc_regs->e_fixed_picture_qp); 1126 writel(0x0, mfc_regs->e_fixed_picture_qp);
1132 if (!p->rc_frame && !p->rc_mb) { 1127 if (!p->rc_frame && !p->rc_mb) {
1133 reg = 0; 1128 reg = 0;
1134 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16); 1129 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1135 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8); 1130 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1136 reg |= p_mpeg4->rc_frame_qp & 0x3F; 1131 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1137 WRITEL(reg, mfc_regs->e_fixed_picture_qp); 1132 writel(reg, mfc_regs->e_fixed_picture_qp);
1138 } 1133 }
1139 1134
1140 /* frame rate */ 1135 /* frame rate */
@@ -1142,21 +1137,21 @@ static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1142 reg = 0; 1137 reg = 0;
1143 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1138 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1144 reg |= p->rc_framerate_denom & 0xFFFF; 1139 reg |= p->rc_framerate_denom & 0xFFFF;
1145 WRITEL(reg, mfc_regs->e_rc_frame_rate); 1140 writel(reg, mfc_regs->e_rc_frame_rate);
1146 } 1141 }
1147 1142
1148 /* vbv buffer size */ 1143 /* vbv buffer size */
1149 if (p->frame_skip_mode == 1144 if (p->frame_skip_mode ==
1150 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1145 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1151 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); 1146 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1152 1147
1153 if (p->rc_frame) 1148 if (p->rc_frame)
1154 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); 1149 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1155 } 1150 }
1156 1151
1157 /* Disable HEC */ 1152 /* Disable HEC */
1158 WRITEL(0x0, mfc_regs->e_mpeg4_options); 1153 writel(0x0, mfc_regs->e_mpeg4_options);
1159 WRITEL(0x0, mfc_regs->e_mpeg4_hec_period); 1154 writel(0x0, mfc_regs->e_mpeg4_hec_period);
1160 1155
1161 mfc_debug_leave(); 1156 mfc_debug_leave();
1162 1157
@@ -1179,19 +1174,19 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1179 reg = 0; 1174 reg = 0;
1180 /** profile */ 1175 /** profile */
1181 reg |= (0x1 << 4); 1176 reg |= (0x1 << 4);
1182 WRITEL(reg, mfc_regs->e_picture_profile); 1177 writel(reg, mfc_regs->e_picture_profile);
1183 1178
1184 /* rate control config. */ 1179 /* rate control config. */
1185 reg = READL(mfc_regs->e_rc_config); 1180 reg = readl(mfc_regs->e_rc_config);
1186 /** macroblock level rate control */ 1181 /** macroblock level rate control */
1187 reg &= ~(0x1 << 8); 1182 reg &= ~(0x1 << 8);
1188 reg |= ((p->rc_mb & 0x1) << 8); 1183 reg |= ((p->rc_mb & 0x1) << 8);
1189 WRITEL(reg, mfc_regs->e_rc_config); 1184 writel(reg, mfc_regs->e_rc_config);
1190 1185
1191 /** frame QP */ 1186 /** frame QP */
1192 reg &= ~(0x3F); 1187 reg &= ~(0x3F);
1193 reg |= p_h263->rc_frame_qp & 0x3F; 1188 reg |= p_h263->rc_frame_qp & 0x3F;
1194 WRITEL(reg, mfc_regs->e_rc_config); 1189 writel(reg, mfc_regs->e_rc_config);
1195 1190
1196 /* max & min value of QP */ 1191 /* max & min value of QP */
1197 reg = 0; 1192 reg = 0;
@@ -1199,16 +1194,16 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1199 reg |= ((p_h263->rc_max_qp & 0x3F) << 8); 1194 reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1200 /** min QP */ 1195 /** min QP */
1201 reg |= p_h263->rc_min_qp & 0x3F; 1196 reg |= p_h263->rc_min_qp & 0x3F;
1202 WRITEL(reg, mfc_regs->e_rc_qp_bound); 1197 writel(reg, mfc_regs->e_rc_qp_bound);
1203 1198
1204 /* other QPs */ 1199 /* other QPs */
1205 WRITEL(0x0, mfc_regs->e_fixed_picture_qp); 1200 writel(0x0, mfc_regs->e_fixed_picture_qp);
1206 if (!p->rc_frame && !p->rc_mb) { 1201 if (!p->rc_frame && !p->rc_mb) {
1207 reg = 0; 1202 reg = 0;
1208 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16); 1203 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1209 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8); 1204 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1210 reg |= p_h263->rc_frame_qp & 0x3F; 1205 reg |= p_h263->rc_frame_qp & 0x3F;
1211 WRITEL(reg, mfc_regs->e_fixed_picture_qp); 1206 writel(reg, mfc_regs->e_fixed_picture_qp);
1212 } 1207 }
1213 1208
1214 /* frame rate */ 1209 /* frame rate */
@@ -1216,16 +1211,16 @@ static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1216 reg = 0; 1211 reg = 0;
1217 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1212 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1218 reg |= p->rc_framerate_denom & 0xFFFF; 1213 reg |= p->rc_framerate_denom & 0xFFFF;
1219 WRITEL(reg, mfc_regs->e_rc_frame_rate); 1214 writel(reg, mfc_regs->e_rc_frame_rate);
1220 } 1215 }
1221 1216
1222 /* vbv buffer size */ 1217 /* vbv buffer size */
1223 if (p->frame_skip_mode == 1218 if (p->frame_skip_mode ==
1224 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1219 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1225 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); 1220 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1226 1221
1227 if (p->rc_frame) 1222 if (p->rc_frame)
1228 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); 1223 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1229 } 1224 }
1230 1225
1231 mfc_debug_leave(); 1226 mfc_debug_leave();
@@ -1247,57 +1242,57 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1247 s5p_mfc_set_enc_params(ctx); 1242 s5p_mfc_set_enc_params(ctx);
1248 1243
1249 /* pictype : number of B */ 1244 /* pictype : number of B */
1250 reg = READL(mfc_regs->e_gop_config); 1245 reg = readl(mfc_regs->e_gop_config);
1251 reg &= ~(0x3 << 16); 1246 reg &= ~(0x3 << 16);
1252 reg |= ((p->num_b_frame & 0x3) << 16); 1247 reg |= ((p->num_b_frame & 0x3) << 16);
1253 WRITEL(reg, mfc_regs->e_gop_config); 1248 writel(reg, mfc_regs->e_gop_config);
1254 1249
1255 /* profile - 0 ~ 3 */ 1250 /* profile - 0 ~ 3 */
1256 reg = p_vp8->profile & 0x3; 1251 reg = p_vp8->profile & 0x3;
1257 WRITEL(reg, mfc_regs->e_picture_profile); 1252 writel(reg, mfc_regs->e_picture_profile);
1258 1253
1259 /* rate control config. */ 1254 /* rate control config. */
1260 reg = READL(mfc_regs->e_rc_config); 1255 reg = readl(mfc_regs->e_rc_config);
1261 /** macroblock level rate control */ 1256 /** macroblock level rate control */
1262 reg &= ~(0x1 << 8); 1257 reg &= ~(0x1 << 8);
1263 reg |= ((p->rc_mb & 0x1) << 8); 1258 reg |= ((p->rc_mb & 0x1) << 8);
1264 WRITEL(reg, mfc_regs->e_rc_config); 1259 writel(reg, mfc_regs->e_rc_config);
1265 1260
1266 /* frame rate */ 1261 /* frame rate */
1267 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) { 1262 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1268 reg = 0; 1263 reg = 0;
1269 reg |= ((p->rc_framerate_num & 0xFFFF) << 16); 1264 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1270 reg |= p->rc_framerate_denom & 0xFFFF; 1265 reg |= p->rc_framerate_denom & 0xFFFF;
1271 WRITEL(reg, mfc_regs->e_rc_frame_rate); 1266 writel(reg, mfc_regs->e_rc_frame_rate);
1272 } 1267 }
1273 1268
1274 /* frame QP */ 1269 /* frame QP */
1275 reg &= ~(0x7F); 1270 reg &= ~(0x7F);
1276 reg |= p_vp8->rc_frame_qp & 0x7F; 1271 reg |= p_vp8->rc_frame_qp & 0x7F;
1277 WRITEL(reg, mfc_regs->e_rc_config); 1272 writel(reg, mfc_regs->e_rc_config);
1278 1273
1279 /* other QPs */ 1274 /* other QPs */
1280 WRITEL(0x0, mfc_regs->e_fixed_picture_qp); 1275 writel(0x0, mfc_regs->e_fixed_picture_qp);
1281 if (!p->rc_frame && !p->rc_mb) { 1276 if (!p->rc_frame && !p->rc_mb) {
1282 reg = 0; 1277 reg = 0;
1283 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8); 1278 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1284 reg |= p_vp8->rc_frame_qp & 0x7F; 1279 reg |= p_vp8->rc_frame_qp & 0x7F;
1285 WRITEL(reg, mfc_regs->e_fixed_picture_qp); 1280 writel(reg, mfc_regs->e_fixed_picture_qp);
1286 } 1281 }
1287 1282
1288 /* max QP */ 1283 /* max QP */
1289 reg = ((p_vp8->rc_max_qp & 0x7F) << 8); 1284 reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1290 /* min QP */ 1285 /* min QP */
1291 reg |= p_vp8->rc_min_qp & 0x7F; 1286 reg |= p_vp8->rc_min_qp & 0x7F;
1292 WRITEL(reg, mfc_regs->e_rc_qp_bound); 1287 writel(reg, mfc_regs->e_rc_qp_bound);
1293 1288
1294 /* vbv buffer size */ 1289 /* vbv buffer size */
1295 if (p->frame_skip_mode == 1290 if (p->frame_skip_mode ==
1296 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { 1291 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1297 WRITEL(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); 1292 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1298 1293
1299 if (p->rc_frame) 1294 if (p->rc_frame)
1300 WRITEL(p->vbv_delay, mfc_regs->e_vbv_init_delay); 1295 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1301 } 1296 }
1302 1297
1303 /* VP8 specific params */ 1298 /* VP8 specific params */
@@ -1319,7 +1314,7 @@ static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1319 } 1314 }
1320 reg |= (val & 0xF) << 3; 1315 reg |= (val & 0xF) << 3;
1321 reg |= (p_vp8->num_ref & 0x2); 1316 reg |= (p_vp8->num_ref & 0x2);
1322 WRITEL(reg, mfc_regs->e_vp8_options); 1317 writel(reg, mfc_regs->e_vp8_options);
1323 1318
1324 mfc_debug_leave(); 1319 mfc_debug_leave();
1325 1320
@@ -1338,9 +1333,9 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1338 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no, 1333 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1339 S5P_FIMV_CH_SEQ_HEADER_V6); 1334 S5P_FIMV_CH_SEQ_HEADER_V6);
1340 mfc_debug(2, "BUFs: %08x %08x %08x\n", 1335 mfc_debug(2, "BUFs: %08x %08x %08x\n",
1341 READL(mfc_regs->d_cpb_buffer_addr), 1336 readl(mfc_regs->d_cpb_buffer_addr),
1342 READL(mfc_regs->d_cpb_buffer_addr), 1337 readl(mfc_regs->d_cpb_buffer_addr),
1343 READL(mfc_regs->d_cpb_buffer_addr)); 1338 readl(mfc_regs->d_cpb_buffer_addr));
1344 1339
1345 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */ 1340 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1346 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6); 1341 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
@@ -1351,11 +1346,11 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1351 * set to negative value. */ 1346 * set to negative value. */
1352 if (ctx->display_delay >= 0) { 1347 if (ctx->display_delay >= 0) {
1353 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6); 1348 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1354 WRITEL(ctx->display_delay, mfc_regs->d_display_delay); 1349 writel(ctx->display_delay, mfc_regs->d_display_delay);
1355 } 1350 }
1356 1351
1357 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) { 1352 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {
1358 WRITEL(reg, mfc_regs->d_dec_options); 1353 writel(reg, mfc_regs->d_dec_options);
1359 reg = 0; 1354 reg = 0;
1360 } 1355 }
1361 1356
@@ -1370,22 +1365,22 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1370 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6); 1365 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1371 1366
1372 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) 1367 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))
1373 WRITEL(reg, mfc_regs->d_init_buffer_options); 1368 writel(reg, mfc_regs->d_init_buffer_options);
1374 else 1369 else
1375 WRITEL(reg, mfc_regs->d_dec_options); 1370 writel(reg, mfc_regs->d_dec_options);
1376 1371
1377 /* 0: NV12(CbCr), 1: NV21(CrCb) */ 1372 /* 0: NV12(CbCr), 1: NV21(CrCb) */
1378 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M) 1373 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1379 WRITEL(0x1, mfc_regs->pixel_format); 1374 writel(0x1, mfc_regs->pixel_format);
1380 else 1375 else
1381 WRITEL(0x0, mfc_regs->pixel_format); 1376 writel(0x0, mfc_regs->pixel_format);
1382 1377
1383 1378
1384 /* sei parse */ 1379 /* sei parse */
1385 WRITEL(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable); 1380 writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1386 1381
1387 WRITEL(ctx->inst_no, mfc_regs->instance_id); 1382 writel(ctx->inst_no, mfc_regs->instance_id);
1388 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1383 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1389 S5P_FIMV_CH_SEQ_HEADER_V6, NULL); 1384 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1390 1385
1391 mfc_debug_leave(); 1386 mfc_debug_leave();
@@ -1400,8 +1395,8 @@ static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1400 if (flush) { 1395 if (flush) {
1401 dev->curr_ctx = ctx->num; 1396 dev->curr_ctx = ctx->num;
1402 s5p_mfc_clean_ctx_int_flags(ctx); 1397 s5p_mfc_clean_ctx_int_flags(ctx);
1403 WRITEL(ctx->inst_no, mfc_regs->instance_id); 1398 writel(ctx->inst_no, mfc_regs->instance_id);
1404 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1399 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1405 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL); 1400 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1406 } 1401 }
1407} 1402}
@@ -1413,19 +1408,19 @@ static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1413 struct s5p_mfc_dev *dev = ctx->dev; 1408 struct s5p_mfc_dev *dev = ctx->dev;
1414 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1409 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1415 1410
1416 WRITEL(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower); 1411 writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1417 WRITEL(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable); 1412 writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1418 1413
1419 WRITEL(ctx->inst_no, mfc_regs->instance_id); 1414 writel(ctx->inst_no, mfc_regs->instance_id);
1420 /* Issue different commands to instance basing on whether it 1415 /* Issue different commands to instance basing on whether it
1421 * is the last frame or not. */ 1416 * is the last frame or not. */
1422 switch (last_frame) { 1417 switch (last_frame) {
1423 case 0: 1418 case 0:
1424 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1419 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1425 S5P_FIMV_CH_FRAME_START_V6, NULL); 1420 S5P_FIMV_CH_FRAME_START_V6, NULL);
1426 break; 1421 break;
1427 case 1: 1422 case 1:
1428 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1423 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1429 S5P_FIMV_CH_LAST_FRAME_V6, NULL); 1424 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1430 break; 1425 break;
1431 default: 1426 default:
@@ -1458,12 +1453,12 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1458 1453
1459 /* Set stride lengths for v7 & above */ 1454 /* Set stride lengths for v7 & above */
1460 if (IS_MFCV7_PLUS(dev)) { 1455 if (IS_MFCV7_PLUS(dev)) {
1461 WRITEL(ctx->img_width, mfc_regs->e_source_first_plane_stride); 1456 writel(ctx->img_width, mfc_regs->e_source_first_plane_stride);
1462 WRITEL(ctx->img_width, mfc_regs->e_source_second_plane_stride); 1457 writel(ctx->img_width, mfc_regs->e_source_second_plane_stride);
1463 } 1458 }
1464 1459
1465 WRITEL(ctx->inst_no, mfc_regs->instance_id); 1460 writel(ctx->inst_no, mfc_regs->instance_id);
1466 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1461 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1467 S5P_FIMV_CH_SEQ_HEADER_V6, NULL); 1462 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1468 1463
1469 return 0; 1464 return 0;
@@ -1479,7 +1474,7 @@ static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1479 1474
1480 if (p_h264->aso) { 1475 if (p_h264->aso) {
1481 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) { 1476 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1482 WRITEL(p_h264->aso_slice_order[i], 1477 writel(p_h264->aso_slice_order[i],
1483 mfc_regs->e_h264_aso_slice_order_0 + i * 4); 1478 mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1484 } 1479 }
1485 } 1480 }
@@ -1501,8 +1496,8 @@ static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1501 1496
1502 s5p_mfc_set_slice_mode(ctx); 1497 s5p_mfc_set_slice_mode(ctx);
1503 1498
1504 WRITEL(ctx->inst_no, mfc_regs->instance_id); 1499 writel(ctx->inst_no, mfc_regs->instance_id);
1505 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, 1500 s5p_mfc_hw_call_void(dev->mfc_cmds, cmd_host2risc, dev,
1506 S5P_FIMV_CH_FRAME_START_V6, NULL); 1501 S5P_FIMV_CH_FRAME_START_V6, NULL);
1507 1502
1508 mfc_debug(2, "--\n"); 1503 mfc_debug(2, "--\n");
@@ -1877,15 +1872,15 @@ static void s5p_mfc_cleanup_queue_v6(struct list_head *lh, struct vb2_queue *vq)
1877static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev) 1872static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
1878{ 1873{
1879 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; 1874 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1880 WRITEL(0, mfc_regs->risc2host_command); 1875 writel(0, mfc_regs->risc2host_command);
1881 WRITEL(0, mfc_regs->risc2host_int); 1876 writel(0, mfc_regs->risc2host_int);
1882} 1877}
1883 1878
1884static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data, 1879static void s5p_mfc_write_info_v6(struct s5p_mfc_ctx *ctx, unsigned int data,
1885 unsigned int ofs) 1880 unsigned int ofs)
1886{ 1881{
1887 s5p_mfc_clock_on(); 1882 s5p_mfc_clock_on();
1888 WRITEL(data, (void *)ofs); 1883 writel(data, (void *)ofs);
1889 s5p_mfc_clock_off(); 1884 s5p_mfc_clock_off();
1890} 1885}
1891 1886
@@ -1895,7 +1890,7 @@ s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1895 int ret; 1890 int ret;
1896 1891
1897 s5p_mfc_clock_on(); 1892 s5p_mfc_clock_on();
1898 ret = READL((void *)ofs); 1893 ret = readl((void *)ofs);
1899 s5p_mfc_clock_off(); 1894 s5p_mfc_clock_off();
1900 1895
1901 return ret; 1896 return ret;
@@ -1903,51 +1898,51 @@ s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned int ofs)
1903 1898
1904static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev) 1899static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
1905{ 1900{
1906 return READL(dev->mfc_regs->d_display_first_plane_addr); 1901 return readl(dev->mfc_regs->d_display_first_plane_addr);
1907} 1902}
1908 1903
1909static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev) 1904static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
1910{ 1905{
1911 return READL(dev->mfc_regs->d_decoded_first_plane_addr); 1906 return readl(dev->mfc_regs->d_decoded_first_plane_addr);
1912} 1907}
1913 1908
1914static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev) 1909static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
1915{ 1910{
1916 return READL(dev->mfc_regs->d_display_status); 1911 return readl(dev->mfc_regs->d_display_status);
1917} 1912}
1918 1913
1919static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev) 1914static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
1920{ 1915{
1921 return READL(dev->mfc_regs->d_decoded_status); 1916 return readl(dev->mfc_regs->d_decoded_status);
1922} 1917}
1923 1918
1924static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev) 1919static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
1925{ 1920{
1926 return READL(dev->mfc_regs->d_decoded_frame_type) & 1921 return readl(dev->mfc_regs->d_decoded_frame_type) &
1927 S5P_FIMV_DECODE_FRAME_MASK_V6; 1922 S5P_FIMV_DECODE_FRAME_MASK_V6;
1928} 1923}
1929 1924
1930static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx) 1925static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
1931{ 1926{
1932 struct s5p_mfc_dev *dev = ctx->dev; 1927 struct s5p_mfc_dev *dev = ctx->dev;
1933 return READL(dev->mfc_regs->d_display_frame_type) & 1928 return readl(dev->mfc_regs->d_display_frame_type) &
1934 S5P_FIMV_DECODE_FRAME_MASK_V6; 1929 S5P_FIMV_DECODE_FRAME_MASK_V6;
1935} 1930}
1936 1931
1937static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev) 1932static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
1938{ 1933{
1939 return READL(dev->mfc_regs->d_decoded_nal_size); 1934 return readl(dev->mfc_regs->d_decoded_nal_size);
1940} 1935}
1941 1936
1942static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev) 1937static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
1943{ 1938{
1944 return READL(dev->mfc_regs->risc2host_command) & 1939 return readl(dev->mfc_regs->risc2host_command) &
1945 S5P_FIMV_RISC2HOST_CMD_MASK; 1940 S5P_FIMV_RISC2HOST_CMD_MASK;
1946} 1941}
1947 1942
1948static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev) 1943static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
1949{ 1944{
1950 return READL(dev->mfc_regs->error_code); 1945 return readl(dev->mfc_regs->error_code);
1951} 1946}
1952 1947
1953static int s5p_mfc_err_dec_v6(unsigned int err) 1948static int s5p_mfc_err_dec_v6(unsigned int err)
@@ -1962,63 +1957,63 @@ static int s5p_mfc_err_dspl_v6(unsigned int err)
1962 1957
1963static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev) 1958static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
1964{ 1959{
1965 return READL(dev->mfc_regs->d_display_frame_width); 1960 return readl(dev->mfc_regs->d_display_frame_width);
1966} 1961}
1967 1962
1968static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev) 1963static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
1969{ 1964{
1970 return READL(dev->mfc_regs->d_display_frame_height); 1965 return readl(dev->mfc_regs->d_display_frame_height);
1971} 1966}
1972 1967
1973static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev) 1968static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
1974{ 1969{
1975 return READL(dev->mfc_regs->d_min_num_dpb); 1970 return readl(dev->mfc_regs->d_min_num_dpb);
1976} 1971}
1977 1972
1978static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev) 1973static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
1979{ 1974{
1980 return READL(dev->mfc_regs->d_min_num_mv); 1975 return readl(dev->mfc_regs->d_min_num_mv);
1981} 1976}
1982 1977
1983static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev) 1978static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
1984{ 1979{
1985 return READL(dev->mfc_regs->ret_instance_id); 1980 return readl(dev->mfc_regs->ret_instance_id);
1986} 1981}
1987 1982
1988static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev) 1983static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
1989{ 1984{
1990 return READL(dev->mfc_regs->e_num_dpb); 1985 return readl(dev->mfc_regs->e_num_dpb);
1991} 1986}
1992 1987
1993static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev) 1988static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
1994{ 1989{
1995 return READL(dev->mfc_regs->e_stream_size); 1990 return readl(dev->mfc_regs->e_stream_size);
1996} 1991}
1997 1992
1998static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev) 1993static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
1999{ 1994{
2000 return READL(dev->mfc_regs->e_slice_type); 1995 return readl(dev->mfc_regs->e_slice_type);
2001} 1996}
2002 1997
2003static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev) 1998static int s5p_mfc_get_enc_pic_count_v6(struct s5p_mfc_dev *dev)
2004{ 1999{
2005 return READL(dev->mfc_regs->e_picture_count); 2000 return readl(dev->mfc_regs->e_picture_count);
2006} 2001}
2007 2002
2008static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx) 2003static int s5p_mfc_get_sei_avail_status_v6(struct s5p_mfc_ctx *ctx)
2009{ 2004{
2010 struct s5p_mfc_dev *dev = ctx->dev; 2005 struct s5p_mfc_dev *dev = ctx->dev;
2011 return READL(dev->mfc_regs->d_frame_pack_sei_avail); 2006 return readl(dev->mfc_regs->d_frame_pack_sei_avail);
2012} 2007}
2013 2008
2014static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev) 2009static int s5p_mfc_get_mvc_num_views_v6(struct s5p_mfc_dev *dev)
2015{ 2010{
2016 return READL(dev->mfc_regs->d_mvc_num_views); 2011 return readl(dev->mfc_regs->d_mvc_num_views);
2017} 2012}
2018 2013
2019static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev) 2014static int s5p_mfc_get_mvc_view_id_v6(struct s5p_mfc_dev *dev)
2020{ 2015{
2021 return READL(dev->mfc_regs->d_mvc_view_id); 2016 return readl(dev->mfc_regs->d_mvc_view_id);
2022} 2017}
2023 2018
2024static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx) 2019static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 17:51:31 -0400