diff options
| author | Tony Lindgren <tony@atomide.com> | 2015-01-14 20:37:15 -0500 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2015-01-14 20:37:15 -0500 |
| commit | e226ebe95e7afb79ff24c53f9984b8acad13cc81 (patch) | |
| tree | c197851102d69a17965ae7eddb6699fdbf3d8a63 | |
| parent | 339d095ab23cf5de223c9633ee4d3ec1794282af (diff) | |
ARM: OMAP2+: Fix ti81xx devtype
Otherwise we get error "Cannot detect omap type!" and many
things can fail with following:
Unhandled fault: imprecise external abort (0xc06) at 0xc6031fb0
This is because the omap_type is being used to set up th SoC
specific functions for omaps.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
| -rw-r--r-- | arch/arm/mach-omap2/control.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/id.c | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a3c013345c45..0fba6d1130a9 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h | |||
| @@ -53,6 +53,7 @@ | |||
| 53 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 | 53 | #define OMAP343X_CONTROL_GENERAL_WKUP 0xa60 |
| 54 | 54 | ||
| 55 | /* TI81XX spefic control submodules */ | 55 | /* TI81XX spefic control submodules */ |
| 56 | #define TI81XX_CONTROL_DEVBOOT 0x040 | ||
| 56 | #define TI81XX_CONTROL_DEVCONF 0x600 | 57 | #define TI81XX_CONTROL_DEVCONF 0x600 |
| 57 | 58 | ||
| 58 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ | 59 | /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */ |
| @@ -246,6 +247,9 @@ | |||
| 246 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 | 247 | #define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 |
| 247 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 | 248 | #define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 |
| 248 | 249 | ||
| 250 | /* TI81XX CONTROL_DEVBOOT register offsets */ | ||
| 251 | #define TI81XX_CONTROL_STATUS (TI81XX_CONTROL_DEVBOOT + 0x000) | ||
| 252 | |||
| 249 | /* TI81XX CONTROL_DEVCONF register offsets */ | 253 | /* TI81XX CONTROL_DEVCONF register offsets */ |
| 250 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) | 254 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) |
| 251 | 255 | ||
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index c25feba05818..2a2f4d56e4c8 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -56,6 +56,8 @@ int omap_type(void) | |||
| 56 | 56 | ||
| 57 | if (cpu_is_omap24xx()) { | 57 | if (cpu_is_omap24xx()) { |
| 58 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); | 58 | val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS); |
| 59 | } else if (cpu_is_ti81xx()) { | ||
| 60 | val = omap_ctrl_readl(TI81XX_CONTROL_STATUS); | ||
| 59 | } else if (soc_is_am33xx() || soc_is_am43xx()) { | 61 | } else if (soc_is_am33xx() || soc_is_am43xx()) { |
| 60 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); | 62 | val = omap_ctrl_readl(AM33XX_CONTROL_STATUS); |
| 61 | } else if (cpu_is_omap34xx()) { | 63 | } else if (cpu_is_omap34xx()) { |
