aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTony Lindgren <tony@atomide.com>2011-07-11 02:18:06 -0400
committerTony Lindgren <tony@atomide.com>2011-07-11 02:18:06 -0400
commite1d62c9bd8779a8e4a335803f0fced9e614d0a9f (patch)
tree1f20939eca46cd6bb169f0174439035fcf324cd2
parent354a183f536a8edf6cb80ee3e3f393736e278810 (diff)
parentc402c0d9dfa8d4fb54dd98fc12525f39d0f29bfe (diff)
Merge branch 'prcm-cleanup-3.1' of git://git.pwsan.com/linux-2.6 into cleanup-part-3
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile16
-rw-r--r--arch/arm/mach-omap2/board-generic.c2
-rw-r--r--arch/arm/mach-omap2/clock44xx.h7
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c237
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c124
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h623
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h64
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h73
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c223
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c832
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c910
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c173
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c322
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c130
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c150
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c654
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c472
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.c20
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.h93
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx_data.c18
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h69
-rw-r--r--arch/arm/mach-omap2/prm44xx.h34
-rw-r--r--arch/arm/plat-omap/Kconfig3
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h2
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h1
-rw-r--r--arch/arm/plat-omap/include/plat/omap-pm.h8
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h20
-rw-r--r--arch/arm/plat-omap/omap_device.c15
28 files changed, 2118 insertions, 3177 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ff1466fbf5c5..f34336560437 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
145obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o 145obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
146 146
147# hwmod data 147# hwmod data
148obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o 148obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
149obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o 149 omap_hwmod_2xxx_3xxx_ipblock_data.o \
150obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o 150 omap_hwmod_2xxx_interconnect_data.o \
151 omap_hwmod_2xxx_3xxx_interconnect_data.o \
152 omap_hwmod_2420_data.o
153obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
154 omap_hwmod_2xxx_3xxx_ipblock_data.o \
155 omap_hwmod_2xxx_interconnect_data.o \
156 omap_hwmod_2xxx_3xxx_interconnect_data.o \
157 omap_hwmod_2430_data.o
158obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
159 omap_hwmod_2xxx_3xxx_interconnect_data.o \
160 omap_hwmod_3xxx_data.o
151obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 161obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
152 162
153# EMU peripherals 163# EMU peripherals
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index c6ecf607ebd6..54db41a84a9b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -72,5 +72,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
72 .init_early = omap_generic_init_early, 72 .init_early = omap_generic_init_early,
73 .init_irq = omap2_init_irq, 73 .init_irq = omap2_init_irq,
74 .init_machine = omap_generic_init, 74 .init_machine = omap_generic_init,
75 .timer = &omap3_timer, 75 .timer = &omap2_timer,
76MACHINE_END 76MACHINE_END
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index 6be1095936db..7ceb870e7ab8 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -8,13 +8,6 @@
8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H 8#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
9#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H 9#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
10 10
11/*
12 * XXX Missing values for the OMAP4 DPLL_USB
13 * XXX Missing min_multiplier values for all OMAP4 DPLLs
14 */
15#define OMAP4430_MAX_DPLL_MULT 2047
16#define OMAP4430_MAX_DPLL_DIV 128
17
18int omap4xxx_clk_init(void); 11int omap4xxx_clk_init(void);
19 12
20#endif 13#endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c965671b4d4..044df38f65ce 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
53static struct clk pad_clks_ck = { 53static struct clk pad_clks_ck = {
54 .name = "pad_clks_ck", 54 .name = "pad_clks_ck",
55 .rate = 12000000, 55 .rate = 12000000,
56 .ops = &clkops_omap2_dflt, 56 .ops = &clkops_omap2_dflt,
57 .enable_reg = OMAP4430_CM_CLKSEL_ABE, 57 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, 58 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
59}; 59};
60 60
61static struct clk pad_slimbus_core_clks_ck = { 61static struct clk pad_slimbus_core_clks_ck = {
@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
73static struct clk slimbus_clk = { 73static struct clk slimbus_clk = {
74 .name = "slimbus_clk", 74 .name = "slimbus_clk",
75 .rate = 12000000, 75 .rate = 12000000,
76 .ops = &clkops_omap2_dflt, 76 .ops = &clkops_omap2_dflt,
77 .enable_reg = OMAP4430_CM_CLKSEL_ABE, 77 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, 78 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
79}; 79};
80 80
81static struct clk sys_32k_ck = { 81static struct clk sys_32k_ck = {
@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
258 .enable_mask = OMAP4430_DPLL_EN_MASK, 258 .enable_mask = OMAP4430_DPLL_EN_MASK,
259 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 259 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
260 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 260 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
261 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 261 .max_multiplier = 2047,
262 .max_divider = OMAP4430_MAX_DPLL_DIV, 262 .max_divider = 128,
263 .min_divider = 1, 263 .min_divider = 1,
264}; 264};
265 265
@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
278static struct clk dpll_abe_x2_ck = { 278static struct clk dpll_abe_x2_ck = {
279 .name = "dpll_abe_x2_ck", 279 .name = "dpll_abe_x2_ck",
280 .parent = &dpll_abe_ck, 280 .parent = &dpll_abe_ck,
281 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
281 .flags = CLOCK_CLKOUTX2, 282 .flags = CLOCK_CLKOUTX2,
282 .ops = &clkops_omap4_dpllmx_ops, 283 .ops = &clkops_omap4_dpllmx_ops,
283 .recalc = &omap3_clkoutx2_recalc, 284 .recalc = &omap3_clkoutx2_recalc,
284 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
285}; 285};
286 286
287static const struct clksel_rate div31_1to31_rates[] = { 287static const struct clksel_rate div31_1to31_rates[] = {
@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
434 .enable_mask = OMAP4430_DPLL_EN_MASK, 434 .enable_mask = OMAP4430_DPLL_EN_MASK,
435 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 435 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
436 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 436 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
437 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 437 .max_multiplier = 2047,
438 .max_divider = OMAP4430_MAX_DPLL_DIV, 438 .max_divider = 128,
439 .min_divider = 1, 439 .min_divider = 1,
440}; 440};
441 441
@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, 622 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 623 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
624 .ops = &clkops_omap2_dflt, 624 .ops = &clkops_omap2_dflt,
625 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
626 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
627 .recalc = &omap2_clksel_recalc, 625 .recalc = &omap2_clksel_recalc,
628 .round_rate = &omap2_clksel_round_rate, 626 .round_rate = &omap2_clksel_round_rate,
629 .set_rate = &omap2_clksel_set_rate, 627 .set_rate = &omap2_clksel_set_rate,
628 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
629 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
630}; 630};
631 631
632static struct clk dpll_core_m7x2_ck = { 632static struct clk dpll_core_m7x2_ck = {
@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
672 .enable_mask = OMAP4430_DPLL_EN_MASK, 672 .enable_mask = OMAP4430_DPLL_EN_MASK,
673 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 673 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
674 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 674 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
675 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 675 .max_multiplier = 2047,
676 .max_divider = OMAP4430_MAX_DPLL_DIV, 676 .max_divider = 128,
677 .min_divider = 1, 677 .min_divider = 1,
678}; 678};
679 679
@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
740 .enable_mask = OMAP4430_DPLL_EN_MASK, 740 .enable_mask = OMAP4430_DPLL_EN_MASK,
741 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 741 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
742 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 742 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
743 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 743 .max_multiplier = 2047,
744 .max_divider = OMAP4430_MAX_DPLL_DIV, 744 .max_divider = 128,
745 .min_divider = 1, 745 .min_divider = 1,
746}; 746};
747 747
@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
813 .enable_mask = OMAP4430_DPLL_EN_MASK, 813 .enable_mask = OMAP4430_DPLL_EN_MASK,
814 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 814 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
815 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 815 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
816 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 816 .max_multiplier = 2047,
817 .max_divider = OMAP4430_MAX_DPLL_DIV, 817 .max_divider = 128,
818 .min_divider = 1, 818 .min_divider = 1,
819}; 819};
820 820
@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
850static struct clk dpll_per_x2_ck = { 850static struct clk dpll_per_x2_ck = {
851 .name = "dpll_per_x2_ck", 851 .name = "dpll_per_x2_ck",
852 .parent = &dpll_per_ck, 852 .parent = &dpll_per_ck,
853 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
853 .flags = CLOCK_CLKOUTX2, 854 .flags = CLOCK_CLKOUTX2,
854 .ops = &clkops_omap4_dpllmx_ops, 855 .ops = &clkops_omap4_dpllmx_ops,
855 .recalc = &omap3_clkoutx2_recalc, 856 .recalc = &omap3_clkoutx2_recalc,
856 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
857}; 857};
858 858
859static const struct clksel dpll_per_m2x2_div[] = { 859static const struct clksel dpll_per_m2x2_div[] = {
@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
880 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, 880 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
881 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, 881 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
882 .ops = &clkops_omap2_dflt, 882 .ops = &clkops_omap2_dflt,
883 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
884 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
885 .recalc = &omap2_clksel_recalc, 883 .recalc = &omap2_clksel_recalc,
886 .round_rate = &omap2_clksel_round_rate, 884 .round_rate = &omap2_clksel_round_rate,
887 .set_rate = &omap2_clksel_set_rate, 885 .set_rate = &omap2_clksel_set_rate,
886 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
887 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
888}; 888};
889 889
890static struct clk dpll_per_m4x2_ck = { 890static struct clk dpll_per_m4x2_ck = {
@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
935 .set_rate = &omap2_clksel_set_rate, 935 .set_rate = &omap2_clksel_set_rate,
936}; 936};
937 937
938/* DPLL_UNIPRO */
939static struct dpll_data dpll_unipro_dd = {
940 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
941 .clk_bypass = &sys_clkin_ck,
942 .clk_ref = &sys_clkin_ck,
943 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
944 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
945 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
946 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
947 .mult_mask = OMAP4430_DPLL_MULT_MASK,
948 .div1_mask = OMAP4430_DPLL_DIV_MASK,
949 .enable_mask = OMAP4430_DPLL_EN_MASK,
950 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
951 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
952 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
953 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
954 .max_divider = OMAP4430_MAX_DPLL_DIV,
955 .min_divider = 1,
956};
957
958
959static struct clk dpll_unipro_ck = {
960 .name = "dpll_unipro_ck",
961 .parent = &sys_clkin_ck,
962 .dpll_data = &dpll_unipro_dd,
963 .init = &omap2_init_dpll_parent,
964 .ops = &clkops_omap3_noncore_dpll_ops,
965 .recalc = &omap3_dpll_recalc,
966 .round_rate = &omap2_dpll_round_rate,
967 .set_rate = &omap3_noncore_dpll_set_rate,
968};
969
970static struct clk dpll_unipro_x2_ck = {
971 .name = "dpll_unipro_x2_ck",
972 .parent = &dpll_unipro_ck,
973 .flags = CLOCK_CLKOUTX2,
974 .ops = &clkops_null,
975 .recalc = &omap3_clkoutx2_recalc,
976};
977
978static const struct clksel dpll_unipro_m2x2_div[] = {
979 { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
980 { .parent = NULL },
981};
982
983static struct clk dpll_unipro_m2x2_ck = {
984 .name = "dpll_unipro_m2x2_ck",
985 .parent = &dpll_unipro_x2_ck,
986 .clksel = dpll_unipro_m2x2_div,
987 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
988 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
989 .ops = &clkops_omap4_dpllmx_ops,
990 .recalc = &omap2_clksel_recalc,
991 .round_rate = &omap2_clksel_round_rate,
992 .set_rate = &omap2_clksel_set_rate,
993};
994
995static struct clk usb_hs_clk_div_ck = { 938static struct clk usb_hs_clk_div_ck = {
996 .name = "usb_hs_clk_div_ck", 939 .name = "usb_hs_clk_div_ck",
997 .parent = &dpll_abe_m3x2_ck, 940 .parent = &dpll_abe_m3x2_ck,
@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
1015 .enable_mask = OMAP4430_DPLL_EN_MASK, 958 .enable_mask = OMAP4430_DPLL_EN_MASK,
1016 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, 959 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
1017 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, 960 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
1018 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 961 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
1019 .max_divider = OMAP4430_MAX_DPLL_DIV, 962 .max_multiplier = 4095,
963 .max_divider = 256,
1020 .min_divider = 1, 964 .min_divider = 1,
1021}; 965};
1022 966
@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
1035static struct clk dpll_usb_clkdcoldo_ck = { 979static struct clk dpll_usb_clkdcoldo_ck = {
1036 .name = "dpll_usb_clkdcoldo_ck", 980 .name = "dpll_usb_clkdcoldo_ck",
1037 .parent = &dpll_usb_ck, 981 .parent = &dpll_usb_ck,
1038 .ops = &clkops_omap4_dpllmx_ops,
1039 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, 982 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
983 .ops = &clkops_omap4_dpllmx_ops,
1040 .recalc = &followparent_recalc, 984 .recalc = &followparent_recalc,
1041}; 985};
1042 986
@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
1169 .set_rate = &omap2_clksel_set_rate, 1113 .set_rate = &omap2_clksel_set_rate,
1170}; 1114};
1171 1115
1172static const struct clksel hsmmc6_fclk_sel[] = {
1173 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1174 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1175 { .parent = NULL },
1176};
1177
1178static struct clk hsmmc6_fclk = {
1179 .name = "hsmmc6_fclk",
1180 .parent = &func_64m_fclk,
1181 .ops = &clkops_null,
1182 .recalc = &followparent_recalc,
1183};
1184
1185static const struct clksel_rate div2_1to8_rates[] = { 1116static const struct clksel_rate div2_1to8_rates[] = {
1186 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 1117 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1187 { .div = 8, .val = 1, .flags = RATE_IN_4430 }, 1118 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
1264 .recalc = &omap2_clksel_recalc, 1195 .recalc = &omap2_clksel_recalc,
1265}; 1196};
1266 1197
1198static struct clk ocp_abe_iclk = {
1199 .name = "ocp_abe_iclk",
1200 .parent = &aess_fclk,
1201 .ops = &clkops_null,
1202 .recalc = &followparent_recalc,
1203};
1204
1205static struct clk per_abe_24m_fclk = {
1206 .name = "per_abe_24m_fclk",
1207 .parent = &dpll_abe_m2_ck,
1208 .ops = &clkops_null,
1209 .fixed_div = 4,
1210 .recalc = &omap_fixed_divisor_recalc,
1211};
1212
1267static const struct clksel per_abe_nc_fclk_div[] = { 1213static const struct clksel per_abe_nc_fclk_div[] = {
1268 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, 1214 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1269 { .parent = NULL }, 1215 { .parent = NULL },
@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
1281 .set_rate = &omap2_clksel_set_rate, 1227 .set_rate = &omap2_clksel_set_rate,
1282}; 1228};
1283 1229
1284static const struct clksel mcasp2_fclk_sel[] = {
1285 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1286 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1287 { .parent = NULL },
1288};
1289
1290static struct clk mcasp2_fclk = {
1291 .name = "mcasp2_fclk",
1292 .parent = &func_96m_fclk,
1293 .ops = &clkops_null,
1294 .recalc = &followparent_recalc,
1295};
1296
1297static struct clk mcasp3_fclk = {
1298 .name = "mcasp3_fclk",
1299 .parent = &func_96m_fclk,
1300 .ops = &clkops_null,
1301 .recalc = &followparent_recalc,
1302};
1303
1304static struct clk ocp_abe_iclk = {
1305 .name = "ocp_abe_iclk",
1306 .parent = &aess_fclk,
1307 .ops = &clkops_null,
1308 .recalc = &followparent_recalc,
1309};
1310
1311static struct clk per_abe_24m_fclk = {
1312 .name = "per_abe_24m_fclk",
1313 .parent = &dpll_abe_m2_ck,
1314 .ops = &clkops_null,
1315 .fixed_div = 4,
1316 .recalc = &omap_fixed_divisor_recalc,
1317};
1318
1319static const struct clksel pmd_stm_clock_mux_sel[] = { 1230static const struct clksel pmd_stm_clock_mux_sel[] = {
1320 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1231 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1321 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, 1232 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@@ -1846,8 +1757,8 @@ static struct clk l3_instr_ick = {
1846 .ops = &clkops_omap2_dflt, 1757 .ops = &clkops_omap2_dflt,
1847 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1758 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1848 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1759 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1849 .clkdm_name = "l3_instr_clkdm",
1850 .flags = ENABLE_ON_INIT, 1760 .flags = ENABLE_ON_INIT,
1761 .clkdm_name = "l3_instr_clkdm",
1851 .parent = &l3_div_ck, 1762 .parent = &l3_div_ck,
1852 .recalc = &followparent_recalc, 1763 .recalc = &followparent_recalc,
1853}; 1764};
@@ -1857,8 +1768,8 @@ static struct clk l3_main_3_ick = {
1857 .ops = &clkops_omap2_dflt, 1768 .ops = &clkops_omap2_dflt,
1858 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1769 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1859 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1770 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1860 .clkdm_name = "l3_instr_clkdm",
1861 .flags = ENABLE_ON_INIT, 1771 .flags = ENABLE_ON_INIT,
1772 .clkdm_name = "l3_instr_clkdm",
1862 .parent = &l3_div_ck, 1773 .parent = &l3_div_ck,
1863 .recalc = &followparent_recalc, 1774 .recalc = &followparent_recalc,
1864}; 1775};
@@ -1995,10 +1906,16 @@ static struct clk mcbsp3_fck = {
1995 .clkdm_name = "abe_clkdm", 1906 .clkdm_name = "abe_clkdm",
1996}; 1907};
1997 1908
1909static const struct clksel mcbsp4_sync_mux_sel[] = {
1910 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1911 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1912 { .parent = NULL },
1913};
1914
1998static struct clk mcbsp4_sync_mux_ck = { 1915static struct clk mcbsp4_sync_mux_ck = {
1999 .name = "mcbsp4_sync_mux_ck", 1916 .name = "mcbsp4_sync_mux_ck",
2000 .parent = &func_96m_fclk, 1917 .parent = &func_96m_fclk,
2001 .clksel = mcasp2_fclk_sel, 1918 .clksel = mcbsp4_sync_mux_sel,
2002 .init = &omap2_init_clksel_parent, 1919 .init = &omap2_init_clksel_parent,
2003 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, 1920 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2004 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, 1921 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@@ -2077,11 +1994,17 @@ static struct clk mcspi4_fck = {
2077 .recalc = &followparent_recalc, 1994 .recalc = &followparent_recalc,
2078}; 1995};
2079 1996
1997static const struct clksel hsmmc1_fclk_sel[] = {
1998 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1999 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
2000 { .parent = NULL },
2001};
2002
2080/* Merged hsmmc1_fclk into mmc1 */ 2003/* Merged hsmmc1_fclk into mmc1 */
2081static struct clk mmc1_fck = { 2004static struct clk mmc1_fck = {
2082 .name = "mmc1_fck", 2005 .name = "mmc1_fck",
2083 .parent = &func_64m_fclk, 2006 .parent = &func_64m_fclk,
2084 .clksel = hsmmc6_fclk_sel, 2007 .clksel = hsmmc1_fclk_sel,
2085 .init = &omap2_init_clksel_parent, 2008 .init = &omap2_init_clksel_parent,
2086 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 2009 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2087 .clksel_mask = OMAP4430_CLKSEL_MASK, 2010 .clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -2096,7 +2019,7 @@ static struct clk mmc1_fck = {
2096static struct clk mmc2_fck = { 2019static struct clk mmc2_fck = {
2097 .name = "mmc2_fck", 2020 .name = "mmc2_fck",
2098 .parent = &func_64m_fclk, 2021 .parent = &func_64m_fclk,
2099 .clksel = hsmmc6_fclk_sel, 2022 .clksel = hsmmc1_fclk_sel,
2100 .init = &omap2_init_clksel_parent, 2023 .init = &omap2_init_clksel_parent,
2101 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 2024 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2102 .clksel_mask = OMAP4430_CLKSEL_MASK, 2025 .clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -2162,8 +2085,8 @@ static struct clk ocp_wp_noc_ick = {
2162 .ops = &clkops_omap2_dflt, 2085 .ops = &clkops_omap2_dflt,
2163 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2086 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2164 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2087 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2165 .clkdm_name = "l3_instr_clkdm",
2166 .flags = ENABLE_ON_INIT, 2088 .flags = ENABLE_ON_INIT,
2089 .clkdm_name = "l3_instr_clkdm",
2167 .parent = &l3_div_ck, 2090 .parent = &l3_div_ck,
2168 .recalc = &followparent_recalc, 2091 .recalc = &followparent_recalc,
2169}; 2092};
@@ -2895,6 +2818,7 @@ static struct clk auxclk2_ck = {
2895 .enable_reg = OMAP4_SCRM_AUXCLK2, 2818 .enable_reg = OMAP4_SCRM_AUXCLK2,
2896 .enable_bit = OMAP4_ENABLE_SHIFT, 2819 .enable_bit = OMAP4_ENABLE_SHIFT,
2897}; 2820};
2821
2898static struct clk auxclk3_ck = { 2822static struct clk auxclk3_ck = {
2899 .name = "auxclk3_ck", 2823 .name = "auxclk3_ck",
2900 .parent = &sys_clkin_ck, 2824 .parent = &sys_clkin_ck,
@@ -3077,9 +3001,6 @@ static struct omap_clk omap44xx_clks[] = {
3077 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), 3001 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
3078 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), 3002 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
3079 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), 3003 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
3080 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
3081 CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
3082 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
3083 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), 3004 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
3084 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), 3005 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
3085 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), 3006 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
@@ -3092,17 +3013,14 @@ static struct omap_clk omap44xx_clks[] = {
3092 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), 3013 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3093 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), 3014 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3094 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), 3015 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3095 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
3096 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), 3016 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3097 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), 3017 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3098 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), 3018 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3099 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), 3019 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3100 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), 3020 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3101 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3102 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
3103 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
3104 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), 3021 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3105 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), 3022 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3023 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3106 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), 3024 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3107 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), 3025 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3108 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), 3026 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
@@ -3204,7 +3122,6 @@ static struct omap_clk omap44xx_clks[] = {
3204 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), 3122 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
3205 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 3123 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3206 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 3124 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3207 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
3208 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), 3125 CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
3209 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), 3126 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3210 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), 3127 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
@@ -3216,9 +3133,7 @@ static struct omap_clk omap44xx_clks[] = {
3216 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), 3133 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3217 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), 3134 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3218 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), 3135 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3219 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
3220 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), 3136 CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
3221 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
3222 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), 3137 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3223 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), 3138 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3224 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), 3139 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
@@ -3226,17 +3141,26 @@ static struct omap_clk omap44xx_clks[] = {
3226 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), 3141 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3227 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), 3142 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3228 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), 3143 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3229 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
3230 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), 3144 CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3231 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
3232 CLK(NULL, "usim_ck", &usim_ck, CK_443X), 3145 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3233 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), 3146 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3234 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 3147 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3235 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), 3148 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
3236 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3237 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), 3149 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3238 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 3150 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3239 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 3151 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3152 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3153 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3154 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3155 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3156 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3157 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3158 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3159 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3160 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3161 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3162 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3163 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3240 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 3164 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
3241 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 3165 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
3242 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), 3166 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
@@ -3253,6 +3177,7 @@ static struct omap_clk omap44xx_clks[] = {
3253 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 3177 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3254 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 3178 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3255 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), 3179 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3180 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3256 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), 3181 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3257 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), 3182 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3258 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), 3183 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
@@ -3270,19 +3195,9 @@ static struct omap_clk omap44xx_clks[] = {
3270 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 3195 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3271 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 3196 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3272 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), 3197 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3198 CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
3199 CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
3273 CLK("omap_wdt", "ick", &dummy_ck, CK_443X), 3200 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3274 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3275 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3276 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3277 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3278 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3279 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3280 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3281 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3282 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3283 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3284 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3285 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3286}; 3201};
3287 3202
3288int __init omap4xxx_clk_init(void) 3203int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index a607ec196e8b..66090f2676ce 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -1,11 +1,12 @@
1/* 1/*
2 * OMAP4 Clock domains framework 2 * OMAP4 Clock domains framework
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2011 Nokia Corporation
6 * 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com) 7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com) 8 * Benoit Cousson (b-cousson@ti.com)
9 * Paul Walmsley (paul@pwsan.com)
9 * 10 *
10 * This file is automatically generated from the OMAP hardware databases. 11 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated 12 * We respectfully ask that any modifications to this file be coordinated
@@ -32,7 +33,7 @@
32 33
33/* Static Dependencies for OMAP4 Clock Domains */ 34/* Static Dependencies for OMAP4 Clock Domains */
34 35
35static struct clkdm_dep ducati_wkup_sleep_deps[] = { 36static struct clkdm_dep d2d_wkup_sleep_deps[] = {
36 { 37 {
37 .clkdm_name = "abe_clkdm", 38 .clkdm_name = "abe_clkdm",
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 39 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = {
50 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 51 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
51 }, 52 },
52 { 53 {
53 .clkdm_name = "l3_dss_clkdm", 54 .clkdm_name = "l3_emif_clkdm",
54 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 55 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
55 }, 56 },
56 { 57 {
57 .clkdm_name = "l3_emif_clkdm", 58 .clkdm_name = "l3_init_clkdm",
58 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 59 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
59 }, 60 },
60 { 61 {
61 .clkdm_name = "l3_gfx_clkdm", 62 .clkdm_name = "l4_cfg_clkdm",
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 63 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
63 }, 64 },
64 { 65 {
65 .clkdm_name = "l3_init_clkdm", 66 .clkdm_name = "l4_per_clkdm",
66 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 67 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
67 }, 68 },
69 { NULL },
70};
71
72static struct clkdm_dep ducati_wkup_sleep_deps[] = {
68 { 73 {
69 .clkdm_name = "l4_cfg_clkdm", 74 .clkdm_name = "abe_clkdm",
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 75 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
71 }, 76 },
72 { 77 {
73 .clkdm_name = "l4_per_clkdm", 78 .clkdm_name = "ivahd_clkdm",
74 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
75 }, 80 },
76 { 81 {
77 .clkdm_name = "l4_secure_clkdm", 82 .clkdm_name = "l3_1_clkdm",
78 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 83 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
79 }, 84 },
80 { 85 {
81 .clkdm_name = "l4_wkup_clkdm", 86 .clkdm_name = "l3_2_clkdm",
82 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
83 }, 88 },
84 { 89 {
85 .clkdm_name = "tesla_clkdm", 90 .clkdm_name = "l3_dss_clkdm",
86 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 91 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
87 }, 92 },
88 { NULL },
89};
90
91static struct clkdm_dep iss_wkup_sleep_deps[] = {
92 { 93 {
93 .clkdm_name = "ivahd_clkdm", 94 .clkdm_name = "l3_emif_clkdm",
94 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
95 }, 96 },
96 { 97 {
97 .clkdm_name = "l3_1_clkdm", 98 .clkdm_name = "l3_gfx_clkdm",
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 99 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
99 }, 100 },
100 { 101 {
101 .clkdm_name = "l3_emif_clkdm", 102 .clkdm_name = "l3_init_clkdm",
102 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
103 }, 104 },
104 { NULL },
105};
106
107static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
108 { 105 {
109 .clkdm_name = "l3_1_clkdm", 106 .clkdm_name = "l4_cfg_clkdm",
110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
111 }, 108 },
112 { 109 {
113 .clkdm_name = "l3_emif_clkdm", 110 .clkdm_name = "l4_per_clkdm",
114 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
115 }, 112 },
116 { NULL },
117};
118
119static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
120 { 113 {
121 .clkdm_name = "abe_clkdm", 114 .clkdm_name = "l4_secure_clkdm",
122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
123 }, 116 },
124 { 117 {
125 .clkdm_name = "ivahd_clkdm", 118 .clkdm_name = "l4_wkup_clkdm",
126 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
127 }, 120 },
128 { 121 {
129 .clkdm_name = "l3_1_clkdm", 122 .clkdm_name = "tesla_clkdm",
130 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
131 }, 124 },
125 { NULL },
126};
127
128static struct clkdm_dep iss_wkup_sleep_deps[] = {
132 { 129 {
133 .clkdm_name = "l3_2_clkdm", 130 .clkdm_name = "ivahd_clkdm",
134 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 131 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
135 }, 132 },
136 { 133 {
137 .clkdm_name = "l3_emif_clkdm", 134 .clkdm_name = "l3_1_clkdm",
138 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
139 }, 136 },
140 { 137 {
141 .clkdm_name = "l3_init_clkdm", 138 .clkdm_name = "l3_emif_clkdm",
142 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 139 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
143 }, 140 },
141 { NULL },
142};
143
144static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
144 { 145 {
145 .clkdm_name = "l4_cfg_clkdm", 146 .clkdm_name = "l3_1_clkdm",
146 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 147 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
147 }, 148 },
148 { 149 {
149 .clkdm_name = "l4_per_clkdm", 150 .clkdm_name = "l3_emif_clkdm",
150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
151 }, 152 },
152 { NULL }, 153 { NULL },
@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
280 { NULL }, 281 { NULL },
281}; 282};
282 283
283static struct clkdm_dep mpuss_wkup_sleep_deps[] = { 284static struct clkdm_dep mpu_wkup_sleep_deps[] = {
284 { 285 {
285 .clkdm_name = "abe_clkdm", 286 .clkdm_name = "abe_clkdm",
286 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430) 287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
497 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 498 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
498}; 499};
499 500
500static struct clockdomain mpuss_44xx_clkdm = { 501static struct clockdomain d2d_44xx_clkdm = {
501 .name = "mpuss_clkdm", 502 .name = "d2d_clkdm",
502 .pwrdm = { .name = "mpu_pwrdm" }, 503 .pwrdm = { .name = "core_pwrdm" },
503 .prcm_partition = OMAP4430_CM1_PARTITION, 504 .prcm_partition = OMAP4430_CM2_PARTITION,
504 .cm_inst = OMAP4430_CM1_MPU_INST, 505 .cm_inst = OMAP4430_CM2_CORE_INST,
505 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS, 506 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
506 .wkdep_srcs = mpuss_wkup_sleep_deps, 507 .wkdep_srcs = d2d_wkup_sleep_deps,
507 .sleepdep_srcs = mpuss_wkup_sleep_deps, 508 .sleepdep_srcs = d2d_wkup_sleep_deps,
508 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, 509 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
510}; 511};
@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 564 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
564}; 565};
565 566
567static struct clockdomain mpu_44xx_clkdm = {
568 .name = "mpu_clkdm",
569 .pwrdm = { .name = "mpu_pwrdm" },
570 .prcm_partition = OMAP4430_CM1_PARTITION,
571 .cm_inst = OMAP4430_CM1_MPU_INST,
572 .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
573 .wkdep_srcs = mpu_wkup_sleep_deps,
574 .sleepdep_srcs = mpu_wkup_sleep_deps,
575 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
576 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
577};
578
566static struct clockdomain l3_2_44xx_clkdm = { 579static struct clockdomain l3_2_44xx_clkdm = {
567 .name = "l3_2_clkdm", 580 .name = "l3_2_clkdm",
568 .pwrdm = { .name = "core_pwrdm" }, 581 .pwrdm = { .name = "core_pwrdm" },
@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
585 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 598 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
586}; 599};
587 600
588static struct clockdomain l3_d2d_44xx_clkdm = {
589 .name = "l3_d2d_clkdm",
590 .pwrdm = { .name = "core_pwrdm" },
591 .prcm_partition = OMAP4430_CM2_PARTITION,
592 .cm_inst = OMAP4430_CM2_CORE_INST,
593 .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
594 .wkdep_srcs = l3_d2d_wkup_sleep_deps,
595 .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
596 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
597 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
598};
599
600static struct clockdomain iss_44xx_clkdm = { 601static struct clockdomain iss_44xx_clkdm = {
601 .name = "iss_clkdm", 602 .name = "iss_clkdm",
602 .pwrdm = { .name = "cam_pwrdm" }, 603 .pwrdm = { .name = "cam_pwrdm" },
@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
655 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 656 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
656}; 657};
657 658
659/* As clockdomains are added or removed above, this list must also be changed */
658static struct clockdomain *clockdomains_omap44xx[] __initdata = { 660static struct clockdomain *clockdomains_omap44xx[] __initdata = {
659 &l4_cefuse_44xx_clkdm, 661 &l4_cefuse_44xx_clkdm,
660 &l4_cfg_44xx_clkdm, 662 &l4_cfg_44xx_clkdm,
@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
666 &abe_44xx_clkdm, 668 &abe_44xx_clkdm,
667 &l3_instr_44xx_clkdm, 669 &l3_instr_44xx_clkdm,
668 &l3_init_44xx_clkdm, 670 &l3_init_44xx_clkdm,
669 &mpuss_44xx_clkdm, 671 &d2d_44xx_clkdm,
670 &mpu0_44xx_clkdm, 672 &mpu0_44xx_clkdm,
671 &mpu1_44xx_clkdm, 673 &mpu1_44xx_clkdm,
672 &l3_emif_44xx_clkdm, 674 &l3_emif_44xx_clkdm,
673 &l4_ao_44xx_clkdm, 675 &l4_ao_44xx_clkdm,
674 &ducati_44xx_clkdm, 676 &ducati_44xx_clkdm,
677 &mpu_44xx_clkdm,
675 &l3_2_44xx_clkdm, 678 &l3_2_44xx_clkdm,
676 &l3_1_44xx_clkdm, 679 &l3_1_44xx_clkdm,
677 &l3_d2d_44xx_clkdm,
678 &iss_44xx_clkdm, 680 &iss_44xx_clkdm,
679 &l3_dss_44xx_clkdm, 681 &l3_dss_44xx_clkdm,
680 &l4_wkup_44xx_clkdm, 682 &l4_wkup_44xx_clkdm,
681 &emu_sys_44xx_clkdm, 683 &emu_sys_44xx_clkdm,
682 &l3_dma_44xx_clkdm, 684 &l3_dma_44xx_clkdm,
683 NULL, 685 NULL
684}; 686};
685 687
686void __init omap44xx_clockdomains_init(void) 688void __init omap44xx_clockdomains_init(void)
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 9d47a05b17b4..0e77945d26ec 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,22 +22,18 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
24 24
25/* 25/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
26 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
27 * CM_TESLA_DYNAMICDEP
28 */
29#define OMAP4430_ABE_DYNDEP_SHIFT 3 26#define OMAP4430_ABE_DYNDEP_SHIFT 3
30#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) 27#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
31 28
32/* 29/*
33 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 30 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
34 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 31 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
35 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
36 */ 32 */
37#define OMAP4430_ABE_STATDEP_SHIFT 3 33#define OMAP4430_ABE_STATDEP_SHIFT 3
38#define OMAP4430_ABE_STATDEP_MASK (1 << 3) 34#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
39 35
40/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 36/* Used by CM_L4CFG_DYNAMICDEP */
41#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 37#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
42#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) 38#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
43 39
@@ -47,14 +43,13 @@
47 43
48/* 44/*
49 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, 45 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
50 * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY, 46 * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
51 * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, 47 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
52 * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
53 */ 48 */
54#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 49#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
55#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 50#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
56 51
57/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 52/* Used by CM_L4CFG_DYNAMICDEP */
58#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 53#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
59#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) 54#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
60 55
@@ -82,15 +77,15 @@
82#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 77#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
83#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) 78#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
84 79
85/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 80/* Used by CM_MEMIF_CLKSTCTRL */
86#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 81#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
87#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) 82#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
88 83
89/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 84/* Used by CM_MEMIF_CLKSTCTRL */
90#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 85#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
91#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) 86#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
92 87
93/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 88/* Used by CM_MEMIF_CLKSTCTRL */
94#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 89#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
95#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) 90#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
96 91
@@ -110,31 +105,31 @@
110#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 105#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
111#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) 106#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
112 107
113/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 108/* Used by CM_MEMIF_CLKSTCTRL */
114#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 109#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
115#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) 110#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
116 111
117/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 112/* Used by CM_L4PER_CLKSTCTRL */
118#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 113#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
119#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) 114#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
120 115
121/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 116/* Used by CM_L4PER_CLKSTCTRL */
122#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 117#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
123#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) 118#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
124 119
125/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 120/* Used by CM_L4PER_CLKSTCTRL */
126#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 121#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
127#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) 122#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
128 123
129/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 124/* Used by CM_L4PER_CLKSTCTRL */
130#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 125#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
131#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) 126#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
132 127
133/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 128/* Used by CM_L4PER_CLKSTCTRL */
134#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 129#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
135#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) 130#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
136 131
137/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 132/* Used by CM_L4PER_CLKSTCTRL */
138#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 133#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
139#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) 134#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
140 135
@@ -158,7 +153,7 @@
158#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 153#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
159#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) 154#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
160 155
161/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 156/* Used by CM_L4PER_CLKSTCTRL */
162#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 157#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
163#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) 158#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
164 159
@@ -170,55 +165,55 @@
170#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 165#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
171#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) 166#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
172 167
173/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 168/* Used by CM_L3INIT_CLKSTCTRL */
174#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 169#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
175#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) 170#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
176 171
177/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 172/* Used by CM_L3INIT_CLKSTCTRL */
178#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 173#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
179#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) 174#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
180 175
181/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 176/* Used by CM_L3INIT_CLKSTCTRL */
182#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 177#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
183#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) 178#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
184 179
185/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 180/* Used by CM_L3INIT_CLKSTCTRL */
186#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 181#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
187#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) 182#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
188 183
189/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 184/* Used by CM_L3INIT_CLKSTCTRL */
190#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 185#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
191#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) 186#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
192 187
193/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 188/* Used by CM_L3INIT_CLKSTCTRL */
194#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 189#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
195#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) 190#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
196 191
197/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 192/* Used by CM_L3INIT_CLKSTCTRL */
198#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 193#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
199#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) 194#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
200 195
201/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 196/* Used by CM_L3INIT_CLKSTCTRL */
202#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 197#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
203#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) 198#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
204 199
205/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 200/* Used by CM_L3INIT_CLKSTCTRL */
206#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 201#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
207#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) 202#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
208 203
209/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 204/* Used by CM_L3INIT_CLKSTCTRL */
210#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 205#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
211#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) 206#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
212 207
213/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 208/* Used by CM_L3INIT_CLKSTCTRL */
214#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 209#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
215#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) 210#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
216 211
217/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 212/* Used by CM_L3INIT_CLKSTCTRL */
218#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 213#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
219#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) 214#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
220 215
221/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 216/* Used by CM_L3INIT_CLKSTCTRL */
222#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 217#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
223#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) 218#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
224 219
@@ -234,11 +229,11 @@
234#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 229#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
235#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) 230#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
236 231
237/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ 232/* Used by CM_L3_1_CLKSTCTRL */
238#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 233#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
239#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) 234#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
240 235
241/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ 236/* Used by CM_L3_2_CLKSTCTRL */
242#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 237#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
243#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) 238#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
244 239
@@ -254,7 +249,7 @@
254#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 249#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
255#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) 250#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
256 251
257/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 252/* Used by CM_MEMIF_CLKSTCTRL */
258#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 253#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
259#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) 254#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
260 255
@@ -262,7 +257,7 @@
262#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 257#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
263#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) 258#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
264 259
265/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 260/* Used by CM_L3INIT_CLKSTCTRL */
266#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 261#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
267#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) 262#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
268 263
@@ -282,7 +277,7 @@
282#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 277#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
283#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) 278#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
284 279
285/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ 280/* Used by CM_L4CFG_CLKSTCTRL */
286#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 281#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
287#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) 282#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
288 283
@@ -290,11 +285,11 @@
290#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 285#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
291#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) 286#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
292 287
293/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 288/* Used by CM_L3INIT_CLKSTCTRL */
294#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 289#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
295#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) 290#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
296 291
297/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 292/* Used by CM_L4PER_CLKSTCTRL */
298#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 293#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
299#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) 294#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
300 295
@@ -306,7 +301,7 @@
306#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 301#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
307#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) 302#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
308 303
309/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ 304/* Used by CM_MPU_CLKSTCTRL */
310#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 305#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
311#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) 306#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
312 307
@@ -314,43 +309,43 @@
314#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 309#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
315#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) 310#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
316 311
317/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 312/* Used by CM_L4PER_CLKSTCTRL */
318#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 313#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
319#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) 314#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
320 315
321/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 316/* Used by CM_L4PER_CLKSTCTRL */
322#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 317#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
323#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) 318#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
324 319
325/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 320/* Used by CM_L4PER_CLKSTCTRL */
326#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 321#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
327#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) 322#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
328 323
329/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 324/* Used by CM_L4PER_CLKSTCTRL */
330#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 325#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
331#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) 326#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
332 327
333/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 328/* Used by CM_L4PER_CLKSTCTRL */
334#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 329#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
335#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) 330#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
336 331
337/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 332/* Used by CM_L4PER_CLKSTCTRL */
338#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 333#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
339#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) 334#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
340 335
341/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 336/* Used by CM_L4PER_CLKSTCTRL */
342#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 337#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
343#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) 338#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
344 339
345/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 340/* Used by CM_L4PER_CLKSTCTRL */
346#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 341#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
347#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) 342#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
348 343
349/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 344/* Used by CM_L4PER_CLKSTCTRL */
350#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 345#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
351#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) 346#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
352 347
353/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 348/* Used by CM_MEMIF_CLKSTCTRL */
354#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 349#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
355#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) 350#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
356 351
@@ -378,27 +373,27 @@
378#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 373#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
379#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) 374#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
380 375
381/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 376/* Used by CM_L3INIT_CLKSTCTRL */
382#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 377#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
383#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) 378#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
384 379
385/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 380/* Used by CM_L3INIT_CLKSTCTRL */
386#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 381#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
387#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) 382#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
388 383
389/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 384/* Used by CM_L3INIT_CLKSTCTRL */
390#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 385#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
391#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) 386#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
392 387
393/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 388/* Used by CM_L3INIT_CLKSTCTRL */
394#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 389#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
395#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) 390#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
396 391
397/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 392/* Used by CM_L3INIT_CLKSTCTRL */
398#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 393#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
399#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) 394#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
400 395
401/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 396/* Used by CM_L3INIT_CLKSTCTRL */
402#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 397#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
403#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) 398#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
404 399
@@ -406,11 +401,11 @@
406#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 401#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
407#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) 402#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
408 403
409/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 404/* Used by CM_L3INIT_CLKSTCTRL */
410#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 405#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
411#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) 406#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
412 407
413/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 408/* Used by CM_L3INIT_CLKSTCTRL */
414#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 409#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
415#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) 410#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
416 411
@@ -432,7 +427,7 @@
432 427
433/* 428/*
434 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, 429 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
435 * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ 430 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
436 */ 431 */
437#define OMAP4430_CLKSEL_0_0_SHIFT 0 432#define OMAP4430_CLKSEL_0_0_SHIFT 0
438#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) 433#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
@@ -453,14 +448,11 @@
453#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 448#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
454#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) 449#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
455 450
456/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 451/* Used by CM_CLKSEL_CORE */
457#define OMAP4430_CLKSEL_CORE_SHIFT 0 452#define OMAP4430_CLKSEL_CORE_SHIFT 0
458#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) 453#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
459 454
460/* 455/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
461 * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
462 * CM_SHADOW_FREQ_CONFIG2
463 */
464#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 456#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
465#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) 457#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
466 458
@@ -484,18 +476,15 @@
484#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 476#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
485#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) 477#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
486 478
487/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 479/* Used by CM_CLKSEL_CORE */
488#define OMAP4430_CLKSEL_L3_SHIFT 4 480#define OMAP4430_CLKSEL_L3_SHIFT 4
489#define OMAP4430_CLKSEL_L3_MASK (1 << 4) 481#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
490 482
491/* 483/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
492 * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
493 * CM_SHADOW_FREQ_CONFIG2
494 */
495#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 484#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
496#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) 485#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
497 486
498/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */ 487/* Used by CM_CLKSEL_CORE */
499#define OMAP4430_CLKSEL_L4_SHIFT 8 488#define OMAP4430_CLKSEL_L4_SHIFT 8
500#define OMAP4430_CLKSEL_L4_MASK (1 << 8) 489#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
501 490
@@ -526,11 +515,11 @@
526#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 515#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
527#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 516#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
528 517
529/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 518/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
530#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 519#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
531#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) 520#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
532 521
533/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 522/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
534#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 523#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
535#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) 524#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
536 525
@@ -538,13 +527,10 @@
538 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, 527 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
539 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, 528 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
540 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, 529 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
541 * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL, 530 * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
542 * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL, 531 * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
543 * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE, 532 * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
544 * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL, 533 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
545 * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
546 * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
547 * CM_WKUP_CLKSTCTRL
548 */ 534 */
549#define OMAP4430_CLKTRCTRL_SHIFT 0 535#define OMAP4430_CLKTRCTRL_SHIFT 0
550#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 536#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
@@ -561,10 +547,7 @@
561#define OMAP4430_CUSTOM_SHIFT 6 547#define OMAP4430_CUSTOM_SHIFT 6
562#define OMAP4430_CUSTOM_MASK (0x3 << 6) 548#define OMAP4430_CUSTOM_MASK (0x3 << 6)
563 549
564/* 550/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
565 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
566 * CM_L4CFG_DYNAMICDEP_RESTORE
567 */
568#define OMAP4430_D2D_DYNDEP_SHIFT 18 551#define OMAP4430_D2D_DYNDEP_SHIFT 18
569#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) 552#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
570 553
@@ -574,31 +557,29 @@
574 557
575/* 558/*
576 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 559 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
577 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY, 560 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
578 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, 561 * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
579 * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, 562 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
580 * CM_SSC_DELTAMSTEP_DPLL_USB
581 */ 563 */
582#define OMAP4430_DELTAMSTEP_SHIFT 0 564#define OMAP4430_DELTAMSTEP_SHIFT 0
583#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) 565#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
584 566
585/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 567/* Used by CM_DLL_CTRL */
586#define OMAP4430_DLL_OVERRIDE_SHIFT 2 568#define OMAP4430_DLL_OVERRIDE_SHIFT 0
587#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2) 569#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
588 570
589/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ 571/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
590#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 572#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
591#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0) 573#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
592 574
593/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 575/* Used by CM_SHADOW_FREQ_CONFIG1 */
594#define OMAP4430_DLL_RESET_SHIFT 3 576#define OMAP4430_DLL_RESET_SHIFT 3
595#define OMAP4430_DLL_RESET_MASK (1 << 3) 577#define OMAP4430_DLL_RESET_MASK (1 << 3)
596 578
597/* 579/*
598 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 580 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
599 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 581 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
600 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 582 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
601 * CM_CLKSEL_DPLL_USB
602 */ 583 */
603#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 584#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
604#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) 585#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
@@ -607,28 +588,19 @@
607#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 588#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
608#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) 589#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
609 590
610/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */ 591/* Used by CM_CLKSEL_DPLL_CORE */
611#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 592#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
612#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) 593#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
613 594
614/* 595/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
615 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
616 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
617 */
618#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 596#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
619#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 597#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
620 598
621/* 599/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
622 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
623 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
624 */
625#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 600#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
626#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) 601#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
627 602
628/* 603/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
629 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
630 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
631 */
632#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 604#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
633#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) 605#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
634 606
@@ -637,9 +609,8 @@
637#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 609#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
638 610
639/* 611/*
640 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 612 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
641 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 613 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
642 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
643 */ 614 */
644#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 615#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
645#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 616#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
@@ -649,9 +620,8 @@
649#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 620#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
650 621
651/* 622/*
652 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 623 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
653 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 624 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
654 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
655 */ 625 */
656#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 626#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
657#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) 627#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
@@ -661,29 +631,28 @@
661#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) 631#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
662 632
663/* 633/*
664 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 634 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
665 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 635 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
666 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
667 */ 636 */
668#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 637#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
669#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 638#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
670 639
671/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 640/* Used by CM_SHADOW_FREQ_CONFIG1 */
672#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 641#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
673#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) 642#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
674 643
675/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 644/* Used by CM_SHADOW_FREQ_CONFIG1 */
676#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 645#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
677#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) 646#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
678 647
679/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 648/* Used by CM_SHADOW_FREQ_CONFIG2 */
680#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 649#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
681#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) 650#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
682 651
683/* 652/*
684 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 653 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
685 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 654 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
686 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 655 * CM_CLKSEL_DPLL_UNIPRO
687 */ 656 */
688#define OMAP4430_DPLL_DIV_SHIFT 0 657#define OMAP4430_DPLL_DIV_SHIFT 0
689#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 658#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
@@ -693,9 +662,8 @@
693#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 662#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
694 663
695/* 664/*
696 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 665 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
697 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 666 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
698 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
699 */ 667 */
700#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 668#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
701#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 669#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
@@ -705,26 +673,25 @@
705#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) 673#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
706 674
707/* 675/*
708 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 676 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
709 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 677 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
710 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 678 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
711 * CM_CLKMODE_DPLL_USB
712 */ 679 */
713#define OMAP4430_DPLL_EN_SHIFT 0 680#define OMAP4430_DPLL_EN_SHIFT 0
714#define OMAP4430_DPLL_EN_MASK (0x7 << 0) 681#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
715 682
716/* 683/*
717 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 684 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
718 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 685 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
719 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 686 * CM_CLKMODE_DPLL_UNIPRO
720 */ 687 */
721#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 688#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
722#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 689#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
723 690
724/* 691/*
725 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 692 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
726 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, 693 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
727 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO 694 * CM_CLKSEL_DPLL_UNIPRO
728 */ 695 */
729#define OMAP4430_DPLL_MULT_SHIFT 8 696#define OMAP4430_DPLL_MULT_SHIFT 8
730#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 697#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
@@ -734,9 +701,9 @@
734#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 701#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
735 702
736/* 703/*
737 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 704 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
738 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 705 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
739 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO 706 * CM_CLKMODE_DPLL_UNIPRO
740 */ 707 */
741#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 708#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
742#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 709#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
@@ -746,55 +713,46 @@
746#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 713#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
747 714
748/* 715/*
749 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 716 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
750 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 717 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
751 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 718 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
752 * CM_CLKMODE_DPLL_USB
753 */ 719 */
754#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 720#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
755#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) 721#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
756 722
757/* 723/*
758 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 724 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
759 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 725 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
760 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 726 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
761 * CM_CLKMODE_DPLL_USB
762 */ 727 */
763#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 728#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
764#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) 729#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
765 730
766/* 731/*
767 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 732 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
768 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, 733 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
769 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 734 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
770 * CM_CLKMODE_DPLL_USB
771 */ 735 */
772#define OMAP4430_DPLL_SSC_EN_SHIFT 12 736#define OMAP4430_DPLL_SSC_EN_SHIFT 12
773#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) 737#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
774 738
775/* 739/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
776 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
777 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
778 */
779#define OMAP4430_DSS_DYNDEP_SHIFT 8 740#define OMAP4430_DSS_DYNDEP_SHIFT 8
780#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) 741#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
781 742
782/* 743/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
783 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
784 * CM_SDMA_STATICDEP_RESTORE
785 */
786#define OMAP4430_DSS_STATDEP_SHIFT 8 744#define OMAP4430_DSS_STATDEP_SHIFT 8
787#define OMAP4430_DSS_STATDEP_MASK (1 << 8) 745#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
788 746
789/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 747/* Used by CM_L3_2_DYNAMICDEP */
790#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 748#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
791#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) 749#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
792 750
793/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */ 751/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
794#define OMAP4430_DUCATI_STATDEP_SHIFT 0 752#define OMAP4430_DUCATI_STATDEP_SHIFT 0
795#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) 753#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
796 754
797/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */ 755/* Used by CM_SHADOW_FREQ_CONFIG1 */
798#define OMAP4430_FREQ_UPDATE_SHIFT 0 756#define OMAP4430_FREQ_UPDATE_SHIFT 0
799#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) 757#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
800 758
@@ -802,7 +760,7 @@
802#define OMAP4430_FUNC_SHIFT 16 760#define OMAP4430_FUNC_SHIFT 16
803#define OMAP4430_FUNC_MASK (0xfff << 16) 761#define OMAP4430_FUNC_MASK (0xfff << 16)
804 762
805/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 763/* Used by CM_L3_2_DYNAMICDEP */
806#define OMAP4430_GFX_DYNDEP_SHIFT 10 764#define OMAP4430_GFX_DYNDEP_SHIFT 10
807#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) 765#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
808 766
@@ -810,119 +768,95 @@
810#define OMAP4430_GFX_STATDEP_SHIFT 10 768#define OMAP4430_GFX_STATDEP_SHIFT 10
811#define OMAP4430_GFX_STATDEP_MASK (1 << 10) 769#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
812 770
813/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */ 771/* Used by CM_SHADOW_FREQ_CONFIG2 */
814#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 772#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
815#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) 773#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
816 774
817/* 775/*
818 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 776 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
819 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 777 * CM_DIV_M4_DPLL_PER
820 */ 778 */
821#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 779#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
822#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 780#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
823 781
824/* 782/*
825 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 783 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
826 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 784 * CM_DIV_M4_DPLL_PER
827 */ 785 */
828#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 786#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
829#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) 787#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
830 788
831/* 789/*
832 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 790 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
833 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 791 * CM_DIV_M4_DPLL_PER
834 */ 792 */
835#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 793#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
836#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) 794#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
837 795
838/* 796/*
839 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 797 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
840 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 798 * CM_DIV_M4_DPLL_PER
841 */ 799 */
842#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 800#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
843#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) 801#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
844 802
845/* 803/*
846 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 804 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
847 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 805 * CM_DIV_M5_DPLL_PER
848 */ 806 */
849#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 807#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
850#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 808#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
851 809
852/* 810/*
853 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 811 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
854 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 812 * CM_DIV_M5_DPLL_PER
855 */ 813 */
856#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 814#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
857#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) 815#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
858 816
859/* 817/*
860 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 818 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
861 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 819 * CM_DIV_M5_DPLL_PER
862 */ 820 */
863#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 821#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
864#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) 822#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
865 823
866/* 824/*
867 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 825 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
868 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 826 * CM_DIV_M5_DPLL_PER
869 */ 827 */
870#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 828#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
871#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) 829#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
872 830
873/* 831/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
874 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
875 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
876 */
877#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 832#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
878#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 833#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
879 834
880/* 835/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
881 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
882 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
883 */
884#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 836#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
885#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) 837#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
886 838
887/* 839/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
888 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
889 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
890 */
891#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 840#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
892#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) 841#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
893 842
894/* 843/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
895 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
896 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
897 */
898#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 844#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
899#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) 845#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
900 846
901/* 847/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
902 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
903 * CM_DIV_M7_DPLL_PER
904 */
905#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 848#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
906#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 849#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
907 850
908/* 851/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
909 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
910 * CM_DIV_M7_DPLL_PER
911 */
912#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 852#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
913#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) 853#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
914 854
915/* 855/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
916 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
917 * CM_DIV_M7_DPLL_PER
918 */
919#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 856#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
920#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) 857#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
921 858
922/* 859/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
923 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
924 * CM_DIV_M7_DPLL_PER
925 */
926#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 860#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
927#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) 861#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
928 862
@@ -934,8 +868,7 @@
934 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 868 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
935 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 869 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
936 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 870 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
937 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 871 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
938 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
939 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 872 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
940 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 873 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
941 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 874 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -944,30 +877,24 @@
944 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 877 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
945 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 878 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
946 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 879 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
947 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 880 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
948 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 881 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
949 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 882 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
950 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
951 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
952 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
953 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 883 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
954 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 884 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
955 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 885 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
956 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 886 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
957 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 887 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
958 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 888 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
959 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 889 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
960 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 890 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
961 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 891 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
962 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 892 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
963 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 893 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
964 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 894 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
965 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 895 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
966 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 896 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
967 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 897 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
968 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
969 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
970 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
971 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 898 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
972 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 899 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
973 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 900 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -983,166 +910,148 @@
983#define OMAP4430_IDLEST_SHIFT 16 910#define OMAP4430_IDLEST_SHIFT 16
984#define OMAP4430_IDLEST_MASK (0x3 << 16) 911#define OMAP4430_IDLEST_MASK (0x3 << 16)
985 912
986/* 913/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
987 * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
988 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
989 */
990#define OMAP4430_ISS_DYNDEP_SHIFT 9 914#define OMAP4430_ISS_DYNDEP_SHIFT 9
991#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) 915#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
992 916
993/* 917/*
994 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 918 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
995 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 919 * CM_TESLA_STATICDEP
996 */ 920 */
997#define OMAP4430_ISS_STATDEP_SHIFT 9 921#define OMAP4430_ISS_STATDEP_SHIFT 9
998#define OMAP4430_ISS_STATDEP_MASK (1 << 9) 922#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
999 923
1000/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */ 924/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
1001#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 925#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
1002#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) 926#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
1003 927
1004/* 928/*
1005 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 929 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1006 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, 930 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
1007 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 931 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1008 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1009 */ 932 */
1010#define OMAP4430_IVAHD_STATDEP_SHIFT 2 933#define OMAP4430_IVAHD_STATDEP_SHIFT 2
1011#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) 934#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
1012 935
1013/* 936/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1014 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1015 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
1016 */
1017#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 937#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
1018#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) 938#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
1019 939
1020/* 940/*
1021 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 941 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
1022 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 942 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1023 * CM_TESLA_STATICDEP
1024 */ 943 */
1025#define OMAP4430_L3INIT_STATDEP_SHIFT 7 944#define OMAP4430_L3INIT_STATDEP_SHIFT 7
1026#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) 945#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
1027 946
1028/* 947/*
1029 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, 948 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1030 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 949 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1031 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1032 */ 950 */
1033#define OMAP4430_L3_1_DYNDEP_SHIFT 5 951#define OMAP4430_L3_1_DYNDEP_SHIFT 5
1034#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) 952#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
1035 953
1036/* 954/*
1037 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 955 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1038 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 956 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1039 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 957 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1040 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 958 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1041 */ 959 */
1042#define OMAP4430_L3_1_STATDEP_SHIFT 5 960#define OMAP4430_L3_1_STATDEP_SHIFT 5
1043#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) 961#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
1044 962
1045/* 963/*
1046 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, 964 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
1047 * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, 965 * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
1048 * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, 966 * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1049 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 967 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1050 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1051 */ 968 */
1052#define OMAP4430_L3_2_DYNDEP_SHIFT 6 969#define OMAP4430_L3_2_DYNDEP_SHIFT 6
1053#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) 970#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
1054 971
1055/* 972/*
1056 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 973 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1057 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 974 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1058 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 975 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1059 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 976 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1060 */ 977 */
1061#define OMAP4430_L3_2_STATDEP_SHIFT 6 978#define OMAP4430_L3_2_STATDEP_SHIFT 6
1062#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) 979#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
1063 980
1064/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */ 981/* Used by CM_L3_1_DYNAMICDEP */
1065#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 982#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
1066#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) 983#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
1067 984
1068/* 985/*
1069 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 986 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1070 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, 987 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1071 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1072 */ 988 */
1073#define OMAP4430_L4CFG_STATDEP_SHIFT 12 989#define OMAP4430_L4CFG_STATDEP_SHIFT 12
1074#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) 990#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
1075 991
1076/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */ 992/* Used by CM_L3_2_DYNAMICDEP */
1077#define OMAP4430_L4PER_DYNDEP_SHIFT 13 993#define OMAP4430_L4PER_DYNDEP_SHIFT 13
1078#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) 994#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
1079 995
1080/* 996/*
1081 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP, 997 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1082 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 998 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1083 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1084 */ 999 */
1085#define OMAP4430_L4PER_STATDEP_SHIFT 13 1000#define OMAP4430_L4PER_STATDEP_SHIFT 13
1086#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) 1001#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
1087 1002
1088/* 1003/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1089 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1090 * CM_L4PER_DYNAMICDEP_RESTORE
1091 */
1092#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1004#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
1093#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) 1005#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
1094 1006
1095/* 1007/*
1096 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1008 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1097 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE 1009 * CM_SDMA_STATICDEP
1098 */ 1010 */
1099#define OMAP4430_L4SEC_STATDEP_SHIFT 14 1011#define OMAP4430_L4SEC_STATDEP_SHIFT 14
1100#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) 1012#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
1101 1013
1102/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1014/* Used by CM_L4CFG_DYNAMICDEP */
1103#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1015#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
1104#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) 1016#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
1105 1017
1106/* 1018/*
1107 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, 1019 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1108 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1020 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1109 */ 1021 */
1110#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1022#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
1111#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) 1023#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
1112 1024
1113/* 1025/*
1114 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP, 1026 * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1115 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1027 * CM_MPU_DYNAMICDEP
1116 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
1117 */ 1028 */
1118#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1029#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
1119#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) 1030#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
1120 1031
1121/* 1032/*
1122 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, 1033 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1123 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, 1034 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1124 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, 1035 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1125 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP 1036 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1126 */ 1037 */
1127#define OMAP4430_MEMIF_STATDEP_SHIFT 4 1038#define OMAP4430_MEMIF_STATDEP_SHIFT 4
1128#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) 1039#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
1129 1040
1130/* 1041/*
1131 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1042 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1132 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1043 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1133 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1044 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1134 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1045 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1135 * CM_SSC_MODFREQDIV_DPLL_USB
1136 */ 1046 */
1137#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1047#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
1138#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) 1048#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1139 1049
1140/* 1050/*
1141 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1051 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1142 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY, 1052 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1143 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, 1053 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1144 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1054 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1145 * CM_SSC_MODFREQDIV_DPLL_USB
1146 */ 1055 */
1147#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1056#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
1148#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) 1057#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
@@ -1155,8 +1064,7 @@
1155 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL, 1064 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1156 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, 1065 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1157 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1066 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1158 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE, 1067 * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
1159 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
1160 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, 1068 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1161 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 1069 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1162 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, 1070 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -1165,30 +1073,24 @@
1165 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1073 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1166 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1074 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1167 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1075 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1168 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1076 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1169 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 1077 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
1170 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL, 1078 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
1171 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
1172 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
1173 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
1174 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL, 1079 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1175 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL, 1080 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1176 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL, 1081 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1177 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, 1082 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1178 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, 1083 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1179 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, 1084 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1180 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1085 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1181 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1086 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1182 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1087 * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
1183 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE, 1088 * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
1184 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 1089 * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
1185 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, 1090 * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
1186 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, 1091 * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
1187 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, 1092 * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
1188 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, 1093 * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1189 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
1190 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1191 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1192 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, 1094 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1193 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, 1095 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1194 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, 1096 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -1221,11 +1123,9 @@
1221#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) 1123#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1222 1124
1223/* 1125/*
1224 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1126 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1225 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE, 1127 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1226 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1128 * CM_WKUP_GPIO1_CLKCTRL
1227 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1228 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
1229 */ 1129 */
1230#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1130#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
1231#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) 1131#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
@@ -1254,23 +1154,23 @@
1254#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1154#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
1255#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) 1155#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
1256 1156
1257/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1157/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1258#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1158#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
1259#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) 1159#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
1260 1160
1261/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1161/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1262#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1162#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1263#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) 1163#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1264 1164
1265/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1165/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1266#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1166#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1267#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) 1167#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1268 1168
1269/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1169/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1270#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1170#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1271#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) 1171#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1272 1172
1273/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1173/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1274#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1174#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1275#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) 1175#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1276 1176
@@ -1306,27 +1206,27 @@
1306#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1206#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
1307#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) 1207#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
1308 1208
1309/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1209/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1310#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1210#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1311#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) 1211#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1312 1212
1313/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1213/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1314#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1214#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1315#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) 1215#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1316 1216
1317/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1217/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1318#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1218#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1319#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) 1219#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1320 1220
1321/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1221/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1322#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1222#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1323#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) 1223#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1324 1224
1325/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1225/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1326#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1226#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1327#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) 1227#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1328 1228
1329/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1229/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1330#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1230#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1331#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) 1231#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1332 1232
@@ -1374,7 +1274,7 @@
1374#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1274#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
1375#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) 1275#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
1376 1276
1377/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */ 1277/* Used by CM_DYN_DEP_PRESCAL */
1378#define OMAP4430_PRESCAL_SHIFT 0 1278#define OMAP4430_PRESCAL_SHIFT 0
1379#define OMAP4430_PRESCAL_MASK (0x3f << 0) 1279#define OMAP4430_PRESCAL_MASK (0x3f << 0)
1380 1280
@@ -1382,10 +1282,7 @@
1382#define OMAP4430_R_RTL_SHIFT 11 1282#define OMAP4430_R_RTL_SHIFT 11
1383#define OMAP4430_R_RTL_MASK (0x1f << 11) 1283#define OMAP4430_R_RTL_MASK (0x1f << 11)
1384 1284
1385/* 1285/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
1386 * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1387 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
1388 */
1389#define OMAP4430_SAR_MODE_SHIFT 4 1286#define OMAP4430_SAR_MODE_SHIFT 4
1390#define OMAP4430_SAR_MODE_MASK (1 << 4) 1287#define OMAP4430_SAR_MODE_MASK (1 << 4)
1391 1288
@@ -1397,7 +1294,7 @@
1397#define OMAP4430_SCHEME_SHIFT 30 1294#define OMAP4430_SCHEME_SHIFT 30
1398#define OMAP4430_SCHEME_MASK (0x3 << 30) 1295#define OMAP4430_SCHEME_MASK (0x3 << 30)
1399 1296
1400/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1297/* Used by CM_L4CFG_DYNAMICDEP */
1401#define OMAP4430_SDMA_DYNDEP_SHIFT 11 1298#define OMAP4430_SDMA_DYNDEP_SHIFT 11
1402#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) 1299#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
1403 1300
@@ -1417,10 +1314,10 @@
1417 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1314 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1418 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1315 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1419 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1316 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1420 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1317 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1421 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1318 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
1422 * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, 1319 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1423 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL 1320 * CM_TESLA_TESLA_CLKCTRL
1424 */ 1321 */
1425#define OMAP4430_STBYST_SHIFT 18 1322#define OMAP4430_STBYST_SHIFT 18
1426#define OMAP4430_STBYST_MASK (1 << 18) 1323#define OMAP4430_STBYST_MASK (1 << 18)
@@ -1438,17 +1335,13 @@
1438#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) 1335#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1439 1336
1440/* 1337/*
1441 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 1338 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
1442 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU, 1339 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1443 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1444 */ 1340 */
1445#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1341#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
1446#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) 1342#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
1447 1343
1448/* 1344/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
1449 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
1450 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
1451 */
1452#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1345#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
1453#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) 1346#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
1454 1347
@@ -1457,30 +1350,24 @@
1457#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) 1350#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
1458 1351
1459/* 1352/*
1460 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE, 1353 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
1461 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER 1354 * CM_DIV_M4_DPLL_PER
1462 */ 1355 */
1463#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1356#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
1464#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) 1357#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
1465 1358
1466/* 1359/*
1467 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE, 1360 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1468 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER 1361 * CM_DIV_M5_DPLL_PER
1469 */ 1362 */
1470#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1363#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
1471#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) 1364#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
1472 1365
1473/* 1366/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1474 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
1475 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
1476 */
1477#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1367#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
1478#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) 1368#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
1479 1369
1480/* 1370/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1481 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
1482 * CM_DIV_M7_DPLL_PER
1483 */
1484#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1371#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
1485#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) 1372#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
1486 1373
@@ -1496,7 +1383,7 @@
1496#define OMAP4430_SYS_CLKSEL_SHIFT 0 1383#define OMAP4430_SYS_CLKSEL_SHIFT 0
1497#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) 1384#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
1498 1385
1499/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */ 1386/* Used by CM_L4CFG_DYNAMICDEP */
1500#define OMAP4430_TESLA_DYNDEP_SHIFT 1 1387#define OMAP4430_TESLA_DYNDEP_SHIFT 1
1501#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) 1388#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
1502 1389
@@ -1505,11 +1392,9 @@
1505#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) 1392#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
1506 1393
1507/* 1394/*
1508 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP, 1395 * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1509 * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, 1396 * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1510 * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, 1397 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1511 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1512 * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1513 */ 1398 */
1514#define OMAP4430_WINDOWSIZE_SHIFT 24 1399#define OMAP4430_WINDOWSIZE_SHIFT 24
1515#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) 1400#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index e2d7a56b2ad6..1bc00dc4876c 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP44xx CM1 instance offset macros 2 * OMAP44xx CM1 instance offset macros
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -41,9 +41,9 @@
41#define OMAP4430_CM1_INSTR_INST 0x0f00 41#define OMAP4430_CM1_INSTR_INST 0x0f00
42 42
43/* CM1 clockdomain register offsets (from instance start) */ 43/* CM1 clockdomain register offsets (from instance start) */
44#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 44#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
45#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 45#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
46#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 46#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
47 47
48/* CM1 */ 48/* CM1 */
49 49
@@ -82,8 +82,8 @@
82#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) 82#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
83#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 83#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
84#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) 84#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
85#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c 85#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
86#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) 86#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
87#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 87#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
88#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) 88#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
89#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 89#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
@@ -98,8 +98,8 @@
98#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) 98#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
99#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 99#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) 100#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
101#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c 101#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
102#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) 102#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c 103#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) 104#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 105#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
@@ -116,8 +116,8 @@
116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) 116#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 117#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) 118#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
119#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc 119#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
120#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) 120#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc 121#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) 122#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 123#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
@@ -134,8 +134,8 @@
134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) 134#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) 136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
137#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c 137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
138#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) 138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 139#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) 140#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 141#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
@@ -154,8 +154,8 @@
154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) 154#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 155#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) 156#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
157#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c 157#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
158#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) 158#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 159#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) 160#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 161#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
@@ -217,42 +217,6 @@
217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 217#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) 218#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
219 219
220/* CM1.RESTORE_CM1 register offsets */
221#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
222#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
223#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
224#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
225#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
226#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
227#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
228#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
229#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
230#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
231#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
232#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
233#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
234#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
235#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
236#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
237#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
238#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
239#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
240#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
241#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
242#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
243#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
244#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
245#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
246#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
247#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
248#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
249#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
250#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
251#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
252#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
253#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
254#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
255
256/* Function prototypes */ 220/* Function prototypes */
257extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx); 221extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
258extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx); 222extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index aa4745044065..b9de72da1a8e 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP44xx CM2 instance offset macros 2 * OMAP44xx CM2 instance offset macros
3 * 3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc. 4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
@@ -40,9 +40,9 @@
40#define OMAP4430_CM2_CAM_INST 0x1000 40#define OMAP4430_CM2_CAM_INST 0x1000
41#define OMAP4430_CM2_DSS_INST 0x1100 41#define OMAP4430_CM2_DSS_INST 0x1100
42#define OMAP4430_CM2_GFX_INST 0x1200 42#define OMAP4430_CM2_GFX_INST 0x1200
43#define OMAP4430_CM2_L3INIT_INST 0x1300 43#define OMAP4430_CM2_L3INIT_INST 0x1300
44#define OMAP4430_CM2_L4PER_INST 0x1400 44#define OMAP4430_CM2_L4PER_INST 0x1400
45#define OMAP4430_CM2_CEFUSE_INST 0x1600 45#define OMAP4430_CM2_CEFUSE_INST 0x1600
46#define OMAP4430_CM2_RESTORE_INST 0x1e00 46#define OMAP4430_CM2_RESTORE_INST 0x1e00
47#define OMAP4430_CM2_INSTR_INST 0x1f00 47#define OMAP4430_CM2_INSTR_INST 0x1f00
48 48
@@ -65,7 +65,6 @@
65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 65#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 66#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
67 67
68
69/* CM2 */ 68/* CM2 */
70 69
71/* CM2.OCP_SOCKET_CM2 register offsets */ 70/* CM2.OCP_SOCKET_CM2 register offsets */
@@ -121,8 +120,8 @@
121#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) 120#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
122#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 121#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
123#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) 122#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
124#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c 123#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
125#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) 124#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
126#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 125#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
127#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) 126#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
128#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 127#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
@@ -135,8 +134,8 @@
135#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) 134#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
136#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 135#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
137#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) 136#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
138#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac 137#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
139#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) 138#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
140#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 139#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
141#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) 140#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
142#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 141#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
@@ -151,8 +150,8 @@
151#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) 150#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
152#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 151#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
153#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) 152#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
154#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 153#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
155#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) 154#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
156 155
157/* CM2.ALWAYS_ON_CM2 register offsets */ 156/* CM2.ALWAYS_ON_CM2 register offsets */
158#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 157#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
@@ -227,8 +226,8 @@
227#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) 226#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
228#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 227#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
229#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) 228#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
230#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528 229#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
231#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) 230#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
232#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 231#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
233#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) 232#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
234#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 233#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
@@ -450,56 +449,6 @@
450#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 449#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
451#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 450#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
452 451
453/* CM2.RESTORE_CM2 register offsets */
454#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
455#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
456#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
457#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
458#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
459#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
460#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
461#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
462#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
463#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
464#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
465#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
466#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
467#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
468#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
469#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
470#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
471#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
472#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
473#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
474#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
475#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
476#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
477#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
478#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
479#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
480#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
481#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
482#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
483#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
484#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
485#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
486#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
487#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
488#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
489#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
490#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
491#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
492#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
493#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
494#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
495#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
496#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
497#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
498#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
499#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
500#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
501#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
502
503/* Function prototypes */ 452/* Function prototypes */
504extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx); 453extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
505extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx); 454extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 293fa6cd50e1..7d242c9e2a2c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,6 +2,7 @@
2 * omap_hwmod implementation for OMAP2/3/4 2 * omap_hwmod implementation for OMAP2/3/4
3 * 3 *
4 * Copyright (C) 2009-2011 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2011 Texas Instruments, Inc.
5 * 6 *
6 * Paul Walmsley, Benoît Cousson, Kevin Hilman 7 * Paul Walmsley, Benoît Cousson, Kevin Hilman
7 * 8 *
@@ -387,11 +388,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
387 */ 388 */
388static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) 389static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
389{ 390{
390 u32 wakeup_mask;
391
392 if (!oh->class->sysc || 391 if (!oh->class->sysc ||
393 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || 392 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
394 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) 393 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
394 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
395 return -EINVAL; 395 return -EINVAL;
396 396
397 if (!oh->class->sysc->sysc_fields) { 397 if (!oh->class->sysc->sysc_fields) {
@@ -399,12 +399,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
399 return -EINVAL; 399 return -EINVAL;
400 } 400 }
401 401
402 wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); 402 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
403 403 *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
404 *v |= wakeup_mask;
405 404
406 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) 405 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
407 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); 406 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
407 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
408 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
408 409
409 /* XXX test pwrdm_get_wken for this hwmod's subsystem */ 410 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
410 411
@@ -422,11 +423,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
422 */ 423 */
423static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) 424static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
424{ 425{
425 u32 wakeup_mask;
426
427 if (!oh->class->sysc || 426 if (!oh->class->sysc ||
428 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || 427 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
429 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP))) 428 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
429 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
430 return -EINVAL; 430 return -EINVAL;
431 431
432 if (!oh->class->sysc->sysc_fields) { 432 if (!oh->class->sysc->sysc_fields) {
@@ -434,12 +434,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
434 return -EINVAL; 434 return -EINVAL;
435 } 435 }
436 436
437 wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); 437 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
438 438 *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
439 *v &= ~wakeup_mask;
440 439
441 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) 440 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
442 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); 441 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
442 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
443 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
443 444
444 /* XXX test pwrdm_get_wken for this hwmod's subsystem */ 445 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
445 446
@@ -678,6 +679,75 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
678} 679}
679 680
680/** 681/**
682 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
683 * @oh: struct omap_hwmod *oh
684 *
685 * Count and return the number of MPU IRQs associated with the hwmod
686 * @oh. Used to allocate struct resource data. Returns 0 if @oh is
687 * NULL.
688 */
689static int _count_mpu_irqs(struct omap_hwmod *oh)
690{
691 struct omap_hwmod_irq_info *ohii;
692 int i = 0;
693
694 if (!oh || !oh->mpu_irqs)
695 return 0;
696
697 do {
698 ohii = &oh->mpu_irqs[i++];
699 } while (ohii->irq != -1);
700
701 return i;
702}
703
704/**
705 * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
706 * @oh: struct omap_hwmod *oh
707 *
708 * Count and return the number of SDMA request lines associated with
709 * the hwmod @oh. Used to allocate struct resource data. Returns 0
710 * if @oh is NULL.
711 */
712static int _count_sdma_reqs(struct omap_hwmod *oh)
713{
714 struct omap_hwmod_dma_info *ohdi;
715 int i = 0;
716
717 if (!oh || !oh->sdma_reqs)
718 return 0;
719
720 do {
721 ohdi = &oh->sdma_reqs[i++];
722 } while (ohdi->dma_req != -1);
723
724 return i;
725}
726
727/**
728 * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
729 * @oh: struct omap_hwmod *oh
730 *
731 * Count and return the number of address space ranges associated with
732 * the hwmod @oh. Used to allocate struct resource data. Returns 0
733 * if @oh is NULL.
734 */
735static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
736{
737 struct omap_hwmod_addr_space *mem;
738 int i = 0;
739
740 if (!os || !os->addr)
741 return 0;
742
743 do {
744 mem = &os->addr[i++];
745 } while (mem->pa_start != mem->pa_end);
746
747 return i;
748}
749
750/**
681 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use 751 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
682 * @oh: struct omap_hwmod * 752 * @oh: struct omap_hwmod *
683 * 753 *
@@ -722,8 +792,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
722{ 792{
723 struct omap_hwmod_ocp_if *os; 793 struct omap_hwmod_ocp_if *os;
724 struct omap_hwmod_addr_space *mem; 794 struct omap_hwmod_addr_space *mem;
725 int i; 795 int i = 0, found = 0;
726 int found = 0;
727 void __iomem *va_start; 796 void __iomem *va_start;
728 797
729 if (!oh || oh->slaves_cnt == 0) 798 if (!oh || oh->slaves_cnt == 0)
@@ -731,12 +800,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
731 800
732 os = oh->slaves[index]; 801 os = oh->slaves[index];
733 802
734 for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { 803 if (!os->addr)
735 if (mem->flags & ADDR_TYPE_RT) { 804 return NULL;
805
806 do {
807 mem = &os->addr[i++];
808 if (mem->flags & ADDR_TYPE_RT)
736 found = 1; 809 found = 1;
737 break; 810 } while (!found && mem->pa_start != mem->pa_end);
738 }
739 }
740 811
741 if (found) { 812 if (found) {
742 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); 813 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
@@ -781,8 +852,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
781 } 852 }
782 853
783 if (sf & SYSC_HAS_MIDLEMODE) { 854 if (sf & SYSC_HAS_MIDLEMODE) {
784 idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? 855 if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
785 HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; 856 idlemode = HWMOD_IDLEMODE_NO;
857 } else {
858 if (sf & SYSC_HAS_ENAWAKEUP)
859 _enable_wakeup(oh, &v);
860 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
861 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
862 else
863 idlemode = HWMOD_IDLEMODE_SMART;
864 }
786 _set_master_standbymode(oh, idlemode, &v); 865 _set_master_standbymode(oh, idlemode, &v);
787 } 866 }
788 867
@@ -840,8 +919,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
840 } 919 }
841 920
842 if (sf & SYSC_HAS_MIDLEMODE) { 921 if (sf & SYSC_HAS_MIDLEMODE) {
843 idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? 922 if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
844 HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; 923 idlemode = HWMOD_IDLEMODE_FORCE;
924 } else {
925 if (sf & SYSC_HAS_ENAWAKEUP)
926 _enable_wakeup(oh, &v);
927 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
928 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
929 else
930 idlemode = HWMOD_IDLEMODE_SMART;
931 }
845 _set_master_standbymode(oh, idlemode, &v); 932 _set_master_standbymode(oh, idlemode, &v);
846 } 933 }
847 934
@@ -928,6 +1015,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
928 1015
929 if (!ret) 1016 if (!ret)
930 oh->_state = _HWMOD_STATE_CLKS_INITED; 1017 oh->_state = _HWMOD_STATE_CLKS_INITED;
1018 else
1019 pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
931 1020
932 return ret; 1021 return ret;
933} 1022}
@@ -1224,6 +1313,8 @@ static int _enable(struct omap_hwmod *oh)
1224{ 1313{
1225 int r; 1314 int r;
1226 1315
1316 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1317
1227 if (oh->_state != _HWMOD_STATE_INITIALIZED && 1318 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1228 oh->_state != _HWMOD_STATE_IDLE && 1319 oh->_state != _HWMOD_STATE_IDLE &&
1229 oh->_state != _HWMOD_STATE_DISABLED) { 1320 oh->_state != _HWMOD_STATE_DISABLED) {
@@ -1232,17 +1323,6 @@ static int _enable(struct omap_hwmod *oh)
1232 return -EINVAL; 1323 return -EINVAL;
1233 } 1324 }
1234 1325
1235 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1236
1237 /*
1238 * If an IP contains only one HW reset line, then de-assert it in order
1239 * to allow to enable the clocks. Otherwise the PRCM will return
1240 * Intransition status, and the init will failed.
1241 */
1242 if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
1243 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
1244 _deassert_hardreset(oh, oh->rst_lines[0].name);
1245
1246 /* Mux pins for device runtime if populated */ 1326 /* Mux pins for device runtime if populated */
1247 if (oh->mux && (!oh->mux->enabled || 1327 if (oh->mux && (!oh->mux->enabled ||
1248 ((oh->_state == _HWMOD_STATE_IDLE) && 1328 ((oh->_state == _HWMOD_STATE_IDLE) &&
@@ -1252,20 +1332,31 @@ static int _enable(struct omap_hwmod *oh)
1252 _add_initiator_dep(oh, mpu_oh); 1332 _add_initiator_dep(oh, mpu_oh);
1253 _enable_clocks(oh); 1333 _enable_clocks(oh);
1254 1334
1255 r = _wait_target_ready(oh); 1335 /*
1256 if (!r) { 1336 * If an IP contains only one HW reset line, then de-assert it in order
1257 oh->_state = _HWMOD_STATE_ENABLED; 1337 * to allow the module state transition. Otherwise the PRCM will return
1338 * Intransition status, and the init will failed.
1339 */
1340 if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
1341 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
1342 _deassert_hardreset(oh, oh->rst_lines[0].name);
1258 1343
1259 /* Access the sysconfig only if the target is ready */ 1344 r = _wait_target_ready(oh);
1260 if (oh->class->sysc) { 1345 if (r) {
1261 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1262 _update_sysc_cache(oh);
1263 _enable_sysc(oh);
1264 }
1265 } else {
1266 _disable_clocks(oh);
1267 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", 1346 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
1268 oh->name, r); 1347 oh->name, r);
1348 _disable_clocks(oh);
1349
1350 return r;
1351 }
1352
1353 oh->_state = _HWMOD_STATE_ENABLED;
1354
1355 /* Access the sysconfig only if the target is ready */
1356 if (oh->class->sysc) {
1357 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1358 _update_sysc_cache(oh);
1359 _enable_sysc(oh);
1269 } 1360 }
1270 1361
1271 return r; 1362 return r;
@@ -1281,14 +1372,14 @@ static int _enable(struct omap_hwmod *oh)
1281 */ 1372 */
1282static int _idle(struct omap_hwmod *oh) 1373static int _idle(struct omap_hwmod *oh)
1283{ 1374{
1375 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1376
1284 if (oh->_state != _HWMOD_STATE_ENABLED) { 1377 if (oh->_state != _HWMOD_STATE_ENABLED) {
1285 WARN(1, "omap_hwmod: %s: idle state can only be entered from " 1378 WARN(1, "omap_hwmod: %s: idle state can only be entered from "
1286 "enabled state\n", oh->name); 1379 "enabled state\n", oh->name);
1287 return -EINVAL; 1380 return -EINVAL;
1288 } 1381 }
1289 1382
1290 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1291
1292 if (oh->class->sysc) 1383 if (oh->class->sysc)
1293 _idle_sysc(oh); 1384 _idle_sysc(oh);
1294 _del_initiator_dep(oh, mpu_oh); 1385 _del_initiator_dep(oh, mpu_oh);
@@ -1374,15 +1465,11 @@ static int _shutdown(struct omap_hwmod *oh)
1374 } 1465 }
1375 } 1466 }
1376 1467
1377 if (oh->class->sysc) 1468 if (oh->class->sysc) {
1469 if (oh->_state == _HWMOD_STATE_IDLE)
1470 _enable(oh);
1378 _shutdown_sysc(oh); 1471 _shutdown_sysc(oh);
1379 1472 }
1380 /*
1381 * If an IP contains only one HW reset line, then assert it
1382 * before disabling the clocks and shutting down the IP.
1383 */
1384 if (oh->rst_lines_cnt == 1)
1385 _assert_hardreset(oh, oh->rst_lines[0].name);
1386 1473
1387 /* clocks and deps are already disabled in idle */ 1474 /* clocks and deps are already disabled in idle */
1388 if (oh->_state == _HWMOD_STATE_ENABLED) { 1475 if (oh->_state == _HWMOD_STATE_ENABLED) {
@@ -1392,6 +1479,13 @@ static int _shutdown(struct omap_hwmod *oh)
1392 } 1479 }
1393 /* XXX Should this code also force-disable the optional clocks? */ 1480 /* XXX Should this code also force-disable the optional clocks? */
1394 1481
1482 /*
1483 * If an IP contains only one HW reset line, then assert it
1484 * after disabling the clocks and before shutting down the IP.
1485 */
1486 if (oh->rst_lines_cnt == 1)
1487 _assert_hardreset(oh, oh->rst_lines[0].name);
1488
1395 /* Mux pins to safe mode or use populated off mode values */ 1489 /* Mux pins to safe mode or use populated off mode values */
1396 if (oh->mux) 1490 if (oh->mux)
1397 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); 1491 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
@@ -1685,9 +1779,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
1685 return 0; 1779 return 0;
1686 1780
1687 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); 1781 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
1688 if (!oh->_mpu_rt_va)
1689 pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
1690 __func__, oh->name);
1691 1782
1692 return 0; 1783 return 0;
1693} 1784}
@@ -1939,10 +2030,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
1939{ 2030{
1940 int ret, i; 2031 int ret, i;
1941 2032
1942 ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; 2033 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
1943 2034
1944 for (i = 0; i < oh->slaves_cnt; i++) 2035 for (i = 0; i < oh->slaves_cnt; i++)
1945 ret += oh->slaves[i]->addr_cnt; 2036 ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
1946 2037
1947 return ret; 2038 return ret;
1948} 2039}
@@ -1959,12 +2050,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
1959 */ 2050 */
1960int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) 2051int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1961{ 2052{
1962 int i, j; 2053 int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
1963 int r = 0; 2054 int r = 0;
1964 2055
1965 /* For each IRQ, DMA, memory area, fill in array.*/ 2056 /* For each IRQ, DMA, memory area, fill in array.*/
1966 2057
1967 for (i = 0; i < oh->mpu_irqs_cnt; i++) { 2058 mpu_irqs_cnt = _count_mpu_irqs(oh);
2059 for (i = 0; i < mpu_irqs_cnt; i++) {
1968 (res + r)->name = (oh->mpu_irqs + i)->name; 2060 (res + r)->name = (oh->mpu_irqs + i)->name;
1969 (res + r)->start = (oh->mpu_irqs + i)->irq; 2061 (res + r)->start = (oh->mpu_irqs + i)->irq;
1970 (res + r)->end = (oh->mpu_irqs + i)->irq; 2062 (res + r)->end = (oh->mpu_irqs + i)->irq;
@@ -1972,7 +2064,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1972 r++; 2064 r++;
1973 } 2065 }
1974 2066
1975 for (i = 0; i < oh->sdma_reqs_cnt; i++) { 2067 sdma_reqs_cnt = _count_sdma_reqs(oh);
2068 for (i = 0; i < sdma_reqs_cnt; i++) {
1976 (res + r)->name = (oh->sdma_reqs + i)->name; 2069 (res + r)->name = (oh->sdma_reqs + i)->name;
1977 (res + r)->start = (oh->sdma_reqs + i)->dma_req; 2070 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
1978 (res + r)->end = (oh->sdma_reqs + i)->dma_req; 2071 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
@@ -1982,10 +2075,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1982 2075
1983 for (i = 0; i < oh->slaves_cnt; i++) { 2076 for (i = 0; i < oh->slaves_cnt; i++) {
1984 struct omap_hwmod_ocp_if *os; 2077 struct omap_hwmod_ocp_if *os;
2078 int addr_cnt;
1985 2079
1986 os = oh->slaves[i]; 2080 os = oh->slaves[i];
2081 addr_cnt = _count_ocp_if_addr_spaces(os);
1987 2082
1988 for (j = 0; j < os->addr_cnt; j++) { 2083 for (j = 0; j < addr_cnt; j++) {
1989 (res + r)->name = (os->addr + j)->name; 2084 (res + r)->name = (os->addr + j)->name;
1990 (res + r)->start = (os->addr + j)->pa_start; 2085 (res + r)->start = (os->addr + j)->pa_start;
1991 (res + r)->end = (os->addr + j)->pa_end; 2086 (res + r)->end = (os->addr + j)->pa_end;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index c4d0ae87d62a..f3901abf2c28 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips 2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
114static struct omap_hwmod omap2420_mcbsp2_hwmod; 114static struct omap_hwmod omap2420_mcbsp2_hwmod;
115 115
116/* l4 core -> mcspi1 interface */ 116/* l4 core -> mcspi1 interface */
117static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
118 {
119 .pa_start = 0x48098000,
120 .pa_end = 0x480980ff,
121 .flags = ADDR_TYPE_RT,
122 },
123};
124
125static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { 117static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
126 .master = &omap2420_l4_core_hwmod, 118 .master = &omap2420_l4_core_hwmod,
127 .slave = &omap2420_mcspi1_hwmod, 119 .slave = &omap2420_mcspi1_hwmod,
128 .clk = "mcspi1_ick", 120 .clk = "mcspi1_ick",
129 .addr = omap2420_mcspi1_addr_space, 121 .addr = omap2_mcspi1_addr_space,
130 .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
131 .user = OCP_USER_MPU | OCP_USER_SDMA, 122 .user = OCP_USER_MPU | OCP_USER_SDMA,
132}; 123};
133 124
134/* l4 core -> mcspi2 interface */ 125/* l4 core -> mcspi2 interface */
135static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
136 {
137 .pa_start = 0x4809a000,
138 .pa_end = 0x4809a0ff,
139 .flags = ADDR_TYPE_RT,
140 },
141};
142
143static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { 126static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
144 .master = &omap2420_l4_core_hwmod, 127 .master = &omap2420_l4_core_hwmod,
145 .slave = &omap2420_mcspi2_hwmod, 128 .slave = &omap2420_mcspi2_hwmod,
146 .clk = "mcspi2_ick", 129 .clk = "mcspi2_ick",
147 .addr = omap2420_mcspi2_addr_space, 130 .addr = omap2_mcspi2_addr_space,
148 .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
149 .user = OCP_USER_MPU | OCP_USER_SDMA, 131 .user = OCP_USER_MPU | OCP_USER_SDMA,
150}; 132};
151 133
@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
157}; 139};
158 140
159/* L4 CORE -> UART1 interface */ 141/* L4 CORE -> UART1 interface */
160static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
161 {
162 .pa_start = OMAP2_UART1_BASE,
163 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
164 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
165 },
166};
167
168static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 142static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
169 .master = &omap2420_l4_core_hwmod, 143 .master = &omap2420_l4_core_hwmod,
170 .slave = &omap2420_uart1_hwmod, 144 .slave = &omap2420_uart1_hwmod,
171 .clk = "uart1_ick", 145 .clk = "uart1_ick",
172 .addr = omap2420_uart1_addr_space, 146 .addr = omap2xxx_uart1_addr_space,
173 .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
174 .user = OCP_USER_MPU | OCP_USER_SDMA, 147 .user = OCP_USER_MPU | OCP_USER_SDMA,
175}; 148};
176 149
177/* L4 CORE -> UART2 interface */ 150/* L4 CORE -> UART2 interface */
178static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
179 {
180 .pa_start = OMAP2_UART2_BASE,
181 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
182 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
183 },
184};
185
186static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 151static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
187 .master = &omap2420_l4_core_hwmod, 152 .master = &omap2420_l4_core_hwmod,
188 .slave = &omap2420_uart2_hwmod, 153 .slave = &omap2420_uart2_hwmod,
189 .clk = "uart2_ick", 154 .clk = "uart2_ick",
190 .addr = omap2420_uart2_addr_space, 155 .addr = omap2xxx_uart2_addr_space,
191 .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
192 .user = OCP_USER_MPU | OCP_USER_SDMA, 156 .user = OCP_USER_MPU | OCP_USER_SDMA,
193}; 157};
194 158
195/* L4 PER -> UART3 interface */ 159/* L4 PER -> UART3 interface */
196static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
197 {
198 .pa_start = OMAP2_UART3_BASE,
199 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
200 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
201 },
202};
203
204static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 160static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
205 .master = &omap2420_l4_core_hwmod, 161 .master = &omap2420_l4_core_hwmod,
206 .slave = &omap2420_uart3_hwmod, 162 .slave = &omap2420_uart3_hwmod,
207 .clk = "uart3_ick", 163 .clk = "uart3_ick",
208 .addr = omap2420_uart3_addr_space, 164 .addr = omap2xxx_uart3_addr_space,
209 .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
210 .user = OCP_USER_MPU | OCP_USER_SDMA, 165 .user = OCP_USER_MPU | OCP_USER_SDMA,
211}; 166};
212 167
213/* I2C IP block address space length (in bytes) */
214#define OMAP2_I2C_AS_LEN 128
215
216/* L4 CORE -> I2C1 interface */ 168/* L4 CORE -> I2C1 interface */
217static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
218 {
219 .pa_start = 0x48070000,
220 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
221 .flags = ADDR_TYPE_RT,
222 },
223};
224
225static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { 169static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
226 .master = &omap2420_l4_core_hwmod, 170 .master = &omap2420_l4_core_hwmod,
227 .slave = &omap2420_i2c1_hwmod, 171 .slave = &omap2420_i2c1_hwmod,
228 .clk = "i2c1_ick", 172 .clk = "i2c1_ick",
229 .addr = omap2420_i2c1_addr_space, 173 .addr = omap2_i2c1_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA, 174 .user = OCP_USER_MPU | OCP_USER_SDMA,
232}; 175};
233 176
234/* L4 CORE -> I2C2 interface */ 177/* L4 CORE -> I2C2 interface */
235static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
236 {
237 .pa_start = 0x48072000,
238 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
239 .flags = ADDR_TYPE_RT,
240 },
241};
242
243static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { 178static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
244 .master = &omap2420_l4_core_hwmod, 179 .master = &omap2420_l4_core_hwmod,
245 .slave = &omap2420_i2c2_hwmod, 180 .slave = &omap2420_i2c2_hwmod,
246 .clk = "i2c2_ick", 181 .clk = "i2c2_ick",
247 .addr = omap2420_i2c2_addr_space, 182 .addr = omap2_i2c2_addr_space,
248 .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
249 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 .user = OCP_USER_MPU | OCP_USER_SDMA,
250}; 184};
251 185
@@ -340,29 +274,8 @@ static struct omap_hwmod omap2420_iva_hwmod = {
340 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
341}; 275};
342 276
343/* Timer Common */
344static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
345 .rev_offs = 0x0000,
346 .sysc_offs = 0x0010,
347 .syss_offs = 0x0014,
348 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
349 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
350 SYSC_HAS_AUTOIDLE),
351 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
352 .sysc_fields = &omap_hwmod_sysc_type1,
353};
354
355static struct omap_hwmod_class omap2420_timer_hwmod_class = {
356 .name = "timer",
357 .sysc = &omap2420_timer_sysc,
358 .rev = OMAP_TIMER_IP_VERSION_1,
359};
360
361/* timer1 */ 277/* timer1 */
362static struct omap_hwmod omap2420_timer1_hwmod; 278static struct omap_hwmod omap2420_timer1_hwmod;
363static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
364 { .irq = 37, },
365};
366 279
367static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { 280static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
368 { 281 {
@@ -370,6 +283,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
370 .pa_end = 0x48028000 + SZ_1K - 1, 283 .pa_end = 0x48028000 + SZ_1K - 1,
371 .flags = ADDR_TYPE_RT 284 .flags = ADDR_TYPE_RT
372 }, 285 },
286 { }
373}; 287};
374 288
375/* l4_wkup -> timer1 */ 289/* l4_wkup -> timer1 */
@@ -378,7 +292,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
378 .slave = &omap2420_timer1_hwmod, 292 .slave = &omap2420_timer1_hwmod,
379 .clk = "gpt1_ick", 293 .clk = "gpt1_ick",
380 .addr = omap2420_timer1_addrs, 294 .addr = omap2420_timer1_addrs,
381 .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
382 .user = OCP_USER_MPU | OCP_USER_SDMA, 295 .user = OCP_USER_MPU | OCP_USER_SDMA,
383}; 296};
384 297
@@ -390,8 +303,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
390/* timer1 hwmod */ 303/* timer1 hwmod */
391static struct omap_hwmod omap2420_timer1_hwmod = { 304static struct omap_hwmod omap2420_timer1_hwmod = {
392 .name = "timer1", 305 .name = "timer1",
393 .mpu_irqs = omap2420_timer1_mpu_irqs, 306 .mpu_irqs = omap2_timer1_mpu_irqs,
394 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
395 .main_clk = "gpt1_fck", 307 .main_clk = "gpt1_fck",
396 .prcm = { 308 .prcm = {
397 .omap2 = { 309 .omap2 = {
@@ -404,31 +316,19 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
404 }, 316 },
405 .slaves = omap2420_timer1_slaves, 317 .slaves = omap2420_timer1_slaves,
406 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves), 318 .slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
407 .class = &omap2420_timer_hwmod_class, 319 .class = &omap2xxx_timer_hwmod_class,
408 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
409}; 321};
410 322
411/* timer2 */ 323/* timer2 */
412static struct omap_hwmod omap2420_timer2_hwmod; 324static struct omap_hwmod omap2420_timer2_hwmod;
413static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
414 { .irq = 38, },
415};
416
417static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
418 {
419 .pa_start = 0x4802a000,
420 .pa_end = 0x4802a000 + SZ_1K - 1,
421 .flags = ADDR_TYPE_RT
422 },
423};
424 325
425/* l4_core -> timer2 */ 326/* l4_core -> timer2 */
426static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { 327static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
427 .master = &omap2420_l4_core_hwmod, 328 .master = &omap2420_l4_core_hwmod,
428 .slave = &omap2420_timer2_hwmod, 329 .slave = &omap2420_timer2_hwmod,
429 .clk = "gpt2_ick", 330 .clk = "gpt2_ick",
430 .addr = omap2420_timer2_addrs, 331 .addr = omap2xxx_timer2_addrs,
431 .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
432 .user = OCP_USER_MPU | OCP_USER_SDMA, 332 .user = OCP_USER_MPU | OCP_USER_SDMA,
433}; 333};
434 334
@@ -440,8 +340,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
440/* timer2 hwmod */ 340/* timer2 hwmod */
441static struct omap_hwmod omap2420_timer2_hwmod = { 341static struct omap_hwmod omap2420_timer2_hwmod = {
442 .name = "timer2", 342 .name = "timer2",
443 .mpu_irqs = omap2420_timer2_mpu_irqs, 343 .mpu_irqs = omap2_timer2_mpu_irqs,
444 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
445 .main_clk = "gpt2_fck", 344 .main_clk = "gpt2_fck",
446 .prcm = { 345 .prcm = {
447 .omap2 = { 346 .omap2 = {
@@ -454,31 +353,19 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
454 }, 353 },
455 .slaves = omap2420_timer2_slaves, 354 .slaves = omap2420_timer2_slaves,
456 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves), 355 .slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
457 .class = &omap2420_timer_hwmod_class, 356 .class = &omap2xxx_timer_hwmod_class,
458 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 357 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
459}; 358};
460 359
461/* timer3 */ 360/* timer3 */
462static struct omap_hwmod omap2420_timer3_hwmod; 361static struct omap_hwmod omap2420_timer3_hwmod;
463static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
464 { .irq = 39, },
465};
466
467static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
468 {
469 .pa_start = 0x48078000,
470 .pa_end = 0x48078000 + SZ_1K - 1,
471 .flags = ADDR_TYPE_RT
472 },
473};
474 362
475/* l4_core -> timer3 */ 363/* l4_core -> timer3 */
476static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { 364static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
477 .master = &omap2420_l4_core_hwmod, 365 .master = &omap2420_l4_core_hwmod,
478 .slave = &omap2420_timer3_hwmod, 366 .slave = &omap2420_timer3_hwmod,
479 .clk = "gpt3_ick", 367 .clk = "gpt3_ick",
480 .addr = omap2420_timer3_addrs, 368 .addr = omap2xxx_timer3_addrs,
481 .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
482 .user = OCP_USER_MPU | OCP_USER_SDMA, 369 .user = OCP_USER_MPU | OCP_USER_SDMA,
483}; 370};
484 371
@@ -490,8 +377,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
490/* timer3 hwmod */ 377/* timer3 hwmod */
491static struct omap_hwmod omap2420_timer3_hwmod = { 378static struct omap_hwmod omap2420_timer3_hwmod = {
492 .name = "timer3", 379 .name = "timer3",
493 .mpu_irqs = omap2420_timer3_mpu_irqs, 380 .mpu_irqs = omap2_timer3_mpu_irqs,
494 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
495 .main_clk = "gpt3_fck", 381 .main_clk = "gpt3_fck",
496 .prcm = { 382 .prcm = {
497 .omap2 = { 383 .omap2 = {
@@ -504,31 +390,19 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
504 }, 390 },
505 .slaves = omap2420_timer3_slaves, 391 .slaves = omap2420_timer3_slaves,
506 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves), 392 .slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
507 .class = &omap2420_timer_hwmod_class, 393 .class = &omap2xxx_timer_hwmod_class,
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 394 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
509}; 395};
510 396
511/* timer4 */ 397/* timer4 */
512static struct omap_hwmod omap2420_timer4_hwmod; 398static struct omap_hwmod omap2420_timer4_hwmod;
513static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
514 { .irq = 40, },
515};
516
517static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
518 {
519 .pa_start = 0x4807a000,
520 .pa_end = 0x4807a000 + SZ_1K - 1,
521 .flags = ADDR_TYPE_RT
522 },
523};
524 399
525/* l4_core -> timer4 */ 400/* l4_core -> timer4 */
526static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { 401static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
527 .master = &omap2420_l4_core_hwmod, 402 .master = &omap2420_l4_core_hwmod,
528 .slave = &omap2420_timer4_hwmod, 403 .slave = &omap2420_timer4_hwmod,
529 .clk = "gpt4_ick", 404 .clk = "gpt4_ick",
530 .addr = omap2420_timer4_addrs, 405 .addr = omap2xxx_timer4_addrs,
531 .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
532 .user = OCP_USER_MPU | OCP_USER_SDMA, 406 .user = OCP_USER_MPU | OCP_USER_SDMA,
533}; 407};
534 408
@@ -540,8 +414,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
540/* timer4 hwmod */ 414/* timer4 hwmod */
541static struct omap_hwmod omap2420_timer4_hwmod = { 415static struct omap_hwmod omap2420_timer4_hwmod = {
542 .name = "timer4", 416 .name = "timer4",
543 .mpu_irqs = omap2420_timer4_mpu_irqs, 417 .mpu_irqs = omap2_timer4_mpu_irqs,
544 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
545 .main_clk = "gpt4_fck", 418 .main_clk = "gpt4_fck",
546 .prcm = { 419 .prcm = {
547 .omap2 = { 420 .omap2 = {
@@ -554,31 +427,19 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
554 }, 427 },
555 .slaves = omap2420_timer4_slaves, 428 .slaves = omap2420_timer4_slaves,
556 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves), 429 .slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
557 .class = &omap2420_timer_hwmod_class, 430 .class = &omap2xxx_timer_hwmod_class,
558 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 431 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
559}; 432};
560 433
561/* timer5 */ 434/* timer5 */
562static struct omap_hwmod omap2420_timer5_hwmod; 435static struct omap_hwmod omap2420_timer5_hwmod;
563static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
564 { .irq = 41, },
565};
566
567static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
568 {
569 .pa_start = 0x4807c000,
570 .pa_end = 0x4807c000 + SZ_1K - 1,
571 .flags = ADDR_TYPE_RT
572 },
573};
574 436
575/* l4_core -> timer5 */ 437/* l4_core -> timer5 */
576static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { 438static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
577 .master = &omap2420_l4_core_hwmod, 439 .master = &omap2420_l4_core_hwmod,
578 .slave = &omap2420_timer5_hwmod, 440 .slave = &omap2420_timer5_hwmod,
579 .clk = "gpt5_ick", 441 .clk = "gpt5_ick",
580 .addr = omap2420_timer5_addrs, 442 .addr = omap2xxx_timer5_addrs,
581 .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
582 .user = OCP_USER_MPU | OCP_USER_SDMA, 443 .user = OCP_USER_MPU | OCP_USER_SDMA,
583}; 444};
584 445
@@ -590,8 +451,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
590/* timer5 hwmod */ 451/* timer5 hwmod */
591static struct omap_hwmod omap2420_timer5_hwmod = { 452static struct omap_hwmod omap2420_timer5_hwmod = {
592 .name = "timer5", 453 .name = "timer5",
593 .mpu_irqs = omap2420_timer5_mpu_irqs, 454 .mpu_irqs = omap2_timer5_mpu_irqs,
594 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
595 .main_clk = "gpt5_fck", 455 .main_clk = "gpt5_fck",
596 .prcm = { 456 .prcm = {
597 .omap2 = { 457 .omap2 = {
@@ -604,32 +464,20 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
604 }, 464 },
605 .slaves = omap2420_timer5_slaves, 465 .slaves = omap2420_timer5_slaves,
606 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves), 466 .slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
607 .class = &omap2420_timer_hwmod_class, 467 .class = &omap2xxx_timer_hwmod_class,
608 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 468 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
609}; 469};
610 470
611 471
612/* timer6 */ 472/* timer6 */
613static struct omap_hwmod omap2420_timer6_hwmod; 473static struct omap_hwmod omap2420_timer6_hwmod;
614static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
615 { .irq = 42, },
616};
617
618static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
619 {
620 .pa_start = 0x4807e000,
621 .pa_end = 0x4807e000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625 474
626/* l4_core -> timer6 */ 475/* l4_core -> timer6 */
627static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { 476static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
628 .master = &omap2420_l4_core_hwmod, 477 .master = &omap2420_l4_core_hwmod,
629 .slave = &omap2420_timer6_hwmod, 478 .slave = &omap2420_timer6_hwmod,
630 .clk = "gpt6_ick", 479 .clk = "gpt6_ick",
631 .addr = omap2420_timer6_addrs, 480 .addr = omap2xxx_timer6_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 481 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 482};
635 483
@@ -641,8 +489,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
641/* timer6 hwmod */ 489/* timer6 hwmod */
642static struct omap_hwmod omap2420_timer6_hwmod = { 490static struct omap_hwmod omap2420_timer6_hwmod = {
643 .name = "timer6", 491 .name = "timer6",
644 .mpu_irqs = omap2420_timer6_mpu_irqs, 492 .mpu_irqs = omap2_timer6_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
646 .main_clk = "gpt6_fck", 493 .main_clk = "gpt6_fck",
647 .prcm = { 494 .prcm = {
648 .omap2 = { 495 .omap2 = {
@@ -655,31 +502,19 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
655 }, 502 },
656 .slaves = omap2420_timer6_slaves, 503 .slaves = omap2420_timer6_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves), 504 .slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
658 .class = &omap2420_timer_hwmod_class, 505 .class = &omap2xxx_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 506 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
660}; 507};
661 508
662/* timer7 */ 509/* timer7 */
663static struct omap_hwmod omap2420_timer7_hwmod; 510static struct omap_hwmod omap2420_timer7_hwmod;
664static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
665 { .irq = 43, },
666};
667
668static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
669 {
670 .pa_start = 0x48080000,
671 .pa_end = 0x48080000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675 511
676/* l4_core -> timer7 */ 512/* l4_core -> timer7 */
677static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { 513static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
678 .master = &omap2420_l4_core_hwmod, 514 .master = &omap2420_l4_core_hwmod,
679 .slave = &omap2420_timer7_hwmod, 515 .slave = &omap2420_timer7_hwmod,
680 .clk = "gpt7_ick", 516 .clk = "gpt7_ick",
681 .addr = omap2420_timer7_addrs, 517 .addr = omap2xxx_timer7_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 518 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 519};
685 520
@@ -691,8 +526,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
691/* timer7 hwmod */ 526/* timer7 hwmod */
692static struct omap_hwmod omap2420_timer7_hwmod = { 527static struct omap_hwmod omap2420_timer7_hwmod = {
693 .name = "timer7", 528 .name = "timer7",
694 .mpu_irqs = omap2420_timer7_mpu_irqs, 529 .mpu_irqs = omap2_timer7_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
696 .main_clk = "gpt7_fck", 530 .main_clk = "gpt7_fck",
697 .prcm = { 531 .prcm = {
698 .omap2 = { 532 .omap2 = {
@@ -705,31 +539,19 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
705 }, 539 },
706 .slaves = omap2420_timer7_slaves, 540 .slaves = omap2420_timer7_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves), 541 .slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
708 .class = &omap2420_timer_hwmod_class, 542 .class = &omap2xxx_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 543 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
710}; 544};
711 545
712/* timer8 */ 546/* timer8 */
713static struct omap_hwmod omap2420_timer8_hwmod; 547static struct omap_hwmod omap2420_timer8_hwmod;
714static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
715 { .irq = 44, },
716};
717
718static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
719 {
720 .pa_start = 0x48082000,
721 .pa_end = 0x48082000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725 548
726/* l4_core -> timer8 */ 549/* l4_core -> timer8 */
727static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { 550static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
728 .master = &omap2420_l4_core_hwmod, 551 .master = &omap2420_l4_core_hwmod,
729 .slave = &omap2420_timer8_hwmod, 552 .slave = &omap2420_timer8_hwmod,
730 .clk = "gpt8_ick", 553 .clk = "gpt8_ick",
731 .addr = omap2420_timer8_addrs, 554 .addr = omap2xxx_timer8_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 555 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 556};
735 557
@@ -741,8 +563,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
741/* timer8 hwmod */ 563/* timer8 hwmod */
742static struct omap_hwmod omap2420_timer8_hwmod = { 564static struct omap_hwmod omap2420_timer8_hwmod = {
743 .name = "timer8", 565 .name = "timer8",
744 .mpu_irqs = omap2420_timer8_mpu_irqs, 566 .mpu_irqs = omap2_timer8_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
746 .main_clk = "gpt8_fck", 567 .main_clk = "gpt8_fck",
747 .prcm = { 568 .prcm = {
748 .omap2 = { 569 .omap2 = {
@@ -755,31 +576,19 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
755 }, 576 },
756 .slaves = omap2420_timer8_slaves, 577 .slaves = omap2420_timer8_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves), 578 .slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
758 .class = &omap2420_timer_hwmod_class, 579 .class = &omap2xxx_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 580 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
760}; 581};
761 582
762/* timer9 */ 583/* timer9 */
763static struct omap_hwmod omap2420_timer9_hwmod; 584static struct omap_hwmod omap2420_timer9_hwmod;
764static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
765 { .irq = 45, },
766};
767
768static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
769 {
770 .pa_start = 0x48084000,
771 .pa_end = 0x48084000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775 585
776/* l4_core -> timer9 */ 586/* l4_core -> timer9 */
777static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { 587static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
778 .master = &omap2420_l4_core_hwmod, 588 .master = &omap2420_l4_core_hwmod,
779 .slave = &omap2420_timer9_hwmod, 589 .slave = &omap2420_timer9_hwmod,
780 .clk = "gpt9_ick", 590 .clk = "gpt9_ick",
781 .addr = omap2420_timer9_addrs, 591 .addr = omap2xxx_timer9_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 592 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 593};
785 594
@@ -791,8 +600,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
791/* timer9 hwmod */ 600/* timer9 hwmod */
792static struct omap_hwmod omap2420_timer9_hwmod = { 601static struct omap_hwmod omap2420_timer9_hwmod = {
793 .name = "timer9", 602 .name = "timer9",
794 .mpu_irqs = omap2420_timer9_mpu_irqs, 603 .mpu_irqs = omap2_timer9_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
796 .main_clk = "gpt9_fck", 604 .main_clk = "gpt9_fck",
797 .prcm = { 605 .prcm = {
798 .omap2 = { 606 .omap2 = {
@@ -805,31 +613,19 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
805 }, 613 },
806 .slaves = omap2420_timer9_slaves, 614 .slaves = omap2420_timer9_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves), 615 .slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
808 .class = &omap2420_timer_hwmod_class, 616 .class = &omap2xxx_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
810}; 618};
811 619
812/* timer10 */ 620/* timer10 */
813static struct omap_hwmod omap2420_timer10_hwmod; 621static struct omap_hwmod omap2420_timer10_hwmod;
814static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
815 { .irq = 46, },
816};
817
818static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
819 {
820 .pa_start = 0x48086000,
821 .pa_end = 0x48086000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825 622
826/* l4_core -> timer10 */ 623/* l4_core -> timer10 */
827static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { 624static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
828 .master = &omap2420_l4_core_hwmod, 625 .master = &omap2420_l4_core_hwmod,
829 .slave = &omap2420_timer10_hwmod, 626 .slave = &omap2420_timer10_hwmod,
830 .clk = "gpt10_ick", 627 .clk = "gpt10_ick",
831 .addr = omap2420_timer10_addrs, 628 .addr = omap2_timer10_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 629 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 630};
835 631
@@ -841,8 +637,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
841/* timer10 hwmod */ 637/* timer10 hwmod */
842static struct omap_hwmod omap2420_timer10_hwmod = { 638static struct omap_hwmod omap2420_timer10_hwmod = {
843 .name = "timer10", 639 .name = "timer10",
844 .mpu_irqs = omap2420_timer10_mpu_irqs, 640 .mpu_irqs = omap2_timer10_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
846 .main_clk = "gpt10_fck", 641 .main_clk = "gpt10_fck",
847 .prcm = { 642 .prcm = {
848 .omap2 = { 643 .omap2 = {
@@ -855,31 +650,19 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
855 }, 650 },
856 .slaves = omap2420_timer10_slaves, 651 .slaves = omap2420_timer10_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves), 652 .slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
858 .class = &omap2420_timer_hwmod_class, 653 .class = &omap2xxx_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 654 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
860}; 655};
861 656
862/* timer11 */ 657/* timer11 */
863static struct omap_hwmod omap2420_timer11_hwmod; 658static struct omap_hwmod omap2420_timer11_hwmod;
864static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
865 { .irq = 47, },
866};
867
868static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
869 {
870 .pa_start = 0x48088000,
871 .pa_end = 0x48088000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875 659
876/* l4_core -> timer11 */ 660/* l4_core -> timer11 */
877static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { 661static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
878 .master = &omap2420_l4_core_hwmod, 662 .master = &omap2420_l4_core_hwmod,
879 .slave = &omap2420_timer11_hwmod, 663 .slave = &omap2420_timer11_hwmod,
880 .clk = "gpt11_ick", 664 .clk = "gpt11_ick",
881 .addr = omap2420_timer11_addrs, 665 .addr = omap2_timer11_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 666 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 667};
885 668
@@ -891,8 +674,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
891/* timer11 hwmod */ 674/* timer11 hwmod */
892static struct omap_hwmod omap2420_timer11_hwmod = { 675static struct omap_hwmod omap2420_timer11_hwmod = {
893 .name = "timer11", 676 .name = "timer11",
894 .mpu_irqs = omap2420_timer11_mpu_irqs, 677 .mpu_irqs = omap2_timer11_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
896 .main_clk = "gpt11_fck", 678 .main_clk = "gpt11_fck",
897 .prcm = { 679 .prcm = {
898 .omap2 = { 680 .omap2 = {
@@ -905,31 +687,19 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
905 }, 687 },
906 .slaves = omap2420_timer11_slaves, 688 .slaves = omap2420_timer11_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves), 689 .slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
908 .class = &omap2420_timer_hwmod_class, 690 .class = &omap2xxx_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 691 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
910}; 692};
911 693
912/* timer12 */ 694/* timer12 */
913static struct omap_hwmod omap2420_timer12_hwmod; 695static struct omap_hwmod omap2420_timer12_hwmod;
914static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
915 { .irq = 48, },
916};
917
918static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
919 {
920 .pa_start = 0x4808a000,
921 .pa_end = 0x4808a000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925 696
926/* l4_core -> timer12 */ 697/* l4_core -> timer12 */
927static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { 698static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
928 .master = &omap2420_l4_core_hwmod, 699 .master = &omap2420_l4_core_hwmod,
929 .slave = &omap2420_timer12_hwmod, 700 .slave = &omap2420_timer12_hwmod,
930 .clk = "gpt12_ick", 701 .clk = "gpt12_ick",
931 .addr = omap2420_timer12_addrs, 702 .addr = omap2xxx_timer12_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 703 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 704};
935 705
@@ -941,8 +711,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
941/* timer12 hwmod */ 711/* timer12 hwmod */
942static struct omap_hwmod omap2420_timer12_hwmod = { 712static struct omap_hwmod omap2420_timer12_hwmod = {
943 .name = "timer12", 713 .name = "timer12",
944 .mpu_irqs = omap2420_timer12_mpu_irqs, 714 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
946 .main_clk = "gpt12_fck", 715 .main_clk = "gpt12_fck",
947 .prcm = { 716 .prcm = {
948 .omap2 = { 717 .omap2 = {
@@ -955,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
955 }, 724 },
956 .slaves = omap2420_timer12_slaves, 725 .slaves = omap2420_timer12_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves), 726 .slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
958 .class = &omap2420_timer_hwmod_class, 727 .class = &omap2xxx_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420) 728 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
960}; 729};
961 730
@@ -966,6 +735,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
966 .pa_end = 0x4802207f, 735 .pa_end = 0x4802207f,
967 .flags = ADDR_TYPE_RT 736 .flags = ADDR_TYPE_RT
968 }, 737 },
738 { }
969}; 739};
970 740
971static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { 741static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
@@ -973,31 +743,9 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
973 .slave = &omap2420_wd_timer2_hwmod, 743 .slave = &omap2420_wd_timer2_hwmod,
974 .clk = "mpu_wdt_ick", 744 .clk = "mpu_wdt_ick",
975 .addr = omap2420_wd_timer2_addrs, 745 .addr = omap2420_wd_timer2_addrs,
976 .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
977 .user = OCP_USER_MPU | OCP_USER_SDMA, 746 .user = OCP_USER_MPU | OCP_USER_SDMA,
978}; 747};
979 748
980/*
981 * 'wd_timer' class
982 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
983 * overflow condition
984 */
985
986static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
987 .rev_offs = 0x0000,
988 .sysc_offs = 0x0010,
989 .syss_offs = 0x0014,
990 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
991 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
992 .sysc_fields = &omap_hwmod_sysc_type1,
993};
994
995static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
996 .name = "wd_timer",
997 .sysc = &omap2420_wd_timer_sysc,
998 .pre_shutdown = &omap2_wd_timer_disable
999};
1000
1001/* wd_timer2 */ 749/* wd_timer2 */
1002static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = { 750static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1003 &omap2420_l4_wkup__wd_timer2, 751 &omap2420_l4_wkup__wd_timer2,
@@ -1005,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
1005 753
1006static struct omap_hwmod omap2420_wd_timer2_hwmod = { 754static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1007 .name = "wd_timer2", 755 .name = "wd_timer2",
1008 .class = &omap2420_wd_timer_hwmod_class, 756 .class = &omap2xxx_wd_timer_hwmod_class,
1009 .main_clk = "mpu_wdt_fck", 757 .main_clk = "mpu_wdt_fck",
1010 .prcm = { 758 .prcm = {
1011 .omap2 = { 759 .omap2 = {
@@ -1021,45 +769,16 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
1021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 769 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1022}; 770};
1023 771
1024/* UART */
1025
1026static struct omap_hwmod_class_sysconfig uart_sysc = {
1027 .rev_offs = 0x50,
1028 .sysc_offs = 0x54,
1029 .syss_offs = 0x58,
1030 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1031 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1032 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1033 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1034 .sysc_fields = &omap_hwmod_sysc_type1,
1035};
1036
1037static struct omap_hwmod_class uart_class = {
1038 .name = "uart",
1039 .sysc = &uart_sysc,
1040};
1041
1042/* UART1 */ 772/* UART1 */
1043 773
1044static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1045 { .irq = INT_24XX_UART1_IRQ, },
1046};
1047
1048static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1049 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1050 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1051};
1052
1053static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = { 774static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
1054 &omap2_l4_core__uart1, 775 &omap2_l4_core__uart1,
1055}; 776};
1056 777
1057static struct omap_hwmod omap2420_uart1_hwmod = { 778static struct omap_hwmod omap2420_uart1_hwmod = {
1058 .name = "uart1", 779 .name = "uart1",
1059 .mpu_irqs = uart1_mpu_irqs, 780 .mpu_irqs = omap2_uart1_mpu_irqs,
1060 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 781 .sdma_reqs = omap2_uart1_sdma_reqs,
1061 .sdma_reqs = uart1_sdma_reqs,
1062 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1063 .main_clk = "uart1_fck", 782 .main_clk = "uart1_fck",
1064 .prcm = { 783 .prcm = {
1065 .omap2 = { 784 .omap2 = {
@@ -1072,31 +791,20 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
1072 }, 791 },
1073 .slaves = omap2420_uart1_slaves, 792 .slaves = omap2420_uart1_slaves,
1074 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves), 793 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
1075 .class = &uart_class, 794 .class = &omap2_uart_class,
1076 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 795 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1077}; 796};
1078 797
1079/* UART2 */ 798/* UART2 */
1080 799
1081static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1082 { .irq = INT_24XX_UART2_IRQ, },
1083};
1084
1085static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1086 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1087 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1088};
1089
1090static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = { 800static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
1091 &omap2_l4_core__uart2, 801 &omap2_l4_core__uart2,
1092}; 802};
1093 803
1094static struct omap_hwmod omap2420_uart2_hwmod = { 804static struct omap_hwmod omap2420_uart2_hwmod = {
1095 .name = "uart2", 805 .name = "uart2",
1096 .mpu_irqs = uart2_mpu_irqs, 806 .mpu_irqs = omap2_uart2_mpu_irqs,
1097 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 807 .sdma_reqs = omap2_uart2_sdma_reqs,
1098 .sdma_reqs = uart2_sdma_reqs,
1099 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1100 .main_clk = "uart2_fck", 808 .main_clk = "uart2_fck",
1101 .prcm = { 809 .prcm = {
1102 .omap2 = { 810 .omap2 = {
@@ -1109,31 +817,20 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
1109 }, 817 },
1110 .slaves = omap2420_uart2_slaves, 818 .slaves = omap2420_uart2_slaves,
1111 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves), 819 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
1112 .class = &uart_class, 820 .class = &omap2_uart_class,
1113 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 821 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1114}; 822};
1115 823
1116/* UART3 */ 824/* UART3 */
1117 825
1118static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1119 { .irq = INT_24XX_UART3_IRQ, },
1120};
1121
1122static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1123 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1124 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1125};
1126
1127static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = { 826static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
1128 &omap2_l4_core__uart3, 827 &omap2_l4_core__uart3,
1129}; 828};
1130 829
1131static struct omap_hwmod omap2420_uart3_hwmod = { 830static struct omap_hwmod omap2420_uart3_hwmod = {
1132 .name = "uart3", 831 .name = "uart3",
1133 .mpu_irqs = uart3_mpu_irqs, 832 .mpu_irqs = omap2_uart3_mpu_irqs,
1134 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 833 .sdma_reqs = omap2_uart3_sdma_reqs,
1135 .sdma_reqs = uart3_sdma_reqs,
1136 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1137 .main_clk = "uart3_fck", 834 .main_clk = "uart3_fck",
1138 .prcm = { 835 .prcm = {
1139 .omap2 = { 836 .omap2 = {
@@ -1146,53 +843,22 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
1146 }, 843 },
1147 .slaves = omap2420_uart3_slaves, 844 .slaves = omap2420_uart3_slaves,
1148 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves), 845 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
1149 .class = &uart_class, 846 .class = &omap2_uart_class,
1150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1151}; 848};
1152 849
1153/*
1154 * 'dss' class
1155 * display sub-system
1156 */
1157
1158static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
1159 .rev_offs = 0x0000,
1160 .sysc_offs = 0x0010,
1161 .syss_offs = 0x0014,
1162 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1163 .sysc_fields = &omap_hwmod_sysc_type1,
1164};
1165
1166static struct omap_hwmod_class omap2420_dss_hwmod_class = {
1167 .name = "dss",
1168 .sysc = &omap2420_dss_sysc,
1169};
1170
1171static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
1172 { .name = "dispc", .dma_req = 5 },
1173};
1174
1175/* dss */ 850/* dss */
1176/* dss master ports */ 851/* dss master ports */
1177static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = { 852static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
1178 &omap2420_dss__l3, 853 &omap2420_dss__l3,
1179}; 854};
1180 855
1181static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
1182 {
1183 .pa_start = 0x48050000,
1184 .pa_end = 0x480503FF,
1185 .flags = ADDR_TYPE_RT
1186 },
1187};
1188
1189/* l4_core -> dss */ 856/* l4_core -> dss */
1190static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { 857static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
1191 .master = &omap2420_l4_core_hwmod, 858 .master = &omap2420_l4_core_hwmod,
1192 .slave = &omap2420_dss_core_hwmod, 859 .slave = &omap2420_dss_core_hwmod,
1193 .clk = "dss_ick", 860 .clk = "dss_ick",
1194 .addr = omap2420_dss_addrs, 861 .addr = omap2_dss_addrs,
1195 .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
1196 .fw = { 862 .fw = {
1197 .omap2 = { 863 .omap2 = {
1198 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 864 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1214,10 +880,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1214 880
1215static struct omap_hwmod omap2420_dss_core_hwmod = { 881static struct omap_hwmod omap2420_dss_core_hwmod = {
1216 .name = "dss_core", 882 .name = "dss_core",
1217 .class = &omap2420_dss_hwmod_class, 883 .class = &omap2_dss_hwmod_class,
1218 .main_clk = "dss1_fck", /* instead of dss_fck */ 884 .main_clk = "dss1_fck", /* instead of dss_fck */
1219 .sdma_reqs = omap2420_dss_sdma_chs, 885 .sdma_reqs = omap2xxx_dss_sdma_chs,
1220 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
1221 .prcm = { 886 .prcm = {
1222 .omap2 = { 887 .omap2 = {
1223 .prcm_reg_id = 1, 888 .prcm_reg_id = 1,
@@ -1237,46 +902,12 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
1237 .flags = HWMOD_NO_IDLEST, 902 .flags = HWMOD_NO_IDLEST,
1238}; 903};
1239 904
1240/*
1241 * 'dispc' class
1242 * display controller
1243 */
1244
1245static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
1246 .rev_offs = 0x0000,
1247 .sysc_offs = 0x0010,
1248 .syss_offs = 0x0014,
1249 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1250 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1252 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1253 .sysc_fields = &omap_hwmod_sysc_type1,
1254};
1255
1256static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
1257 .name = "dispc",
1258 .sysc = &omap2420_dispc_sysc,
1259};
1260
1261static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
1262 { .irq = 25 },
1263};
1264
1265static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
1266 {
1267 .pa_start = 0x48050400,
1268 .pa_end = 0x480507FF,
1269 .flags = ADDR_TYPE_RT
1270 },
1271};
1272
1273/* l4_core -> dss_dispc */ 905/* l4_core -> dss_dispc */
1274static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { 906static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1275 .master = &omap2420_l4_core_hwmod, 907 .master = &omap2420_l4_core_hwmod,
1276 .slave = &omap2420_dss_dispc_hwmod, 908 .slave = &omap2420_dss_dispc_hwmod,
1277 .clk = "dss_ick", 909 .clk = "dss_ick",
1278 .addr = omap2420_dss_dispc_addrs, 910 .addr = omap2_dss_dispc_addrs,
1279 .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
1280 .fw = { 911 .fw = {
1281 .omap2 = { 912 .omap2 = {
1282 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, 913 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1293,9 +924,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1293 924
1294static struct omap_hwmod omap2420_dss_dispc_hwmod = { 925static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1295 .name = "dss_dispc", 926 .name = "dss_dispc",
1296 .class = &omap2420_dispc_hwmod_class, 927 .class = &omap2_dispc_hwmod_class,
1297 .mpu_irqs = omap2420_dispc_irqs, 928 .mpu_irqs = omap2_dispc_irqs,
1298 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
1299 .main_clk = "dss1_fck", 929 .main_clk = "dss1_fck",
1300 .prcm = { 930 .prcm = {
1301 .omap2 = { 931 .omap2 = {
@@ -1312,41 +942,12 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1312 .flags = HWMOD_NO_IDLEST, 942 .flags = HWMOD_NO_IDLEST,
1313}; 943};
1314 944
1315/*
1316 * 'rfbi' class
1317 * remote frame buffer interface
1318 */
1319
1320static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1321 .rev_offs = 0x0000,
1322 .sysc_offs = 0x0010,
1323 .syss_offs = 0x0014,
1324 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1325 SYSC_HAS_AUTOIDLE),
1326 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1327 .sysc_fields = &omap_hwmod_sysc_type1,
1328};
1329
1330static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1331 .name = "rfbi",
1332 .sysc = &omap2420_rfbi_sysc,
1333};
1334
1335static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
1336 {
1337 .pa_start = 0x48050800,
1338 .pa_end = 0x48050BFF,
1339 .flags = ADDR_TYPE_RT
1340 },
1341};
1342
1343/* l4_core -> dss_rfbi */ 945/* l4_core -> dss_rfbi */
1344static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { 946static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1345 .master = &omap2420_l4_core_hwmod, 947 .master = &omap2420_l4_core_hwmod,
1346 .slave = &omap2420_dss_rfbi_hwmod, 948 .slave = &omap2420_dss_rfbi_hwmod,
1347 .clk = "dss_ick", 949 .clk = "dss_ick",
1348 .addr = omap2420_dss_rfbi_addrs, 950 .addr = omap2_dss_rfbi_addrs,
1349 .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
1350 .fw = { 951 .fw = {
1351 .omap2 = { 952 .omap2 = {
1352 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, 953 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1363,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1363 964
1364static struct omap_hwmod omap2420_dss_rfbi_hwmod = { 965static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1365 .name = "dss_rfbi", 966 .name = "dss_rfbi",
1366 .class = &omap2420_rfbi_hwmod_class, 967 .class = &omap2_rfbi_hwmod_class,
1367 .main_clk = "dss1_fck", 968 .main_clk = "dss1_fck",
1368 .prcm = { 969 .prcm = {
1369 .omap2 = { 970 .omap2 = {
@@ -1378,31 +979,12 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1378 .flags = HWMOD_NO_IDLEST, 979 .flags = HWMOD_NO_IDLEST,
1379}; 980};
1380 981
1381/*
1382 * 'venc' class
1383 * video encoder
1384 */
1385
1386static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1387 .name = "venc",
1388};
1389
1390/* dss_venc */
1391static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
1392 {
1393 .pa_start = 0x48050C00,
1394 .pa_end = 0x48050FFF,
1395 .flags = ADDR_TYPE_RT
1396 },
1397};
1398
1399/* l4_core -> dss_venc */ 982/* l4_core -> dss_venc */
1400static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { 983static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1401 .master = &omap2420_l4_core_hwmod, 984 .master = &omap2420_l4_core_hwmod,
1402 .slave = &omap2420_dss_venc_hwmod, 985 .slave = &omap2420_dss_venc_hwmod,
1403 .clk = "dss_54m_fck", 986 .clk = "dss_54m_fck",
1404 .addr = omap2420_dss_venc_addrs, 987 .addr = omap2_dss_venc_addrs,
1405 .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
1406 .fw = { 988 .fw = {
1407 .omap2 = { 989 .omap2 = {
1408 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, 990 .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
@@ -1420,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1420 1002
1421static struct omap_hwmod omap2420_dss_venc_hwmod = { 1003static struct omap_hwmod omap2420_dss_venc_hwmod = {
1422 .name = "dss_venc", 1004 .name = "dss_venc",
1423 .class = &omap2420_venc_hwmod_class, 1005 .class = &omap2_venc_hwmod_class,
1424 .main_clk = "dss1_fck", 1006 .main_clk = "dss1_fck",
1425 .prcm = { 1007 .prcm = {
1426 .omap2 = { 1008 .omap2 = {
@@ -1453,25 +1035,14 @@ static struct omap_i2c_dev_attr i2c_dev_attr;
1453 1035
1454/* I2C1 */ 1036/* I2C1 */
1455 1037
1456static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1457 { .irq = INT_24XX_I2C1_IRQ, },
1458};
1459
1460static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1461 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1462 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1463};
1464
1465static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { 1038static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1466 &omap2420_l4_core__i2c1, 1039 &omap2420_l4_core__i2c1,
1467}; 1040};
1468 1041
1469static struct omap_hwmod omap2420_i2c1_hwmod = { 1042static struct omap_hwmod omap2420_i2c1_hwmod = {
1470 .name = "i2c1", 1043 .name = "i2c1",
1471 .mpu_irqs = i2c1_mpu_irqs, 1044 .mpu_irqs = omap2_i2c1_mpu_irqs,
1472 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1045 .sdma_reqs = omap2_i2c1_sdma_reqs,
1473 .sdma_reqs = i2c1_sdma_reqs,
1474 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1475 .main_clk = "i2c1_fck", 1046 .main_clk = "i2c1_fck",
1476 .prcm = { 1047 .prcm = {
1477 .omap2 = { 1048 .omap2 = {
@@ -1492,25 +1063,14 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
1492 1063
1493/* I2C2 */ 1064/* I2C2 */
1494 1065
1495static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1496 { .irq = INT_24XX_I2C2_IRQ, },
1497};
1498
1499static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1500 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1501 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1502};
1503
1504static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { 1066static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1505 &omap2420_l4_core__i2c2, 1067 &omap2420_l4_core__i2c2,
1506}; 1068};
1507 1069
1508static struct omap_hwmod omap2420_i2c2_hwmod = { 1070static struct omap_hwmod omap2420_i2c2_hwmod = {
1509 .name = "i2c2", 1071 .name = "i2c2",
1510 .mpu_irqs = i2c2_mpu_irqs, 1072 .mpu_irqs = omap2_i2c2_mpu_irqs,
1511 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1073 .sdma_reqs = omap2_i2c2_sdma_reqs,
1512 .sdma_reqs = i2c2_sdma_reqs,
1513 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1514 .main_clk = "i2c2_fck", 1074 .main_clk = "i2c2_fck",
1515 .prcm = { 1075 .prcm = {
1516 .omap2 = { 1076 .omap2 = {
@@ -1536,6 +1096,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1536 .pa_end = 0x480181ff, 1096 .pa_end = 0x480181ff,
1537 .flags = ADDR_TYPE_RT 1097 .flags = ADDR_TYPE_RT
1538 }, 1098 },
1099 { }
1539}; 1100};
1540 1101
1541static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { 1102static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
@@ -1543,7 +1104,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1543 .slave = &omap2420_gpio1_hwmod, 1104 .slave = &omap2420_gpio1_hwmod,
1544 .clk = "gpios_ick", 1105 .clk = "gpios_ick",
1545 .addr = omap2420_gpio1_addr_space, 1106 .addr = omap2420_gpio1_addr_space,
1546 .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
1547 .user = OCP_USER_MPU | OCP_USER_SDMA, 1107 .user = OCP_USER_MPU | OCP_USER_SDMA,
1548}; 1108};
1549 1109
@@ -1554,6 +1114,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1554 .pa_end = 0x4801a1ff, 1114 .pa_end = 0x4801a1ff,
1555 .flags = ADDR_TYPE_RT 1115 .flags = ADDR_TYPE_RT
1556 }, 1116 },
1117 { }
1557}; 1118};
1558 1119
1559static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { 1120static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
@@ -1561,7 +1122,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1561 .slave = &omap2420_gpio2_hwmod, 1122 .slave = &omap2420_gpio2_hwmod,
1562 .clk = "gpios_ick", 1123 .clk = "gpios_ick",
1563 .addr = omap2420_gpio2_addr_space, 1124 .addr = omap2420_gpio2_addr_space,
1564 .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
1565 .user = OCP_USER_MPU | OCP_USER_SDMA, 1125 .user = OCP_USER_MPU | OCP_USER_SDMA,
1566}; 1126};
1567 1127
@@ -1572,6 +1132,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1572 .pa_end = 0x4801c1ff, 1132 .pa_end = 0x4801c1ff,
1573 .flags = ADDR_TYPE_RT 1133 .flags = ADDR_TYPE_RT
1574 }, 1134 },
1135 { }
1575}; 1136};
1576 1137
1577static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { 1138static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
@@ -1579,7 +1140,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1579 .slave = &omap2420_gpio3_hwmod, 1140 .slave = &omap2420_gpio3_hwmod,
1580 .clk = "gpios_ick", 1141 .clk = "gpios_ick",
1581 .addr = omap2420_gpio3_addr_space, 1142 .addr = omap2420_gpio3_addr_space,
1582 .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
1583 .user = OCP_USER_MPU | OCP_USER_SDMA, 1143 .user = OCP_USER_MPU | OCP_USER_SDMA,
1584}; 1144};
1585 1145
@@ -1590,6 +1150,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1590 .pa_end = 0x4801e1ff, 1150 .pa_end = 0x4801e1ff,
1591 .flags = ADDR_TYPE_RT 1151 .flags = ADDR_TYPE_RT
1592 }, 1152 },
1153 { }
1593}; 1154};
1594 1155
1595static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { 1156static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
@@ -1597,7 +1158,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1597 .slave = &omap2420_gpio4_hwmod, 1158 .slave = &omap2420_gpio4_hwmod,
1598 .clk = "gpios_ick", 1159 .clk = "gpios_ick",
1599 .addr = omap2420_gpio4_addr_space, 1160 .addr = omap2420_gpio4_addr_space,
1600 .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
1601 .user = OCP_USER_MPU | OCP_USER_SDMA, 1161 .user = OCP_USER_MPU | OCP_USER_SDMA,
1602}; 1162};
1603 1163
@@ -1607,32 +1167,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1607 .dbck_flag = false, 1167 .dbck_flag = false,
1608}; 1168};
1609 1169
1610static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1611 .rev_offs = 0x0000,
1612 .sysc_offs = 0x0010,
1613 .syss_offs = 0x0014,
1614 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1615 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1616 SYSS_HAS_RESET_STATUS),
1617 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1618 .sysc_fields = &omap_hwmod_sysc_type1,
1619};
1620
1621/*
1622 * 'gpio' class
1623 * general purpose io module
1624 */
1625static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1626 .name = "gpio",
1627 .sysc = &omap242x_gpio_sysc,
1628 .rev = 0,
1629};
1630
1631/* gpio1 */ 1170/* gpio1 */
1632static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
1633 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1634};
1635
1636static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = { 1171static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1637 &omap2420_l4_wkup__gpio1, 1172 &omap2420_l4_wkup__gpio1,
1638}; 1173};
@@ -1640,8 +1175,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1640static struct omap_hwmod omap2420_gpio1_hwmod = { 1175static struct omap_hwmod omap2420_gpio1_hwmod = {
1641 .name = "gpio1", 1176 .name = "gpio1",
1642 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1177 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1643 .mpu_irqs = omap242x_gpio1_irqs, 1178 .mpu_irqs = omap2_gpio1_irqs,
1644 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
1645 .main_clk = "gpios_fck", 1179 .main_clk = "gpios_fck",
1646 .prcm = { 1180 .prcm = {
1647 .omap2 = { 1181 .omap2 = {
@@ -1654,16 +1188,12 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
1654 }, 1188 },
1655 .slaves = omap2420_gpio1_slaves, 1189 .slaves = omap2420_gpio1_slaves,
1656 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves), 1190 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
1657 .class = &omap242x_gpio_hwmod_class, 1191 .class = &omap2xxx_gpio_hwmod_class,
1658 .dev_attr = &gpio_dev_attr, 1192 .dev_attr = &gpio_dev_attr,
1659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1193 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1660}; 1194};
1661 1195
1662/* gpio2 */ 1196/* gpio2 */
1663static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
1664 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1665};
1666
1667static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = { 1197static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1668 &omap2420_l4_wkup__gpio2, 1198 &omap2420_l4_wkup__gpio2,
1669}; 1199};
@@ -1671,8 +1201,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1671static struct omap_hwmod omap2420_gpio2_hwmod = { 1201static struct omap_hwmod omap2420_gpio2_hwmod = {
1672 .name = "gpio2", 1202 .name = "gpio2",
1673 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1203 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1674 .mpu_irqs = omap242x_gpio2_irqs, 1204 .mpu_irqs = omap2_gpio2_irqs,
1675 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
1676 .main_clk = "gpios_fck", 1205 .main_clk = "gpios_fck",
1677 .prcm = { 1206 .prcm = {
1678 .omap2 = { 1207 .omap2 = {
@@ -1685,16 +1214,12 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
1685 }, 1214 },
1686 .slaves = omap2420_gpio2_slaves, 1215 .slaves = omap2420_gpio2_slaves,
1687 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves), 1216 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
1688 .class = &omap242x_gpio_hwmod_class, 1217 .class = &omap2xxx_gpio_hwmod_class,
1689 .dev_attr = &gpio_dev_attr, 1218 .dev_attr = &gpio_dev_attr,
1690 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1691}; 1220};
1692 1221
1693/* gpio3 */ 1222/* gpio3 */
1694static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
1695 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1696};
1697
1698static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = { 1223static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1699 &omap2420_l4_wkup__gpio3, 1224 &omap2420_l4_wkup__gpio3,
1700}; 1225};
@@ -1702,8 +1227,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1702static struct omap_hwmod omap2420_gpio3_hwmod = { 1227static struct omap_hwmod omap2420_gpio3_hwmod = {
1703 .name = "gpio3", 1228 .name = "gpio3",
1704 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1229 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1705 .mpu_irqs = omap242x_gpio3_irqs, 1230 .mpu_irqs = omap2_gpio3_irqs,
1706 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
1707 .main_clk = "gpios_fck", 1231 .main_clk = "gpios_fck",
1708 .prcm = { 1232 .prcm = {
1709 .omap2 = { 1233 .omap2 = {
@@ -1716,16 +1240,12 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
1716 }, 1240 },
1717 .slaves = omap2420_gpio3_slaves, 1241 .slaves = omap2420_gpio3_slaves,
1718 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves), 1242 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
1719 .class = &omap242x_gpio_hwmod_class, 1243 .class = &omap2xxx_gpio_hwmod_class,
1720 .dev_attr = &gpio_dev_attr, 1244 .dev_attr = &gpio_dev_attr,
1721 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1245 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1722}; 1246};
1723 1247
1724/* gpio4 */ 1248/* gpio4 */
1725static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
1726 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1727};
1728
1729static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = { 1249static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1730 &omap2420_l4_wkup__gpio4, 1250 &omap2420_l4_wkup__gpio4,
1731}; 1251};
@@ -1733,8 +1253,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1733static struct omap_hwmod omap2420_gpio4_hwmod = { 1253static struct omap_hwmod omap2420_gpio4_hwmod = {
1734 .name = "gpio4", 1254 .name = "gpio4",
1735 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1255 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1736 .mpu_irqs = omap242x_gpio4_irqs, 1256 .mpu_irqs = omap2_gpio4_irqs,
1737 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
1738 .main_clk = "gpios_fck", 1257 .main_clk = "gpios_fck",
1739 .prcm = { 1258 .prcm = {
1740 .omap2 = { 1259 .omap2 = {
@@ -1747,28 +1266,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
1747 }, 1266 },
1748 .slaves = omap2420_gpio4_slaves, 1267 .slaves = omap2420_gpio4_slaves,
1749 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves), 1268 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
1750 .class = &omap242x_gpio_hwmod_class, 1269 .class = &omap2xxx_gpio_hwmod_class,
1751 .dev_attr = &gpio_dev_attr, 1270 .dev_attr = &gpio_dev_attr,
1752 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1271 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1753}; 1272};
1754 1273
1755/* system dma */
1756static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1757 .rev_offs = 0x0000,
1758 .sysc_offs = 0x002c,
1759 .syss_offs = 0x0028,
1760 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1761 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1762 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1763 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1764 .sysc_fields = &omap_hwmod_sysc_type1,
1765};
1766
1767static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1768 .name = "dma",
1769 .sysc = &omap2420_dma_sysc,
1770};
1771
1772/* dma attributes */ 1274/* dma attributes */
1773static struct omap_dma_dev_attr dma_dev_attr = { 1275static struct omap_dma_dev_attr dma_dev_attr = {
1774 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1276 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1776,21 +1278,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
1776 .lch_count = 32, 1278 .lch_count = 32,
1777}; 1279};
1778 1280
1779static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
1780 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1781 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1782 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1783 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1784};
1785
1786static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
1787 {
1788 .pa_start = 0x48056000,
1789 .pa_end = 0x48056fff,
1790 .flags = ADDR_TYPE_RT
1791 },
1792};
1793
1794/* dma_system -> L3 */ 1281/* dma_system -> L3 */
1795static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { 1282static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1796 .master = &omap2420_dma_system_hwmod, 1283 .master = &omap2420_dma_system_hwmod,
@@ -1809,8 +1296,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1809 .master = &omap2420_l4_core_hwmod, 1296 .master = &omap2420_l4_core_hwmod,
1810 .slave = &omap2420_dma_system_hwmod, 1297 .slave = &omap2420_dma_system_hwmod,
1811 .clk = "sdma_ick", 1298 .clk = "sdma_ick",
1812 .addr = omap2420_dma_system_addrs, 1299 .addr = omap2_dma_system_addrs,
1813 .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
1814 .user = OCP_USER_MPU | OCP_USER_SDMA, 1300 .user = OCP_USER_MPU | OCP_USER_SDMA,
1815}; 1301};
1816 1302
@@ -1821,9 +1307,8 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1821 1307
1822static struct omap_hwmod omap2420_dma_system_hwmod = { 1308static struct omap_hwmod omap2420_dma_system_hwmod = {
1823 .name = "dma", 1309 .name = "dma",
1824 .class = &omap2420_dma_hwmod_class, 1310 .class = &omap2xxx_dma_hwmod_class,
1825 .mpu_irqs = omap2420_dma_system_irqs, 1311 .mpu_irqs = omap2_dma_system_irqs,
1826 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
1827 .main_clk = "core_l3_ck", 1312 .main_clk = "core_l3_ck",
1828 .slaves = omap2420_dma_system_slaves, 1313 .slaves = omap2420_dma_system_slaves,
1829 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves), 1314 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
@@ -1834,48 +1319,19 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
1834 .flags = HWMOD_NO_IDLEST, 1319 .flags = HWMOD_NO_IDLEST,
1835}; 1320};
1836 1321
1837/*
1838 * 'mailbox' class
1839 * mailbox module allowing communication between the on-chip processors
1840 * using a queued mailbox-interrupt mechanism.
1841 */
1842
1843static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1844 .rev_offs = 0x000,
1845 .sysc_offs = 0x010,
1846 .syss_offs = 0x014,
1847 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1848 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1849 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1850 .sysc_fields = &omap_hwmod_sysc_type1,
1851};
1852
1853static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1854 .name = "mailbox",
1855 .sysc = &omap2420_mailbox_sysc,
1856};
1857
1858/* mailbox */ 1322/* mailbox */
1859static struct omap_hwmod omap2420_mailbox_hwmod; 1323static struct omap_hwmod omap2420_mailbox_hwmod;
1860static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { 1324static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1861 { .name = "dsp", .irq = 26 }, 1325 { .name = "dsp", .irq = 26 },
1862 { .name = "iva", .irq = 34 }, 1326 { .name = "iva", .irq = 34 },
1863}; 1327 { .irq = -1 }
1864
1865static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
1866 {
1867 .pa_start = 0x48094000,
1868 .pa_end = 0x480941ff,
1869 .flags = ADDR_TYPE_RT,
1870 },
1871}; 1328};
1872 1329
1873/* l4_core -> mailbox */ 1330/* l4_core -> mailbox */
1874static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { 1331static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1875 .master = &omap2420_l4_core_hwmod, 1332 .master = &omap2420_l4_core_hwmod,
1876 .slave = &omap2420_mailbox_hwmod, 1333 .slave = &omap2420_mailbox_hwmod,
1877 .addr = omap2420_mailbox_addrs, 1334 .addr = omap2_mailbox_addrs,
1878 .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
1879 .user = OCP_USER_MPU | OCP_USER_SDMA, 1335 .user = OCP_USER_MPU | OCP_USER_SDMA,
1880}; 1336};
1881 1337
@@ -1886,9 +1342,8 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1886 1342
1887static struct omap_hwmod omap2420_mailbox_hwmod = { 1343static struct omap_hwmod omap2420_mailbox_hwmod = {
1888 .name = "mailbox", 1344 .name = "mailbox",
1889 .class = &omap2420_mailbox_hwmod_class, 1345 .class = &omap2xxx_mailbox_hwmod_class,
1890 .mpu_irqs = omap2420_mailbox_irqs, 1346 .mpu_irqs = omap2420_mailbox_irqs,
1891 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
1892 .main_clk = "mailboxes_ick", 1347 .main_clk = "mailboxes_ick",
1893 .prcm = { 1348 .prcm = {
1894 .omap2 = { 1349 .omap2 = {
@@ -1904,45 +1359,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
1904 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1359 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1905}; 1360};
1906 1361
1907/*
1908 * 'mcspi' class
1909 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1910 * bus
1911 */
1912
1913static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1914 .rev_offs = 0x0000,
1915 .sysc_offs = 0x0010,
1916 .syss_offs = 0x0014,
1917 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1918 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1919 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1921 .sysc_fields = &omap_hwmod_sysc_type1,
1922};
1923
1924static struct omap_hwmod_class omap2420_mcspi_class = {
1925 .name = "mcspi",
1926 .sysc = &omap2420_mcspi_sysc,
1927 .rev = OMAP2_MCSPI_REV,
1928};
1929
1930/* mcspi1 */ 1362/* mcspi1 */
1931static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
1932 { .irq = 65 },
1933};
1934
1935static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
1936 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1937 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1938 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1939 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1940 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1941 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1942 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1943 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1944};
1945
1946static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = { 1363static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1947 &omap2420_l4_core__mcspi1, 1364 &omap2420_l4_core__mcspi1,
1948}; 1365};
@@ -1953,10 +1370,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1953 1370
1954static struct omap_hwmod omap2420_mcspi1_hwmod = { 1371static struct omap_hwmod omap2420_mcspi1_hwmod = {
1955 .name = "mcspi1_hwmod", 1372 .name = "mcspi1_hwmod",
1956 .mpu_irqs = omap2420_mcspi1_mpu_irqs, 1373 .mpu_irqs = omap2_mcspi1_mpu_irqs,
1957 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs), 1374 .sdma_reqs = omap2_mcspi1_sdma_reqs,
1958 .sdma_reqs = omap2420_mcspi1_sdma_reqs,
1959 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
1960 .main_clk = "mcspi1_fck", 1375 .main_clk = "mcspi1_fck",
1961 .prcm = { 1376 .prcm = {
1962 .omap2 = { 1377 .omap2 = {
@@ -1969,23 +1384,12 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
1969 }, 1384 },
1970 .slaves = omap2420_mcspi1_slaves, 1385 .slaves = omap2420_mcspi1_slaves,
1971 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves), 1386 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
1972 .class = &omap2420_mcspi_class, 1387 .class = &omap2xxx_mcspi_class,
1973 .dev_attr = &omap_mcspi1_dev_attr, 1388 .dev_attr = &omap_mcspi1_dev_attr,
1974 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1389 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1975}; 1390};
1976 1391
1977/* mcspi2 */ 1392/* mcspi2 */
1978static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
1979 { .irq = 66 },
1980};
1981
1982static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
1983 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1984 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1985 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1986 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1987};
1988
1989static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = { 1393static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1990 &omap2420_l4_core__mcspi2, 1394 &omap2420_l4_core__mcspi2,
1991}; 1395};
@@ -1996,10 +1400,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1996 1400
1997static struct omap_hwmod omap2420_mcspi2_hwmod = { 1401static struct omap_hwmod omap2420_mcspi2_hwmod = {
1998 .name = "mcspi2_hwmod", 1402 .name = "mcspi2_hwmod",
1999 .mpu_irqs = omap2420_mcspi2_mpu_irqs, 1403 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2000 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs), 1404 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2001 .sdma_reqs = omap2420_mcspi2_sdma_reqs,
2002 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
2003 .main_clk = "mcspi2_fck", 1405 .main_clk = "mcspi2_fck",
2004 .prcm = { 1406 .prcm = {
2005 .omap2 = { 1407 .omap2 = {
@@ -2012,8 +1414,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
2012 }, 1414 },
2013 .slaves = omap2420_mcspi2_slaves, 1415 .slaves = omap2420_mcspi2_slaves,
2014 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves), 1416 .slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
2015 .class = &omap2420_mcspi_class, 1417 .class = &omap2xxx_mcspi_class,
2016 .dev_attr = &omap_mcspi2_dev_attr, 1418 .dev_attr = &omap_mcspi2_dev_attr,
2017 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 1419 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2018}; 1420};
2019 1421
@@ -2030,20 +1432,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
2030static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { 1432static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
2031 { .name = "tx", .irq = 59 }, 1433 { .name = "tx", .irq = 59 },
2032 { .name = "rx", .irq = 60 }, 1434 { .name = "rx", .irq = 60 },
2033}; 1435 { .irq = -1 }
2034
2035static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
2036 { .name = "rx", .dma_req = 32 },
2037 { .name = "tx", .dma_req = 31 },
2038};
2039
2040static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
2041 {
2042 .name = "mpu",
2043 .pa_start = 0x48074000,
2044 .pa_end = 0x480740ff,
2045 .flags = ADDR_TYPE_RT
2046 },
2047}; 1436};
2048 1437
2049/* l4_core -> mcbsp1 */ 1438/* l4_core -> mcbsp1 */
@@ -2051,8 +1440,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
2051 .master = &omap2420_l4_core_hwmod, 1440 .master = &omap2420_l4_core_hwmod,
2052 .slave = &omap2420_mcbsp1_hwmod, 1441 .slave = &omap2420_mcbsp1_hwmod,
2053 .clk = "mcbsp1_ick", 1442 .clk = "mcbsp1_ick",
2054 .addr = omap2420_mcbsp1_addrs, 1443 .addr = omap2_mcbsp1_addrs,
2055 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
2056 .user = OCP_USER_MPU | OCP_USER_SDMA, 1444 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057}; 1445};
2058 1446
@@ -2065,9 +1453,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2065 .name = "mcbsp1", 1453 .name = "mcbsp1",
2066 .class = &omap2420_mcbsp_hwmod_class, 1454 .class = &omap2420_mcbsp_hwmod_class,
2067 .mpu_irqs = omap2420_mcbsp1_irqs, 1455 .mpu_irqs = omap2420_mcbsp1_irqs,
2068 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs), 1456 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2069 .sdma_reqs = omap2420_mcbsp1_sdma_chs,
2070 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
2071 .main_clk = "mcbsp1_fck", 1457 .main_clk = "mcbsp1_fck",
2072 .prcm = { 1458 .prcm = {
2073 .omap2 = { 1459 .omap2 = {
@@ -2087,20 +1473,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2087static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { 1473static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
2088 { .name = "tx", .irq = 62 }, 1474 { .name = "tx", .irq = 62 },
2089 { .name = "rx", .irq = 63 }, 1475 { .name = "rx", .irq = 63 },
2090}; 1476 { .irq = -1 }
2091
2092static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
2093 { .name = "rx", .dma_req = 34 },
2094 { .name = "tx", .dma_req = 33 },
2095};
2096
2097static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
2098 {
2099 .name = "mpu",
2100 .pa_start = 0x48076000,
2101 .pa_end = 0x480760ff,
2102 .flags = ADDR_TYPE_RT
2103 },
2104}; 1477};
2105 1478
2106/* l4_core -> mcbsp2 */ 1479/* l4_core -> mcbsp2 */
@@ -2108,8 +1481,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
2108 .master = &omap2420_l4_core_hwmod, 1481 .master = &omap2420_l4_core_hwmod,
2109 .slave = &omap2420_mcbsp2_hwmod, 1482 .slave = &omap2420_mcbsp2_hwmod,
2110 .clk = "mcbsp2_ick", 1483 .clk = "mcbsp2_ick",
2111 .addr = omap2420_mcbsp2_addrs, 1484 .addr = omap2xxx_mcbsp2_addrs,
2112 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
2113 .user = OCP_USER_MPU | OCP_USER_SDMA, 1485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2114}; 1486};
2115 1487
@@ -2122,9 +1494,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
2122 .name = "mcbsp2", 1494 .name = "mcbsp2",
2123 .class = &omap2420_mcbsp_hwmod_class, 1495 .class = &omap2420_mcbsp_hwmod_class,
2124 .mpu_irqs = omap2420_mcbsp2_irqs, 1496 .mpu_irqs = omap2420_mcbsp2_irqs,
2125 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs), 1497 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2126 .sdma_reqs = omap2420_mcbsp2_sdma_chs,
2127 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
2128 .main_clk = "mcbsp2_fck", 1498 .main_clk = "mcbsp2_fck",
2129 .prcm = { 1499 .prcm = {
2130 .omap2 = { 1500 .omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 9682dd519f8d..2a52f025bd06 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips 2 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
131 .user = OCP_USER_MPU, 131 .user = OCP_USER_MPU,
132}; 132};
133 133
134/* I2C IP block address space length (in bytes) */
135#define OMAP2_I2C_AS_LEN 128
136
137/* L4 CORE -> I2C1 interface */ 134/* L4 CORE -> I2C1 interface */
138static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
139 {
140 .pa_start = 0x48070000,
141 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
142 .flags = ADDR_TYPE_RT,
143 },
144};
145
146static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { 135static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
147 .master = &omap2430_l4_core_hwmod, 136 .master = &omap2430_l4_core_hwmod,
148 .slave = &omap2430_i2c1_hwmod, 137 .slave = &omap2430_i2c1_hwmod,
149 .clk = "i2c1_ick", 138 .clk = "i2c1_ick",
150 .addr = omap2430_i2c1_addr_space, 139 .addr = omap2_i2c1_addr_space,
151 .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
152 .user = OCP_USER_MPU | OCP_USER_SDMA, 140 .user = OCP_USER_MPU | OCP_USER_SDMA,
153}; 141};
154 142
155/* L4 CORE -> I2C2 interface */ 143/* L4 CORE -> I2C2 interface */
156static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
157 {
158 .pa_start = 0x48072000,
159 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
160 .flags = ADDR_TYPE_RT,
161 },
162};
163
164static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { 144static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
165 .master = &omap2430_l4_core_hwmod, 145 .master = &omap2430_l4_core_hwmod,
166 .slave = &omap2430_i2c2_hwmod, 146 .slave = &omap2430_i2c2_hwmod,
167 .clk = "i2c2_ick", 147 .clk = "i2c2_ick",
168 .addr = omap2430_i2c2_addr_space, 148 .addr = omap2_i2c2_addr_space,
169 .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
170 .user = OCP_USER_MPU | OCP_USER_SDMA, 149 .user = OCP_USER_MPU | OCP_USER_SDMA,
171}; 150};
172 151
@@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
178}; 157};
179 158
180/* L4 CORE -> UART1 interface */ 159/* L4 CORE -> UART1 interface */
181static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
182 {
183 .pa_start = OMAP2_UART1_BASE,
184 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
185 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
186 },
187};
188
189static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { 160static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
190 .master = &omap2430_l4_core_hwmod, 161 .master = &omap2430_l4_core_hwmod,
191 .slave = &omap2430_uart1_hwmod, 162 .slave = &omap2430_uart1_hwmod,
192 .clk = "uart1_ick", 163 .clk = "uart1_ick",
193 .addr = omap2430_uart1_addr_space, 164 .addr = omap2xxx_uart1_addr_space,
194 .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
195 .user = OCP_USER_MPU | OCP_USER_SDMA, 165 .user = OCP_USER_MPU | OCP_USER_SDMA,
196}; 166};
197 167
198/* L4 CORE -> UART2 interface */ 168/* L4 CORE -> UART2 interface */
199static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
200 {
201 .pa_start = OMAP2_UART2_BASE,
202 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
203 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
204 },
205};
206
207static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { 169static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
208 .master = &omap2430_l4_core_hwmod, 170 .master = &omap2430_l4_core_hwmod,
209 .slave = &omap2430_uart2_hwmod, 171 .slave = &omap2430_uart2_hwmod,
210 .clk = "uart2_ick", 172 .clk = "uart2_ick",
211 .addr = omap2430_uart2_addr_space, 173 .addr = omap2xxx_uart2_addr_space,
212 .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
213 .user = OCP_USER_MPU | OCP_USER_SDMA, 174 .user = OCP_USER_MPU | OCP_USER_SDMA,
214}; 175};
215 176
216/* L4 PER -> UART3 interface */ 177/* L4 PER -> UART3 interface */
217static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
218 {
219 .pa_start = OMAP2_UART3_BASE,
220 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
221 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
222 },
223};
224
225static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { 178static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
226 .master = &omap2430_l4_core_hwmod, 179 .master = &omap2430_l4_core_hwmod,
227 .slave = &omap2430_uart3_hwmod, 180 .slave = &omap2430_uart3_hwmod,
228 .clk = "uart3_ick", 181 .clk = "uart3_ick",
229 .addr = omap2430_uart3_addr_space, 182 .addr = omap2xxx_uart3_addr_space,
230 .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
231 .user = OCP_USER_MPU | OCP_USER_SDMA, 183 .user = OCP_USER_MPU | OCP_USER_SDMA,
232}; 184};
233 185
@@ -248,7 +200,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
248 .slave = &omap2430_usbhsotg_hwmod, 200 .slave = &omap2430_usbhsotg_hwmod,
249 .clk = "usb_l4_ick", 201 .clk = "usb_l4_ick",
250 .addr = omap2430_usbhsotg_addrs, 202 .addr = omap2430_usbhsotg_addrs,
251 .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
252 .user = OCP_USER_MPU, 203 .user = OCP_USER_MPU,
253}; 204};
254 205
@@ -261,38 +212,20 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
261}; 212};
262 213
263/* L4 CORE -> MMC1 interface */ 214/* L4 CORE -> MMC1 interface */
264static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
265 {
266 .pa_start = 0x4809c000,
267 .pa_end = 0x4809c1ff,
268 .flags = ADDR_TYPE_RT,
269 },
270};
271
272static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { 215static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
273 .master = &omap2430_l4_core_hwmod, 216 .master = &omap2430_l4_core_hwmod,
274 .slave = &omap2430_mmc1_hwmod, 217 .slave = &omap2430_mmc1_hwmod,
275 .clk = "mmchs1_ick", 218 .clk = "mmchs1_ick",
276 .addr = omap2430_mmc1_addr_space, 219 .addr = omap2430_mmc1_addr_space,
277 .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
278 .user = OCP_USER_MPU | OCP_USER_SDMA, 220 .user = OCP_USER_MPU | OCP_USER_SDMA,
279}; 221};
280 222
281/* L4 CORE -> MMC2 interface */ 223/* L4 CORE -> MMC2 interface */
282static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
283 {
284 .pa_start = 0x480b4000,
285 .pa_end = 0x480b41ff,
286 .flags = ADDR_TYPE_RT,
287 },
288};
289
290static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { 224static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
291 .master = &omap2430_l4_core_hwmod, 225 .master = &omap2430_l4_core_hwmod,
292 .slave = &omap2430_mmc2_hwmod, 226 .slave = &omap2430_mmc2_hwmod,
293 .addr = omap2430_mmc2_addr_space,
294 .clk = "mmchs2_ick", 227 .clk = "mmchs2_ick",
295 .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space), 228 .addr = omap2430_mmc2_addr_space,
296 .user = OCP_USER_MPU | OCP_USER_SDMA, 229 .user = OCP_USER_MPU | OCP_USER_SDMA,
297}; 230};
298 231
@@ -333,56 +266,29 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
333}; 266};
334 267
335/* l4 core -> mcspi1 interface */ 268/* l4 core -> mcspi1 interface */
336static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
337 {
338 .pa_start = 0x48098000,
339 .pa_end = 0x480980ff,
340 .flags = ADDR_TYPE_RT,
341 },
342};
343
344static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = { 269static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
345 .master = &omap2430_l4_core_hwmod, 270 .master = &omap2430_l4_core_hwmod,
346 .slave = &omap2430_mcspi1_hwmod, 271 .slave = &omap2430_mcspi1_hwmod,
347 .clk = "mcspi1_ick", 272 .clk = "mcspi1_ick",
348 .addr = omap2430_mcspi1_addr_space, 273 .addr = omap2_mcspi1_addr_space,
349 .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
350 .user = OCP_USER_MPU | OCP_USER_SDMA, 274 .user = OCP_USER_MPU | OCP_USER_SDMA,
351}; 275};
352 276
353/* l4 core -> mcspi2 interface */ 277/* l4 core -> mcspi2 interface */
354static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
355 {
356 .pa_start = 0x4809a000,
357 .pa_end = 0x4809a0ff,
358 .flags = ADDR_TYPE_RT,
359 },
360};
361
362static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = { 278static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
363 .master = &omap2430_l4_core_hwmod, 279 .master = &omap2430_l4_core_hwmod,
364 .slave = &omap2430_mcspi2_hwmod, 280 .slave = &omap2430_mcspi2_hwmod,
365 .clk = "mcspi2_ick", 281 .clk = "mcspi2_ick",
366 .addr = omap2430_mcspi2_addr_space, 282 .addr = omap2_mcspi2_addr_space,
367 .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
368 .user = OCP_USER_MPU | OCP_USER_SDMA, 283 .user = OCP_USER_MPU | OCP_USER_SDMA,
369}; 284};
370 285
371/* l4 core -> mcspi3 interface */ 286/* l4 core -> mcspi3 interface */
372static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
373 {
374 .pa_start = 0x480b8000,
375 .pa_end = 0x480b80ff,
376 .flags = ADDR_TYPE_RT,
377 },
378};
379
380static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { 287static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
381 .master = &omap2430_l4_core_hwmod, 288 .master = &omap2430_l4_core_hwmod,
382 .slave = &omap2430_mcspi3_hwmod, 289 .slave = &omap2430_mcspi3_hwmod,
383 .clk = "mcspi3_ick", 290 .clk = "mcspi3_ick",
384 .addr = omap2430_mcspi3_addr_space, 291 .addr = omap2430_mcspi3_addr_space,
385 .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
386 .user = OCP_USER_MPU | OCP_USER_SDMA, 292 .user = OCP_USER_MPU | OCP_USER_SDMA,
387}; 293};
388 294
@@ -441,29 +347,8 @@ static struct omap_hwmod omap2430_iva_hwmod = {
441 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 347 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
442}; 348};
443 349
444/* Timer Common */
445static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
446 .rev_offs = 0x0000,
447 .sysc_offs = 0x0010,
448 .syss_offs = 0x0014,
449 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
450 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
451 SYSC_HAS_AUTOIDLE),
452 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454};
455
456static struct omap_hwmod_class omap2430_timer_hwmod_class = {
457 .name = "timer",
458 .sysc = &omap2430_timer_sysc,
459 .rev = OMAP_TIMER_IP_VERSION_1,
460};
461
462/* timer1 */ 350/* timer1 */
463static struct omap_hwmod omap2430_timer1_hwmod; 351static struct omap_hwmod omap2430_timer1_hwmod;
464static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
465 { .irq = 37, },
466};
467 352
468static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = { 353static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
469 { 354 {
@@ -471,6 +356,7 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
471 .pa_end = 0x49018000 + SZ_1K - 1, 356 .pa_end = 0x49018000 + SZ_1K - 1,
472 .flags = ADDR_TYPE_RT 357 .flags = ADDR_TYPE_RT
473 }, 358 },
359 { }
474}; 360};
475 361
476/* l4_wkup -> timer1 */ 362/* l4_wkup -> timer1 */
@@ -479,7 +365,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
479 .slave = &omap2430_timer1_hwmod, 365 .slave = &omap2430_timer1_hwmod,
480 .clk = "gpt1_ick", 366 .clk = "gpt1_ick",
481 .addr = omap2430_timer1_addrs, 367 .addr = omap2430_timer1_addrs,
482 .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
483 .user = OCP_USER_MPU | OCP_USER_SDMA, 368 .user = OCP_USER_MPU | OCP_USER_SDMA,
484}; 369};
485 370
@@ -491,8 +376,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
491/* timer1 hwmod */ 376/* timer1 hwmod */
492static struct omap_hwmod omap2430_timer1_hwmod = { 377static struct omap_hwmod omap2430_timer1_hwmod = {
493 .name = "timer1", 378 .name = "timer1",
494 .mpu_irqs = omap2430_timer1_mpu_irqs, 379 .mpu_irqs = omap2_timer1_mpu_irqs,
495 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
496 .main_clk = "gpt1_fck", 380 .main_clk = "gpt1_fck",
497 .prcm = { 381 .prcm = {
498 .omap2 = { 382 .omap2 = {
@@ -505,31 +389,19 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
505 }, 389 },
506 .slaves = omap2430_timer1_slaves, 390 .slaves = omap2430_timer1_slaves,
507 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves), 391 .slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
508 .class = &omap2430_timer_hwmod_class, 392 .class = &omap2xxx_timer_hwmod_class,
509 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 393 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
510}; 394};
511 395
512/* timer2 */ 396/* timer2 */
513static struct omap_hwmod omap2430_timer2_hwmod; 397static struct omap_hwmod omap2430_timer2_hwmod;
514static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
515 { .irq = 38, },
516};
517
518static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
519 {
520 .pa_start = 0x4802a000,
521 .pa_end = 0x4802a000 + SZ_1K - 1,
522 .flags = ADDR_TYPE_RT
523 },
524};
525 398
526/* l4_core -> timer2 */ 399/* l4_core -> timer2 */
527static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = { 400static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
528 .master = &omap2430_l4_core_hwmod, 401 .master = &omap2430_l4_core_hwmod,
529 .slave = &omap2430_timer2_hwmod, 402 .slave = &omap2430_timer2_hwmod,
530 .clk = "gpt2_ick", 403 .clk = "gpt2_ick",
531 .addr = omap2430_timer2_addrs, 404 .addr = omap2xxx_timer2_addrs,
532 .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
533 .user = OCP_USER_MPU | OCP_USER_SDMA, 405 .user = OCP_USER_MPU | OCP_USER_SDMA,
534}; 406};
535 407
@@ -541,8 +413,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
541/* timer2 hwmod */ 413/* timer2 hwmod */
542static struct omap_hwmod omap2430_timer2_hwmod = { 414static struct omap_hwmod omap2430_timer2_hwmod = {
543 .name = "timer2", 415 .name = "timer2",
544 .mpu_irqs = omap2430_timer2_mpu_irqs, 416 .mpu_irqs = omap2_timer2_mpu_irqs,
545 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
546 .main_clk = "gpt2_fck", 417 .main_clk = "gpt2_fck",
547 .prcm = { 418 .prcm = {
548 .omap2 = { 419 .omap2 = {
@@ -555,31 +426,19 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
555 }, 426 },
556 .slaves = omap2430_timer2_slaves, 427 .slaves = omap2430_timer2_slaves,
557 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves), 428 .slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
558 .class = &omap2430_timer_hwmod_class, 429 .class = &omap2xxx_timer_hwmod_class,
559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 430 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
560}; 431};
561 432
562/* timer3 */ 433/* timer3 */
563static struct omap_hwmod omap2430_timer3_hwmod; 434static struct omap_hwmod omap2430_timer3_hwmod;
564static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
565 { .irq = 39, },
566};
567
568static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
569 {
570 .pa_start = 0x48078000,
571 .pa_end = 0x48078000 + SZ_1K - 1,
572 .flags = ADDR_TYPE_RT
573 },
574};
575 435
576/* l4_core -> timer3 */ 436/* l4_core -> timer3 */
577static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = { 437static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
578 .master = &omap2430_l4_core_hwmod, 438 .master = &omap2430_l4_core_hwmod,
579 .slave = &omap2430_timer3_hwmod, 439 .slave = &omap2430_timer3_hwmod,
580 .clk = "gpt3_ick", 440 .clk = "gpt3_ick",
581 .addr = omap2430_timer3_addrs, 441 .addr = omap2xxx_timer3_addrs,
582 .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
583 .user = OCP_USER_MPU | OCP_USER_SDMA, 442 .user = OCP_USER_MPU | OCP_USER_SDMA,
584}; 443};
585 444
@@ -591,8 +450,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
591/* timer3 hwmod */ 450/* timer3 hwmod */
592static struct omap_hwmod omap2430_timer3_hwmod = { 451static struct omap_hwmod omap2430_timer3_hwmod = {
593 .name = "timer3", 452 .name = "timer3",
594 .mpu_irqs = omap2430_timer3_mpu_irqs, 453 .mpu_irqs = omap2_timer3_mpu_irqs,
595 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
596 .main_clk = "gpt3_fck", 454 .main_clk = "gpt3_fck",
597 .prcm = { 455 .prcm = {
598 .omap2 = { 456 .omap2 = {
@@ -605,31 +463,19 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
605 }, 463 },
606 .slaves = omap2430_timer3_slaves, 464 .slaves = omap2430_timer3_slaves,
607 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves), 465 .slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
608 .class = &omap2430_timer_hwmod_class, 466 .class = &omap2xxx_timer_hwmod_class,
609 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 467 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
610}; 468};
611 469
612/* timer4 */ 470/* timer4 */
613static struct omap_hwmod omap2430_timer4_hwmod; 471static struct omap_hwmod omap2430_timer4_hwmod;
614static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
615 { .irq = 40, },
616};
617
618static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
619 {
620 .pa_start = 0x4807a000,
621 .pa_end = 0x4807a000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT
623 },
624};
625 472
626/* l4_core -> timer4 */ 473/* l4_core -> timer4 */
627static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = { 474static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
628 .master = &omap2430_l4_core_hwmod, 475 .master = &omap2430_l4_core_hwmod,
629 .slave = &omap2430_timer4_hwmod, 476 .slave = &omap2430_timer4_hwmod,
630 .clk = "gpt4_ick", 477 .clk = "gpt4_ick",
631 .addr = omap2430_timer4_addrs, 478 .addr = omap2xxx_timer4_addrs,
632 .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 479 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 480};
635 481
@@ -641,8 +487,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
641/* timer4 hwmod */ 487/* timer4 hwmod */
642static struct omap_hwmod omap2430_timer4_hwmod = { 488static struct omap_hwmod omap2430_timer4_hwmod = {
643 .name = "timer4", 489 .name = "timer4",
644 .mpu_irqs = omap2430_timer4_mpu_irqs, 490 .mpu_irqs = omap2_timer4_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
646 .main_clk = "gpt4_fck", 491 .main_clk = "gpt4_fck",
647 .prcm = { 492 .prcm = {
648 .omap2 = { 493 .omap2 = {
@@ -655,31 +500,19 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
655 }, 500 },
656 .slaves = omap2430_timer4_slaves, 501 .slaves = omap2430_timer4_slaves,
657 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves), 502 .slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
658 .class = &omap2430_timer_hwmod_class, 503 .class = &omap2xxx_timer_hwmod_class,
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 504 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
660}; 505};
661 506
662/* timer5 */ 507/* timer5 */
663static struct omap_hwmod omap2430_timer5_hwmod; 508static struct omap_hwmod omap2430_timer5_hwmod;
664static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
665 { .irq = 41, },
666};
667
668static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
669 {
670 .pa_start = 0x4807c000,
671 .pa_end = 0x4807c000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
673 },
674};
675 509
676/* l4_core -> timer5 */ 510/* l4_core -> timer5 */
677static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = { 511static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
678 .master = &omap2430_l4_core_hwmod, 512 .master = &omap2430_l4_core_hwmod,
679 .slave = &omap2430_timer5_hwmod, 513 .slave = &omap2430_timer5_hwmod,
680 .clk = "gpt5_ick", 514 .clk = "gpt5_ick",
681 .addr = omap2430_timer5_addrs, 515 .addr = omap2xxx_timer5_addrs,
682 .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 516 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 517};
685 518
@@ -691,8 +524,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
691/* timer5 hwmod */ 524/* timer5 hwmod */
692static struct omap_hwmod omap2430_timer5_hwmod = { 525static struct omap_hwmod omap2430_timer5_hwmod = {
693 .name = "timer5", 526 .name = "timer5",
694 .mpu_irqs = omap2430_timer5_mpu_irqs, 527 .mpu_irqs = omap2_timer5_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
696 .main_clk = "gpt5_fck", 528 .main_clk = "gpt5_fck",
697 .prcm = { 529 .prcm = {
698 .omap2 = { 530 .omap2 = {
@@ -705,31 +537,19 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
705 }, 537 },
706 .slaves = omap2430_timer5_slaves, 538 .slaves = omap2430_timer5_slaves,
707 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves), 539 .slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
708 .class = &omap2430_timer_hwmod_class, 540 .class = &omap2xxx_timer_hwmod_class,
709 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 541 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
710}; 542};
711 543
712/* timer6 */ 544/* timer6 */
713static struct omap_hwmod omap2430_timer6_hwmod; 545static struct omap_hwmod omap2430_timer6_hwmod;
714static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
715 { .irq = 42, },
716};
717
718static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
719 {
720 .pa_start = 0x4807e000,
721 .pa_end = 0x4807e000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT
723 },
724};
725 546
726/* l4_core -> timer6 */ 547/* l4_core -> timer6 */
727static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = { 548static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
728 .master = &omap2430_l4_core_hwmod, 549 .master = &omap2430_l4_core_hwmod,
729 .slave = &omap2430_timer6_hwmod, 550 .slave = &omap2430_timer6_hwmod,
730 .clk = "gpt6_ick", 551 .clk = "gpt6_ick",
731 .addr = omap2430_timer6_addrs, 552 .addr = omap2xxx_timer6_addrs,
732 .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 553 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 554};
735 555
@@ -741,8 +561,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
741/* timer6 hwmod */ 561/* timer6 hwmod */
742static struct omap_hwmod omap2430_timer6_hwmod = { 562static struct omap_hwmod omap2430_timer6_hwmod = {
743 .name = "timer6", 563 .name = "timer6",
744 .mpu_irqs = omap2430_timer6_mpu_irqs, 564 .mpu_irqs = omap2_timer6_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
746 .main_clk = "gpt6_fck", 565 .main_clk = "gpt6_fck",
747 .prcm = { 566 .prcm = {
748 .omap2 = { 567 .omap2 = {
@@ -755,31 +574,19 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
755 }, 574 },
756 .slaves = omap2430_timer6_slaves, 575 .slaves = omap2430_timer6_slaves,
757 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves), 576 .slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
758 .class = &omap2430_timer_hwmod_class, 577 .class = &omap2xxx_timer_hwmod_class,
759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 578 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
760}; 579};
761 580
762/* timer7 */ 581/* timer7 */
763static struct omap_hwmod omap2430_timer7_hwmod; 582static struct omap_hwmod omap2430_timer7_hwmod;
764static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
765 { .irq = 43, },
766};
767
768static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
769 {
770 .pa_start = 0x48080000,
771 .pa_end = 0x48080000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT
773 },
774};
775 583
776/* l4_core -> timer7 */ 584/* l4_core -> timer7 */
777static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = { 585static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
778 .master = &omap2430_l4_core_hwmod, 586 .master = &omap2430_l4_core_hwmod,
779 .slave = &omap2430_timer7_hwmod, 587 .slave = &omap2430_timer7_hwmod,
780 .clk = "gpt7_ick", 588 .clk = "gpt7_ick",
781 .addr = omap2430_timer7_addrs, 589 .addr = omap2xxx_timer7_addrs,
782 .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 590 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 591};
785 592
@@ -791,8 +598,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
791/* timer7 hwmod */ 598/* timer7 hwmod */
792static struct omap_hwmod omap2430_timer7_hwmod = { 599static struct omap_hwmod omap2430_timer7_hwmod = {
793 .name = "timer7", 600 .name = "timer7",
794 .mpu_irqs = omap2430_timer7_mpu_irqs, 601 .mpu_irqs = omap2_timer7_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
796 .main_clk = "gpt7_fck", 602 .main_clk = "gpt7_fck",
797 .prcm = { 603 .prcm = {
798 .omap2 = { 604 .omap2 = {
@@ -805,31 +611,19 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
805 }, 611 },
806 .slaves = omap2430_timer7_slaves, 612 .slaves = omap2430_timer7_slaves,
807 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves), 613 .slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
808 .class = &omap2430_timer_hwmod_class, 614 .class = &omap2xxx_timer_hwmod_class,
809 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 615 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
810}; 616};
811 617
812/* timer8 */ 618/* timer8 */
813static struct omap_hwmod omap2430_timer8_hwmod; 619static struct omap_hwmod omap2430_timer8_hwmod;
814static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
815 { .irq = 44, },
816};
817
818static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
819 {
820 .pa_start = 0x48082000,
821 .pa_end = 0x48082000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT
823 },
824};
825 620
826/* l4_core -> timer8 */ 621/* l4_core -> timer8 */
827static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = { 622static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
828 .master = &omap2430_l4_core_hwmod, 623 .master = &omap2430_l4_core_hwmod,
829 .slave = &omap2430_timer8_hwmod, 624 .slave = &omap2430_timer8_hwmod,
830 .clk = "gpt8_ick", 625 .clk = "gpt8_ick",
831 .addr = omap2430_timer8_addrs, 626 .addr = omap2xxx_timer8_addrs,
832 .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 627 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 628};
835 629
@@ -841,8 +635,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
841/* timer8 hwmod */ 635/* timer8 hwmod */
842static struct omap_hwmod omap2430_timer8_hwmod = { 636static struct omap_hwmod omap2430_timer8_hwmod = {
843 .name = "timer8", 637 .name = "timer8",
844 .mpu_irqs = omap2430_timer8_mpu_irqs, 638 .mpu_irqs = omap2_timer8_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
846 .main_clk = "gpt8_fck", 639 .main_clk = "gpt8_fck",
847 .prcm = { 640 .prcm = {
848 .omap2 = { 641 .omap2 = {
@@ -855,31 +648,19 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
855 }, 648 },
856 .slaves = omap2430_timer8_slaves, 649 .slaves = omap2430_timer8_slaves,
857 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves), 650 .slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
858 .class = &omap2430_timer_hwmod_class, 651 .class = &omap2xxx_timer_hwmod_class,
859 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 652 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
860}; 653};
861 654
862/* timer9 */ 655/* timer9 */
863static struct omap_hwmod omap2430_timer9_hwmod; 656static struct omap_hwmod omap2430_timer9_hwmod;
864static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
865 { .irq = 45, },
866};
867
868static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
869 {
870 .pa_start = 0x48084000,
871 .pa_end = 0x48084000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT
873 },
874};
875 657
876/* l4_core -> timer9 */ 658/* l4_core -> timer9 */
877static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = { 659static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
878 .master = &omap2430_l4_core_hwmod, 660 .master = &omap2430_l4_core_hwmod,
879 .slave = &omap2430_timer9_hwmod, 661 .slave = &omap2430_timer9_hwmod,
880 .clk = "gpt9_ick", 662 .clk = "gpt9_ick",
881 .addr = omap2430_timer9_addrs, 663 .addr = omap2xxx_timer9_addrs,
882 .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 664 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 665};
885 666
@@ -891,8 +672,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
891/* timer9 hwmod */ 672/* timer9 hwmod */
892static struct omap_hwmod omap2430_timer9_hwmod = { 673static struct omap_hwmod omap2430_timer9_hwmod = {
893 .name = "timer9", 674 .name = "timer9",
894 .mpu_irqs = omap2430_timer9_mpu_irqs, 675 .mpu_irqs = omap2_timer9_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
896 .main_clk = "gpt9_fck", 676 .main_clk = "gpt9_fck",
897 .prcm = { 677 .prcm = {
898 .omap2 = { 678 .omap2 = {
@@ -905,31 +685,19 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
905 }, 685 },
906 .slaves = omap2430_timer9_slaves, 686 .slaves = omap2430_timer9_slaves,
907 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves), 687 .slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
908 .class = &omap2430_timer_hwmod_class, 688 .class = &omap2xxx_timer_hwmod_class,
909 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 689 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
910}; 690};
911 691
912/* timer10 */ 692/* timer10 */
913static struct omap_hwmod omap2430_timer10_hwmod; 693static struct omap_hwmod omap2430_timer10_hwmod;
914static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
915 { .irq = 46, },
916};
917
918static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
919 {
920 .pa_start = 0x48086000,
921 .pa_end = 0x48086000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT
923 },
924};
925 694
926/* l4_core -> timer10 */ 695/* l4_core -> timer10 */
927static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = { 696static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
928 .master = &omap2430_l4_core_hwmod, 697 .master = &omap2430_l4_core_hwmod,
929 .slave = &omap2430_timer10_hwmod, 698 .slave = &omap2430_timer10_hwmod,
930 .clk = "gpt10_ick", 699 .clk = "gpt10_ick",
931 .addr = omap2430_timer10_addrs, 700 .addr = omap2_timer10_addrs,
932 .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 701 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 702};
935 703
@@ -941,8 +709,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
941/* timer10 hwmod */ 709/* timer10 hwmod */
942static struct omap_hwmod omap2430_timer10_hwmod = { 710static struct omap_hwmod omap2430_timer10_hwmod = {
943 .name = "timer10", 711 .name = "timer10",
944 .mpu_irqs = omap2430_timer10_mpu_irqs, 712 .mpu_irqs = omap2_timer10_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
946 .main_clk = "gpt10_fck", 713 .main_clk = "gpt10_fck",
947 .prcm = { 714 .prcm = {
948 .omap2 = { 715 .omap2 = {
@@ -955,31 +722,19 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
955 }, 722 },
956 .slaves = omap2430_timer10_slaves, 723 .slaves = omap2430_timer10_slaves,
957 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves), 724 .slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
958 .class = &omap2430_timer_hwmod_class, 725 .class = &omap2xxx_timer_hwmod_class,
959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 726 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
960}; 727};
961 728
962/* timer11 */ 729/* timer11 */
963static struct omap_hwmod omap2430_timer11_hwmod; 730static struct omap_hwmod omap2430_timer11_hwmod;
964static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
965 { .irq = 47, },
966};
967
968static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
969 {
970 .pa_start = 0x48088000,
971 .pa_end = 0x48088000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT
973 },
974};
975 731
976/* l4_core -> timer11 */ 732/* l4_core -> timer11 */
977static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = { 733static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
978 .master = &omap2430_l4_core_hwmod, 734 .master = &omap2430_l4_core_hwmod,
979 .slave = &omap2430_timer11_hwmod, 735 .slave = &omap2430_timer11_hwmod,
980 .clk = "gpt11_ick", 736 .clk = "gpt11_ick",
981 .addr = omap2430_timer11_addrs, 737 .addr = omap2_timer11_addrs,
982 .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA, 738 .user = OCP_USER_MPU | OCP_USER_SDMA,
984}; 739};
985 740
@@ -991,8 +746,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
991/* timer11 hwmod */ 746/* timer11 hwmod */
992static struct omap_hwmod omap2430_timer11_hwmod = { 747static struct omap_hwmod omap2430_timer11_hwmod = {
993 .name = "timer11", 748 .name = "timer11",
994 .mpu_irqs = omap2430_timer11_mpu_irqs, 749 .mpu_irqs = omap2_timer11_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
996 .main_clk = "gpt11_fck", 750 .main_clk = "gpt11_fck",
997 .prcm = { 751 .prcm = {
998 .omap2 = { 752 .omap2 = {
@@ -1005,31 +759,19 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
1005 }, 759 },
1006 .slaves = omap2430_timer11_slaves, 760 .slaves = omap2430_timer11_slaves,
1007 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves), 761 .slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
1008 .class = &omap2430_timer_hwmod_class, 762 .class = &omap2xxx_timer_hwmod_class,
1009 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 763 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1010}; 764};
1011 765
1012/* timer12 */ 766/* timer12 */
1013static struct omap_hwmod omap2430_timer12_hwmod; 767static struct omap_hwmod omap2430_timer12_hwmod;
1014static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
1015 { .irq = 48, },
1016};
1017
1018static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
1019 {
1020 .pa_start = 0x4808a000,
1021 .pa_end = 0x4808a000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT
1023 },
1024};
1025 768
1026/* l4_core -> timer12 */ 769/* l4_core -> timer12 */
1027static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = { 770static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
1028 .master = &omap2430_l4_core_hwmod, 771 .master = &omap2430_l4_core_hwmod,
1029 .slave = &omap2430_timer12_hwmod, 772 .slave = &omap2430_timer12_hwmod,
1030 .clk = "gpt12_ick", 773 .clk = "gpt12_ick",
1031 .addr = omap2430_timer12_addrs, 774 .addr = omap2xxx_timer12_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA, 775 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034}; 776};
1035 777
@@ -1041,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
1041/* timer12 hwmod */ 783/* timer12 hwmod */
1042static struct omap_hwmod omap2430_timer12_hwmod = { 784static struct omap_hwmod omap2430_timer12_hwmod = {
1043 .name = "timer12", 785 .name = "timer12",
1044 .mpu_irqs = omap2430_timer12_mpu_irqs, 786 .mpu_irqs = omap2xxx_timer12_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
1046 .main_clk = "gpt12_fck", 787 .main_clk = "gpt12_fck",
1047 .prcm = { 788 .prcm = {
1048 .omap2 = { 789 .omap2 = {
@@ -1055,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
1055 }, 796 },
1056 .slaves = omap2430_timer12_slaves, 797 .slaves = omap2430_timer12_slaves,
1057 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves), 798 .slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
1058 .class = &omap2430_timer_hwmod_class, 799 .class = &omap2xxx_timer_hwmod_class,
1059 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
1060}; 801};
1061 802
@@ -1066,6 +807,7 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
1066 .pa_end = 0x4901607f, 807 .pa_end = 0x4901607f,
1067 .flags = ADDR_TYPE_RT 808 .flags = ADDR_TYPE_RT
1068 }, 809 },
810 { }
1069}; 811};
1070 812
1071static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { 813static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
@@ -1073,31 +815,9 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
1073 .slave = &omap2430_wd_timer2_hwmod, 815 .slave = &omap2430_wd_timer2_hwmod,
1074 .clk = "mpu_wdt_ick", 816 .clk = "mpu_wdt_ick",
1075 .addr = omap2430_wd_timer2_addrs, 817 .addr = omap2430_wd_timer2_addrs,
1076 .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
1077 .user = OCP_USER_MPU | OCP_USER_SDMA, 818 .user = OCP_USER_MPU | OCP_USER_SDMA,
1078}; 819};
1079 820
1080/*
1081 * 'wd_timer' class
1082 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1083 * overflow condition
1084 */
1085
1086static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
1087 .rev_offs = 0x0,
1088 .sysc_offs = 0x0010,
1089 .syss_offs = 0x0014,
1090 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
1091 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1092 .sysc_fields = &omap_hwmod_sysc_type1,
1093};
1094
1095static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
1096 .name = "wd_timer",
1097 .sysc = &omap2430_wd_timer_sysc,
1098 .pre_shutdown = &omap2_wd_timer_disable
1099};
1100
1101/* wd_timer2 */ 821/* wd_timer2 */
1102static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = { 822static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1103 &omap2430_l4_wkup__wd_timer2, 823 &omap2430_l4_wkup__wd_timer2,
@@ -1105,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
1105 825
1106static struct omap_hwmod omap2430_wd_timer2_hwmod = { 826static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1107 .name = "wd_timer2", 827 .name = "wd_timer2",
1108 .class = &omap2430_wd_timer_hwmod_class, 828 .class = &omap2xxx_wd_timer_hwmod_class,
1109 .main_clk = "mpu_wdt_fck", 829 .main_clk = "mpu_wdt_fck",
1110 .prcm = { 830 .prcm = {
1111 .omap2 = { 831 .omap2 = {
@@ -1121,45 +841,16 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
1121 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 841 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1122}; 842};
1123 843
1124/* UART */
1125
1126static struct omap_hwmod_class_sysconfig uart_sysc = {
1127 .rev_offs = 0x50,
1128 .sysc_offs = 0x54,
1129 .syss_offs = 0x58,
1130 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1131 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1132 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1133 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1134 .sysc_fields = &omap_hwmod_sysc_type1,
1135};
1136
1137static struct omap_hwmod_class uart_class = {
1138 .name = "uart",
1139 .sysc = &uart_sysc,
1140};
1141
1142/* UART1 */ 844/* UART1 */
1143 845
1144static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1145 { .irq = INT_24XX_UART1_IRQ, },
1146};
1147
1148static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1149 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1150 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1151};
1152
1153static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = { 846static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
1154 &omap2_l4_core__uart1, 847 &omap2_l4_core__uart1,
1155}; 848};
1156 849
1157static struct omap_hwmod omap2430_uart1_hwmod = { 850static struct omap_hwmod omap2430_uart1_hwmod = {
1158 .name = "uart1", 851 .name = "uart1",
1159 .mpu_irqs = uart1_mpu_irqs, 852 .mpu_irqs = omap2_uart1_mpu_irqs,
1160 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 853 .sdma_reqs = omap2_uart1_sdma_reqs,
1161 .sdma_reqs = uart1_sdma_reqs,
1162 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1163 .main_clk = "uart1_fck", 854 .main_clk = "uart1_fck",
1164 .prcm = { 855 .prcm = {
1165 .omap2 = { 856 .omap2 = {
@@ -1172,31 +863,20 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
1172 }, 863 },
1173 .slaves = omap2430_uart1_slaves, 864 .slaves = omap2430_uart1_slaves,
1174 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves), 865 .slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
1175 .class = &uart_class, 866 .class = &omap2_uart_class,
1176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 867 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1177}; 868};
1178 869
1179/* UART2 */ 870/* UART2 */
1180 871
1181static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1182 { .irq = INT_24XX_UART2_IRQ, },
1183};
1184
1185static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1186 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1187 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1188};
1189
1190static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = { 872static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
1191 &omap2_l4_core__uart2, 873 &omap2_l4_core__uart2,
1192}; 874};
1193 875
1194static struct omap_hwmod omap2430_uart2_hwmod = { 876static struct omap_hwmod omap2430_uart2_hwmod = {
1195 .name = "uart2", 877 .name = "uart2",
1196 .mpu_irqs = uart2_mpu_irqs, 878 .mpu_irqs = omap2_uart2_mpu_irqs,
1197 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 879 .sdma_reqs = omap2_uart2_sdma_reqs,
1198 .sdma_reqs = uart2_sdma_reqs,
1199 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1200 .main_clk = "uart2_fck", 880 .main_clk = "uart2_fck",
1201 .prcm = { 881 .prcm = {
1202 .omap2 = { 882 .omap2 = {
@@ -1209,31 +889,20 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
1209 }, 889 },
1210 .slaves = omap2430_uart2_slaves, 890 .slaves = omap2430_uart2_slaves,
1211 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves), 891 .slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
1212 .class = &uart_class, 892 .class = &omap2_uart_class,
1213 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 893 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1214}; 894};
1215 895
1216/* UART3 */ 896/* UART3 */
1217 897
1218static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1219 { .irq = INT_24XX_UART3_IRQ, },
1220};
1221
1222static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1223 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1224 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1225};
1226
1227static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = { 898static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
1228 &omap2_l4_core__uart3, 899 &omap2_l4_core__uart3,
1229}; 900};
1230 901
1231static struct omap_hwmod omap2430_uart3_hwmod = { 902static struct omap_hwmod omap2430_uart3_hwmod = {
1232 .name = "uart3", 903 .name = "uart3",
1233 .mpu_irqs = uart3_mpu_irqs, 904 .mpu_irqs = omap2_uart3_mpu_irqs,
1234 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 905 .sdma_reqs = omap2_uart3_sdma_reqs,
1235 .sdma_reqs = uart3_sdma_reqs,
1236 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1237 .main_clk = "uart3_fck", 906 .main_clk = "uart3_fck",
1238 .prcm = { 907 .prcm = {
1239 .omap2 = { 908 .omap2 = {
@@ -1246,53 +915,22 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
1246 }, 915 },
1247 .slaves = omap2430_uart3_slaves, 916 .slaves = omap2430_uart3_slaves,
1248 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves), 917 .slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
1249 .class = &uart_class, 918 .class = &omap2_uart_class,
1250 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 919 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1251}; 920};
1252 921
1253/*
1254 * 'dss' class
1255 * display sub-system
1256 */
1257
1258static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
1259 .rev_offs = 0x0000,
1260 .sysc_offs = 0x0010,
1261 .syss_offs = 0x0014,
1262 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1263 .sysc_fields = &omap_hwmod_sysc_type1,
1264};
1265
1266static struct omap_hwmod_class omap2430_dss_hwmod_class = {
1267 .name = "dss",
1268 .sysc = &omap2430_dss_sysc,
1269};
1270
1271static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
1272 { .name = "dispc", .dma_req = 5 },
1273};
1274
1275/* dss */ 922/* dss */
1276/* dss master ports */ 923/* dss master ports */
1277static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = { 924static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
1278 &omap2430_dss__l3, 925 &omap2430_dss__l3,
1279}; 926};
1280 927
1281static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
1282 {
1283 .pa_start = 0x48050000,
1284 .pa_end = 0x480503FF,
1285 .flags = ADDR_TYPE_RT
1286 },
1287};
1288
1289/* l4_core -> dss */ 928/* l4_core -> dss */
1290static struct omap_hwmod_ocp_if omap2430_l4_core__dss = { 929static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
1291 .master = &omap2430_l4_core_hwmod, 930 .master = &omap2430_l4_core_hwmod,
1292 .slave = &omap2430_dss_core_hwmod, 931 .slave = &omap2430_dss_core_hwmod,
1293 .clk = "dss_ick", 932 .clk = "dss_ick",
1294 .addr = omap2430_dss_addrs, 933 .addr = omap2_dss_addrs,
1295 .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
1296 .user = OCP_USER_MPU | OCP_USER_SDMA, 934 .user = OCP_USER_MPU | OCP_USER_SDMA,
1297}; 935};
1298 936
@@ -1308,10 +946,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1308 946
1309static struct omap_hwmod omap2430_dss_core_hwmod = { 947static struct omap_hwmod omap2430_dss_core_hwmod = {
1310 .name = "dss_core", 948 .name = "dss_core",
1311 .class = &omap2430_dss_hwmod_class, 949 .class = &omap2_dss_hwmod_class,
1312 .main_clk = "dss1_fck", /* instead of dss_fck */ 950 .main_clk = "dss1_fck", /* instead of dss_fck */
1313 .sdma_reqs = omap2430_dss_sdma_chs, 951 .sdma_reqs = omap2xxx_dss_sdma_chs,
1314 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
1315 .prcm = { 952 .prcm = {
1316 .omap2 = { 953 .omap2 = {
1317 .prcm_reg_id = 1, 954 .prcm_reg_id = 1,
@@ -1331,46 +968,12 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
1331 .flags = HWMOD_NO_IDLEST, 968 .flags = HWMOD_NO_IDLEST,
1332}; 969};
1333 970
1334/*
1335 * 'dispc' class
1336 * display controller
1337 */
1338
1339static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
1340 .rev_offs = 0x0000,
1341 .sysc_offs = 0x0010,
1342 .syss_offs = 0x0014,
1343 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1344 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1345 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1346 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1347 .sysc_fields = &omap_hwmod_sysc_type1,
1348};
1349
1350static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
1351 .name = "dispc",
1352 .sysc = &omap2430_dispc_sysc,
1353};
1354
1355static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
1356 { .irq = 25 },
1357};
1358
1359static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
1360 {
1361 .pa_start = 0x48050400,
1362 .pa_end = 0x480507FF,
1363 .flags = ADDR_TYPE_RT
1364 },
1365};
1366
1367/* l4_core -> dss_dispc */ 971/* l4_core -> dss_dispc */
1368static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = { 972static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
1369 .master = &omap2430_l4_core_hwmod, 973 .master = &omap2430_l4_core_hwmod,
1370 .slave = &omap2430_dss_dispc_hwmod, 974 .slave = &omap2430_dss_dispc_hwmod,
1371 .clk = "dss_ick", 975 .clk = "dss_ick",
1372 .addr = omap2430_dss_dispc_addrs, 976 .addr = omap2_dss_dispc_addrs,
1373 .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
1374 .user = OCP_USER_MPU | OCP_USER_SDMA, 977 .user = OCP_USER_MPU | OCP_USER_SDMA,
1375}; 978};
1376 979
@@ -1381,9 +984,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
1381 984
1382static struct omap_hwmod omap2430_dss_dispc_hwmod = { 985static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1383 .name = "dss_dispc", 986 .name = "dss_dispc",
1384 .class = &omap2430_dispc_hwmod_class, 987 .class = &omap2_dispc_hwmod_class,
1385 .mpu_irqs = omap2430_dispc_irqs, 988 .mpu_irqs = omap2_dispc_irqs,
1386 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs),
1387 .main_clk = "dss1_fck", 989 .main_clk = "dss1_fck",
1388 .prcm = { 990 .prcm = {
1389 .omap2 = { 991 .omap2 = {
@@ -1400,41 +1002,12 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
1400 .flags = HWMOD_NO_IDLEST, 1002 .flags = HWMOD_NO_IDLEST,
1401}; 1003};
1402 1004
1403/*
1404 * 'rfbi' class
1405 * remote frame buffer interface
1406 */
1407
1408static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
1409 .rev_offs = 0x0000,
1410 .sysc_offs = 0x0010,
1411 .syss_offs = 0x0014,
1412 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1413 SYSC_HAS_AUTOIDLE),
1414 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1415 .sysc_fields = &omap_hwmod_sysc_type1,
1416};
1417
1418static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
1419 .name = "rfbi",
1420 .sysc = &omap2430_rfbi_sysc,
1421};
1422
1423static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
1424 {
1425 .pa_start = 0x48050800,
1426 .pa_end = 0x48050BFF,
1427 .flags = ADDR_TYPE_RT
1428 },
1429};
1430
1431/* l4_core -> dss_rfbi */ 1005/* l4_core -> dss_rfbi */
1432static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = { 1006static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
1433 .master = &omap2430_l4_core_hwmod, 1007 .master = &omap2430_l4_core_hwmod,
1434 .slave = &omap2430_dss_rfbi_hwmod, 1008 .slave = &omap2430_dss_rfbi_hwmod,
1435 .clk = "dss_ick", 1009 .clk = "dss_ick",
1436 .addr = omap2430_dss_rfbi_addrs, 1010 .addr = omap2_dss_rfbi_addrs,
1437 .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
1438 .user = OCP_USER_MPU | OCP_USER_SDMA, 1011 .user = OCP_USER_MPU | OCP_USER_SDMA,
1439}; 1012};
1440 1013
@@ -1445,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
1445 1018
1446static struct omap_hwmod omap2430_dss_rfbi_hwmod = { 1019static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1447 .name = "dss_rfbi", 1020 .name = "dss_rfbi",
1448 .class = &omap2430_rfbi_hwmod_class, 1021 .class = &omap2_rfbi_hwmod_class,
1449 .main_clk = "dss1_fck", 1022 .main_clk = "dss1_fck",
1450 .prcm = { 1023 .prcm = {
1451 .omap2 = { 1024 .omap2 = {
@@ -1460,31 +1033,12 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
1460 .flags = HWMOD_NO_IDLEST, 1033 .flags = HWMOD_NO_IDLEST,
1461}; 1034};
1462 1035
1463/*
1464 * 'venc' class
1465 * video encoder
1466 */
1467
1468static struct omap_hwmod_class omap2430_venc_hwmod_class = {
1469 .name = "venc",
1470};
1471
1472/* dss_venc */
1473static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
1474 {
1475 .pa_start = 0x48050C00,
1476 .pa_end = 0x48050FFF,
1477 .flags = ADDR_TYPE_RT
1478 },
1479};
1480
1481/* l4_core -> dss_venc */ 1036/* l4_core -> dss_venc */
1482static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = { 1037static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
1483 .master = &omap2430_l4_core_hwmod, 1038 .master = &omap2430_l4_core_hwmod,
1484 .slave = &omap2430_dss_venc_hwmod, 1039 .slave = &omap2430_dss_venc_hwmod,
1485 .clk = "dss_54m_fck", 1040 .clk = "dss_54m_fck",
1486 .addr = omap2430_dss_venc_addrs, 1041 .addr = omap2_dss_venc_addrs,
1487 .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
1488 .flags = OCPIF_SWSUP_IDLE, 1042 .flags = OCPIF_SWSUP_IDLE,
1489 .user = OCP_USER_MPU | OCP_USER_SDMA, 1043 .user = OCP_USER_MPU | OCP_USER_SDMA,
1490}; 1044};
@@ -1496,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
1496 1050
1497static struct omap_hwmod omap2430_dss_venc_hwmod = { 1051static struct omap_hwmod omap2430_dss_venc_hwmod = {
1498 .name = "dss_venc", 1052 .name = "dss_venc",
1499 .class = &omap2430_venc_hwmod_class, 1053 .class = &omap2_venc_hwmod_class,
1500 .main_clk = "dss1_fck", 1054 .main_clk = "dss1_fck",
1501 .prcm = { 1055 .prcm = {
1502 .omap2 = { 1056 .omap2 = {
@@ -1532,25 +1086,14 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
1532 1086
1533/* I2C1 */ 1087/* I2C1 */
1534 1088
1535static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1536 { .irq = INT_24XX_I2C1_IRQ, },
1537};
1538
1539static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1540 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1541 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1542};
1543
1544static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { 1089static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
1545 &omap2430_l4_core__i2c1, 1090 &omap2430_l4_core__i2c1,
1546}; 1091};
1547 1092
1548static struct omap_hwmod omap2430_i2c1_hwmod = { 1093static struct omap_hwmod omap2430_i2c1_hwmod = {
1549 .name = "i2c1", 1094 .name = "i2c1",
1550 .mpu_irqs = i2c1_mpu_irqs, 1095 .mpu_irqs = omap2_i2c1_mpu_irqs,
1551 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1096 .sdma_reqs = omap2_i2c1_sdma_reqs,
1552 .sdma_reqs = i2c1_sdma_reqs,
1553 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1554 .main_clk = "i2chs1_fck", 1097 .main_clk = "i2chs1_fck",
1555 .prcm = { 1098 .prcm = {
1556 .omap2 = { 1099 .omap2 = {
@@ -1578,25 +1121,14 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
1578 1121
1579/* I2C2 */ 1122/* I2C2 */
1580 1123
1581static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1582 { .irq = INT_24XX_I2C2_IRQ, },
1583};
1584
1585static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1586 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1587 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1588};
1589
1590static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { 1124static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
1591 &omap2430_l4_core__i2c2, 1125 &omap2430_l4_core__i2c2,
1592}; 1126};
1593 1127
1594static struct omap_hwmod omap2430_i2c2_hwmod = { 1128static struct omap_hwmod omap2430_i2c2_hwmod = {
1595 .name = "i2c2", 1129 .name = "i2c2",
1596 .mpu_irqs = i2c2_mpu_irqs, 1130 .mpu_irqs = omap2_i2c2_mpu_irqs,
1597 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1131 .sdma_reqs = omap2_i2c2_sdma_reqs,
1598 .sdma_reqs = i2c2_sdma_reqs,
1599 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1600 .main_clk = "i2chs2_fck", 1132 .main_clk = "i2chs2_fck",
1601 .prcm = { 1133 .prcm = {
1602 .omap2 = { 1134 .omap2 = {
@@ -1621,6 +1153,7 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
1621 .pa_end = 0x4900C1ff, 1153 .pa_end = 0x4900C1ff,
1622 .flags = ADDR_TYPE_RT 1154 .flags = ADDR_TYPE_RT
1623 }, 1155 },
1156 { }
1624}; 1157};
1625 1158
1626static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { 1159static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
@@ -1628,7 +1161,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
1628 .slave = &omap2430_gpio1_hwmod, 1161 .slave = &omap2430_gpio1_hwmod,
1629 .clk = "gpios_ick", 1162 .clk = "gpios_ick",
1630 .addr = omap2430_gpio1_addr_space, 1163 .addr = omap2430_gpio1_addr_space,
1631 .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
1632 .user = OCP_USER_MPU | OCP_USER_SDMA, 1164 .user = OCP_USER_MPU | OCP_USER_SDMA,
1633}; 1165};
1634 1166
@@ -1639,6 +1171,7 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
1639 .pa_end = 0x4900E1ff, 1171 .pa_end = 0x4900E1ff,
1640 .flags = ADDR_TYPE_RT 1172 .flags = ADDR_TYPE_RT
1641 }, 1173 },
1174 { }
1642}; 1175};
1643 1176
1644static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { 1177static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
@@ -1646,7 +1179,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
1646 .slave = &omap2430_gpio2_hwmod, 1179 .slave = &omap2430_gpio2_hwmod,
1647 .clk = "gpios_ick", 1180 .clk = "gpios_ick",
1648 .addr = omap2430_gpio2_addr_space, 1181 .addr = omap2430_gpio2_addr_space,
1649 .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
1650 .user = OCP_USER_MPU | OCP_USER_SDMA, 1182 .user = OCP_USER_MPU | OCP_USER_SDMA,
1651}; 1183};
1652 1184
@@ -1657,6 +1189,7 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
1657 .pa_end = 0x490101ff, 1189 .pa_end = 0x490101ff,
1658 .flags = ADDR_TYPE_RT 1190 .flags = ADDR_TYPE_RT
1659 }, 1191 },
1192 { }
1660}; 1193};
1661 1194
1662static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { 1195static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
@@ -1664,7 +1197,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
1664 .slave = &omap2430_gpio3_hwmod, 1197 .slave = &omap2430_gpio3_hwmod,
1665 .clk = "gpios_ick", 1198 .clk = "gpios_ick",
1666 .addr = omap2430_gpio3_addr_space, 1199 .addr = omap2430_gpio3_addr_space,
1667 .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
1668 .user = OCP_USER_MPU | OCP_USER_SDMA, 1200 .user = OCP_USER_MPU | OCP_USER_SDMA,
1669}; 1201};
1670 1202
@@ -1675,6 +1207,7 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
1675 .pa_end = 0x490121ff, 1207 .pa_end = 0x490121ff,
1676 .flags = ADDR_TYPE_RT 1208 .flags = ADDR_TYPE_RT
1677 }, 1209 },
1210 { }
1678}; 1211};
1679 1212
1680static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { 1213static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
@@ -1682,7 +1215,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
1682 .slave = &omap2430_gpio4_hwmod, 1215 .slave = &omap2430_gpio4_hwmod,
1683 .clk = "gpios_ick", 1216 .clk = "gpios_ick",
1684 .addr = omap2430_gpio4_addr_space, 1217 .addr = omap2430_gpio4_addr_space,
1685 .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
1686 .user = OCP_USER_MPU | OCP_USER_SDMA, 1218 .user = OCP_USER_MPU | OCP_USER_SDMA,
1687}; 1219};
1688 1220
@@ -1693,6 +1225,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
1693 .pa_end = 0x480B61ff, 1225 .pa_end = 0x480B61ff,
1694 .flags = ADDR_TYPE_RT 1226 .flags = ADDR_TYPE_RT
1695 }, 1227 },
1228 { }
1696}; 1229};
1697 1230
1698static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { 1231static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
@@ -1700,7 +1233,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
1700 .slave = &omap2430_gpio5_hwmod, 1233 .slave = &omap2430_gpio5_hwmod,
1701 .clk = "gpio5_ick", 1234 .clk = "gpio5_ick",
1702 .addr = omap2430_gpio5_addr_space, 1235 .addr = omap2430_gpio5_addr_space,
1703 .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
1704 .user = OCP_USER_MPU | OCP_USER_SDMA, 1236 .user = OCP_USER_MPU | OCP_USER_SDMA,
1705}; 1237};
1706 1238
@@ -1710,32 +1242,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1710 .dbck_flag = false, 1242 .dbck_flag = false,
1711}; 1243};
1712 1244
1713static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
1714 .rev_offs = 0x0000,
1715 .sysc_offs = 0x0010,
1716 .syss_offs = 0x0014,
1717 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1718 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1719 SYSS_HAS_RESET_STATUS),
1720 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1721 .sysc_fields = &omap_hwmod_sysc_type1,
1722};
1723
1724/*
1725 * 'gpio' class
1726 * general purpose io module
1727 */
1728static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
1729 .name = "gpio",
1730 .sysc = &omap243x_gpio_sysc,
1731 .rev = 0,
1732};
1733
1734/* gpio1 */ 1245/* gpio1 */
1735static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
1736 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
1737};
1738
1739static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = { 1246static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1740 &omap2430_l4_wkup__gpio1, 1247 &omap2430_l4_wkup__gpio1,
1741}; 1248};
@@ -1743,8 +1250,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
1743static struct omap_hwmod omap2430_gpio1_hwmod = { 1250static struct omap_hwmod omap2430_gpio1_hwmod = {
1744 .name = "gpio1", 1251 .name = "gpio1",
1745 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1252 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1746 .mpu_irqs = omap243x_gpio1_irqs, 1253 .mpu_irqs = omap2_gpio1_irqs,
1747 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
1748 .main_clk = "gpios_fck", 1254 .main_clk = "gpios_fck",
1749 .prcm = { 1255 .prcm = {
1750 .omap2 = { 1256 .omap2 = {
@@ -1757,16 +1263,12 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
1757 }, 1263 },
1758 .slaves = omap2430_gpio1_slaves, 1264 .slaves = omap2430_gpio1_slaves,
1759 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves), 1265 .slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
1760 .class = &omap243x_gpio_hwmod_class, 1266 .class = &omap2xxx_gpio_hwmod_class,
1761 .dev_attr = &gpio_dev_attr, 1267 .dev_attr = &gpio_dev_attr,
1762 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1763}; 1269};
1764 1270
1765/* gpio2 */ 1271/* gpio2 */
1766static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
1767 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
1768};
1769
1770static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = { 1272static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1771 &omap2430_l4_wkup__gpio2, 1273 &omap2430_l4_wkup__gpio2,
1772}; 1274};
@@ -1774,8 +1276,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
1774static struct omap_hwmod omap2430_gpio2_hwmod = { 1276static struct omap_hwmod omap2430_gpio2_hwmod = {
1775 .name = "gpio2", 1277 .name = "gpio2",
1776 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1278 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1777 .mpu_irqs = omap243x_gpio2_irqs, 1279 .mpu_irqs = omap2_gpio2_irqs,
1778 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
1779 .main_clk = "gpios_fck", 1280 .main_clk = "gpios_fck",
1780 .prcm = { 1281 .prcm = {
1781 .omap2 = { 1282 .omap2 = {
@@ -1788,16 +1289,12 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
1788 }, 1289 },
1789 .slaves = omap2430_gpio2_slaves, 1290 .slaves = omap2430_gpio2_slaves,
1790 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves), 1291 .slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
1791 .class = &omap243x_gpio_hwmod_class, 1292 .class = &omap2xxx_gpio_hwmod_class,
1792 .dev_attr = &gpio_dev_attr, 1293 .dev_attr = &gpio_dev_attr,
1793 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1294 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1794}; 1295};
1795 1296
1796/* gpio3 */ 1297/* gpio3 */
1797static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
1798 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
1799};
1800
1801static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = { 1298static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1802 &omap2430_l4_wkup__gpio3, 1299 &omap2430_l4_wkup__gpio3,
1803}; 1300};
@@ -1805,8 +1302,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
1805static struct omap_hwmod omap2430_gpio3_hwmod = { 1302static struct omap_hwmod omap2430_gpio3_hwmod = {
1806 .name = "gpio3", 1303 .name = "gpio3",
1807 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1304 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1808 .mpu_irqs = omap243x_gpio3_irqs, 1305 .mpu_irqs = omap2_gpio3_irqs,
1809 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
1810 .main_clk = "gpios_fck", 1306 .main_clk = "gpios_fck",
1811 .prcm = { 1307 .prcm = {
1812 .omap2 = { 1308 .omap2 = {
@@ -1819,16 +1315,12 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
1819 }, 1315 },
1820 .slaves = omap2430_gpio3_slaves, 1316 .slaves = omap2430_gpio3_slaves,
1821 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves), 1317 .slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
1822 .class = &omap243x_gpio_hwmod_class, 1318 .class = &omap2xxx_gpio_hwmod_class,
1823 .dev_attr = &gpio_dev_attr, 1319 .dev_attr = &gpio_dev_attr,
1824 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1320 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1825}; 1321};
1826 1322
1827/* gpio4 */ 1323/* gpio4 */
1828static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
1829 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
1830};
1831
1832static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = { 1324static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1833 &omap2430_l4_wkup__gpio4, 1325 &omap2430_l4_wkup__gpio4,
1834}; 1326};
@@ -1836,8 +1328,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
1836static struct omap_hwmod omap2430_gpio4_hwmod = { 1328static struct omap_hwmod omap2430_gpio4_hwmod = {
1837 .name = "gpio4", 1329 .name = "gpio4",
1838 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1330 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1839 .mpu_irqs = omap243x_gpio4_irqs, 1331 .mpu_irqs = omap2_gpio4_irqs,
1840 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
1841 .main_clk = "gpios_fck", 1332 .main_clk = "gpios_fck",
1842 .prcm = { 1333 .prcm = {
1843 .omap2 = { 1334 .omap2 = {
@@ -1850,7 +1341,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
1850 }, 1341 },
1851 .slaves = omap2430_gpio4_slaves, 1342 .slaves = omap2430_gpio4_slaves,
1852 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves), 1343 .slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
1853 .class = &omap243x_gpio_hwmod_class, 1344 .class = &omap2xxx_gpio_hwmod_class,
1854 .dev_attr = &gpio_dev_attr, 1345 .dev_attr = &gpio_dev_attr,
1855 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1856}; 1347};
@@ -1858,6 +1349,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
1858/* gpio5 */ 1349/* gpio5 */
1859static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = { 1350static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
1860 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */ 1351 { .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
1352 { .irq = -1 }
1861}; 1353};
1862 1354
1863static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = { 1355static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
@@ -1868,7 +1360,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
1868 .name = "gpio5", 1360 .name = "gpio5",
1869 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1361 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1870 .mpu_irqs = omap243x_gpio5_irqs, 1362 .mpu_irqs = omap243x_gpio5_irqs,
1871 .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
1872 .main_clk = "gpio5_fck", 1363 .main_clk = "gpio5_fck",
1873 .prcm = { 1364 .prcm = {
1874 .omap2 = { 1365 .omap2 = {
@@ -1881,28 +1372,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
1881 }, 1372 },
1882 .slaves = omap2430_gpio5_slaves, 1373 .slaves = omap2430_gpio5_slaves,
1883 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves), 1374 .slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
1884 .class = &omap243x_gpio_hwmod_class, 1375 .class = &omap2xxx_gpio_hwmod_class,
1885 .dev_attr = &gpio_dev_attr, 1376 .dev_attr = &gpio_dev_attr,
1886 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1377 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
1887}; 1378};
1888 1379
1889/* dma_system */
1890static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
1891 .rev_offs = 0x0000,
1892 .sysc_offs = 0x002c,
1893 .syss_offs = 0x0028,
1894 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1895 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1896 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1897 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1898 .sysc_fields = &omap_hwmod_sysc_type1,
1899};
1900
1901static struct omap_hwmod_class omap2430_dma_hwmod_class = {
1902 .name = "dma",
1903 .sysc = &omap2430_dma_sysc,
1904};
1905
1906/* dma attributes */ 1380/* dma attributes */
1907static struct omap_dma_dev_attr dma_dev_attr = { 1381static struct omap_dma_dev_attr dma_dev_attr = {
1908 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | 1382 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1910,21 +1384,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
1910 .lch_count = 32, 1384 .lch_count = 32,
1911}; 1385};
1912 1386
1913static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
1914 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1915 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1916 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1917 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1918};
1919
1920static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
1921 {
1922 .pa_start = 0x48056000,
1923 .pa_end = 0x48056fff,
1924 .flags = ADDR_TYPE_RT
1925 },
1926};
1927
1928/* dma_system -> L3 */ 1387/* dma_system -> L3 */
1929static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = { 1388static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
1930 .master = &omap2430_dma_system_hwmod, 1389 .master = &omap2430_dma_system_hwmod,
@@ -1943,8 +1402,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
1943 .master = &omap2430_l4_core_hwmod, 1402 .master = &omap2430_l4_core_hwmod,
1944 .slave = &omap2430_dma_system_hwmod, 1403 .slave = &omap2430_dma_system_hwmod,
1945 .clk = "sdma_ick", 1404 .clk = "sdma_ick",
1946 .addr = omap2430_dma_system_addrs, 1405 .addr = omap2_dma_system_addrs,
1947 .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
1948 .user = OCP_USER_MPU | OCP_USER_SDMA, 1406 .user = OCP_USER_MPU | OCP_USER_SDMA,
1949}; 1407};
1950 1408
@@ -1955,9 +1413,8 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
1955 1413
1956static struct omap_hwmod omap2430_dma_system_hwmod = { 1414static struct omap_hwmod omap2430_dma_system_hwmod = {
1957 .name = "dma", 1415 .name = "dma",
1958 .class = &omap2430_dma_hwmod_class, 1416 .class = &omap2xxx_dma_hwmod_class,
1959 .mpu_irqs = omap2430_dma_system_irqs, 1417 .mpu_irqs = omap2_dma_system_irqs,
1960 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
1961 .main_clk = "core_l3_ck", 1418 .main_clk = "core_l3_ck",
1962 .slaves = omap2430_dma_system_slaves, 1419 .slaves = omap2430_dma_system_slaves,
1963 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves), 1420 .slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
@@ -1968,47 +1425,18 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
1968 .flags = HWMOD_NO_IDLEST, 1425 .flags = HWMOD_NO_IDLEST,
1969}; 1426};
1970 1427
1971/*
1972 * 'mailbox' class
1973 * mailbox module allowing communication between the on-chip processors
1974 * using a queued mailbox-interrupt mechanism.
1975 */
1976
1977static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1978 .rev_offs = 0x000,
1979 .sysc_offs = 0x010,
1980 .syss_offs = 0x014,
1981 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1982 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1983 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1984 .sysc_fields = &omap_hwmod_sysc_type1,
1985};
1986
1987static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1988 .name = "mailbox",
1989 .sysc = &omap2430_mailbox_sysc,
1990};
1991
1992/* mailbox */ 1428/* mailbox */
1993static struct omap_hwmod omap2430_mailbox_hwmod; 1429static struct omap_hwmod omap2430_mailbox_hwmod;
1994static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = { 1430static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1995 { .irq = 26 }, 1431 { .irq = 26 },
1996}; 1432 { .irq = -1 }
1997
1998static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1999 {
2000 .pa_start = 0x48094000,
2001 .pa_end = 0x480941ff,
2002 .flags = ADDR_TYPE_RT,
2003 },
2004}; 1433};
2005 1434
2006/* l4_core -> mailbox */ 1435/* l4_core -> mailbox */
2007static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { 1436static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2008 .master = &omap2430_l4_core_hwmod, 1437 .master = &omap2430_l4_core_hwmod,
2009 .slave = &omap2430_mailbox_hwmod, 1438 .slave = &omap2430_mailbox_hwmod,
2010 .addr = omap2430_mailbox_addrs, 1439 .addr = omap2_mailbox_addrs,
2011 .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
2012 .user = OCP_USER_MPU | OCP_USER_SDMA, 1440 .user = OCP_USER_MPU | OCP_USER_SDMA,
2013}; 1441};
2014 1442
@@ -2019,9 +1447,8 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2019 1447
2020static struct omap_hwmod omap2430_mailbox_hwmod = { 1448static struct omap_hwmod omap2430_mailbox_hwmod = {
2021 .name = "mailbox", 1449 .name = "mailbox",
2022 .class = &omap2430_mailbox_hwmod_class, 1450 .class = &omap2xxx_mailbox_hwmod_class,
2023 .mpu_irqs = omap2430_mailbox_irqs, 1451 .mpu_irqs = omap2430_mailbox_irqs,
2024 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
2025 .main_clk = "mailboxes_ick", 1452 .main_clk = "mailboxes_ick",
2026 .prcm = { 1453 .prcm = {
2027 .omap2 = { 1454 .omap2 = {
@@ -2037,45 +1464,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
2037 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1464 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2038}; 1465};
2039 1466
2040/*
2041 * 'mcspi' class
2042 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2043 * bus
2044 */
2045
2046static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
2047 .rev_offs = 0x0000,
2048 .sysc_offs = 0x0010,
2049 .syss_offs = 0x0014,
2050 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2051 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2052 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2053 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2054 .sysc_fields = &omap_hwmod_sysc_type1,
2055};
2056
2057static struct omap_hwmod_class omap2430_mcspi_class = {
2058 .name = "mcspi",
2059 .sysc = &omap2430_mcspi_sysc,
2060 .rev = OMAP2_MCSPI_REV,
2061};
2062
2063/* mcspi1 */ 1467/* mcspi1 */
2064static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
2065 { .irq = 65 },
2066};
2067
2068static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
2069 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
2070 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
2071 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
2072 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
2073 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
2074 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
2075 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
2076 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
2077};
2078
2079static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = { 1468static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
2080 &omap2430_l4_core__mcspi1, 1469 &omap2430_l4_core__mcspi1,
2081}; 1470};
@@ -2086,10 +1475,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2086 1475
2087static struct omap_hwmod omap2430_mcspi1_hwmod = { 1476static struct omap_hwmod omap2430_mcspi1_hwmod = {
2088 .name = "mcspi1_hwmod", 1477 .name = "mcspi1_hwmod",
2089 .mpu_irqs = omap2430_mcspi1_mpu_irqs, 1478 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2090 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs), 1479 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2091 .sdma_reqs = omap2430_mcspi1_sdma_reqs,
2092 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
2093 .main_clk = "mcspi1_fck", 1480 .main_clk = "mcspi1_fck",
2094 .prcm = { 1481 .prcm = {
2095 .omap2 = { 1482 .omap2 = {
@@ -2102,23 +1489,12 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
2102 }, 1489 },
2103 .slaves = omap2430_mcspi1_slaves, 1490 .slaves = omap2430_mcspi1_slaves,
2104 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves), 1491 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
2105 .class = &omap2430_mcspi_class, 1492 .class = &omap2xxx_mcspi_class,
2106 .dev_attr = &omap_mcspi1_dev_attr, 1493 .dev_attr = &omap_mcspi1_dev_attr,
2107 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1494 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2108}; 1495};
2109 1496
2110/* mcspi2 */ 1497/* mcspi2 */
2111static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
2112 { .irq = 66 },
2113};
2114
2115static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
2116 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
2117 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
2118 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
2119 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
2120};
2121
2122static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = { 1498static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
2123 &omap2430_l4_core__mcspi2, 1499 &omap2430_l4_core__mcspi2,
2124}; 1500};
@@ -2129,10 +1505,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2129 1505
2130static struct omap_hwmod omap2430_mcspi2_hwmod = { 1506static struct omap_hwmod omap2430_mcspi2_hwmod = {
2131 .name = "mcspi2_hwmod", 1507 .name = "mcspi2_hwmod",
2132 .mpu_irqs = omap2430_mcspi2_mpu_irqs, 1508 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2133 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs), 1509 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2134 .sdma_reqs = omap2430_mcspi2_sdma_reqs,
2135 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
2136 .main_clk = "mcspi2_fck", 1510 .main_clk = "mcspi2_fck",
2137 .prcm = { 1511 .prcm = {
2138 .omap2 = { 1512 .omap2 = {
@@ -2145,14 +1519,15 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
2145 }, 1519 },
2146 .slaves = omap2430_mcspi2_slaves, 1520 .slaves = omap2430_mcspi2_slaves,
2147 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves), 1521 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
2148 .class = &omap2430_mcspi_class, 1522 .class = &omap2xxx_mcspi_class,
2149 .dev_attr = &omap_mcspi2_dev_attr, 1523 .dev_attr = &omap_mcspi2_dev_attr,
2150 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1524 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2151}; 1525};
2152 1526
2153/* mcspi3 */ 1527/* mcspi3 */
2154static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = { 1528static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
2155 { .irq = 91 }, 1529 { .irq = 91 },
1530 { .irq = -1 }
2156}; 1531};
2157 1532
2158static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = { 1533static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
@@ -2160,6 +1535,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
2160 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */ 1535 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
2161 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */ 1536 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
2162 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */ 1537 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
1538 { .dma_req = -1 }
2163}; 1539};
2164 1540
2165static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = { 1541static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
@@ -2173,9 +1549,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2173static struct omap_hwmod omap2430_mcspi3_hwmod = { 1549static struct omap_hwmod omap2430_mcspi3_hwmod = {
2174 .name = "mcspi3_hwmod", 1550 .name = "mcspi3_hwmod",
2175 .mpu_irqs = omap2430_mcspi3_mpu_irqs, 1551 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
2176 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
2177 .sdma_reqs = omap2430_mcspi3_sdma_reqs, 1552 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
2178 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
2179 .main_clk = "mcspi3_fck", 1553 .main_clk = "mcspi3_fck",
2180 .prcm = { 1554 .prcm = {
2181 .omap2 = { 1555 .omap2 = {
@@ -2188,8 +1562,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
2188 }, 1562 },
2189 .slaves = omap2430_mcspi3_slaves, 1563 .slaves = omap2430_mcspi3_slaves,
2190 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves), 1564 .slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
2191 .class = &omap2430_mcspi_class, 1565 .class = &omap2xxx_mcspi_class,
2192 .dev_attr = &omap_mcspi3_dev_attr, 1566 .dev_attr = &omap_mcspi3_dev_attr,
2193 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), 1567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2194}; 1568};
2195 1569
@@ -2218,12 +1592,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
2218 1592
2219 { .name = "mc", .irq = 92 }, 1593 { .name = "mc", .irq = 92 },
2220 { .name = "dma", .irq = 93 }, 1594 { .name = "dma", .irq = 93 },
1595 { .irq = -1 }
2221}; 1596};
2222 1597
2223static struct omap_hwmod omap2430_usbhsotg_hwmod = { 1598static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2224 .name = "usb_otg_hs", 1599 .name = "usb_otg_hs",
2225 .mpu_irqs = omap2430_usbhsotg_mpu_irqs, 1600 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
2226 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
2227 .main_clk = "usbhs_ick", 1601 .main_clk = "usbhs_ick",
2228 .prcm = { 1602 .prcm = {
2229 .omap2 = { 1603 .omap2 = {
@@ -2273,20 +1647,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2273 { .name = "rx", .irq = 60 }, 1647 { .name = "rx", .irq = 60 },
2274 { .name = "ovr", .irq = 61 }, 1648 { .name = "ovr", .irq = 61 },
2275 { .name = "common", .irq = 64 }, 1649 { .name = "common", .irq = 64 },
2276}; 1650 { .irq = -1 }
2277
2278static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2279 { .name = "rx", .dma_req = 32 },
2280 { .name = "tx", .dma_req = 31 },
2281};
2282
2283static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2284 {
2285 .name = "mpu",
2286 .pa_start = 0x48074000,
2287 .pa_end = 0x480740ff,
2288 .flags = ADDR_TYPE_RT
2289 },
2290}; 1651};
2291 1652
2292/* l4_core -> mcbsp1 */ 1653/* l4_core -> mcbsp1 */
@@ -2294,8 +1655,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2294 .master = &omap2430_l4_core_hwmod, 1655 .master = &omap2430_l4_core_hwmod,
2295 .slave = &omap2430_mcbsp1_hwmod, 1656 .slave = &omap2430_mcbsp1_hwmod,
2296 .clk = "mcbsp1_ick", 1657 .clk = "mcbsp1_ick",
2297 .addr = omap2430_mcbsp1_addrs, 1658 .addr = omap2_mcbsp1_addrs,
2298 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
2299 .user = OCP_USER_MPU | OCP_USER_SDMA, 1659 .user = OCP_USER_MPU | OCP_USER_SDMA,
2300}; 1660};
2301 1661
@@ -2308,9 +1668,7 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2308 .name = "mcbsp1", 1668 .name = "mcbsp1",
2309 .class = &omap2430_mcbsp_hwmod_class, 1669 .class = &omap2430_mcbsp_hwmod_class,
2310 .mpu_irqs = omap2430_mcbsp1_irqs, 1670 .mpu_irqs = omap2430_mcbsp1_irqs,
2311 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs), 1671 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2312 .sdma_reqs = omap2430_mcbsp1_sdma_chs,
2313 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2314 .main_clk = "mcbsp1_fck", 1672 .main_clk = "mcbsp1_fck",
2315 .prcm = { 1673 .prcm = {
2316 .omap2 = { 1674 .omap2 = {
@@ -2331,20 +1689,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2331 { .name = "tx", .irq = 62 }, 1689 { .name = "tx", .irq = 62 },
2332 { .name = "rx", .irq = 63 }, 1690 { .name = "rx", .irq = 63 },
2333 { .name = "common", .irq = 16 }, 1691 { .name = "common", .irq = 16 },
2334}; 1692 { .irq = -1 }
2335
2336static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2337 { .name = "rx", .dma_req = 34 },
2338 { .name = "tx", .dma_req = 33 },
2339};
2340
2341static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2342 {
2343 .name = "mpu",
2344 .pa_start = 0x48076000,
2345 .pa_end = 0x480760ff,
2346 .flags = ADDR_TYPE_RT
2347 },
2348}; 1693};
2349 1694
2350/* l4_core -> mcbsp2 */ 1695/* l4_core -> mcbsp2 */
@@ -2352,8 +1697,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2352 .master = &omap2430_l4_core_hwmod, 1697 .master = &omap2430_l4_core_hwmod,
2353 .slave = &omap2430_mcbsp2_hwmod, 1698 .slave = &omap2430_mcbsp2_hwmod,
2354 .clk = "mcbsp2_ick", 1699 .clk = "mcbsp2_ick",
2355 .addr = omap2430_mcbsp2_addrs, 1700 .addr = omap2xxx_mcbsp2_addrs,
2356 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
2357 .user = OCP_USER_MPU | OCP_USER_SDMA, 1701 .user = OCP_USER_MPU | OCP_USER_SDMA,
2358}; 1702};
2359 1703
@@ -2366,9 +1710,7 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2366 .name = "mcbsp2", 1710 .name = "mcbsp2",
2367 .class = &omap2430_mcbsp_hwmod_class, 1711 .class = &omap2430_mcbsp_hwmod_class,
2368 .mpu_irqs = omap2430_mcbsp2_irqs, 1712 .mpu_irqs = omap2430_mcbsp2_irqs,
2369 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs), 1713 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2370 .sdma_reqs = omap2430_mcbsp2_sdma_chs,
2371 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2372 .main_clk = "mcbsp2_fck", 1714 .main_clk = "mcbsp2_fck",
2373 .prcm = { 1715 .prcm = {
2374 .omap2 = { 1716 .omap2 = {
@@ -2389,11 +1731,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2389 { .name = "tx", .irq = 89 }, 1731 { .name = "tx", .irq = 89 },
2390 { .name = "rx", .irq = 90 }, 1732 { .name = "rx", .irq = 90 },
2391 { .name = "common", .irq = 17 }, 1733 { .name = "common", .irq = 17 },
2392}; 1734 { .irq = -1 }
2393
2394static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2395 { .name = "rx", .dma_req = 18 },
2396 { .name = "tx", .dma_req = 17 },
2397}; 1735};
2398 1736
2399static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = { 1737static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
@@ -2403,6 +1741,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2403 .pa_end = 0x4808C0ff, 1741 .pa_end = 0x4808C0ff,
2404 .flags = ADDR_TYPE_RT 1742 .flags = ADDR_TYPE_RT
2405 }, 1743 },
1744 { }
2406}; 1745};
2407 1746
2408/* l4_core -> mcbsp3 */ 1747/* l4_core -> mcbsp3 */
@@ -2411,7 +1750,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2411 .slave = &omap2430_mcbsp3_hwmod, 1750 .slave = &omap2430_mcbsp3_hwmod,
2412 .clk = "mcbsp3_ick", 1751 .clk = "mcbsp3_ick",
2413 .addr = omap2430_mcbsp3_addrs, 1752 .addr = omap2430_mcbsp3_addrs,
2414 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
2415 .user = OCP_USER_MPU | OCP_USER_SDMA, 1753 .user = OCP_USER_MPU | OCP_USER_SDMA,
2416}; 1754};
2417 1755
@@ -2424,9 +1762,7 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2424 .name = "mcbsp3", 1762 .name = "mcbsp3",
2425 .class = &omap2430_mcbsp_hwmod_class, 1763 .class = &omap2430_mcbsp_hwmod_class,
2426 .mpu_irqs = omap2430_mcbsp3_irqs, 1764 .mpu_irqs = omap2430_mcbsp3_irqs,
2427 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs), 1765 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2428 .sdma_reqs = omap2430_mcbsp3_sdma_chs,
2429 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2430 .main_clk = "mcbsp3_fck", 1766 .main_clk = "mcbsp3_fck",
2431 .prcm = { 1767 .prcm = {
2432 .omap2 = { 1768 .omap2 = {
@@ -2447,11 +1783,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2447 { .name = "tx", .irq = 54 }, 1783 { .name = "tx", .irq = 54 },
2448 { .name = "rx", .irq = 55 }, 1784 { .name = "rx", .irq = 55 },
2449 { .name = "common", .irq = 18 }, 1785 { .name = "common", .irq = 18 },
1786 { .irq = -1 }
2450}; 1787};
2451 1788
2452static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = { 1789static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2453 { .name = "rx", .dma_req = 20 }, 1790 { .name = "rx", .dma_req = 20 },
2454 { .name = "tx", .dma_req = 19 }, 1791 { .name = "tx", .dma_req = 19 },
1792 { .dma_req = -1 }
2455}; 1793};
2456 1794
2457static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = { 1795static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
@@ -2461,6 +1799,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2461 .pa_end = 0x4808E0ff, 1799 .pa_end = 0x4808E0ff,
2462 .flags = ADDR_TYPE_RT 1800 .flags = ADDR_TYPE_RT
2463 }, 1801 },
1802 { }
2464}; 1803};
2465 1804
2466/* l4_core -> mcbsp4 */ 1805/* l4_core -> mcbsp4 */
@@ -2469,7 +1808,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2469 .slave = &omap2430_mcbsp4_hwmod, 1808 .slave = &omap2430_mcbsp4_hwmod,
2470 .clk = "mcbsp4_ick", 1809 .clk = "mcbsp4_ick",
2471 .addr = omap2430_mcbsp4_addrs, 1810 .addr = omap2430_mcbsp4_addrs,
2472 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
2473 .user = OCP_USER_MPU | OCP_USER_SDMA, 1811 .user = OCP_USER_MPU | OCP_USER_SDMA,
2474}; 1812};
2475 1813
@@ -2482,9 +1820,7 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2482 .name = "mcbsp4", 1820 .name = "mcbsp4",
2483 .class = &omap2430_mcbsp_hwmod_class, 1821 .class = &omap2430_mcbsp_hwmod_class,
2484 .mpu_irqs = omap2430_mcbsp4_irqs, 1822 .mpu_irqs = omap2430_mcbsp4_irqs,
2485 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2486 .sdma_reqs = omap2430_mcbsp4_sdma_chs, 1823 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
2487 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2488 .main_clk = "mcbsp4_fck", 1824 .main_clk = "mcbsp4_fck",
2489 .prcm = { 1825 .prcm = {
2490 .omap2 = { 1826 .omap2 = {
@@ -2505,11 +1841,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2505 { .name = "tx", .irq = 81 }, 1841 { .name = "tx", .irq = 81 },
2506 { .name = "rx", .irq = 82 }, 1842 { .name = "rx", .irq = 82 },
2507 { .name = "common", .irq = 19 }, 1843 { .name = "common", .irq = 19 },
1844 { .irq = -1 }
2508}; 1845};
2509 1846
2510static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = { 1847static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2511 { .name = "rx", .dma_req = 22 }, 1848 { .name = "rx", .dma_req = 22 },
2512 { .name = "tx", .dma_req = 21 }, 1849 { .name = "tx", .dma_req = 21 },
1850 { .dma_req = -1 }
2513}; 1851};
2514 1852
2515static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = { 1853static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
@@ -2519,6 +1857,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2519 .pa_end = 0x480960ff, 1857 .pa_end = 0x480960ff,
2520 .flags = ADDR_TYPE_RT 1858 .flags = ADDR_TYPE_RT
2521 }, 1859 },
1860 { }
2522}; 1861};
2523 1862
2524/* l4_core -> mcbsp5 */ 1863/* l4_core -> mcbsp5 */
@@ -2527,7 +1866,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2527 .slave = &omap2430_mcbsp5_hwmod, 1866 .slave = &omap2430_mcbsp5_hwmod,
2528 .clk = "mcbsp5_ick", 1867 .clk = "mcbsp5_ick",
2529 .addr = omap2430_mcbsp5_addrs, 1868 .addr = omap2430_mcbsp5_addrs,
2530 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
2531 .user = OCP_USER_MPU | OCP_USER_SDMA, 1869 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532}; 1870};
2533 1871
@@ -2540,9 +1878,7 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2540 .name = "mcbsp5", 1878 .name = "mcbsp5",
2541 .class = &omap2430_mcbsp_hwmod_class, 1879 .class = &omap2430_mcbsp_hwmod_class,
2542 .mpu_irqs = omap2430_mcbsp5_irqs, 1880 .mpu_irqs = omap2430_mcbsp5_irqs,
2543 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2544 .sdma_reqs = omap2430_mcbsp5_sdma_chs, 1881 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
2545 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2546 .main_clk = "mcbsp5_fck", 1882 .main_clk = "mcbsp5_fck",
2547 .prcm = { 1883 .prcm = {
2548 .omap2 = { 1884 .omap2 = {
@@ -2580,11 +1916,13 @@ static struct omap_hwmod_class omap2430_mmc_class = {
2580 1916
2581static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = { 1917static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2582 { .irq = 83 }, 1918 { .irq = 83 },
1919 { .irq = -1 }
2583}; 1920};
2584 1921
2585static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = { 1922static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2586 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */ 1923 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2587 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */ 1924 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
1925 { .dma_req = -1 }
2588}; 1926};
2589 1927
2590static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { 1928static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
@@ -2603,9 +1941,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
2603 .name = "mmc1", 1941 .name = "mmc1",
2604 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1942 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2605 .mpu_irqs = omap2430_mmc1_mpu_irqs, 1943 .mpu_irqs = omap2430_mmc1_mpu_irqs,
2606 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2607 .sdma_reqs = omap2430_mmc1_sdma_reqs, 1944 .sdma_reqs = omap2430_mmc1_sdma_reqs,
2608 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2609 .opt_clks = omap2430_mmc1_opt_clks, 1945 .opt_clks = omap2430_mmc1_opt_clks,
2610 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), 1946 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2611 .main_clk = "mmchs1_fck", 1947 .main_clk = "mmchs1_fck",
@@ -2629,11 +1965,13 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
2629 1965
2630static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = { 1966static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2631 { .irq = 86 }, 1967 { .irq = 86 },
1968 { .irq = -1 }
2632}; 1969};
2633 1970
2634static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = { 1971static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2635 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */ 1972 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2636 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */ 1973 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
1974 { .dma_req = -1 }
2637}; 1975};
2638 1976
2639static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { 1977static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
@@ -2648,9 +1986,7 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
2648 .name = "mmc2", 1986 .name = "mmc2",
2649 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1987 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2650 .mpu_irqs = omap2430_mmc2_mpu_irqs, 1988 .mpu_irqs = omap2430_mmc2_mpu_irqs,
2651 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2652 .sdma_reqs = omap2430_mmc2_sdma_reqs, 1989 .sdma_reqs = omap2430_mmc2_sdma_reqs,
2653 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2654 .opt_clks = omap2430_mmc2_opt_clks, 1990 .opt_clks = omap2430_mmc2_opt_clks,
2655 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), 1991 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2656 .main_clk = "mmchs2_fck", 1992 .main_clk = "mmchs2_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
new file mode 100644
index 000000000000..04637fabadd2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -0,0 +1,173 @@
1/*
2 * omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <asm/sizes.h>
15
16#include <plat/omap_hwmod.h>
17#include <plat/serial.h>
18
19#include "omap_hwmod_common_data.h"
20
21struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
22 {
23 .pa_start = 0x4809c000,
24 .pa_end = 0x4809c1ff,
25 .flags = ADDR_TYPE_RT,
26 },
27 { }
28};
29
30struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
31 {
32 .pa_start = 0x480b4000,
33 .pa_end = 0x480b41ff,
34 .flags = ADDR_TYPE_RT,
35 },
36 { }
37};
38
39struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
40 {
41 .pa_start = 0x48070000,
42 .pa_end = 0x48070000 + SZ_128 - 1,
43 .flags = ADDR_TYPE_RT,
44 },
45 { }
46};
47
48struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
49 {
50 .pa_start = 0x48072000,
51 .pa_end = 0x48072000 + SZ_128 - 1,
52 .flags = ADDR_TYPE_RT,
53 },
54 { }
55};
56
57struct omap_hwmod_addr_space omap2_dss_addrs[] = {
58 {
59 .pa_start = 0x48050000,
60 .pa_end = 0x48050000 + SZ_1K - 1,
61 .flags = ADDR_TYPE_RT
62 },
63 { }
64};
65
66struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
67 {
68 .pa_start = 0x48050400,
69 .pa_end = 0x48050400 + SZ_1K - 1,
70 .flags = ADDR_TYPE_RT
71 },
72 { }
73};
74
75struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
76 {
77 .pa_start = 0x48050800,
78 .pa_end = 0x48050800 + SZ_1K - 1,
79 .flags = ADDR_TYPE_RT
80 },
81 { }
82};
83
84struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
85 {
86 .pa_start = 0x48050C00,
87 .pa_end = 0x48050C00 + SZ_1K - 1,
88 .flags = ADDR_TYPE_RT
89 },
90 { }
91};
92
93struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
94 {
95 .pa_start = 0x48086000,
96 .pa_end = 0x48086000 + SZ_1K - 1,
97 .flags = ADDR_TYPE_RT
98 },
99 { }
100};
101
102struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
103 {
104 .pa_start = 0x48088000,
105 .pa_end = 0x48088000 + SZ_1K - 1,
106 .flags = ADDR_TYPE_RT
107 },
108 { }
109};
110
111struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
112 {
113 .pa_start = 0x4808a000,
114 .pa_end = 0x4808a000 + SZ_1K - 1,
115 .flags = ADDR_TYPE_RT
116 },
117 { }
118};
119
120struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
121 {
122 .pa_start = 0x48098000,
123 .pa_end = 0x48098000 + SZ_256 - 1,
124 .flags = ADDR_TYPE_RT,
125 },
126 { }
127};
128
129struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
130 {
131 .pa_start = 0x4809a000,
132 .pa_end = 0x4809a000 + SZ_256 - 1,
133 .flags = ADDR_TYPE_RT,
134 },
135 { }
136};
137
138struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
139 {
140 .pa_start = 0x480b8000,
141 .pa_end = 0x480b8000 + SZ_256 - 1,
142 .flags = ADDR_TYPE_RT,
143 },
144 { }
145};
146
147struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
148 {
149 .pa_start = 0x48056000,
150 .pa_end = 0x48056000 + SZ_4K - 1,
151 .flags = ADDR_TYPE_RT
152 },
153 { }
154};
155
156struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
157 {
158 .pa_start = 0x48094000,
159 .pa_end = 0x48094000 + SZ_512 - 1,
160 .flags = ADDR_TYPE_RT,
161 },
162 { }
163};
164
165struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
166 {
167 .name = "mpu",
168 .pa_start = 0x48074000,
169 .pa_end = 0x480740ff,
170 .flags = ADDR_TYPE_RT
171 },
172 { }
173};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
new file mode 100644
index 000000000000..c451729d289a
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -0,0 +1,322 @@
1/*
2 * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>
13#include <plat/dma.h>
14
15#include <mach/irqs.h>
16
17#include "omap_hwmod_common_data.h"
18
19/* UART */
20
21static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
22 .rev_offs = 0x50,
23 .sysc_offs = 0x54,
24 .syss_offs = 0x58,
25 .sysc_flags = (SYSC_HAS_SIDLEMODE |
26 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
27 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
28 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
29 .sysc_fields = &omap_hwmod_sysc_type1,
30};
31
32struct omap_hwmod_class omap2_uart_class = {
33 .name = "uart",
34 .sysc = &omap2_uart_sysc,
35};
36
37/*
38 * 'dss' class
39 * display sub-system
40 */
41
42static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
43 .rev_offs = 0x0000,
44 .sysc_offs = 0x0010,
45 .syss_offs = 0x0014,
46 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
47 .sysc_fields = &omap_hwmod_sysc_type1,
48};
49
50struct omap_hwmod_class omap2_dss_hwmod_class = {
51 .name = "dss",
52 .sysc = &omap2_dss_sysc,
53};
54
55/*
56 * 'dispc' class
57 * display controller
58 */
59
60static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
61 .rev_offs = 0x0000,
62 .sysc_offs = 0x0010,
63 .syss_offs = 0x0014,
64 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
65 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
66 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
67 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
68 .sysc_fields = &omap_hwmod_sysc_type1,
69};
70
71struct omap_hwmod_class omap2_dispc_hwmod_class = {
72 .name = "dispc",
73 .sysc = &omap2_dispc_sysc,
74};
75
76/*
77 * 'rfbi' class
78 * remote frame buffer interface
79 */
80
81static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
82 .rev_offs = 0x0000,
83 .sysc_offs = 0x0010,
84 .syss_offs = 0x0014,
85 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
86 SYSC_HAS_AUTOIDLE),
87 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
88 .sysc_fields = &omap_hwmod_sysc_type1,
89};
90
91struct omap_hwmod_class omap2_rfbi_hwmod_class = {
92 .name = "rfbi",
93 .sysc = &omap2_rfbi_sysc,
94};
95
96/*
97 * 'venc' class
98 * video encoder
99 */
100
101struct omap_hwmod_class omap2_venc_hwmod_class = {
102 .name = "venc",
103};
104
105
106/* Common DMA request line data */
107struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
108 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
109 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
110 { .dma_req = -1 }
111};
112
113struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
114 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
115 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
116 { .dma_req = -1 }
117};
118
119struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
120 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
121 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
122 { .dma_req = -1 }
123};
124
125struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
126 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
127 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
128 { .dma_req = -1 }
129};
130
131struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
132 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
133 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
134 { .dma_req = -1 }
135};
136
137struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
138 { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
139 { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
140 { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
141 { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
142 { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
143 { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
144 { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
145 { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
146 { .dma_req = -1 }
147};
148
149struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
150 { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
151 { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
152 { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
153 { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
154 { .dma_req = -1 }
155};
156
157struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
158 { .name = "rx", .dma_req = 32 },
159 { .name = "tx", .dma_req = 31 },
160 { .dma_req = -1 }
161};
162
163struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
164 { .name = "rx", .dma_req = 34 },
165 { .name = "tx", .dma_req = 33 },
166 { .dma_req = -1 }
167};
168
169struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
170 { .name = "rx", .dma_req = 18 },
171 { .name = "tx", .dma_req = 17 },
172 { .dma_req = -1 }
173};
174
175/* Other IP block data */
176
177
178/*
179 * omap_hwmod class data
180 */
181
182struct omap_hwmod_class l3_hwmod_class = {
183 .name = "l3"
184};
185
186struct omap_hwmod_class l4_hwmod_class = {
187 .name = "l4"
188};
189
190struct omap_hwmod_class mpu_hwmod_class = {
191 .name = "mpu"
192};
193
194struct omap_hwmod_class iva_hwmod_class = {
195 .name = "iva"
196};
197
198/* Common MPU IRQ line data */
199
200struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
201 { .irq = 37, },
202 { .irq = -1 }
203};
204
205struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
206 { .irq = 38, },
207 { .irq = -1 }
208};
209
210struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
211 { .irq = 39, },
212 { .irq = -1 }
213};
214
215struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
216 { .irq = 40, },
217 { .irq = -1 }
218};
219
220struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
221 { .irq = 41, },
222 { .irq = -1 }
223};
224
225struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
226 { .irq = 42, },
227 { .irq = -1 }
228};
229
230struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
231 { .irq = 43, },
232 { .irq = -1 }
233};
234
235struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
236 { .irq = 44, },
237 { .irq = -1 }
238};
239
240struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
241 { .irq = 45, },
242 { .irq = -1 }
243};
244
245struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
246 { .irq = 46, },
247 { .irq = -1 }
248};
249
250struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
251 { .irq = 47, },
252 { .irq = -1 }
253};
254
255struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
256 { .irq = INT_24XX_UART1_IRQ, },
257 { .irq = -1 }
258};
259
260struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
261 { .irq = INT_24XX_UART2_IRQ, },
262 { .irq = -1 }
263};
264
265struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
266 { .irq = INT_24XX_UART3_IRQ, },
267 { .irq = -1 }
268};
269
270struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
271 { .irq = 25 },
272 { .irq = -1 }
273};
274
275struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
276 { .irq = INT_24XX_I2C1_IRQ, },
277 { .irq = -1 }
278};
279
280struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
281 { .irq = INT_24XX_I2C2_IRQ, },
282 { .irq = -1 }
283};
284
285struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
286 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
287 { .irq = -1 }
288};
289
290struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
291 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
292 { .irq = -1 }
293};
294
295struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
296 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
297 { .irq = -1 }
298};
299
300struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
301 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
302 { .irq = -1 }
303};
304
305struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
306 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
307 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
308 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
309 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
310 { .irq = -1 }
311};
312
313struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
314 { .irq = 65 },
315 { .irq = -1 }
316};
317
318struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
319 { .irq = 66 },
320 { .irq = -1 }
321};
322
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
new file mode 100644
index 000000000000..4f3547c2a49e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -0,0 +1,130 @@
1/*
2 * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
3 *
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
13 */
14#include <asm/sizes.h>
15
16#include <plat/omap_hwmod.h>
17#include <plat/serial.h>
18
19#include "omap_hwmod_common_data.h"
20
21struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
22 {
23 .pa_start = OMAP2_UART1_BASE,
24 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
25 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
26 },
27 { }
28};
29
30struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
31 {
32 .pa_start = OMAP2_UART2_BASE,
33 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
34 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
35 },
36 { }
37};
38
39struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
40 {
41 .pa_start = OMAP2_UART3_BASE,
42 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
43 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
44 },
45 { }
46};
47
48struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
49 {
50 .pa_start = 0x4802a000,
51 .pa_end = 0x4802a000 + SZ_1K - 1,
52 .flags = ADDR_TYPE_RT
53 },
54 { }
55};
56
57struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
58 {
59 .pa_start = 0x48078000,
60 .pa_end = 0x48078000 + SZ_1K - 1,
61 .flags = ADDR_TYPE_RT
62 },
63 { }
64};
65
66struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
67 {
68 .pa_start = 0x4807a000,
69 .pa_end = 0x4807a000 + SZ_1K - 1,
70 .flags = ADDR_TYPE_RT
71 },
72 { }
73};
74
75struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
76 {
77 .pa_start = 0x4807c000,
78 .pa_end = 0x4807c000 + SZ_1K - 1,
79 .flags = ADDR_TYPE_RT
80 },
81 { }
82};
83
84struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
85 {
86 .pa_start = 0x4807e000,
87 .pa_end = 0x4807e000 + SZ_1K - 1,
88 .flags = ADDR_TYPE_RT
89 },
90 { }
91};
92
93struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
94 {
95 .pa_start = 0x48080000,
96 .pa_end = 0x48080000 + SZ_1K - 1,
97 .flags = ADDR_TYPE_RT
98 },
99 { }
100};
101
102struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
103 {
104 .pa_start = 0x48082000,
105 .pa_end = 0x48082000 + SZ_1K - 1,
106 .flags = ADDR_TYPE_RT
107 },
108 { }
109};
110
111struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
112 {
113 .pa_start = 0x48084000,
114 .pa_end = 0x48084000 + SZ_1K - 1,
115 .flags = ADDR_TYPE_RT
116 },
117 { }
118};
119
120struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
121 {
122 .name = "mpu",
123 .pa_start = 0x48076000,
124 .pa_end = 0x480760ff,
125 .flags = ADDR_TYPE_RT
126 },
127 { }
128};
129
130
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
new file mode 100644
index 000000000000..177dee20faef
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -0,0 +1,150 @@
1/*
2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
3 *
4 * Copyright (C) 2011 Nokia Corporation
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <plat/omap_hwmod.h>
12#include <plat/serial.h>
13#include <plat/dma.h>
14#include <plat/dmtimer.h>
15#include <plat/mcspi.h>
16
17#include <mach/irqs.h>
18
19#include "omap_hwmod_common_data.h"
20#include "wd_timer.h"
21
22struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
23 { .irq = 48, },
24 { .irq = -1 }
25};
26
27struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
28 { .name = "dispc", .dma_req = 5 },
29 { .dma_req = -1 }
30};
31/* OMAP2xxx Timer Common */
32static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
33 .rev_offs = 0x0000,
34 .sysc_offs = 0x0010,
35 .syss_offs = 0x0014,
36 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
37 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
38 SYSC_HAS_AUTOIDLE),
39 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
40 .sysc_fields = &omap_hwmod_sysc_type1,
41};
42
43struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
44 .name = "timer",
45 .sysc = &omap2xxx_timer_sysc,
46 .rev = OMAP_TIMER_IP_VERSION_1,
47};
48
49/*
50 * 'wd_timer' class
51 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
52 * overflow condition
53 */
54
55static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
56 .rev_offs = 0x0000,
57 .sysc_offs = 0x0010,
58 .syss_offs = 0x0014,
59 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
60 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
61 .sysc_fields = &omap_hwmod_sysc_type1,
62};
63
64struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
65 .name = "wd_timer",
66 .sysc = &omap2xxx_wd_timer_sysc,
67 .pre_shutdown = &omap2_wd_timer_disable
68};
69
70/*
71 * 'gpio' class
72 * general purpose io module
73 */
74static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
75 .rev_offs = 0x0000,
76 .sysc_offs = 0x0010,
77 .syss_offs = 0x0014,
78 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
79 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
80 SYSS_HAS_RESET_STATUS),
81 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
82 .sysc_fields = &omap_hwmod_sysc_type1,
83};
84
85struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
86 .name = "gpio",
87 .sysc = &omap2xxx_gpio_sysc,
88 .rev = 0,
89};
90
91/* system dma */
92static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
93 .rev_offs = 0x0000,
94 .sysc_offs = 0x002c,
95 .syss_offs = 0x0028,
96 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
97 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
98 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
99 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
100 .sysc_fields = &omap_hwmod_sysc_type1,
101};
102
103struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
104 .name = "dma",
105 .sysc = &omap2xxx_dma_sysc,
106};
107
108/*
109 * 'mailbox' class
110 * mailbox module allowing communication between the on-chip processors
111 * using a queued mailbox-interrupt mechanism.
112 */
113
114static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
115 .rev_offs = 0x000,
116 .sysc_offs = 0x010,
117 .syss_offs = 0x014,
118 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
119 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
120 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
121 .sysc_fields = &omap_hwmod_sysc_type1,
122};
123
124struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
125 .name = "mailbox",
126 .sysc = &omap2xxx_mailbox_sysc,
127};
128
129/*
130 * 'mcspi' class
131 * multichannel serial port interface (mcspi) / master/slave synchronous serial
132 * bus
133 */
134
135static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
136 .rev_offs = 0x0000,
137 .sysc_offs = 0x0010,
138 .syss_offs = 0x0014,
139 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
141 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
142 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
143 .sysc_fields = &omap_hwmod_sysc_type1,
144};
145
146struct omap_hwmod_class omap2xxx_mcspi_class = {
147 .name = "mcspi",
148 .sysc = &omap2xxx_mcspi_sysc,
149 .rev = OMAP2_MCSPI_REV,
150};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 909a84de6682..1a52716e48bf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips 2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
3 * 3 *
4 * Copyright (C) 2009-2010 Nokia Corporation 4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
103static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = { 103static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ }, 104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ }, 105 { .irq = INT_34XX_L3_APP_IRQ },
106 { .irq = -1 }
106}; 107};
107 108
108static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = { 109static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
@@ -111,6 +112,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_end = 0x6800ffff, 112 .pa_end = 0x6800ffff,
112 .flags = ADDR_TYPE_RT, 113 .flags = ADDR_TYPE_RT,
113 }, 114 },
115 { }
114}; 116};
115 117
116/* MPU -> L3 interface */ 118/* MPU -> L3 interface */
@@ -118,7 +120,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
118 .master = &omap3xxx_mpu_hwmod, 120 .master = &omap3xxx_mpu_hwmod,
119 .slave = &omap3xxx_l3_main_hwmod, 121 .slave = &omap3xxx_l3_main_hwmod,
120 .addr = omap3xxx_l3_main_addrs, 122 .addr = omap3xxx_l3_main_addrs,
121 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
122 .user = OCP_USER_MPU, 123 .user = OCP_USER_MPU,
123}; 124};
124 125
@@ -150,8 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
150static struct omap_hwmod omap3xxx_l3_main_hwmod = { 151static struct omap_hwmod omap3xxx_l3_main_hwmod = {
151 .name = "l3_main", 152 .name = "l3_main",
152 .class = &l3_hwmod_class, 153 .class = &l3_hwmod_class,
153 .mpu_irqs = omap3xxx_l3_main_irqs, 154 .mpu_irqs = omap3xxx_l3_main_irqs,
154 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
155 .masters = omap3xxx_l3_main_masters, 155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves, 157 .slaves = omap3xxx_l3_main_slaves,
@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
190}; 190};
191 191
192/* L4 CORE -> MMC1 interface */ 192/* L4 CORE -> MMC1 interface */
193static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
194 {
195 .pa_start = 0x4809c000,
196 .pa_end = 0x4809c1ff,
197 .flags = ADDR_TYPE_RT,
198 },
199};
200
201static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = { 193static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
202 .master = &omap3xxx_l4_core_hwmod, 194 .master = &omap3xxx_l4_core_hwmod,
203 .slave = &omap3xxx_mmc1_hwmod, 195 .slave = &omap3xxx_mmc1_hwmod,
204 .clk = "mmchs1_ick", 196 .clk = "mmchs1_ick",
205 .addr = omap3xxx_mmc1_addr_space, 197 .addr = omap2430_mmc1_addr_space,
206 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
207 .user = OCP_USER_MPU | OCP_USER_SDMA, 198 .user = OCP_USER_MPU | OCP_USER_SDMA,
208 .flags = OMAP_FIREWALL_L4 199 .flags = OMAP_FIREWALL_L4
209}; 200};
210 201
211/* L4 CORE -> MMC2 interface */ 202/* L4 CORE -> MMC2 interface */
212static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
213 {
214 .pa_start = 0x480b4000,
215 .pa_end = 0x480b41ff,
216 .flags = ADDR_TYPE_RT,
217 },
218};
219
220static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = { 203static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
221 .master = &omap3xxx_l4_core_hwmod, 204 .master = &omap3xxx_l4_core_hwmod,
222 .slave = &omap3xxx_mmc2_hwmod, 205 .slave = &omap3xxx_mmc2_hwmod,
223 .clk = "mmchs2_ick", 206 .clk = "mmchs2_ick",
224 .addr = omap3xxx_mmc2_addr_space, 207 .addr = omap2430_mmc2_addr_space,
225 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
226 .user = OCP_USER_MPU | OCP_USER_SDMA, 208 .user = OCP_USER_MPU | OCP_USER_SDMA,
227 .flags = OMAP_FIREWALL_L4 209 .flags = OMAP_FIREWALL_L4
228}; 210};
@@ -234,6 +216,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
234 .pa_end = 0x480ad1ff, 216 .pa_end = 0x480ad1ff,
235 .flags = ADDR_TYPE_RT, 217 .flags = ADDR_TYPE_RT,
236 }, 218 },
219 { }
237}; 220};
238 221
239static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = { 222static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
@@ -241,7 +224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
241 .slave = &omap3xxx_mmc3_hwmod, 224 .slave = &omap3xxx_mmc3_hwmod,
242 .clk = "mmchs3_ick", 225 .clk = "mmchs3_ick",
243 .addr = omap3xxx_mmc3_addr_space, 226 .addr = omap3xxx_mmc3_addr_space,
244 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
245 .user = OCP_USER_MPU | OCP_USER_SDMA, 227 .user = OCP_USER_MPU | OCP_USER_SDMA,
246 .flags = OMAP_FIREWALL_L4 228 .flags = OMAP_FIREWALL_L4
247}; 229};
@@ -253,6 +235,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
253 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1, 235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
255 }, 237 },
238 { }
256}; 239};
257 240
258static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = { 241static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
@@ -260,7 +243,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
260 .slave = &omap3xxx_uart1_hwmod, 243 .slave = &omap3xxx_uart1_hwmod,
261 .clk = "uart1_ick", 244 .clk = "uart1_ick",
262 .addr = omap3xxx_uart1_addr_space, 245 .addr = omap3xxx_uart1_addr_space,
263 .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
264 .user = OCP_USER_MPU | OCP_USER_SDMA, 246 .user = OCP_USER_MPU | OCP_USER_SDMA,
265}; 247};
266 248
@@ -271,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
271 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1, 253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
273 }, 255 },
256 { }
274}; 257};
275 258
276static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = { 259static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
@@ -278,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
278 .slave = &omap3xxx_uart2_hwmod, 261 .slave = &omap3xxx_uart2_hwmod,
279 .clk = "uart2_ick", 262 .clk = "uart2_ick",
280 .addr = omap3xxx_uart2_addr_space, 263 .addr = omap3xxx_uart2_addr_space,
281 .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
282 .user = OCP_USER_MPU | OCP_USER_SDMA, 264 .user = OCP_USER_MPU | OCP_USER_SDMA,
283}; 265};
284 266
@@ -289,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
289 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1, 271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
291 }, 273 },
274 { }
292}; 275};
293 276
294static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = { 277static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
@@ -296,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
296 .slave = &omap3xxx_uart3_hwmod, 279 .slave = &omap3xxx_uart3_hwmod,
297 .clk = "uart3_ick", 280 .clk = "uart3_ick",
298 .addr = omap3xxx_uart3_addr_space, 281 .addr = omap3xxx_uart3_addr_space,
299 .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
300 .user = OCP_USER_MPU | OCP_USER_SDMA, 282 .user = OCP_USER_MPU | OCP_USER_SDMA,
301}; 283};
302 284
@@ -307,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
307 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1, 289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
308 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, 290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
309 }, 291 },
292 { }
310}; 293};
311 294
312static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { 295static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
@@ -314,28 +297,15 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
314 .slave = &omap3xxx_uart4_hwmod, 297 .slave = &omap3xxx_uart4_hwmod,
315 .clk = "uart4_ick", 298 .clk = "uart4_ick",
316 .addr = omap3xxx_uart4_addr_space, 299 .addr = omap3xxx_uart4_addr_space,
317 .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
318 .user = OCP_USER_MPU | OCP_USER_SDMA, 300 .user = OCP_USER_MPU | OCP_USER_SDMA,
319}; 301};
320 302
321/* I2C IP block address space length (in bytes) */
322#define OMAP2_I2C_AS_LEN 128
323
324/* L4 CORE -> I2C1 interface */ 303/* L4 CORE -> I2C1 interface */
325static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
326 {
327 .pa_start = 0x48070000,
328 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
329 .flags = ADDR_TYPE_RT,
330 },
331};
332
333static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { 304static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
334 .master = &omap3xxx_l4_core_hwmod, 305 .master = &omap3xxx_l4_core_hwmod,
335 .slave = &omap3xxx_i2c1_hwmod, 306 .slave = &omap3xxx_i2c1_hwmod,
336 .clk = "i2c1_ick", 307 .clk = "i2c1_ick",
337 .addr = omap3xxx_i2c1_addr_space, 308 .addr = omap2_i2c1_addr_space,
338 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
339 .fw = { 309 .fw = {
340 .omap2 = { 310 .omap2 = {
341 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, 311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
347}; 317};
348 318
349/* L4 CORE -> I2C2 interface */ 319/* L4 CORE -> I2C2 interface */
350static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
351 {
352 .pa_start = 0x48072000,
353 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
354 .flags = ADDR_TYPE_RT,
355 },
356};
357
358static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { 320static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
359 .master = &omap3xxx_l4_core_hwmod, 321 .master = &omap3xxx_l4_core_hwmod,
360 .slave = &omap3xxx_i2c2_hwmod, 322 .slave = &omap3xxx_i2c2_hwmod,
361 .clk = "i2c2_ick", 323 .clk = "i2c2_ick",
362 .addr = omap3xxx_i2c2_addr_space, 324 .addr = omap2_i2c2_addr_space,
363 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
364 .fw = { 325 .fw = {
365 .omap2 = { 326 .omap2 = {
366 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, 327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
@@ -375,9 +336,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
375static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { 336static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
376 { 337 {
377 .pa_start = 0x48060000, 338 .pa_start = 0x48060000,
378 .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, 339 .pa_end = 0x48060000 + SZ_128 - 1,
379 .flags = ADDR_TYPE_RT, 340 .flags = ADDR_TYPE_RT,
380 }, 341 },
342 { }
381}; 343};
382 344
383static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { 345static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
@@ -385,7 +347,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
385 .slave = &omap3xxx_i2c3_hwmod, 347 .slave = &omap3xxx_i2c3_hwmod,
386 .clk = "i2c3_ick", 348 .clk = "i2c3_ick",
387 .addr = omap3xxx_i2c3_addr_space, 349 .addr = omap3xxx_i2c3_addr_space,
388 .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
389 .fw = { 350 .fw = {
390 .omap2 = { 351 .omap2 = {
391 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, 352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
@@ -403,6 +364,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
403 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1, 364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
404 .flags = ADDR_TYPE_RT, 365 .flags = ADDR_TYPE_RT,
405 }, 366 },
367 { }
406}; 368};
407 369
408static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = { 370static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
@@ -410,7 +372,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
410 .slave = &omap34xx_sr1_hwmod, 372 .slave = &omap34xx_sr1_hwmod,
411 .clk = "sr_l4_ick", 373 .clk = "sr_l4_ick",
412 .addr = omap3_sr1_addr_space, 374 .addr = omap3_sr1_addr_space,
413 .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
414 .user = OCP_USER_MPU, 375 .user = OCP_USER_MPU,
415}; 376};
416 377
@@ -421,6 +382,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
421 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1, 382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
422 .flags = ADDR_TYPE_RT, 383 .flags = ADDR_TYPE_RT,
423 }, 384 },
385 { }
424}; 386};
425 387
426static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = { 388static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
@@ -428,7 +390,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
428 .slave = &omap34xx_sr2_hwmod, 390 .slave = &omap34xx_sr2_hwmod,
429 .clk = "sr_l4_ick", 391 .clk = "sr_l4_ick",
430 .addr = omap3_sr2_addr_space, 392 .addr = omap3_sr2_addr_space,
431 .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
432 .user = OCP_USER_MPU, 393 .user = OCP_USER_MPU,
433}; 394};
434 395
@@ -442,6 +403,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
442 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1, 403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
443 .flags = ADDR_TYPE_RT 404 .flags = ADDR_TYPE_RT
444 }, 405 },
406 { }
445}; 407};
446 408
447/* l4_core -> usbhsotg */ 409/* l4_core -> usbhsotg */
@@ -450,7 +412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
450 .slave = &omap3xxx_usbhsotg_hwmod, 412 .slave = &omap3xxx_usbhsotg_hwmod,
451 .clk = "l4_ick", 413 .clk = "l4_ick",
452 .addr = omap3xxx_usbhsotg_addrs, 414 .addr = omap3xxx_usbhsotg_addrs,
453 .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
454 .user = OCP_USER_MPU, 415 .user = OCP_USER_MPU,
455}; 416};
456 417
@@ -468,6 +429,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
468 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1, 429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
469 .flags = ADDR_TYPE_RT 430 .flags = ADDR_TYPE_RT
470 }, 431 },
432 { }
471}; 433};
472 434
473/* l4_core -> usbhsotg */ 435/* l4_core -> usbhsotg */
@@ -476,7 +438,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
476 .slave = &am35xx_usbhsotg_hwmod, 438 .slave = &am35xx_usbhsotg_hwmod,
477 .clk = "l4_ick", 439 .clk = "l4_ick",
478 .addr = am35xx_usbhsotg_addrs, 440 .addr = am35xx_usbhsotg_addrs,
479 .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
480 .user = OCP_USER_MPU, 441 .user = OCP_USER_MPU,
481}; 442};
482 443
@@ -611,9 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
611 572
612/* timer1 */ 573/* timer1 */
613static struct omap_hwmod omap3xxx_timer1_hwmod; 574static struct omap_hwmod omap3xxx_timer1_hwmod;
614static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
615 { .irq = 37, },
616};
617 575
618static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = { 576static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
619 { 577 {
@@ -621,6 +579,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
621 .pa_end = 0x48318000 + SZ_1K - 1, 579 .pa_end = 0x48318000 + SZ_1K - 1,
622 .flags = ADDR_TYPE_RT 580 .flags = ADDR_TYPE_RT
623 }, 581 },
582 { }
624}; 583};
625 584
626/* l4_wkup -> timer1 */ 585/* l4_wkup -> timer1 */
@@ -629,7 +588,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
629 .slave = &omap3xxx_timer1_hwmod, 588 .slave = &omap3xxx_timer1_hwmod,
630 .clk = "gpt1_ick", 589 .clk = "gpt1_ick",
631 .addr = omap3xxx_timer1_addrs, 590 .addr = omap3xxx_timer1_addrs,
632 .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
633 .user = OCP_USER_MPU | OCP_USER_SDMA, 591 .user = OCP_USER_MPU | OCP_USER_SDMA,
634}; 592};
635 593
@@ -641,8 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
641/* timer1 hwmod */ 599/* timer1 hwmod */
642static struct omap_hwmod omap3xxx_timer1_hwmod = { 600static struct omap_hwmod omap3xxx_timer1_hwmod = {
643 .name = "timer1", 601 .name = "timer1",
644 .mpu_irqs = omap3xxx_timer1_mpu_irqs, 602 .mpu_irqs = omap2_timer1_mpu_irqs,
645 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
646 .main_clk = "gpt1_fck", 603 .main_clk = "gpt1_fck",
647 .prcm = { 604 .prcm = {
648 .omap2 = { 605 .omap2 = {
@@ -661,9 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
661 618
662/* timer2 */ 619/* timer2 */
663static struct omap_hwmod omap3xxx_timer2_hwmod; 620static struct omap_hwmod omap3xxx_timer2_hwmod;
664static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
665 { .irq = 38, },
666};
667 621
668static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = { 622static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
669 { 623 {
@@ -671,6 +625,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
671 .pa_end = 0x49032000 + SZ_1K - 1, 625 .pa_end = 0x49032000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT 626 .flags = ADDR_TYPE_RT
673 }, 627 },
628 { }
674}; 629};
675 630
676/* l4_per -> timer2 */ 631/* l4_per -> timer2 */
@@ -679,7 +634,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
679 .slave = &omap3xxx_timer2_hwmod, 634 .slave = &omap3xxx_timer2_hwmod,
680 .clk = "gpt2_ick", 635 .clk = "gpt2_ick",
681 .addr = omap3xxx_timer2_addrs, 636 .addr = omap3xxx_timer2_addrs,
682 .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
683 .user = OCP_USER_MPU | OCP_USER_SDMA, 637 .user = OCP_USER_MPU | OCP_USER_SDMA,
684}; 638};
685 639
@@ -691,8 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
691/* timer2 hwmod */ 645/* timer2 hwmod */
692static struct omap_hwmod omap3xxx_timer2_hwmod = { 646static struct omap_hwmod omap3xxx_timer2_hwmod = {
693 .name = "timer2", 647 .name = "timer2",
694 .mpu_irqs = omap3xxx_timer2_mpu_irqs, 648 .mpu_irqs = omap2_timer2_mpu_irqs,
695 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
696 .main_clk = "gpt2_fck", 649 .main_clk = "gpt2_fck",
697 .prcm = { 650 .prcm = {
698 .omap2 = { 651 .omap2 = {
@@ -711,9 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
711 664
712/* timer3 */ 665/* timer3 */
713static struct omap_hwmod omap3xxx_timer3_hwmod; 666static struct omap_hwmod omap3xxx_timer3_hwmod;
714static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
715 { .irq = 39, },
716};
717 667
718static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = { 668static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
719 { 669 {
@@ -721,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
721 .pa_end = 0x49034000 + SZ_1K - 1, 671 .pa_end = 0x49034000 + SZ_1K - 1,
722 .flags = ADDR_TYPE_RT 672 .flags = ADDR_TYPE_RT
723 }, 673 },
674 { }
724}; 675};
725 676
726/* l4_per -> timer3 */ 677/* l4_per -> timer3 */
@@ -729,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
729 .slave = &omap3xxx_timer3_hwmod, 680 .slave = &omap3xxx_timer3_hwmod,
730 .clk = "gpt3_ick", 681 .clk = "gpt3_ick",
731 .addr = omap3xxx_timer3_addrs, 682 .addr = omap3xxx_timer3_addrs,
732 .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
733 .user = OCP_USER_MPU | OCP_USER_SDMA, 683 .user = OCP_USER_MPU | OCP_USER_SDMA,
734}; 684};
735 685
@@ -741,8 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
741/* timer3 hwmod */ 691/* timer3 hwmod */
742static struct omap_hwmod omap3xxx_timer3_hwmod = { 692static struct omap_hwmod omap3xxx_timer3_hwmod = {
743 .name = "timer3", 693 .name = "timer3",
744 .mpu_irqs = omap3xxx_timer3_mpu_irqs, 694 .mpu_irqs = omap2_timer3_mpu_irqs,
745 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
746 .main_clk = "gpt3_fck", 695 .main_clk = "gpt3_fck",
747 .prcm = { 696 .prcm = {
748 .omap2 = { 697 .omap2 = {
@@ -761,9 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
761 710
762/* timer4 */ 711/* timer4 */
763static struct omap_hwmod omap3xxx_timer4_hwmod; 712static struct omap_hwmod omap3xxx_timer4_hwmod;
764static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
765 { .irq = 40, },
766};
767 713
768static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = { 714static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
769 { 715 {
@@ -771,6 +717,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
771 .pa_end = 0x49036000 + SZ_1K - 1, 717 .pa_end = 0x49036000 + SZ_1K - 1,
772 .flags = ADDR_TYPE_RT 718 .flags = ADDR_TYPE_RT
773 }, 719 },
720 { }
774}; 721};
775 722
776/* l4_per -> timer4 */ 723/* l4_per -> timer4 */
@@ -779,7 +726,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
779 .slave = &omap3xxx_timer4_hwmod, 726 .slave = &omap3xxx_timer4_hwmod,
780 .clk = "gpt4_ick", 727 .clk = "gpt4_ick",
781 .addr = omap3xxx_timer4_addrs, 728 .addr = omap3xxx_timer4_addrs,
782 .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
783 .user = OCP_USER_MPU | OCP_USER_SDMA, 729 .user = OCP_USER_MPU | OCP_USER_SDMA,
784}; 730};
785 731
@@ -791,8 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
791/* timer4 hwmod */ 737/* timer4 hwmod */
792static struct omap_hwmod omap3xxx_timer4_hwmod = { 738static struct omap_hwmod omap3xxx_timer4_hwmod = {
793 .name = "timer4", 739 .name = "timer4",
794 .mpu_irqs = omap3xxx_timer4_mpu_irqs, 740 .mpu_irqs = omap2_timer4_mpu_irqs,
795 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
796 .main_clk = "gpt4_fck", 741 .main_clk = "gpt4_fck",
797 .prcm = { 742 .prcm = {
798 .omap2 = { 743 .omap2 = {
@@ -811,9 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
811 756
812/* timer5 */ 757/* timer5 */
813static struct omap_hwmod omap3xxx_timer5_hwmod; 758static struct omap_hwmod omap3xxx_timer5_hwmod;
814static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
815 { .irq = 41, },
816};
817 759
818static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = { 760static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
819 { 761 {
@@ -821,6 +763,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
821 .pa_end = 0x49038000 + SZ_1K - 1, 763 .pa_end = 0x49038000 + SZ_1K - 1,
822 .flags = ADDR_TYPE_RT 764 .flags = ADDR_TYPE_RT
823 }, 765 },
766 { }
824}; 767};
825 768
826/* l4_per -> timer5 */ 769/* l4_per -> timer5 */
@@ -829,7 +772,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
829 .slave = &omap3xxx_timer5_hwmod, 772 .slave = &omap3xxx_timer5_hwmod,
830 .clk = "gpt5_ick", 773 .clk = "gpt5_ick",
831 .addr = omap3xxx_timer5_addrs, 774 .addr = omap3xxx_timer5_addrs,
832 .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
833 .user = OCP_USER_MPU | OCP_USER_SDMA, 775 .user = OCP_USER_MPU | OCP_USER_SDMA,
834}; 776};
835 777
@@ -841,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
841/* timer5 hwmod */ 783/* timer5 hwmod */
842static struct omap_hwmod omap3xxx_timer5_hwmod = { 784static struct omap_hwmod omap3xxx_timer5_hwmod = {
843 .name = "timer5", 785 .name = "timer5",
844 .mpu_irqs = omap3xxx_timer5_mpu_irqs, 786 .mpu_irqs = omap2_timer5_mpu_irqs,
845 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
846 .main_clk = "gpt5_fck", 787 .main_clk = "gpt5_fck",
847 .prcm = { 788 .prcm = {
848 .omap2 = { 789 .omap2 = {
@@ -861,9 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
861 802
862/* timer6 */ 803/* timer6 */
863static struct omap_hwmod omap3xxx_timer6_hwmod; 804static struct omap_hwmod omap3xxx_timer6_hwmod;
864static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
865 { .irq = 42, },
866};
867 805
868static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = { 806static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
869 { 807 {
@@ -871,6 +809,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
871 .pa_end = 0x4903A000 + SZ_1K - 1, 809 .pa_end = 0x4903A000 + SZ_1K - 1,
872 .flags = ADDR_TYPE_RT 810 .flags = ADDR_TYPE_RT
873 }, 811 },
812 { }
874}; 813};
875 814
876/* l4_per -> timer6 */ 815/* l4_per -> timer6 */
@@ -879,7 +818,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
879 .slave = &omap3xxx_timer6_hwmod, 818 .slave = &omap3xxx_timer6_hwmod,
880 .clk = "gpt6_ick", 819 .clk = "gpt6_ick",
881 .addr = omap3xxx_timer6_addrs, 820 .addr = omap3xxx_timer6_addrs,
882 .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
883 .user = OCP_USER_MPU | OCP_USER_SDMA, 821 .user = OCP_USER_MPU | OCP_USER_SDMA,
884}; 822};
885 823
@@ -891,8 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
891/* timer6 hwmod */ 829/* timer6 hwmod */
892static struct omap_hwmod omap3xxx_timer6_hwmod = { 830static struct omap_hwmod omap3xxx_timer6_hwmod = {
893 .name = "timer6", 831 .name = "timer6",
894 .mpu_irqs = omap3xxx_timer6_mpu_irqs, 832 .mpu_irqs = omap2_timer6_mpu_irqs,
895 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
896 .main_clk = "gpt6_fck", 833 .main_clk = "gpt6_fck",
897 .prcm = { 834 .prcm = {
898 .omap2 = { 835 .omap2 = {
@@ -911,9 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
911 848
912/* timer7 */ 849/* timer7 */
913static struct omap_hwmod omap3xxx_timer7_hwmod; 850static struct omap_hwmod omap3xxx_timer7_hwmod;
914static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
915 { .irq = 43, },
916};
917 851
918static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = { 852static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
919 { 853 {
@@ -921,6 +855,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
921 .pa_end = 0x4903C000 + SZ_1K - 1, 855 .pa_end = 0x4903C000 + SZ_1K - 1,
922 .flags = ADDR_TYPE_RT 856 .flags = ADDR_TYPE_RT
923 }, 857 },
858 { }
924}; 859};
925 860
926/* l4_per -> timer7 */ 861/* l4_per -> timer7 */
@@ -929,7 +864,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
929 .slave = &omap3xxx_timer7_hwmod, 864 .slave = &omap3xxx_timer7_hwmod,
930 .clk = "gpt7_ick", 865 .clk = "gpt7_ick",
931 .addr = omap3xxx_timer7_addrs, 866 .addr = omap3xxx_timer7_addrs,
932 .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
933 .user = OCP_USER_MPU | OCP_USER_SDMA, 867 .user = OCP_USER_MPU | OCP_USER_SDMA,
934}; 868};
935 869
@@ -941,8 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
941/* timer7 hwmod */ 875/* timer7 hwmod */
942static struct omap_hwmod omap3xxx_timer7_hwmod = { 876static struct omap_hwmod omap3xxx_timer7_hwmod = {
943 .name = "timer7", 877 .name = "timer7",
944 .mpu_irqs = omap3xxx_timer7_mpu_irqs, 878 .mpu_irqs = omap2_timer7_mpu_irqs,
945 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
946 .main_clk = "gpt7_fck", 879 .main_clk = "gpt7_fck",
947 .prcm = { 880 .prcm = {
948 .omap2 = { 881 .omap2 = {
@@ -961,9 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
961 894
962/* timer8 */ 895/* timer8 */
963static struct omap_hwmod omap3xxx_timer8_hwmod; 896static struct omap_hwmod omap3xxx_timer8_hwmod;
964static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
965 { .irq = 44, },
966};
967 897
968static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = { 898static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
969 { 899 {
@@ -971,6 +901,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
971 .pa_end = 0x4903E000 + SZ_1K - 1, 901 .pa_end = 0x4903E000 + SZ_1K - 1,
972 .flags = ADDR_TYPE_RT 902 .flags = ADDR_TYPE_RT
973 }, 903 },
904 { }
974}; 905};
975 906
976/* l4_per -> timer8 */ 907/* l4_per -> timer8 */
@@ -979,7 +910,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
979 .slave = &omap3xxx_timer8_hwmod, 910 .slave = &omap3xxx_timer8_hwmod,
980 .clk = "gpt8_ick", 911 .clk = "gpt8_ick",
981 .addr = omap3xxx_timer8_addrs, 912 .addr = omap3xxx_timer8_addrs,
982 .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
983 .user = OCP_USER_MPU | OCP_USER_SDMA, 913 .user = OCP_USER_MPU | OCP_USER_SDMA,
984}; 914};
985 915
@@ -991,8 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
991/* timer8 hwmod */ 921/* timer8 hwmod */
992static struct omap_hwmod omap3xxx_timer8_hwmod = { 922static struct omap_hwmod omap3xxx_timer8_hwmod = {
993 .name = "timer8", 923 .name = "timer8",
994 .mpu_irqs = omap3xxx_timer8_mpu_irqs, 924 .mpu_irqs = omap2_timer8_mpu_irqs,
995 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
996 .main_clk = "gpt8_fck", 925 .main_clk = "gpt8_fck",
997 .prcm = { 926 .prcm = {
998 .omap2 = { 927 .omap2 = {
@@ -1011,9 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
1011 940
1012/* timer9 */ 941/* timer9 */
1013static struct omap_hwmod omap3xxx_timer9_hwmod; 942static struct omap_hwmod omap3xxx_timer9_hwmod;
1014static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1015 { .irq = 45, },
1016};
1017 943
1018static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = { 944static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1019 { 945 {
@@ -1021,6 +947,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1021 .pa_end = 0x49040000 + SZ_1K - 1, 947 .pa_end = 0x49040000 + SZ_1K - 1,
1022 .flags = ADDR_TYPE_RT 948 .flags = ADDR_TYPE_RT
1023 }, 949 },
950 { }
1024}; 951};
1025 952
1026/* l4_per -> timer9 */ 953/* l4_per -> timer9 */
@@ -1029,7 +956,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1029 .slave = &omap3xxx_timer9_hwmod, 956 .slave = &omap3xxx_timer9_hwmod,
1030 .clk = "gpt9_ick", 957 .clk = "gpt9_ick",
1031 .addr = omap3xxx_timer9_addrs, 958 .addr = omap3xxx_timer9_addrs,
1032 .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
1033 .user = OCP_USER_MPU | OCP_USER_SDMA, 959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1034}; 960};
1035 961
@@ -1041,8 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1041/* timer9 hwmod */ 967/* timer9 hwmod */
1042static struct omap_hwmod omap3xxx_timer9_hwmod = { 968static struct omap_hwmod omap3xxx_timer9_hwmod = {
1043 .name = "timer9", 969 .name = "timer9",
1044 .mpu_irqs = omap3xxx_timer9_mpu_irqs, 970 .mpu_irqs = omap2_timer9_mpu_irqs,
1045 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1046 .main_clk = "gpt9_fck", 971 .main_clk = "gpt9_fck",
1047 .prcm = { 972 .prcm = {
1048 .omap2 = { 973 .omap2 = {
@@ -1061,25 +986,13 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
1061 986
1062/* timer10 */ 987/* timer10 */
1063static struct omap_hwmod omap3xxx_timer10_hwmod; 988static struct omap_hwmod omap3xxx_timer10_hwmod;
1064static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1065 { .irq = 46, },
1066};
1067
1068static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1069 {
1070 .pa_start = 0x48086000,
1071 .pa_end = 0x48086000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1073 },
1074};
1075 989
1076/* l4_core -> timer10 */ 990/* l4_core -> timer10 */
1077static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = { 991static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1078 .master = &omap3xxx_l4_core_hwmod, 992 .master = &omap3xxx_l4_core_hwmod,
1079 .slave = &omap3xxx_timer10_hwmod, 993 .slave = &omap3xxx_timer10_hwmod,
1080 .clk = "gpt10_ick", 994 .clk = "gpt10_ick",
1081 .addr = omap3xxx_timer10_addrs, 995 .addr = omap2_timer10_addrs,
1082 .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
1083 .user = OCP_USER_MPU | OCP_USER_SDMA, 996 .user = OCP_USER_MPU | OCP_USER_SDMA,
1084}; 997};
1085 998
@@ -1091,8 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1091/* timer10 hwmod */ 1004/* timer10 hwmod */
1092static struct omap_hwmod omap3xxx_timer10_hwmod = { 1005static struct omap_hwmod omap3xxx_timer10_hwmod = {
1093 .name = "timer10", 1006 .name = "timer10",
1094 .mpu_irqs = omap3xxx_timer10_mpu_irqs, 1007 .mpu_irqs = omap2_timer10_mpu_irqs,
1095 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1096 .main_clk = "gpt10_fck", 1008 .main_clk = "gpt10_fck",
1097 .prcm = { 1009 .prcm = {
1098 .omap2 = { 1010 .omap2 = {
@@ -1111,25 +1023,13 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
1111 1023
1112/* timer11 */ 1024/* timer11 */
1113static struct omap_hwmod omap3xxx_timer11_hwmod; 1025static struct omap_hwmod omap3xxx_timer11_hwmod;
1114static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1115 { .irq = 47, },
1116};
1117
1118static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1119 {
1120 .pa_start = 0x48088000,
1121 .pa_end = 0x48088000 + SZ_1K - 1,
1122 .flags = ADDR_TYPE_RT
1123 },
1124};
1125 1026
1126/* l4_core -> timer11 */ 1027/* l4_core -> timer11 */
1127static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = { 1028static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1128 .master = &omap3xxx_l4_core_hwmod, 1029 .master = &omap3xxx_l4_core_hwmod,
1129 .slave = &omap3xxx_timer11_hwmod, 1030 .slave = &omap3xxx_timer11_hwmod,
1130 .clk = "gpt11_ick", 1031 .clk = "gpt11_ick",
1131 .addr = omap3xxx_timer11_addrs, 1032 .addr = omap2_timer11_addrs,
1132 .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
1133 .user = OCP_USER_MPU | OCP_USER_SDMA, 1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1134}; 1034};
1135 1035
@@ -1141,8 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1141/* timer11 hwmod */ 1041/* timer11 hwmod */
1142static struct omap_hwmod omap3xxx_timer11_hwmod = { 1042static struct omap_hwmod omap3xxx_timer11_hwmod = {
1143 .name = "timer11", 1043 .name = "timer11",
1144 .mpu_irqs = omap3xxx_timer11_mpu_irqs, 1044 .mpu_irqs = omap2_timer11_mpu_irqs,
1145 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1146 .main_clk = "gpt11_fck", 1045 .main_clk = "gpt11_fck",
1147 .prcm = { 1046 .prcm = {
1148 .omap2 = { 1047 .omap2 = {
@@ -1163,6 +1062,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
1163static struct omap_hwmod omap3xxx_timer12_hwmod; 1062static struct omap_hwmod omap3xxx_timer12_hwmod;
1164static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = { 1063static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1165 { .irq = 95, }, 1064 { .irq = 95, },
1065 { .irq = -1 }
1166}; 1066};
1167 1067
1168static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = { 1068static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
@@ -1171,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1171 .pa_end = 0x48304000 + SZ_1K - 1, 1071 .pa_end = 0x48304000 + SZ_1K - 1,
1172 .flags = ADDR_TYPE_RT 1072 .flags = ADDR_TYPE_RT
1173 }, 1073 },
1074 { }
1174}; 1075};
1175 1076
1176/* l4_core -> timer12 */ 1077/* l4_core -> timer12 */
@@ -1179,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1179 .slave = &omap3xxx_timer12_hwmod, 1080 .slave = &omap3xxx_timer12_hwmod,
1180 .clk = "gpt12_ick", 1081 .clk = "gpt12_ick",
1181 .addr = omap3xxx_timer12_addrs, 1082 .addr = omap3xxx_timer12_addrs,
1182 .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
1183 .user = OCP_USER_MPU | OCP_USER_SDMA, 1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1184}; 1084};
1185 1085
@@ -1192,7 +1092,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1192static struct omap_hwmod omap3xxx_timer12_hwmod = { 1092static struct omap_hwmod omap3xxx_timer12_hwmod = {
1193 .name = "timer12", 1093 .name = "timer12",
1194 .mpu_irqs = omap3xxx_timer12_mpu_irqs, 1094 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1195 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1196 .main_clk = "gpt12_fck", 1095 .main_clk = "gpt12_fck",
1197 .prcm = { 1096 .prcm = {
1198 .omap2 = { 1097 .omap2 = {
@@ -1216,6 +1115,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1216 .pa_end = 0x4831407f, 1115 .pa_end = 0x4831407f,
1217 .flags = ADDR_TYPE_RT 1116 .flags = ADDR_TYPE_RT
1218 }, 1117 },
1118 { }
1219}; 1119};
1220 1120
1221static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = { 1121static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@@ -1223,7 +1123,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1223 .slave = &omap3xxx_wd_timer2_hwmod, 1123 .slave = &omap3xxx_wd_timer2_hwmod,
1224 .clk = "wdt2_ick", 1124 .clk = "wdt2_ick",
1225 .addr = omap3xxx_wd_timer2_addrs, 1125 .addr = omap3xxx_wd_timer2_addrs,
1226 .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
1227 .user = OCP_USER_MPU | OCP_USER_SDMA, 1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1228}; 1127};
1229 1128
@@ -1291,45 +1190,16 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1291 .flags = HWMOD_SWSUP_SIDLE, 1190 .flags = HWMOD_SWSUP_SIDLE,
1292}; 1191};
1293 1192
1294/* UART common */
1295
1296static struct omap_hwmod_class_sysconfig uart_sysc = {
1297 .rev_offs = 0x50,
1298 .sysc_offs = 0x54,
1299 .syss_offs = 0x58,
1300 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1301 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1302 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304 .sysc_fields = &omap_hwmod_sysc_type1,
1305};
1306
1307static struct omap_hwmod_class uart_class = {
1308 .name = "uart",
1309 .sysc = &uart_sysc,
1310};
1311
1312/* UART1 */ 1193/* UART1 */
1313 1194
1314static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1315 { .irq = INT_24XX_UART1_IRQ, },
1316};
1317
1318static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1319 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1320 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1321};
1322
1323static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = { 1195static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1324 &omap3_l4_core__uart1, 1196 &omap3_l4_core__uart1,
1325}; 1197};
1326 1198
1327static struct omap_hwmod omap3xxx_uart1_hwmod = { 1199static struct omap_hwmod omap3xxx_uart1_hwmod = {
1328 .name = "uart1", 1200 .name = "uart1",
1329 .mpu_irqs = uart1_mpu_irqs, 1201 .mpu_irqs = omap2_uart1_mpu_irqs,
1330 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs), 1202 .sdma_reqs = omap2_uart1_sdma_reqs,
1331 .sdma_reqs = uart1_sdma_reqs,
1332 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1333 .main_clk = "uart1_fck", 1203 .main_clk = "uart1_fck",
1334 .prcm = { 1204 .prcm = {
1335 .omap2 = { 1205 .omap2 = {
@@ -1342,31 +1212,20 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
1342 }, 1212 },
1343 .slaves = omap3xxx_uart1_slaves, 1213 .slaves = omap3xxx_uart1_slaves,
1344 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves), 1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1345 .class = &uart_class, 1215 .class = &omap2_uart_class,
1346 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1347}; 1217};
1348 1218
1349/* UART2 */ 1219/* UART2 */
1350 1220
1351static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1352 { .irq = INT_24XX_UART2_IRQ, },
1353};
1354
1355static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1356 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1357 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1358};
1359
1360static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = { 1221static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1361 &omap3_l4_core__uart2, 1222 &omap3_l4_core__uart2,
1362}; 1223};
1363 1224
1364static struct omap_hwmod omap3xxx_uart2_hwmod = { 1225static struct omap_hwmod omap3xxx_uart2_hwmod = {
1365 .name = "uart2", 1226 .name = "uart2",
1366 .mpu_irqs = uart2_mpu_irqs, 1227 .mpu_irqs = omap2_uart2_mpu_irqs,
1367 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs), 1228 .sdma_reqs = omap2_uart2_sdma_reqs,
1368 .sdma_reqs = uart2_sdma_reqs,
1369 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1370 .main_clk = "uart2_fck", 1229 .main_clk = "uart2_fck",
1371 .prcm = { 1230 .prcm = {
1372 .omap2 = { 1231 .omap2 = {
@@ -1379,31 +1238,20 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
1379 }, 1238 },
1380 .slaves = omap3xxx_uart2_slaves, 1239 .slaves = omap3xxx_uart2_slaves,
1381 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves), 1240 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1382 .class = &uart_class, 1241 .class = &omap2_uart_class,
1383 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1384}; 1243};
1385 1244
1386/* UART3 */ 1245/* UART3 */
1387 1246
1388static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1389 { .irq = INT_24XX_UART3_IRQ, },
1390};
1391
1392static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1393 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1394 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1395};
1396
1397static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = { 1247static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1398 &omap3_l4_per__uart3, 1248 &omap3_l4_per__uart3,
1399}; 1249};
1400 1250
1401static struct omap_hwmod omap3xxx_uart3_hwmod = { 1251static struct omap_hwmod omap3xxx_uart3_hwmod = {
1402 .name = "uart3", 1252 .name = "uart3",
1403 .mpu_irqs = uart3_mpu_irqs, 1253 .mpu_irqs = omap2_uart3_mpu_irqs,
1404 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs), 1254 .sdma_reqs = omap2_uart3_sdma_reqs,
1405 .sdma_reqs = uart3_sdma_reqs,
1406 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1407 .main_clk = "uart3_fck", 1255 .main_clk = "uart3_fck",
1408 .prcm = { 1256 .prcm = {
1409 .omap2 = { 1257 .omap2 = {
@@ -1416,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1416 }, 1264 },
1417 .slaves = omap3xxx_uart3_slaves, 1265 .slaves = omap3xxx_uart3_slaves,
1418 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves), 1266 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1419 .class = &uart_class, 1267 .class = &omap2_uart_class,
1420 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), 1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1421}; 1269};
1422 1270
@@ -1424,11 +1272,13 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
1424 1272
1425static struct omap_hwmod_irq_info uart4_mpu_irqs[] = { 1273static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1426 { .irq = INT_36XX_UART4_IRQ, }, 1274 { .irq = INT_36XX_UART4_IRQ, },
1275 { .irq = -1 }
1427}; 1276};
1428 1277
1429static struct omap_hwmod_dma_info uart4_sdma_reqs[] = { 1278static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1430 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, }, 1279 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1431 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, }, 1280 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1281 { .dma_req = -1 }
1432}; 1282};
1433 1283
1434static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = { 1284static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
@@ -1438,9 +1288,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1438static struct omap_hwmod omap3xxx_uart4_hwmod = { 1288static struct omap_hwmod omap3xxx_uart4_hwmod = {
1439 .name = "uart4", 1289 .name = "uart4",
1440 .mpu_irqs = uart4_mpu_irqs, 1290 .mpu_irqs = uart4_mpu_irqs,
1441 .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
1442 .sdma_reqs = uart4_sdma_reqs, 1291 .sdma_reqs = uart4_sdma_reqs,
1443 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1444 .main_clk = "uart4_fck", 1292 .main_clk = "uart4_fck",
1445 .prcm = { 1293 .prcm = {
1446 .omap2 = { 1294 .omap2 = {
@@ -1453,7 +1301,7 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
1453 }, 1301 },
1454 .slaves = omap3xxx_uart4_slaves, 1302 .slaves = omap3xxx_uart4_slaves,
1455 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves), 1303 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1456 .class = &uart_class, 1304 .class = &omap2_uart_class,
1457 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 1305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1458}; 1306};
1459 1307
@@ -1462,27 +1310,10 @@ static struct omap_hwmod_class i2c_class = {
1462 .sysc = &i2c_sysc, 1310 .sysc = &i2c_sysc,
1463}; 1311};
1464 1312
1465/*
1466 * 'dss' class
1467 * display sub-system
1468 */
1469
1470static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1471 .rev_offs = 0x0000,
1472 .sysc_offs = 0x0010,
1473 .syss_offs = 0x0014,
1474 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1475 .sysc_fields = &omap_hwmod_sysc_type1,
1476};
1477
1478static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1479 .name = "dss",
1480 .sysc = &omap3xxx_dss_sysc,
1481};
1482
1483static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = { 1313static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1484 { .name = "dispc", .dma_req = 5 }, 1314 { .name = "dispc", .dma_req = 5 },
1485 { .name = "dsi1", .dma_req = 74 }, 1315 { .name = "dsi1", .dma_req = 74 },
1316 { .dma_req = -1 }
1486}; 1317};
1487 1318
1488/* dss */ 1319/* dss */
@@ -1491,21 +1322,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1491 &omap3xxx_dss__l3, 1322 &omap3xxx_dss__l3,
1492}; 1323};
1493 1324
1494static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1495 {
1496 .pa_start = 0x48050000,
1497 .pa_end = 0x480503FF,
1498 .flags = ADDR_TYPE_RT
1499 },
1500};
1501
1502/* l4_core -> dss */ 1325/* l4_core -> dss */
1503static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = { 1326static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1504 .master = &omap3xxx_l4_core_hwmod, 1327 .master = &omap3xxx_l4_core_hwmod,
1505 .slave = &omap3430es1_dss_core_hwmod, 1328 .slave = &omap3430es1_dss_core_hwmod,
1506 .clk = "dss_ick", 1329 .clk = "dss_ick",
1507 .addr = omap3xxx_dss_addrs, 1330 .addr = omap2_dss_addrs,
1508 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1509 .fw = { 1331 .fw = {
1510 .omap2 = { 1332 .omap2 = {
1511 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION, 1333 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
@@ -1520,8 +1342,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1520 .master = &omap3xxx_l4_core_hwmod, 1342 .master = &omap3xxx_l4_core_hwmod,
1521 .slave = &omap3xxx_dss_core_hwmod, 1343 .slave = &omap3xxx_dss_core_hwmod,
1522 .clk = "dss_ick", 1344 .clk = "dss_ick",
1523 .addr = omap3xxx_dss_addrs, 1345 .addr = omap2_dss_addrs,
1524 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
1525 .fw = { 1346 .fw = {
1526 .omap2 = { 1347 .omap2 = {
1527 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION, 1348 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
@@ -1549,11 +1370,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1549 1370
1550static struct omap_hwmod omap3430es1_dss_core_hwmod = { 1371static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1551 .name = "dss_core", 1372 .name = "dss_core",
1552 .class = &omap3xxx_dss_hwmod_class, 1373 .class = &omap2_dss_hwmod_class,
1553 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1374 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1554 .sdma_reqs = omap3xxx_dss_sdma_chs, 1375 .sdma_reqs = omap3xxx_dss_sdma_chs,
1555 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1556
1557 .prcm = { 1376 .prcm = {
1558 .omap2 = { 1377 .omap2 = {
1559 .prcm_reg_id = 1, 1378 .prcm_reg_id = 1,
@@ -1575,11 +1394,9 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1575 1394
1576static struct omap_hwmod omap3xxx_dss_core_hwmod = { 1395static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1577 .name = "dss_core", 1396 .name = "dss_core",
1578 .class = &omap3xxx_dss_hwmod_class, 1397 .class = &omap2_dss_hwmod_class,
1579 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */ 1398 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1580 .sdma_reqs = omap3xxx_dss_sdma_chs, 1399 .sdma_reqs = omap3xxx_dss_sdma_chs,
1581 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1582
1583 .prcm = { 1400 .prcm = {
1584 .omap2 = { 1401 .omap2 = {
1585 .prcm_reg_id = 1, 1402 .prcm_reg_id = 1,
@@ -1600,47 +1417,12 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1600 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1), 1417 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1601}; 1418};
1602 1419
1603/*
1604 * 'dispc' class
1605 * display controller
1606 */
1607
1608static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1609 .rev_offs = 0x0000,
1610 .sysc_offs = 0x0010,
1611 .syss_offs = 0x0014,
1612 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1613 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1614 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1615 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1616 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1617 .sysc_fields = &omap_hwmod_sysc_type1,
1618};
1619
1620static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1621 .name = "dispc",
1622 .sysc = &omap3xxx_dispc_sysc,
1623};
1624
1625static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1626 { .irq = 25 },
1627};
1628
1629static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1630 {
1631 .pa_start = 0x48050400,
1632 .pa_end = 0x480507FF,
1633 .flags = ADDR_TYPE_RT
1634 },
1635};
1636
1637/* l4_core -> dss_dispc */ 1420/* l4_core -> dss_dispc */
1638static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = { 1421static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1639 .master = &omap3xxx_l4_core_hwmod, 1422 .master = &omap3xxx_l4_core_hwmod,
1640 .slave = &omap3xxx_dss_dispc_hwmod, 1423 .slave = &omap3xxx_dss_dispc_hwmod,
1641 .clk = "dss_ick", 1424 .clk = "dss_ick",
1642 .addr = omap3xxx_dss_dispc_addrs, 1425 .addr = omap2_dss_dispc_addrs,
1643 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
1644 .fw = { 1426 .fw = {
1645 .omap2 = { 1427 .omap2 = {
1646 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION, 1428 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1658,9 +1440,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1658 1440
1659static struct omap_hwmod omap3xxx_dss_dispc_hwmod = { 1441static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1660 .name = "dss_dispc", 1442 .name = "dss_dispc",
1661 .class = &omap3xxx_dispc_hwmod_class, 1443 .class = &omap2_dispc_hwmod_class,
1662 .mpu_irqs = omap3xxx_dispc_irqs, 1444 .mpu_irqs = omap2_dispc_irqs,
1663 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
1664 .main_clk = "dss1_alwon_fck", 1445 .main_clk = "dss1_alwon_fck",
1665 .prcm = { 1446 .prcm = {
1666 .omap2 = { 1447 .omap2 = {
@@ -1688,6 +1469,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1688 1469
1689static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = { 1470static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1690 { .irq = 25 }, 1471 { .irq = 25 },
1472 { .irq = -1 }
1691}; 1473};
1692 1474
1693/* dss_dsi1 */ 1475/* dss_dsi1 */
@@ -1697,6 +1479,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1697 .pa_end = 0x4804FFFF, 1479 .pa_end = 0x4804FFFF,
1698 .flags = ADDR_TYPE_RT 1480 .flags = ADDR_TYPE_RT
1699 }, 1481 },
1482 { }
1700}; 1483};
1701 1484
1702/* l4_core -> dss_dsi1 */ 1485/* l4_core -> dss_dsi1 */
@@ -1704,7 +1487,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1704 .master = &omap3xxx_l4_core_hwmod, 1487 .master = &omap3xxx_l4_core_hwmod,
1705 .slave = &omap3xxx_dss_dsi1_hwmod, 1488 .slave = &omap3xxx_dss_dsi1_hwmod,
1706 .addr = omap3xxx_dss_dsi1_addrs, 1489 .addr = omap3xxx_dss_dsi1_addrs,
1707 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
1708 .fw = { 1490 .fw = {
1709 .omap2 = { 1491 .omap2 = {
1710 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION, 1492 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
@@ -1724,7 +1506,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1724 .name = "dss_dsi1", 1506 .name = "dss_dsi1",
1725 .class = &omap3xxx_dsi_hwmod_class, 1507 .class = &omap3xxx_dsi_hwmod_class,
1726 .mpu_irqs = omap3xxx_dsi1_irqs, 1508 .mpu_irqs = omap3xxx_dsi1_irqs,
1727 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
1728 .main_clk = "dss1_alwon_fck", 1509 .main_clk = "dss1_alwon_fck",
1729 .prcm = { 1510 .prcm = {
1730 .omap2 = { 1511 .omap2 = {
@@ -1741,41 +1522,12 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1741 .flags = HWMOD_NO_IDLEST, 1522 .flags = HWMOD_NO_IDLEST,
1742}; 1523};
1743 1524
1744/*
1745 * 'rfbi' class
1746 * remote frame buffer interface
1747 */
1748
1749static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1750 .rev_offs = 0x0000,
1751 .sysc_offs = 0x0010,
1752 .syss_offs = 0x0014,
1753 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1754 SYSC_HAS_AUTOIDLE),
1755 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1756 .sysc_fields = &omap_hwmod_sysc_type1,
1757};
1758
1759static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1760 .name = "rfbi",
1761 .sysc = &omap3xxx_rfbi_sysc,
1762};
1763
1764static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1765 {
1766 .pa_start = 0x48050800,
1767 .pa_end = 0x48050BFF,
1768 .flags = ADDR_TYPE_RT
1769 },
1770};
1771
1772/* l4_core -> dss_rfbi */ 1525/* l4_core -> dss_rfbi */
1773static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = { 1526static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1774 .master = &omap3xxx_l4_core_hwmod, 1527 .master = &omap3xxx_l4_core_hwmod,
1775 .slave = &omap3xxx_dss_rfbi_hwmod, 1528 .slave = &omap3xxx_dss_rfbi_hwmod,
1776 .clk = "dss_ick", 1529 .clk = "dss_ick",
1777 .addr = omap3xxx_dss_rfbi_addrs, 1530 .addr = omap2_dss_rfbi_addrs,
1778 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
1779 .fw = { 1531 .fw = {
1780 .omap2 = { 1532 .omap2 = {
1781 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION, 1533 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
@@ -1793,7 +1545,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1793 1545
1794static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = { 1546static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1795 .name = "dss_rfbi", 1547 .name = "dss_rfbi",
1796 .class = &omap3xxx_rfbi_hwmod_class, 1548 .class = &omap2_rfbi_hwmod_class,
1797 .main_clk = "dss1_alwon_fck", 1549 .main_clk = "dss1_alwon_fck",
1798 .prcm = { 1550 .prcm = {
1799 .omap2 = { 1551 .omap2 = {
@@ -1810,31 +1562,12 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1810 .flags = HWMOD_NO_IDLEST, 1562 .flags = HWMOD_NO_IDLEST,
1811}; 1563};
1812 1564
1813/*
1814 * 'venc' class
1815 * video encoder
1816 */
1817
1818static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1819 .name = "venc",
1820};
1821
1822/* dss_venc */
1823static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1824 {
1825 .pa_start = 0x48050C00,
1826 .pa_end = 0x48050FFF,
1827 .flags = ADDR_TYPE_RT
1828 },
1829};
1830
1831/* l4_core -> dss_venc */ 1565/* l4_core -> dss_venc */
1832static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = { 1566static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1833 .master = &omap3xxx_l4_core_hwmod, 1567 .master = &omap3xxx_l4_core_hwmod,
1834 .slave = &omap3xxx_dss_venc_hwmod, 1568 .slave = &omap3xxx_dss_venc_hwmod,
1835 .clk = "dss_tv_fck", 1569 .clk = "dss_tv_fck",
1836 .addr = omap3xxx_dss_venc_addrs, 1570 .addr = omap2_dss_venc_addrs,
1837 .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
1838 .fw = { 1571 .fw = {
1839 .omap2 = { 1572 .omap2 = {
1840 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION, 1573 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
@@ -1853,7 +1586,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1853 1586
1854static struct omap_hwmod omap3xxx_dss_venc_hwmod = { 1587static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1855 .name = "dss_venc", 1588 .name = "dss_venc",
1856 .class = &omap3xxx_venc_hwmod_class, 1589 .class = &omap2_venc_hwmod_class,
1857 .main_clk = "dss1_alwon_fck", 1590 .main_clk = "dss1_alwon_fck",
1858 .prcm = { 1591 .prcm = {
1859 .omap2 = { 1592 .omap2 = {
@@ -1876,25 +1609,14 @@ static struct omap_i2c_dev_attr i2c1_dev_attr = {
1876 .fifo_depth = 8, /* bytes */ 1609 .fifo_depth = 8, /* bytes */
1877}; 1610};
1878 1611
1879static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1880 { .irq = INT_24XX_I2C1_IRQ, },
1881};
1882
1883static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1884 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1885 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1886};
1887
1888static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { 1612static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1889 &omap3_l4_core__i2c1, 1613 &omap3_l4_core__i2c1,
1890}; 1614};
1891 1615
1892static struct omap_hwmod omap3xxx_i2c1_hwmod = { 1616static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1893 .name = "i2c1", 1617 .name = "i2c1",
1894 .mpu_irqs = i2c1_mpu_irqs, 1618 .mpu_irqs = omap2_i2c1_mpu_irqs,
1895 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), 1619 .sdma_reqs = omap2_i2c1_sdma_reqs,
1896 .sdma_reqs = i2c1_sdma_reqs,
1897 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1898 .main_clk = "i2c1_fck", 1620 .main_clk = "i2c1_fck",
1899 .prcm = { 1621 .prcm = {
1900 .omap2 = { 1622 .omap2 = {
@@ -1918,25 +1640,14 @@ static struct omap_i2c_dev_attr i2c2_dev_attr = {
1918 .fifo_depth = 8, /* bytes */ 1640 .fifo_depth = 8, /* bytes */
1919}; 1641};
1920 1642
1921static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1922 { .irq = INT_24XX_I2C2_IRQ, },
1923};
1924
1925static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1926 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1927 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1928};
1929
1930static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { 1643static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1931 &omap3_l4_core__i2c2, 1644 &omap3_l4_core__i2c2,
1932}; 1645};
1933 1646
1934static struct omap_hwmod omap3xxx_i2c2_hwmod = { 1647static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1935 .name = "i2c2", 1648 .name = "i2c2",
1936 .mpu_irqs = i2c2_mpu_irqs, 1649 .mpu_irqs = omap2_i2c2_mpu_irqs,
1937 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), 1650 .sdma_reqs = omap2_i2c2_sdma_reqs,
1938 .sdma_reqs = i2c2_sdma_reqs,
1939 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1940 .main_clk = "i2c2_fck", 1651 .main_clk = "i2c2_fck",
1941 .prcm = { 1652 .prcm = {
1942 .omap2 = { 1653 .omap2 = {
@@ -1962,11 +1673,13 @@ static struct omap_i2c_dev_attr i2c3_dev_attr = {
1962 1673
1963static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { 1674static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1964 { .irq = INT_34XX_I2C3_IRQ, }, 1675 { .irq = INT_34XX_I2C3_IRQ, },
1676 { .irq = -1 }
1965}; 1677};
1966 1678
1967static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { 1679static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1968 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, 1680 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1969 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, 1681 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1682 { .dma_req = -1 }
1970}; 1683};
1971 1684
1972static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { 1685static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
@@ -1976,9 +1689,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1976static struct omap_hwmod omap3xxx_i2c3_hwmod = { 1689static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1977 .name = "i2c3", 1690 .name = "i2c3",
1978 .mpu_irqs = i2c3_mpu_irqs, 1691 .mpu_irqs = i2c3_mpu_irqs,
1979 .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
1980 .sdma_reqs = i2c3_sdma_reqs, 1692 .sdma_reqs = i2c3_sdma_reqs,
1981 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1982 .main_clk = "i2c3_fck", 1693 .main_clk = "i2c3_fck",
1983 .prcm = { 1694 .prcm = {
1984 .omap2 = { 1695 .omap2 = {
@@ -2003,13 +1714,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2003 .pa_end = 0x483101ff, 1714 .pa_end = 0x483101ff,
2004 .flags = ADDR_TYPE_RT 1715 .flags = ADDR_TYPE_RT
2005 }, 1716 },
1717 { }
2006}; 1718};
2007 1719
2008static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = { 1720static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2009 .master = &omap3xxx_l4_wkup_hwmod, 1721 .master = &omap3xxx_l4_wkup_hwmod,
2010 .slave = &omap3xxx_gpio1_hwmod, 1722 .slave = &omap3xxx_gpio1_hwmod,
2011 .addr = omap3xxx_gpio1_addrs, 1723 .addr = omap3xxx_gpio1_addrs,
2012 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
2013 .user = OCP_USER_MPU | OCP_USER_SDMA, 1724 .user = OCP_USER_MPU | OCP_USER_SDMA,
2014}; 1725};
2015 1726
@@ -2020,13 +1731,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2020 .pa_end = 0x490501ff, 1731 .pa_end = 0x490501ff,
2021 .flags = ADDR_TYPE_RT 1732 .flags = ADDR_TYPE_RT
2022 }, 1733 },
1734 { }
2023}; 1735};
2024 1736
2025static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = { 1737static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2026 .master = &omap3xxx_l4_per_hwmod, 1738 .master = &omap3xxx_l4_per_hwmod,
2027 .slave = &omap3xxx_gpio2_hwmod, 1739 .slave = &omap3xxx_gpio2_hwmod,
2028 .addr = omap3xxx_gpio2_addrs, 1740 .addr = omap3xxx_gpio2_addrs,
2029 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
2030 .user = OCP_USER_MPU | OCP_USER_SDMA, 1741 .user = OCP_USER_MPU | OCP_USER_SDMA,
2031}; 1742};
2032 1743
@@ -2037,13 +1748,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2037 .pa_end = 0x490521ff, 1748 .pa_end = 0x490521ff,
2038 .flags = ADDR_TYPE_RT 1749 .flags = ADDR_TYPE_RT
2039 }, 1750 },
1751 { }
2040}; 1752};
2041 1753
2042static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = { 1754static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2043 .master = &omap3xxx_l4_per_hwmod, 1755 .master = &omap3xxx_l4_per_hwmod,
2044 .slave = &omap3xxx_gpio3_hwmod, 1756 .slave = &omap3xxx_gpio3_hwmod,
2045 .addr = omap3xxx_gpio3_addrs, 1757 .addr = omap3xxx_gpio3_addrs,
2046 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
2047 .user = OCP_USER_MPU | OCP_USER_SDMA, 1758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2048}; 1759};
2049 1760
@@ -2054,13 +1765,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2054 .pa_end = 0x490541ff, 1765 .pa_end = 0x490541ff,
2055 .flags = ADDR_TYPE_RT 1766 .flags = ADDR_TYPE_RT
2056 }, 1767 },
1768 { }
2057}; 1769};
2058 1770
2059static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = { 1771static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2060 .master = &omap3xxx_l4_per_hwmod, 1772 .master = &omap3xxx_l4_per_hwmod,
2061 .slave = &omap3xxx_gpio4_hwmod, 1773 .slave = &omap3xxx_gpio4_hwmod,
2062 .addr = omap3xxx_gpio4_addrs, 1774 .addr = omap3xxx_gpio4_addrs,
2063 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
2064 .user = OCP_USER_MPU | OCP_USER_SDMA, 1775 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065}; 1776};
2066 1777
@@ -2071,13 +1782,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2071 .pa_end = 0x490561ff, 1782 .pa_end = 0x490561ff,
2072 .flags = ADDR_TYPE_RT 1783 .flags = ADDR_TYPE_RT
2073 }, 1784 },
1785 { }
2074}; 1786};
2075 1787
2076static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = { 1788static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2077 .master = &omap3xxx_l4_per_hwmod, 1789 .master = &omap3xxx_l4_per_hwmod,
2078 .slave = &omap3xxx_gpio5_hwmod, 1790 .slave = &omap3xxx_gpio5_hwmod,
2079 .addr = omap3xxx_gpio5_addrs, 1791 .addr = omap3xxx_gpio5_addrs,
2080 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
2081 .user = OCP_USER_MPU | OCP_USER_SDMA, 1792 .user = OCP_USER_MPU | OCP_USER_SDMA,
2082}; 1793};
2083 1794
@@ -2088,13 +1799,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2088 .pa_end = 0x490581ff, 1799 .pa_end = 0x490581ff,
2089 .flags = ADDR_TYPE_RT 1800 .flags = ADDR_TYPE_RT
2090 }, 1801 },
1802 { }
2091}; 1803};
2092 1804
2093static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = { 1805static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2094 .master = &omap3xxx_l4_per_hwmod, 1806 .master = &omap3xxx_l4_per_hwmod,
2095 .slave = &omap3xxx_gpio6_hwmod, 1807 .slave = &omap3xxx_gpio6_hwmod,
2096 .addr = omap3xxx_gpio6_addrs, 1808 .addr = omap3xxx_gpio6_addrs,
2097 .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
2098 .user = OCP_USER_MPU | OCP_USER_SDMA, 1809 .user = OCP_USER_MPU | OCP_USER_SDMA,
2099}; 1810};
2100 1811
@@ -2127,10 +1838,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
2127}; 1838};
2128 1839
2129/* gpio1 */ 1840/* gpio1 */
2130static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2131 { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2132};
2133
2134static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 1841static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2135 { .role = "dbclk", .clk = "gpio1_dbck", }, 1842 { .role = "dbclk", .clk = "gpio1_dbck", },
2136}; 1843};
@@ -2142,8 +1849,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2142static struct omap_hwmod omap3xxx_gpio1_hwmod = { 1849static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2143 .name = "gpio1", 1850 .name = "gpio1",
2144 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1851 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2145 .mpu_irqs = omap3xxx_gpio1_irqs, 1852 .mpu_irqs = omap2_gpio1_irqs,
2146 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2147 .main_clk = "gpio1_ick", 1853 .main_clk = "gpio1_ick",
2148 .opt_clks = gpio1_opt_clks, 1854 .opt_clks = gpio1_opt_clks,
2149 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 1855 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
@@ -2164,10 +1870,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2164}; 1870};
2165 1871
2166/* gpio2 */ 1872/* gpio2 */
2167static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2168 { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2169};
2170
2171static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 1873static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2172 { .role = "dbclk", .clk = "gpio2_dbck", }, 1874 { .role = "dbclk", .clk = "gpio2_dbck", },
2173}; 1875};
@@ -2179,8 +1881,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2179static struct omap_hwmod omap3xxx_gpio2_hwmod = { 1881static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2180 .name = "gpio2", 1882 .name = "gpio2",
2181 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1883 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2182 .mpu_irqs = omap3xxx_gpio2_irqs, 1884 .mpu_irqs = omap2_gpio2_irqs,
2183 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2184 .main_clk = "gpio2_ick", 1885 .main_clk = "gpio2_ick",
2185 .opt_clks = gpio2_opt_clks, 1886 .opt_clks = gpio2_opt_clks,
2186 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 1887 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
@@ -2201,10 +1902,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2201}; 1902};
2202 1903
2203/* gpio3 */ 1904/* gpio3 */
2204static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2205 { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2206};
2207
2208static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 1905static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2209 { .role = "dbclk", .clk = "gpio3_dbck", }, 1906 { .role = "dbclk", .clk = "gpio3_dbck", },
2210}; 1907};
@@ -2216,8 +1913,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2216static struct omap_hwmod omap3xxx_gpio3_hwmod = { 1913static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2217 .name = "gpio3", 1914 .name = "gpio3",
2218 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1915 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2219 .mpu_irqs = omap3xxx_gpio3_irqs, 1916 .mpu_irqs = omap2_gpio3_irqs,
2220 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2221 .main_clk = "gpio3_ick", 1917 .main_clk = "gpio3_ick",
2222 .opt_clks = gpio3_opt_clks, 1918 .opt_clks = gpio3_opt_clks,
2223 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 1919 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
@@ -2238,10 +1934,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2238}; 1934};
2239 1935
2240/* gpio4 */ 1936/* gpio4 */
2241static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2242 { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2243};
2244
2245static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 1937static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2246 { .role = "dbclk", .clk = "gpio4_dbck", }, 1938 { .role = "dbclk", .clk = "gpio4_dbck", },
2247}; 1939};
@@ -2253,8 +1945,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2253static struct omap_hwmod omap3xxx_gpio4_hwmod = { 1945static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2254 .name = "gpio4", 1946 .name = "gpio4",
2255 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1947 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2256 .mpu_irqs = omap3xxx_gpio4_irqs, 1948 .mpu_irqs = omap2_gpio4_irqs,
2257 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2258 .main_clk = "gpio4_ick", 1949 .main_clk = "gpio4_ick",
2259 .opt_clks = gpio4_opt_clks, 1950 .opt_clks = gpio4_opt_clks,
2260 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 1951 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
@@ -2277,6 +1968,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2277/* gpio5 */ 1968/* gpio5 */
2278static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = { 1969static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2279 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */ 1970 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1971 { .irq = -1 }
2280}; 1972};
2281 1973
2282static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1974static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -2291,7 +1983,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2291 .name = "gpio5", 1983 .name = "gpio5",
2292 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1984 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2293 .mpu_irqs = omap3xxx_gpio5_irqs, 1985 .mpu_irqs = omap3xxx_gpio5_irqs,
2294 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2295 .main_clk = "gpio5_ick", 1986 .main_clk = "gpio5_ick",
2296 .opt_clks = gpio5_opt_clks, 1987 .opt_clks = gpio5_opt_clks,
2297 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 1988 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
@@ -2314,6 +2005,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2314/* gpio6 */ 2005/* gpio6 */
2315static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = { 2006static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2316 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */ 2007 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2008 { .irq = -1 }
2317}; 2009};
2318 2010
2319static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { 2011static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -2328,7 +2020,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2328 .name = "gpio6", 2020 .name = "gpio6",
2329 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2021 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2330 .mpu_irqs = omap3xxx_gpio6_irqs, 2022 .mpu_irqs = omap3xxx_gpio6_irqs,
2331 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2332 .main_clk = "gpio6_ick", 2023 .main_clk = "gpio6_ick",
2333 .opt_clks = gpio6_opt_clks, 2024 .opt_clks = gpio6_opt_clks,
2334 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), 2025 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
@@ -2382,19 +2073,13 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2382}; 2073};
2383 2074
2384/* dma_system */ 2075/* dma_system */
2385static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2386 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2387 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2388 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2389 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2390};
2391
2392static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = { 2076static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2393 { 2077 {
2394 .pa_start = 0x48056000, 2078 .pa_start = 0x48056000,
2395 .pa_end = 0x48056fff, 2079 .pa_end = 0x48056fff,
2396 .flags = ADDR_TYPE_RT 2080 .flags = ADDR_TYPE_RT
2397 }, 2081 },
2082 { }
2398}; 2083};
2399 2084
2400/* dma_system master ports */ 2085/* dma_system master ports */
@@ -2408,7 +2093,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2408 .slave = &omap3xxx_dma_system_hwmod, 2093 .slave = &omap3xxx_dma_system_hwmod,
2409 .clk = "core_l4_ick", 2094 .clk = "core_l4_ick",
2410 .addr = omap3xxx_dma_system_addrs, 2095 .addr = omap3xxx_dma_system_addrs,
2411 .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
2412 .user = OCP_USER_MPU | OCP_USER_SDMA, 2096 .user = OCP_USER_MPU | OCP_USER_SDMA,
2413}; 2097};
2414 2098
@@ -2420,8 +2104,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2420static struct omap_hwmod omap3xxx_dma_system_hwmod = { 2104static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2421 .name = "dma", 2105 .name = "dma",
2422 .class = &omap3xxx_dma_hwmod_class, 2106 .class = &omap3xxx_dma_hwmod_class,
2423 .mpu_irqs = omap3xxx_dma_system_irqs, 2107 .mpu_irqs = omap2_dma_system_irqs,
2424 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2425 .main_clk = "core_l3_ick", 2108 .main_clk = "core_l3_ick",
2426 .prcm = { 2109 .prcm = {
2427 .omap2 = { 2110 .omap2 = {
@@ -2466,11 +2149,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2466 { .name = "irq", .irq = 16 }, 2149 { .name = "irq", .irq = 16 },
2467 { .name = "tx", .irq = 59 }, 2150 { .name = "tx", .irq = 59 },
2468 { .name = "rx", .irq = 60 }, 2151 { .name = "rx", .irq = 60 },
2469}; 2152 { .irq = -1 }
2470
2471static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2472 { .name = "rx", .dma_req = 32 },
2473 { .name = "tx", .dma_req = 31 },
2474}; 2153};
2475 2154
2476static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = { 2155static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
@@ -2480,6 +2159,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2480 .pa_end = 0x480740ff, 2159 .pa_end = 0x480740ff,
2481 .flags = ADDR_TYPE_RT 2160 .flags = ADDR_TYPE_RT
2482 }, 2161 },
2162 { }
2483}; 2163};
2484 2164
2485/* l4_core -> mcbsp1 */ 2165/* l4_core -> mcbsp1 */
@@ -2488,7 +2168,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2488 .slave = &omap3xxx_mcbsp1_hwmod, 2168 .slave = &omap3xxx_mcbsp1_hwmod,
2489 .clk = "mcbsp1_ick", 2169 .clk = "mcbsp1_ick",
2490 .addr = omap3xxx_mcbsp1_addrs, 2170 .addr = omap3xxx_mcbsp1_addrs,
2491 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2492 .user = OCP_USER_MPU | OCP_USER_SDMA, 2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493}; 2172};
2494 2173
@@ -2501,9 +2180,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2501 .name = "mcbsp1", 2180 .name = "mcbsp1",
2502 .class = &omap3xxx_mcbsp_hwmod_class, 2181 .class = &omap3xxx_mcbsp_hwmod_class,
2503 .mpu_irqs = omap3xxx_mcbsp1_irqs, 2182 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2504 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs), 2183 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2505 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2506 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2507 .main_clk = "mcbsp1_fck", 2184 .main_clk = "mcbsp1_fck",
2508 .prcm = { 2185 .prcm = {
2509 .omap2 = { 2186 .omap2 = {
@@ -2524,11 +2201,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2524 { .name = "irq", .irq = 17 }, 2201 { .name = "irq", .irq = 17 },
2525 { .name = "tx", .irq = 62 }, 2202 { .name = "tx", .irq = 62 },
2526 { .name = "rx", .irq = 63 }, 2203 { .name = "rx", .irq = 63 },
2527}; 2204 { .irq = -1 }
2528
2529static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2530 { .name = "rx", .dma_req = 34 },
2531 { .name = "tx", .dma_req = 33 },
2532}; 2205};
2533 2206
2534static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = { 2207static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
@@ -2538,6 +2211,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2538 .pa_end = 0x490220ff, 2211 .pa_end = 0x490220ff,
2539 .flags = ADDR_TYPE_RT 2212 .flags = ADDR_TYPE_RT
2540 }, 2213 },
2214 { }
2541}; 2215};
2542 2216
2543/* l4_per -> mcbsp2 */ 2217/* l4_per -> mcbsp2 */
@@ -2546,7 +2220,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2546 .slave = &omap3xxx_mcbsp2_hwmod, 2220 .slave = &omap3xxx_mcbsp2_hwmod,
2547 .clk = "mcbsp2_ick", 2221 .clk = "mcbsp2_ick",
2548 .addr = omap3xxx_mcbsp2_addrs, 2222 .addr = omap3xxx_mcbsp2_addrs,
2549 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2550 .user = OCP_USER_MPU | OCP_USER_SDMA, 2223 .user = OCP_USER_MPU | OCP_USER_SDMA,
2551}; 2224};
2552 2225
@@ -2563,9 +2236,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2563 .name = "mcbsp2", 2236 .name = "mcbsp2",
2564 .class = &omap3xxx_mcbsp_hwmod_class, 2237 .class = &omap3xxx_mcbsp_hwmod_class,
2565 .mpu_irqs = omap3xxx_mcbsp2_irqs, 2238 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2566 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs), 2239 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2567 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2568 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2569 .main_clk = "mcbsp2_fck", 2240 .main_clk = "mcbsp2_fck",
2570 .prcm = { 2241 .prcm = {
2571 .omap2 = { 2242 .omap2 = {
@@ -2587,11 +2258,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2587 { .name = "irq", .irq = 22 }, 2258 { .name = "irq", .irq = 22 },
2588 { .name = "tx", .irq = 89 }, 2259 { .name = "tx", .irq = 89 },
2589 { .name = "rx", .irq = 90 }, 2260 { .name = "rx", .irq = 90 },
2590}; 2261 { .irq = -1 }
2591
2592static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2593 { .name = "rx", .dma_req = 18 },
2594 { .name = "tx", .dma_req = 17 },
2595}; 2262};
2596 2263
2597static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = { 2264static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
@@ -2601,6 +2268,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2601 .pa_end = 0x490240ff, 2268 .pa_end = 0x490240ff,
2602 .flags = ADDR_TYPE_RT 2269 .flags = ADDR_TYPE_RT
2603 }, 2270 },
2271 { }
2604}; 2272};
2605 2273
2606/* l4_per -> mcbsp3 */ 2274/* l4_per -> mcbsp3 */
@@ -2609,7 +2277,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2609 .slave = &omap3xxx_mcbsp3_hwmod, 2277 .slave = &omap3xxx_mcbsp3_hwmod,
2610 .clk = "mcbsp3_ick", 2278 .clk = "mcbsp3_ick",
2611 .addr = omap3xxx_mcbsp3_addrs, 2279 .addr = omap3xxx_mcbsp3_addrs,
2612 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2613 .user = OCP_USER_MPU | OCP_USER_SDMA, 2280 .user = OCP_USER_MPU | OCP_USER_SDMA,
2614}; 2281};
2615 2282
@@ -2626,9 +2293,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2626 .name = "mcbsp3", 2293 .name = "mcbsp3",
2627 .class = &omap3xxx_mcbsp_hwmod_class, 2294 .class = &omap3xxx_mcbsp_hwmod_class,
2628 .mpu_irqs = omap3xxx_mcbsp3_irqs, 2295 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2629 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs), 2296 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2630 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2631 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2632 .main_clk = "mcbsp3_fck", 2297 .main_clk = "mcbsp3_fck",
2633 .prcm = { 2298 .prcm = {
2634 .omap2 = { 2299 .omap2 = {
@@ -2650,11 +2315,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2650 { .name = "irq", .irq = 23 }, 2315 { .name = "irq", .irq = 23 },
2651 { .name = "tx", .irq = 54 }, 2316 { .name = "tx", .irq = 54 },
2652 { .name = "rx", .irq = 55 }, 2317 { .name = "rx", .irq = 55 },
2318 { .irq = -1 }
2653}; 2319};
2654 2320
2655static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = { 2321static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2656 { .name = "rx", .dma_req = 20 }, 2322 { .name = "rx", .dma_req = 20 },
2657 { .name = "tx", .dma_req = 19 }, 2323 { .name = "tx", .dma_req = 19 },
2324 { .dma_req = -1 }
2658}; 2325};
2659 2326
2660static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = { 2327static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
@@ -2664,6 +2331,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2664 .pa_end = 0x490260ff, 2331 .pa_end = 0x490260ff,
2665 .flags = ADDR_TYPE_RT 2332 .flags = ADDR_TYPE_RT
2666 }, 2333 },
2334 { }
2667}; 2335};
2668 2336
2669/* l4_per -> mcbsp4 */ 2337/* l4_per -> mcbsp4 */
@@ -2672,7 +2340,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2672 .slave = &omap3xxx_mcbsp4_hwmod, 2340 .slave = &omap3xxx_mcbsp4_hwmod,
2673 .clk = "mcbsp4_ick", 2341 .clk = "mcbsp4_ick",
2674 .addr = omap3xxx_mcbsp4_addrs, 2342 .addr = omap3xxx_mcbsp4_addrs,
2675 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2676 .user = OCP_USER_MPU | OCP_USER_SDMA, 2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677}; 2344};
2678 2345
@@ -2685,9 +2352,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2685 .name = "mcbsp4", 2352 .name = "mcbsp4",
2686 .class = &omap3xxx_mcbsp_hwmod_class, 2353 .class = &omap3xxx_mcbsp_hwmod_class,
2687 .mpu_irqs = omap3xxx_mcbsp4_irqs, 2354 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2688 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2689 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs, 2355 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2690 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2691 .main_clk = "mcbsp4_fck", 2356 .main_clk = "mcbsp4_fck",
2692 .prcm = { 2357 .prcm = {
2693 .omap2 = { 2358 .omap2 = {
@@ -2708,11 +2373,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2708 { .name = "irq", .irq = 27 }, 2373 { .name = "irq", .irq = 27 },
2709 { .name = "tx", .irq = 81 }, 2374 { .name = "tx", .irq = 81 },
2710 { .name = "rx", .irq = 82 }, 2375 { .name = "rx", .irq = 82 },
2376 { .irq = -1 }
2711}; 2377};
2712 2378
2713static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = { 2379static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2714 { .name = "rx", .dma_req = 22 }, 2380 { .name = "rx", .dma_req = 22 },
2715 { .name = "tx", .dma_req = 21 }, 2381 { .name = "tx", .dma_req = 21 },
2382 { .dma_req = -1 }
2716}; 2383};
2717 2384
2718static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = { 2385static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
@@ -2722,6 +2389,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2722 .pa_end = 0x480960ff, 2389 .pa_end = 0x480960ff,
2723 .flags = ADDR_TYPE_RT 2390 .flags = ADDR_TYPE_RT
2724 }, 2391 },
2392 { }
2725}; 2393};
2726 2394
2727/* l4_core -> mcbsp5 */ 2395/* l4_core -> mcbsp5 */
@@ -2730,7 +2398,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2730 .slave = &omap3xxx_mcbsp5_hwmod, 2398 .slave = &omap3xxx_mcbsp5_hwmod,
2731 .clk = "mcbsp5_ick", 2399 .clk = "mcbsp5_ick",
2732 .addr = omap3xxx_mcbsp5_addrs, 2400 .addr = omap3xxx_mcbsp5_addrs,
2733 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2734 .user = OCP_USER_MPU | OCP_USER_SDMA, 2401 .user = OCP_USER_MPU | OCP_USER_SDMA,
2735}; 2402};
2736 2403
@@ -2743,9 +2410,7 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2743 .name = "mcbsp5", 2410 .name = "mcbsp5",
2744 .class = &omap3xxx_mcbsp_hwmod_class, 2411 .class = &omap3xxx_mcbsp_hwmod_class,
2745 .mpu_irqs = omap3xxx_mcbsp5_irqs, 2412 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2746 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2747 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs, 2413 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2748 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2749 .main_clk = "mcbsp5_fck", 2414 .main_clk = "mcbsp5_fck",
2750 .prcm = { 2415 .prcm = {
2751 .omap2 = { 2416 .omap2 = {
@@ -2776,6 +2441,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2776/* mcbsp2_sidetone */ 2441/* mcbsp2_sidetone */
2777static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = { 2442static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2778 { .name = "irq", .irq = 4 }, 2443 { .name = "irq", .irq = 4 },
2444 { .irq = -1 }
2779}; 2445};
2780 2446
2781static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = { 2447static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
@@ -2785,6 +2451,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2785 .pa_end = 0x490280ff, 2451 .pa_end = 0x490280ff,
2786 .flags = ADDR_TYPE_RT 2452 .flags = ADDR_TYPE_RT
2787 }, 2453 },
2454 { }
2788}; 2455};
2789 2456
2790/* l4_per -> mcbsp2_sidetone */ 2457/* l4_per -> mcbsp2_sidetone */
@@ -2793,7 +2460,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2793 .slave = &omap3xxx_mcbsp2_sidetone_hwmod, 2460 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2794 .clk = "mcbsp2_ick", 2461 .clk = "mcbsp2_ick",
2795 .addr = omap3xxx_mcbsp2_sidetone_addrs, 2462 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2796 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2797 .user = OCP_USER_MPU, 2463 .user = OCP_USER_MPU,
2798}; 2464};
2799 2465
@@ -2806,7 +2472,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2806 .name = "mcbsp2_sidetone", 2472 .name = "mcbsp2_sidetone",
2807 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2473 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2808 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs, 2474 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2809 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2810 .main_clk = "mcbsp2_fck", 2475 .main_clk = "mcbsp2_fck",
2811 .prcm = { 2476 .prcm = {
2812 .omap2 = { 2477 .omap2 = {
@@ -2825,6 +2490,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2825/* mcbsp3_sidetone */ 2490/* mcbsp3_sidetone */
2826static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = { 2491static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2827 { .name = "irq", .irq = 5 }, 2492 { .name = "irq", .irq = 5 },
2493 { .irq = -1 }
2828}; 2494};
2829 2495
2830static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = { 2496static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
@@ -2834,6 +2500,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2834 .pa_end = 0x4902A0ff, 2500 .pa_end = 0x4902A0ff,
2835 .flags = ADDR_TYPE_RT 2501 .flags = ADDR_TYPE_RT
2836 }, 2502 },
2503 { }
2837}; 2504};
2838 2505
2839/* l4_per -> mcbsp3_sidetone */ 2506/* l4_per -> mcbsp3_sidetone */
@@ -2842,7 +2509,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2842 .slave = &omap3xxx_mcbsp3_sidetone_hwmod, 2509 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2843 .clk = "mcbsp3_ick", 2510 .clk = "mcbsp3_ick",
2844 .addr = omap3xxx_mcbsp3_sidetone_addrs, 2511 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2845 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2846 .user = OCP_USER_MPU, 2512 .user = OCP_USER_MPU,
2847}; 2513};
2848 2514
@@ -2855,7 +2521,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2855 .name = "mcbsp3_sidetone", 2521 .name = "mcbsp3_sidetone",
2856 .class = &omap3xxx_mcbsp_sidetone_hwmod_class, 2522 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2857 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs, 2523 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2858 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2859 .main_clk = "mcbsp3_fck", 2524 .main_clk = "mcbsp3_fck",
2860 .prcm = { 2525 .prcm = {
2861 .omap2 = { 2526 .omap2 = {
@@ -3025,6 +2690,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3025static struct omap_hwmod omap3xxx_mailbox_hwmod; 2690static struct omap_hwmod omap3xxx_mailbox_hwmod;
3026static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = { 2691static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3027 { .irq = 26 }, 2692 { .irq = 26 },
2693 { .irq = -1 }
3028}; 2694};
3029 2695
3030static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = { 2696static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
@@ -3033,6 +2699,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3033 .pa_end = 0x480941ff, 2699 .pa_end = 0x480941ff,
3034 .flags = ADDR_TYPE_RT, 2700 .flags = ADDR_TYPE_RT,
3035 }, 2701 },
2702 { }
3036}; 2703};
3037 2704
3038/* l4_core -> mailbox */ 2705/* l4_core -> mailbox */
@@ -3040,7 +2707,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3040 .master = &omap3xxx_l4_core_hwmod, 2707 .master = &omap3xxx_l4_core_hwmod,
3041 .slave = &omap3xxx_mailbox_hwmod, 2708 .slave = &omap3xxx_mailbox_hwmod,
3042 .addr = omap3xxx_mailbox_addrs, 2709 .addr = omap3xxx_mailbox_addrs,
3043 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3044 .user = OCP_USER_MPU | OCP_USER_SDMA, 2710 .user = OCP_USER_MPU | OCP_USER_SDMA,
3045}; 2711};
3046 2712
@@ -3053,7 +2719,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3053 .name = "mailbox", 2719 .name = "mailbox",
3054 .class = &omap3xxx_mailbox_hwmod_class, 2720 .class = &omap3xxx_mailbox_hwmod_class,
3055 .mpu_irqs = omap3xxx_mailbox_irqs, 2721 .mpu_irqs = omap3xxx_mailbox_irqs,
3056 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3057 .main_clk = "mailboxes_ick", 2722 .main_clk = "mailboxes_ick",
3058 .prcm = { 2723 .prcm = {
3059 .omap2 = { 2724 .omap2 = {
@@ -3070,56 +2735,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3070}; 2735};
3071 2736
3072/* l4 core -> mcspi1 interface */ 2737/* l4 core -> mcspi1 interface */
3073static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3074 {
3075 .pa_start = 0x48098000,
3076 .pa_end = 0x480980ff,
3077 .flags = ADDR_TYPE_RT,
3078 },
3079};
3080
3081static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = { 2738static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3082 .master = &omap3xxx_l4_core_hwmod, 2739 .master = &omap3xxx_l4_core_hwmod,
3083 .slave = &omap34xx_mcspi1, 2740 .slave = &omap34xx_mcspi1,
3084 .clk = "mcspi1_ick", 2741 .clk = "mcspi1_ick",
3085 .addr = omap34xx_mcspi1_addr_space, 2742 .addr = omap2_mcspi1_addr_space,
3086 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
3087 .user = OCP_USER_MPU | OCP_USER_SDMA, 2743 .user = OCP_USER_MPU | OCP_USER_SDMA,
3088}; 2744};
3089 2745
3090/* l4 core -> mcspi2 interface */ 2746/* l4 core -> mcspi2 interface */
3091static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3092 {
3093 .pa_start = 0x4809a000,
3094 .pa_end = 0x4809a0ff,
3095 .flags = ADDR_TYPE_RT,
3096 },
3097};
3098
3099static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = { 2747static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3100 .master = &omap3xxx_l4_core_hwmod, 2748 .master = &omap3xxx_l4_core_hwmod,
3101 .slave = &omap34xx_mcspi2, 2749 .slave = &omap34xx_mcspi2,
3102 .clk = "mcspi2_ick", 2750 .clk = "mcspi2_ick",
3103 .addr = omap34xx_mcspi2_addr_space, 2751 .addr = omap2_mcspi2_addr_space,
3104 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
3105 .user = OCP_USER_MPU | OCP_USER_SDMA, 2752 .user = OCP_USER_MPU | OCP_USER_SDMA,
3106}; 2753};
3107 2754
3108/* l4 core -> mcspi3 interface */ 2755/* l4 core -> mcspi3 interface */
3109static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3110 {
3111 .pa_start = 0x480b8000,
3112 .pa_end = 0x480b80ff,
3113 .flags = ADDR_TYPE_RT,
3114 },
3115};
3116
3117static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = { 2756static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3118 .master = &omap3xxx_l4_core_hwmod, 2757 .master = &omap3xxx_l4_core_hwmod,
3119 .slave = &omap34xx_mcspi3, 2758 .slave = &omap34xx_mcspi3,
3120 .clk = "mcspi3_ick", 2759 .clk = "mcspi3_ick",
3121 .addr = omap34xx_mcspi3_addr_space, 2760 .addr = omap2430_mcspi3_addr_space,
3122 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
3123 .user = OCP_USER_MPU | OCP_USER_SDMA, 2761 .user = OCP_USER_MPU | OCP_USER_SDMA,
3124}; 2762};
3125 2763
@@ -3130,6 +2768,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3130 .pa_end = 0x480ba0ff, 2768 .pa_end = 0x480ba0ff,
3131 .flags = ADDR_TYPE_RT, 2769 .flags = ADDR_TYPE_RT,
3132 }, 2770 },
2771 { }
3133}; 2772};
3134 2773
3135static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = { 2774static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
@@ -3137,7 +2776,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3137 .slave = &omap34xx_mcspi4, 2776 .slave = &omap34xx_mcspi4,
3138 .clk = "mcspi4_ick", 2777 .clk = "mcspi4_ick",
3139 .addr = omap34xx_mcspi4_addr_space, 2778 .addr = omap34xx_mcspi4_addr_space,
3140 .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
3141 .user = OCP_USER_MPU | OCP_USER_SDMA, 2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
3142}; 2780};
3143 2781
@@ -3165,21 +2803,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
3165}; 2803};
3166 2804
3167/* mcspi1 */ 2805/* mcspi1 */
3168static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3169 { .name = "irq", .irq = 65 },
3170};
3171
3172static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3173 { .name = "tx0", .dma_req = 35 },
3174 { .name = "rx0", .dma_req = 36 },
3175 { .name = "tx1", .dma_req = 37 },
3176 { .name = "rx1", .dma_req = 38 },
3177 { .name = "tx2", .dma_req = 39 },
3178 { .name = "rx2", .dma_req = 40 },
3179 { .name = "tx3", .dma_req = 41 },
3180 { .name = "rx3", .dma_req = 42 },
3181};
3182
3183static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = { 2806static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3184 &omap34xx_l4_core__mcspi1, 2807 &omap34xx_l4_core__mcspi1,
3185}; 2808};
@@ -3190,10 +2813,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3190 2813
3191static struct omap_hwmod omap34xx_mcspi1 = { 2814static struct omap_hwmod omap34xx_mcspi1 = {
3192 .name = "mcspi1", 2815 .name = "mcspi1",
3193 .mpu_irqs = omap34xx_mcspi1_mpu_irqs, 2816 .mpu_irqs = omap2_mcspi1_mpu_irqs,
3194 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs), 2817 .sdma_reqs = omap2_mcspi1_sdma_reqs,
3195 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
3196 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3197 .main_clk = "mcspi1_fck", 2818 .main_clk = "mcspi1_fck",
3198 .prcm = { 2819 .prcm = {
3199 .omap2 = { 2820 .omap2 = {
@@ -3212,17 +2833,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
3212}; 2833};
3213 2834
3214/* mcspi2 */ 2835/* mcspi2 */
3215static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3216 { .name = "irq", .irq = 66 },
3217};
3218
3219static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3220 { .name = "tx0", .dma_req = 43 },
3221 { .name = "rx0", .dma_req = 44 },
3222 { .name = "tx1", .dma_req = 45 },
3223 { .name = "rx1", .dma_req = 46 },
3224};
3225
3226static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = { 2836static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3227 &omap34xx_l4_core__mcspi2, 2837 &omap34xx_l4_core__mcspi2,
3228}; 2838};
@@ -3233,10 +2843,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3233 2843
3234static struct omap_hwmod omap34xx_mcspi2 = { 2844static struct omap_hwmod omap34xx_mcspi2 = {
3235 .name = "mcspi2", 2845 .name = "mcspi2",
3236 .mpu_irqs = omap34xx_mcspi2_mpu_irqs, 2846 .mpu_irqs = omap2_mcspi2_mpu_irqs,
3237 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs), 2847 .sdma_reqs = omap2_mcspi2_sdma_reqs,
3238 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3239 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3240 .main_clk = "mcspi2_fck", 2848 .main_clk = "mcspi2_fck",
3241 .prcm = { 2849 .prcm = {
3242 .omap2 = { 2850 .omap2 = {
@@ -3257,6 +2865,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
3257/* mcspi3 */ 2865/* mcspi3 */
3258static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = { 2866static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3259 { .name = "irq", .irq = 91 }, /* 91 */ 2867 { .name = "irq", .irq = 91 }, /* 91 */
2868 { .irq = -1 }
3260}; 2869};
3261 2870
3262static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = { 2871static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -3264,6 +2873,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3264 { .name = "rx0", .dma_req = 16 }, 2873 { .name = "rx0", .dma_req = 16 },
3265 { .name = "tx1", .dma_req = 23 }, 2874 { .name = "tx1", .dma_req = 23 },
3266 { .name = "rx1", .dma_req = 24 }, 2875 { .name = "rx1", .dma_req = 24 },
2876 { .dma_req = -1 }
3267}; 2877};
3268 2878
3269static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = { 2879static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
@@ -3277,9 +2887,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3277static struct omap_hwmod omap34xx_mcspi3 = { 2887static struct omap_hwmod omap34xx_mcspi3 = {
3278 .name = "mcspi3", 2888 .name = "mcspi3",
3279 .mpu_irqs = omap34xx_mcspi3_mpu_irqs, 2889 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3280 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3281 .sdma_reqs = omap34xx_mcspi3_sdma_reqs, 2890 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3282 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3283 .main_clk = "mcspi3_fck", 2891 .main_clk = "mcspi3_fck",
3284 .prcm = { 2892 .prcm = {
3285 .omap2 = { 2893 .omap2 = {
@@ -3300,11 +2908,13 @@ static struct omap_hwmod omap34xx_mcspi3 = {
3300/* SPI4 */ 2908/* SPI4 */
3301static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = { 2909static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3302 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */ 2910 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2911 { .irq = -1 }
3303}; 2912};
3304 2913
3305static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = { 2914static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3306 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */ 2915 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3307 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */ 2916 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2917 { .dma_req = -1 }
3308}; 2918};
3309 2919
3310static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = { 2920static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
@@ -3318,9 +2928,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3318static struct omap_hwmod omap34xx_mcspi4 = { 2928static struct omap_hwmod omap34xx_mcspi4 = {
3319 .name = "mcspi4", 2929 .name = "mcspi4",
3320 .mpu_irqs = omap34xx_mcspi4_mpu_irqs, 2930 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3321 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3322 .sdma_reqs = omap34xx_mcspi4_sdma_reqs, 2931 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3323 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3324 .main_clk = "mcspi4_fck", 2932 .main_clk = "mcspi4_fck",
3325 .prcm = { 2933 .prcm = {
3326 .omap2 = { 2934 .omap2 = {
@@ -3362,12 +2970,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3362 2970
3363 { .name = "mc", .irq = 92 }, 2971 { .name = "mc", .irq = 92 },
3364 { .name = "dma", .irq = 93 }, 2972 { .name = "dma", .irq = 93 },
2973 { .irq = -1 }
3365}; 2974};
3366 2975
3367static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { 2976static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3368 .name = "usb_otg_hs", 2977 .name = "usb_otg_hs",
3369 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs, 2978 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3370 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3371 .main_clk = "hsotgusb_ick", 2979 .main_clk = "hsotgusb_ick",
3372 .prcm = { 2980 .prcm = {
3373 .omap2 = { 2981 .omap2 = {
@@ -3399,6 +3007,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3399static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { 3007static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3400 3008
3401 { .name = "mc", .irq = 71 }, 3009 { .name = "mc", .irq = 71 },
3010 { .irq = -1 }
3402}; 3011};
3403 3012
3404static struct omap_hwmod_class am35xx_usbotg_class = { 3013static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -3409,7 +3018,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
3409static struct omap_hwmod am35xx_usbhsotg_hwmod = { 3018static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3410 .name = "am35x_otg_hs", 3019 .name = "am35x_otg_hs",
3411 .mpu_irqs = am35xx_usbhsotg_mpu_irqs, 3020 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3412 .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3413 .main_clk = NULL, 3021 .main_clk = NULL,
3414 .prcm = { 3022 .prcm = {
3415 .omap2 = { 3023 .omap2 = {
@@ -3445,11 +3053,13 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
3445 3053
3446static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = { 3054static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3447 { .irq = 83, }, 3055 { .irq = 83, },
3056 { .irq = -1 }
3448}; 3057};
3449 3058
3450static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = { 3059static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3451 { .name = "tx", .dma_req = 61, }, 3060 { .name = "tx", .dma_req = 61, },
3452 { .name = "rx", .dma_req = 62, }, 3061 { .name = "rx", .dma_req = 62, },
3062 { .dma_req = -1 }
3453}; 3063};
3454 3064
3455static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = { 3065static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
@@ -3467,9 +3077,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
3467static struct omap_hwmod omap3xxx_mmc1_hwmod = { 3077static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3468 .name = "mmc1", 3078 .name = "mmc1",
3469 .mpu_irqs = omap34xx_mmc1_mpu_irqs, 3079 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3470 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3471 .sdma_reqs = omap34xx_mmc1_sdma_reqs, 3080 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3472 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3473 .opt_clks = omap34xx_mmc1_opt_clks, 3081 .opt_clks = omap34xx_mmc1_opt_clks,
3474 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks), 3082 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3475 .main_clk = "mmchs1_fck", 3083 .main_clk = "mmchs1_fck",
@@ -3493,11 +3101,13 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3493 3101
3494static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = { 3102static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3495 { .irq = INT_24XX_MMC2_IRQ, }, 3103 { .irq = INT_24XX_MMC2_IRQ, },
3104 { .irq = -1 }
3496}; 3105};
3497 3106
3498static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = { 3107static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3499 { .name = "tx", .dma_req = 47, }, 3108 { .name = "tx", .dma_req = 47, },
3500 { .name = "rx", .dma_req = 48, }, 3109 { .name = "rx", .dma_req = 48, },
3110 { .dma_req = -1 }
3501}; 3111};
3502 3112
3503static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = { 3113static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
@@ -3511,9 +3121,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3511static struct omap_hwmod omap3xxx_mmc2_hwmod = { 3121static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3512 .name = "mmc2", 3122 .name = "mmc2",
3513 .mpu_irqs = omap34xx_mmc2_mpu_irqs, 3123 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3514 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3515 .sdma_reqs = omap34xx_mmc2_sdma_reqs, 3124 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3516 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3517 .opt_clks = omap34xx_mmc2_opt_clks, 3125 .opt_clks = omap34xx_mmc2_opt_clks,
3518 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks), 3126 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3519 .main_clk = "mmchs2_fck", 3127 .main_clk = "mmchs2_fck",
@@ -3536,11 +3144,13 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3536 3144
3537static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = { 3145static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3538 { .irq = 94, }, 3146 { .irq = 94, },
3147 { .irq = -1 }
3539}; 3148};
3540 3149
3541static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = { 3150static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3542 { .name = "tx", .dma_req = 77, }, 3151 { .name = "tx", .dma_req = 77, },
3543 { .name = "rx", .dma_req = 78, }, 3152 { .name = "rx", .dma_req = 78, },
3153 { .dma_req = -1 }
3544}; 3154};
3545 3155
3546static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = { 3156static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
@@ -3554,9 +3164,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3554static struct omap_hwmod omap3xxx_mmc3_hwmod = { 3164static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3555 .name = "mmc3", 3165 .name = "mmc3",
3556 .mpu_irqs = omap34xx_mmc3_mpu_irqs, 3166 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3557 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3558 .sdma_reqs = omap34xx_mmc3_sdma_reqs, 3167 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3559 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3560 .opt_clks = omap34xx_mmc3_opt_clks, 3168 .opt_clks = omap34xx_mmc3_opt_clks,
3561 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks), 3169 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3562 .main_clk = "mmchs3_fck", 3170 .main_clk = "mmchs3_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e1c69ffe0f69..e01143725b08 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -80,7 +80,12 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
80 .name = "dmm", 80 .name = "dmm",
81}; 81};
82 82
83/* dmm interface data */ 83/* dmm */
84static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
85 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
86 { .irq = -1 }
87};
88
84/* l3_main_1 -> dmm */ 89/* l3_main_1 -> dmm */
85static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { 90static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
86 .master = &omap44xx_l3_main_1_hwmod, 91 .master = &omap44xx_l3_main_1_hwmod,
@@ -95,6 +100,7 @@ static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
95 .pa_end = 0x4e0007ff, 100 .pa_end = 0x4e0007ff,
96 .flags = ADDR_TYPE_RT 101 .flags = ADDR_TYPE_RT
97 }, 102 },
103 { }
98}; 104};
99 105
100/* mpu -> dmm */ 106/* mpu -> dmm */
@@ -103,7 +109,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
103 .slave = &omap44xx_dmm_hwmod, 109 .slave = &omap44xx_dmm_hwmod,
104 .clk = "l3_div_ck", 110 .clk = "l3_div_ck",
105 .addr = omap44xx_dmm_addrs, 111 .addr = omap44xx_dmm_addrs,
106 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
107 .user = OCP_USER_MPU, 112 .user = OCP_USER_MPU,
108}; 113};
109 114
@@ -113,17 +118,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
113 &omap44xx_mpu__dmm, 118 &omap44xx_mpu__dmm,
114}; 119};
115 120
116static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
117 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
118};
119
120static struct omap_hwmod omap44xx_dmm_hwmod = { 121static struct omap_hwmod omap44xx_dmm_hwmod = {
121 .name = "dmm", 122 .name = "dmm",
122 .class = &omap44xx_dmm_hwmod_class, 123 .class = &omap44xx_dmm_hwmod_class,
124 .mpu_irqs = omap44xx_dmm_irqs,
123 .slaves = omap44xx_dmm_slaves, 125 .slaves = omap44xx_dmm_slaves,
124 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves), 126 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
125 .mpu_irqs = omap44xx_dmm_irqs,
126 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 127 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
128}; 128};
129 129
@@ -135,7 +135,7 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
135 .name = "emif_fw", 135 .name = "emif_fw",
136}; 136};
137 137
138/* emif_fw interface data */ 138/* emif_fw */
139/* dmm -> emif_fw */ 139/* dmm -> emif_fw */
140static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { 140static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
141 .master = &omap44xx_dmm_hwmod, 141 .master = &omap44xx_dmm_hwmod,
@@ -150,6 +150,7 @@ static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
150 .pa_end = 0x4a20c0ff, 150 .pa_end = 0x4a20c0ff,
151 .flags = ADDR_TYPE_RT 151 .flags = ADDR_TYPE_RT
152 }, 152 },
153 { }
153}; 154};
154 155
155/* l4_cfg -> emif_fw */ 156/* l4_cfg -> emif_fw */
@@ -158,7 +159,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
158 .slave = &omap44xx_emif_fw_hwmod, 159 .slave = &omap44xx_emif_fw_hwmod,
159 .clk = "l4_div_ck", 160 .clk = "l4_div_ck",
160 .addr = omap44xx_emif_fw_addrs, 161 .addr = omap44xx_emif_fw_addrs,
161 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
162 .user = OCP_USER_MPU, 162 .user = OCP_USER_MPU,
163}; 163};
164 164
@@ -184,7 +184,7 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
184 .name = "l3", 184 .name = "l3",
185}; 185};
186 186
187/* l3_instr interface data */ 187/* l3_instr */
188/* iva -> l3_instr */ 188/* iva -> l3_instr */
189static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { 189static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
190 .master = &omap44xx_iva_hwmod, 190 .master = &omap44xx_iva_hwmod,
@@ -215,7 +215,13 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 215 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
216}; 216};
217 217
218/* l3_main_1 interface data */ 218/* l3_main_1 */
219static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
220 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
221 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
222 { .irq = -1 }
223};
224
219/* dsp -> l3_main_1 */ 225/* dsp -> l3_main_1 */
220static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { 226static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
221 .master = &omap44xx_dsp_hwmod, 227 .master = &omap44xx_dsp_hwmod,
@@ -264,18 +270,13 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
264 .user = OCP_USER_MPU | OCP_USER_SDMA, 270 .user = OCP_USER_MPU | OCP_USER_SDMA,
265}; 271};
266 272
267/* L3 target configuration and error log registers */
268static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
269 { .irq = 9 + OMAP44XX_IRQ_GIC_START },
270 { .irq = 10 + OMAP44XX_IRQ_GIC_START },
271};
272
273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { 273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 { 274 {
275 .pa_start = 0x44000000, 275 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff, 276 .pa_end = 0x44000fff,
277 .flags = ADDR_TYPE_RT, 277 .flags = ADDR_TYPE_RT
278 }, 278 },
279 { }
279}; 280};
280 281
281/* mpu -> l3_main_1 */ 282/* mpu -> l3_main_1 */
@@ -284,8 +285,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
284 .slave = &omap44xx_l3_main_1_hwmod, 285 .slave = &omap44xx_l3_main_1_hwmod,
285 .clk = "l3_div_ck", 286 .clk = "l3_div_ck",
286 .addr = omap44xx_l3_main_1_addrs, 287 .addr = omap44xx_l3_main_1_addrs,
287 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs), 288 .user = OCP_USER_MPU,
288 .user = OCP_USER_MPU | OCP_USER_SDMA,
289}; 289};
290 290
291/* l3_main_1 slave ports */ 291/* l3_main_1 slave ports */
@@ -302,14 +302,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
302static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 302static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
303 .name = "l3_main_1", 303 .name = "l3_main_1",
304 .class = &omap44xx_l3_hwmod_class, 304 .class = &omap44xx_l3_hwmod_class,
305 .mpu_irqs = omap44xx_l3_targ_irqs, 305 .mpu_irqs = omap44xx_l3_main_1_irqs,
306 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
307 .slaves = omap44xx_l3_main_1_slaves, 306 .slaves = omap44xx_l3_main_1_slaves,
308 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 307 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
309 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 308 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
310}; 309};
311 310
312/* l3_main_2 interface data */ 311/* l3_main_2 */
313/* dma_system -> l3_main_2 */ 312/* dma_system -> l3_main_2 */
314static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { 313static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
315 .master = &omap44xx_dma_system_hwmod, 314 .master = &omap44xx_dma_system_hwmod,
@@ -354,8 +353,9 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
354 { 353 {
355 .pa_start = 0x44800000, 354 .pa_start = 0x44800000,
356 .pa_end = 0x44801fff, 355 .pa_end = 0x44801fff,
357 .flags = ADDR_TYPE_RT, 356 .flags = ADDR_TYPE_RT
358 }, 357 },
358 { }
359}; 359};
360 360
361/* l3_main_1 -> l3_main_2 */ 361/* l3_main_1 -> l3_main_2 */
@@ -364,8 +364,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
364 .slave = &omap44xx_l3_main_2_hwmod, 364 .slave = &omap44xx_l3_main_2_hwmod,
365 .clk = "l3_div_ck", 365 .clk = "l3_div_ck",
366 .addr = omap44xx_l3_main_2_addrs, 366 .addr = omap44xx_l3_main_2_addrs,
367 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs), 367 .user = OCP_USER_MPU,
368 .user = OCP_USER_MPU | OCP_USER_SDMA,
369}; 368};
370 369
371/* l4_cfg -> l3_main_2 */ 370/* l4_cfg -> l3_main_2 */
@@ -404,13 +403,14 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
404 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 403 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
405}; 404};
406 405
407/* l3_main_3 interface data */ 406/* l3_main_3 */
408static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { 407static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
409 { 408 {
410 .pa_start = 0x45000000, 409 .pa_start = 0x45000000,
411 .pa_end = 0x45000fff, 410 .pa_end = 0x45000fff,
412 .flags = ADDR_TYPE_RT, 411 .flags = ADDR_TYPE_RT
413 }, 412 },
413 { }
414}; 414};
415 415
416/* l3_main_1 -> l3_main_3 */ 416/* l3_main_1 -> l3_main_3 */
@@ -419,8 +419,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
419 .slave = &omap44xx_l3_main_3_hwmod, 419 .slave = &omap44xx_l3_main_3_hwmod,
420 .clk = "l3_div_ck", 420 .clk = "l3_div_ck",
421 .addr = omap44xx_l3_main_3_addrs, 421 .addr = omap44xx_l3_main_3_addrs,
422 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs), 422 .user = OCP_USER_MPU,
423 .user = OCP_USER_MPU | OCP_USER_SDMA,
424}; 423};
425 424
426/* l3_main_2 -> l3_main_3 */ 425/* l3_main_2 -> l3_main_3 */
@@ -462,7 +461,7 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
462 .name = "l4", 461 .name = "l4",
463}; 462};
464 463
465/* l4_abe interface data */ 464/* l4_abe */
466/* aess -> l4_abe */ 465/* aess -> l4_abe */
467static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { 466static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
468 .master = &omap44xx_aess_hwmod, 467 .master = &omap44xx_aess_hwmod,
@@ -511,7 +510,7 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
511 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 510 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
512}; 511};
513 512
514/* l4_cfg interface data */ 513/* l4_cfg */
515/* l3_main_1 -> l4_cfg */ 514/* l3_main_1 -> l4_cfg */
516static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { 515static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
517 .master = &omap44xx_l3_main_1_hwmod, 516 .master = &omap44xx_l3_main_1_hwmod,
@@ -533,7 +532,7 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
533 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 532 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
534}; 533};
535 534
536/* l4_per interface data */ 535/* l4_per */
537/* l3_main_2 -> l4_per */ 536/* l3_main_2 -> l4_per */
538static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { 537static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
539 .master = &omap44xx_l3_main_2_hwmod, 538 .master = &omap44xx_l3_main_2_hwmod,
@@ -555,7 +554,7 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
555 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 554 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
556}; 555};
557 556
558/* l4_wkup interface data */ 557/* l4_wkup */
559/* l4_cfg -> l4_wkup */ 558/* l4_cfg -> l4_wkup */
560static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { 559static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
561 .master = &omap44xx_l4_cfg_hwmod, 560 .master = &omap44xx_l4_cfg_hwmod,
@@ -585,7 +584,7 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
585 .name = "mpu_bus", 584 .name = "mpu_bus",
586}; 585};
587 586
588/* mpu_private interface data */ 587/* mpu_private */
589/* mpu -> mpu_private */ 588/* mpu -> mpu_private */
590static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { 589static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
591 .master = &omap44xx_mpu_hwmod, 590 .master = &omap44xx_mpu_hwmod,
@@ -633,7 +632,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
633 * gpmc 632 * gpmc
634 * gpu 633 * gpu
635 * hdq1w 634 * hdq1w
636 * hsi 635 * mcasp
636 * mpu_c0
637 * mpu_c1
637 * ocmc_ram 638 * ocmc_ram
638 * ocp2scp_usb_phy 639 * ocp2scp_usb_phy
639 * ocp_wp_noc 640 * ocp_wp_noc
@@ -660,7 +661,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
660 .sysc_offs = 0x0010, 661 .sysc_offs = 0x0010,
661 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), 662 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
662 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 663 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
663 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), 664 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
665 MSTANDBY_SMART_WKUP),
664 .sysc_fields = &omap_hwmod_sysc_type2, 666 .sysc_fields = &omap_hwmod_sysc_type2,
665}; 667};
666 668
@@ -672,6 +674,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
672/* aess */ 674/* aess */
673static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { 675static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
674 { .irq = 99 + OMAP44XX_IRQ_GIC_START }, 676 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
677 { .irq = -1 }
675}; 678};
676 679
677static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { 680static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
@@ -683,6 +686,7 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
683 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, 686 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
684 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, 687 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
685 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, 688 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
689 { .dma_req = -1 }
686}; 690};
687 691
688/* aess master ports */ 692/* aess master ports */
@@ -696,6 +700,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
696 .pa_end = 0x401f13ff, 700 .pa_end = 0x401f13ff,
697 .flags = ADDR_TYPE_RT 701 .flags = ADDR_TYPE_RT
698 }, 702 },
703 { }
699}; 704};
700 705
701/* l4_abe -> aess */ 706/* l4_abe -> aess */
@@ -704,7 +709,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
704 .slave = &omap44xx_aess_hwmod, 709 .slave = &omap44xx_aess_hwmod,
705 .clk = "ocp_abe_iclk", 710 .clk = "ocp_abe_iclk",
706 .addr = omap44xx_aess_addrs, 711 .addr = omap44xx_aess_addrs,
707 .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
708 .user = OCP_USER_MPU, 712 .user = OCP_USER_MPU,
709}; 713};
710 714
@@ -714,6 +718,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
714 .pa_end = 0x490f13ff, 718 .pa_end = 0x490f13ff,
715 .flags = ADDR_TYPE_RT 719 .flags = ADDR_TYPE_RT
716 }, 720 },
721 { }
717}; 722};
718 723
719/* l4_abe -> aess (dma) */ 724/* l4_abe -> aess (dma) */
@@ -722,7 +727,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
722 .slave = &omap44xx_aess_hwmod, 727 .slave = &omap44xx_aess_hwmod,
723 .clk = "ocp_abe_iclk", 728 .clk = "ocp_abe_iclk",
724 .addr = omap44xx_aess_dma_addrs, 729 .addr = omap44xx_aess_dma_addrs,
725 .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
726 .user = OCP_USER_SDMA, 730 .user = OCP_USER_SDMA,
727}; 731};
728 732
@@ -736,11 +740,9 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
736 .name = "aess", 740 .name = "aess",
737 .class = &omap44xx_aess_hwmod_class, 741 .class = &omap44xx_aess_hwmod_class,
738 .mpu_irqs = omap44xx_aess_irqs, 742 .mpu_irqs = omap44xx_aess_irqs,
739 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
740 .sdma_reqs = omap44xx_aess_sdma_reqs, 743 .sdma_reqs = omap44xx_aess_sdma_reqs,
741 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
742 .main_clk = "aess_fck", 744 .main_clk = "aess_fck",
743 .prcm = { 745 .prcm = {
744 .omap4 = { 746 .omap4 = {
745 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, 747 .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
746 }, 748 },
@@ -769,7 +771,7 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
769static struct omap_hwmod omap44xx_bandgap_hwmod = { 771static struct omap_hwmod omap44xx_bandgap_hwmod = {
770 .name = "bandgap", 772 .name = "bandgap",
771 .class = &omap44xx_bandgap_hwmod_class, 773 .class = &omap44xx_bandgap_hwmod_class,
772 .prcm = { 774 .prcm = {
773 .omap4 = { 775 .omap4 = {
774 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, 776 .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
775 }, 777 },
@@ -806,6 +808,7 @@ static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
806 .pa_end = 0x4a30401f, 808 .pa_end = 0x4a30401f,
807 .flags = ADDR_TYPE_RT 809 .flags = ADDR_TYPE_RT
808 }, 810 },
811 { }
809}; 812};
810 813
811/* l4_wkup -> counter_32k */ 814/* l4_wkup -> counter_32k */
@@ -814,7 +817,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
814 .slave = &omap44xx_counter_32k_hwmod, 817 .slave = &omap44xx_counter_32k_hwmod,
815 .clk = "l4_wkup_clk_mux_ck", 818 .clk = "l4_wkup_clk_mux_ck",
816 .addr = omap44xx_counter_32k_addrs, 819 .addr = omap44xx_counter_32k_addrs,
817 .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
818 .user = OCP_USER_MPU | OCP_USER_SDMA, 820 .user = OCP_USER_MPU | OCP_USER_SDMA,
819}; 821};
820 822
@@ -828,7 +830,7 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
828 .class = &omap44xx_counter_hwmod_class, 830 .class = &omap44xx_counter_hwmod_class,
829 .flags = HWMOD_SWSUP_SIDLE, 831 .flags = HWMOD_SWSUP_SIDLE,
830 .main_clk = "sys_32k_ck", 832 .main_clk = "sys_32k_ck",
831 .prcm = { 833 .prcm = {
832 .omap4 = { 834 .omap4 = {
833 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL, 835 .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
834 }, 836 },
@@ -875,6 +877,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
875 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, 877 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
876 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, 878 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
877 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, 879 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
880 { .irq = -1 }
878}; 881};
879 882
880/* dma_system master ports */ 883/* dma_system master ports */
@@ -888,6 +891,7 @@ static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
888 .pa_end = 0x4a056fff, 891 .pa_end = 0x4a056fff,
889 .flags = ADDR_TYPE_RT 892 .flags = ADDR_TYPE_RT
890 }, 893 },
894 { }
891}; 895};
892 896
893/* l4_cfg -> dma_system */ 897/* l4_cfg -> dma_system */
@@ -896,7 +900,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
896 .slave = &omap44xx_dma_system_hwmod, 900 .slave = &omap44xx_dma_system_hwmod,
897 .clk = "l4_div_ck", 901 .clk = "l4_div_ck",
898 .addr = omap44xx_dma_system_addrs, 902 .addr = omap44xx_dma_system_addrs,
899 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
900 .user = OCP_USER_MPU | OCP_USER_SDMA, 903 .user = OCP_USER_MPU | OCP_USER_SDMA,
901}; 904};
902 905
@@ -909,7 +912,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
909 .name = "dma_system", 912 .name = "dma_system",
910 .class = &omap44xx_dma_hwmod_class, 913 .class = &omap44xx_dma_hwmod_class,
911 .mpu_irqs = omap44xx_dma_system_irqs, 914 .mpu_irqs = omap44xx_dma_system_irqs,
912 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
913 .main_clk = "l3_div_ck", 915 .main_clk = "l3_div_ck",
914 .prcm = { 916 .prcm = {
915 .omap4 = { 917 .omap4 = {
@@ -948,10 +950,12 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
948static struct omap_hwmod omap44xx_dmic_hwmod; 950static struct omap_hwmod omap44xx_dmic_hwmod;
949static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { 951static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
950 { .irq = 114 + OMAP44XX_IRQ_GIC_START }, 952 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
953 { .irq = -1 }
951}; 954};
952 955
953static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { 956static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
954 { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, 957 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
958 { .dma_req = -1 }
955}; 959};
956 960
957static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { 961static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
@@ -960,6 +964,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
960 .pa_end = 0x4012e07f, 964 .pa_end = 0x4012e07f,
961 .flags = ADDR_TYPE_RT 965 .flags = ADDR_TYPE_RT
962 }, 966 },
967 { }
963}; 968};
964 969
965/* l4_abe -> dmic */ 970/* l4_abe -> dmic */
@@ -968,7 +973,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
968 .slave = &omap44xx_dmic_hwmod, 973 .slave = &omap44xx_dmic_hwmod,
969 .clk = "ocp_abe_iclk", 974 .clk = "ocp_abe_iclk",
970 .addr = omap44xx_dmic_addrs, 975 .addr = omap44xx_dmic_addrs,
971 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
972 .user = OCP_USER_MPU, 976 .user = OCP_USER_MPU,
973}; 977};
974 978
@@ -978,6 +982,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
978 .pa_end = 0x4902e07f, 982 .pa_end = 0x4902e07f,
979 .flags = ADDR_TYPE_RT 983 .flags = ADDR_TYPE_RT
980 }, 984 },
985 { }
981}; 986};
982 987
983/* l4_abe -> dmic (dma) */ 988/* l4_abe -> dmic (dma) */
@@ -986,7 +991,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
986 .slave = &omap44xx_dmic_hwmod, 991 .slave = &omap44xx_dmic_hwmod,
987 .clk = "ocp_abe_iclk", 992 .clk = "ocp_abe_iclk",
988 .addr = omap44xx_dmic_dma_addrs, 993 .addr = omap44xx_dmic_dma_addrs,
989 .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
990 .user = OCP_USER_SDMA, 994 .user = OCP_USER_SDMA,
991}; 995};
992 996
@@ -1000,11 +1004,9 @@ static struct omap_hwmod omap44xx_dmic_hwmod = {
1000 .name = "dmic", 1004 .name = "dmic",
1001 .class = &omap44xx_dmic_hwmod_class, 1005 .class = &omap44xx_dmic_hwmod_class,
1002 .mpu_irqs = omap44xx_dmic_irqs, 1006 .mpu_irqs = omap44xx_dmic_irqs,
1003 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
1004 .sdma_reqs = omap44xx_dmic_sdma_reqs, 1007 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1005 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
1006 .main_clk = "dmic_fck", 1008 .main_clk = "dmic_fck",
1007 .prcm = { 1009 .prcm = {
1008 .omap4 = { 1010 .omap4 = {
1009 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, 1011 .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1010 }, 1012 },
@@ -1026,6 +1028,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1026/* dsp */ 1028/* dsp */
1027static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { 1029static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1028 { .irq = 28 + OMAP44XX_IRQ_GIC_START }, 1030 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1031 { .irq = -1 }
1029}; 1032};
1030 1033
1031static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { 1034static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
@@ -1082,7 +1085,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
1082 .name = "dsp", 1085 .name = "dsp",
1083 .class = &omap44xx_dsp_hwmod_class, 1086 .class = &omap44xx_dsp_hwmod_class,
1084 .mpu_irqs = omap44xx_dsp_irqs, 1087 .mpu_irqs = omap44xx_dsp_irqs,
1085 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
1086 .rst_lines = omap44xx_dsp_resets, 1088 .rst_lines = omap44xx_dsp_resets,
1087 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), 1089 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1088 .main_clk = "dsp_fck", 1090 .main_clk = "dsp_fck",
@@ -1127,6 +1129,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1127 .pa_end = 0x5800007f, 1129 .pa_end = 0x5800007f,
1128 .flags = ADDR_TYPE_RT 1130 .flags = ADDR_TYPE_RT
1129 }, 1131 },
1132 { }
1130}; 1133};
1131 1134
1132/* l3_main_2 -> dss */ 1135/* l3_main_2 -> dss */
@@ -1135,7 +1138,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1135 .slave = &omap44xx_dss_hwmod, 1138 .slave = &omap44xx_dss_hwmod,
1136 .clk = "l3_div_ck", 1139 .clk = "l3_div_ck",
1137 .addr = omap44xx_dss_dma_addrs, 1140 .addr = omap44xx_dss_dma_addrs,
1138 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1139 .user = OCP_USER_SDMA, 1141 .user = OCP_USER_SDMA,
1140}; 1142};
1141 1143
@@ -1145,6 +1147,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1145 .pa_end = 0x4804007f, 1147 .pa_end = 0x4804007f,
1146 .flags = ADDR_TYPE_RT 1148 .flags = ADDR_TYPE_RT
1147 }, 1149 },
1150 { }
1148}; 1151};
1149 1152
1150/* l4_per -> dss */ 1153/* l4_per -> dss */
@@ -1153,7 +1156,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1153 .slave = &omap44xx_dss_hwmod, 1156 .slave = &omap44xx_dss_hwmod,
1154 .clk = "l4_div_ck", 1157 .clk = "l4_div_ck",
1155 .addr = omap44xx_dss_addrs, 1158 .addr = omap44xx_dss_addrs,
1156 .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
1157 .user = OCP_USER_MPU, 1159 .user = OCP_USER_MPU,
1158}; 1160};
1159 1161
@@ -1215,10 +1217,12 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1215static struct omap_hwmod omap44xx_dss_dispc_hwmod; 1217static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1216static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { 1218static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1217 { .irq = 25 + OMAP44XX_IRQ_GIC_START }, 1219 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1220 { .irq = -1 }
1218}; 1221};
1219 1222
1220static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { 1223static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1221 { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, 1224 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1225 { .dma_req = -1 }
1222}; 1226};
1223 1227
1224static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { 1228static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
@@ -1227,6 +1231,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1227 .pa_end = 0x58001fff, 1231 .pa_end = 0x58001fff,
1228 .flags = ADDR_TYPE_RT 1232 .flags = ADDR_TYPE_RT
1229 }, 1233 },
1234 { }
1230}; 1235};
1231 1236
1232/* l3_main_2 -> dss_dispc */ 1237/* l3_main_2 -> dss_dispc */
@@ -1235,7 +1240,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1235 .slave = &omap44xx_dss_dispc_hwmod, 1240 .slave = &omap44xx_dss_dispc_hwmod,
1236 .clk = "l3_div_ck", 1241 .clk = "l3_div_ck",
1237 .addr = omap44xx_dss_dispc_dma_addrs, 1242 .addr = omap44xx_dss_dispc_dma_addrs,
1238 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1239 .user = OCP_USER_SDMA, 1243 .user = OCP_USER_SDMA,
1240}; 1244};
1241 1245
@@ -1245,6 +1249,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1245 .pa_end = 0x48041fff, 1249 .pa_end = 0x48041fff,
1246 .flags = ADDR_TYPE_RT 1250 .flags = ADDR_TYPE_RT
1247 }, 1251 },
1252 { }
1248}; 1253};
1249 1254
1250/* l4_per -> dss_dispc */ 1255/* l4_per -> dss_dispc */
@@ -1253,7 +1258,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1253 .slave = &omap44xx_dss_dispc_hwmod, 1258 .slave = &omap44xx_dss_dispc_hwmod,
1254 .clk = "l4_div_ck", 1259 .clk = "l4_div_ck",
1255 .addr = omap44xx_dss_dispc_addrs, 1260 .addr = omap44xx_dss_dispc_addrs,
1256 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1257 .user = OCP_USER_MPU, 1261 .user = OCP_USER_MPU,
1258}; 1262};
1259 1263
@@ -1267,9 +1271,7 @@ static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1267 .name = "dss_dispc", 1271 .name = "dss_dispc",
1268 .class = &omap44xx_dispc_hwmod_class, 1272 .class = &omap44xx_dispc_hwmod_class,
1269 .mpu_irqs = omap44xx_dss_dispc_irqs, 1273 .mpu_irqs = omap44xx_dss_dispc_irqs,
1270 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1271 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, 1274 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1272 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1273 .main_clk = "dss_fck", 1275 .main_clk = "dss_fck",
1274 .prcm = { 1276 .prcm = {
1275 .omap4 = { 1277 .omap4 = {
@@ -1306,10 +1308,12 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1306static struct omap_hwmod omap44xx_dss_dsi1_hwmod; 1308static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1307static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { 1309static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1308 { .irq = 53 + OMAP44XX_IRQ_GIC_START }, 1310 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1311 { .irq = -1 }
1309}; 1312};
1310 1313
1311static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { 1314static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1312 { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, 1315 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1316 { .dma_req = -1 }
1313}; 1317};
1314 1318
1315static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { 1319static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
@@ -1318,6 +1322,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1318 .pa_end = 0x580041ff, 1322 .pa_end = 0x580041ff,
1319 .flags = ADDR_TYPE_RT 1323 .flags = ADDR_TYPE_RT
1320 }, 1324 },
1325 { }
1321}; 1326};
1322 1327
1323/* l3_main_2 -> dss_dsi1 */ 1328/* l3_main_2 -> dss_dsi1 */
@@ -1326,7 +1331,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1326 .slave = &omap44xx_dss_dsi1_hwmod, 1331 .slave = &omap44xx_dss_dsi1_hwmod,
1327 .clk = "l3_div_ck", 1332 .clk = "l3_div_ck",
1328 .addr = omap44xx_dss_dsi1_dma_addrs, 1333 .addr = omap44xx_dss_dsi1_dma_addrs,
1329 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1330 .user = OCP_USER_SDMA, 1334 .user = OCP_USER_SDMA,
1331}; 1335};
1332 1336
@@ -1336,6 +1340,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1336 .pa_end = 0x480441ff, 1340 .pa_end = 0x480441ff,
1337 .flags = ADDR_TYPE_RT 1341 .flags = ADDR_TYPE_RT
1338 }, 1342 },
1343 { }
1339}; 1344};
1340 1345
1341/* l4_per -> dss_dsi1 */ 1346/* l4_per -> dss_dsi1 */
@@ -1344,7 +1349,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1344 .slave = &omap44xx_dss_dsi1_hwmod, 1349 .slave = &omap44xx_dss_dsi1_hwmod,
1345 .clk = "l4_div_ck", 1350 .clk = "l4_div_ck",
1346 .addr = omap44xx_dss_dsi1_addrs, 1351 .addr = omap44xx_dss_dsi1_addrs,
1347 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1348 .user = OCP_USER_MPU, 1352 .user = OCP_USER_MPU,
1349}; 1353};
1350 1354
@@ -1358,9 +1362,7 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1358 .name = "dss_dsi1", 1362 .name = "dss_dsi1",
1359 .class = &omap44xx_dsi_hwmod_class, 1363 .class = &omap44xx_dsi_hwmod_class,
1360 .mpu_irqs = omap44xx_dss_dsi1_irqs, 1364 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1361 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1362 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, 1365 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1363 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1364 .main_clk = "dss_fck", 1366 .main_clk = "dss_fck",
1365 .prcm = { 1367 .prcm = {
1366 .omap4 = { 1368 .omap4 = {
@@ -1376,10 +1378,12 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1376static struct omap_hwmod omap44xx_dss_dsi2_hwmod; 1378static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1377static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { 1379static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1378 { .irq = 84 + OMAP44XX_IRQ_GIC_START }, 1380 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1381 { .irq = -1 }
1379}; 1382};
1380 1383
1381static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { 1384static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1382 { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, 1385 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1386 { .dma_req = -1 }
1383}; 1387};
1384 1388
1385static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { 1389static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
@@ -1388,6 +1392,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1388 .pa_end = 0x580051ff, 1392 .pa_end = 0x580051ff,
1389 .flags = ADDR_TYPE_RT 1393 .flags = ADDR_TYPE_RT
1390 }, 1394 },
1395 { }
1391}; 1396};
1392 1397
1393/* l3_main_2 -> dss_dsi2 */ 1398/* l3_main_2 -> dss_dsi2 */
@@ -1396,7 +1401,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1396 .slave = &omap44xx_dss_dsi2_hwmod, 1401 .slave = &omap44xx_dss_dsi2_hwmod,
1397 .clk = "l3_div_ck", 1402 .clk = "l3_div_ck",
1398 .addr = omap44xx_dss_dsi2_dma_addrs, 1403 .addr = omap44xx_dss_dsi2_dma_addrs,
1399 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1400 .user = OCP_USER_SDMA, 1404 .user = OCP_USER_SDMA,
1401}; 1405};
1402 1406
@@ -1406,6 +1410,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1406 .pa_end = 0x480451ff, 1410 .pa_end = 0x480451ff,
1407 .flags = ADDR_TYPE_RT 1411 .flags = ADDR_TYPE_RT
1408 }, 1412 },
1413 { }
1409}; 1414};
1410 1415
1411/* l4_per -> dss_dsi2 */ 1416/* l4_per -> dss_dsi2 */
@@ -1414,7 +1419,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1414 .slave = &omap44xx_dss_dsi2_hwmod, 1419 .slave = &omap44xx_dss_dsi2_hwmod,
1415 .clk = "l4_div_ck", 1420 .clk = "l4_div_ck",
1416 .addr = omap44xx_dss_dsi2_addrs, 1421 .addr = omap44xx_dss_dsi2_addrs,
1417 .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1418 .user = OCP_USER_MPU, 1422 .user = OCP_USER_MPU,
1419}; 1423};
1420 1424
@@ -1428,9 +1432,7 @@ static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1428 .name = "dss_dsi2", 1432 .name = "dss_dsi2",
1429 .class = &omap44xx_dsi_hwmod_class, 1433 .class = &omap44xx_dsi_hwmod_class,
1430 .mpu_irqs = omap44xx_dss_dsi2_irqs, 1434 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1431 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1432 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, 1435 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1433 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1434 .main_clk = "dss_fck", 1436 .main_clk = "dss_fck",
1435 .prcm = { 1437 .prcm = {
1436 .omap4 = { 1438 .omap4 = {
@@ -1466,10 +1468,12 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1466static struct omap_hwmod omap44xx_dss_hdmi_hwmod; 1468static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1467static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { 1469static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1468 { .irq = 101 + OMAP44XX_IRQ_GIC_START }, 1470 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1471 { .irq = -1 }
1469}; 1472};
1470 1473
1471static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { 1474static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1472 { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, 1475 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1476 { .dma_req = -1 }
1473}; 1477};
1474 1478
1475static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { 1479static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
@@ -1478,6 +1482,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1478 .pa_end = 0x58006fff, 1482 .pa_end = 0x58006fff,
1479 .flags = ADDR_TYPE_RT 1483 .flags = ADDR_TYPE_RT
1480 }, 1484 },
1485 { }
1481}; 1486};
1482 1487
1483/* l3_main_2 -> dss_hdmi */ 1488/* l3_main_2 -> dss_hdmi */
@@ -1486,7 +1491,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1486 .slave = &omap44xx_dss_hdmi_hwmod, 1491 .slave = &omap44xx_dss_hdmi_hwmod,
1487 .clk = "l3_div_ck", 1492 .clk = "l3_div_ck",
1488 .addr = omap44xx_dss_hdmi_dma_addrs, 1493 .addr = omap44xx_dss_hdmi_dma_addrs,
1489 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1490 .user = OCP_USER_SDMA, 1494 .user = OCP_USER_SDMA,
1491}; 1495};
1492 1496
@@ -1496,6 +1500,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1496 .pa_end = 0x48046fff, 1500 .pa_end = 0x48046fff,
1497 .flags = ADDR_TYPE_RT 1501 .flags = ADDR_TYPE_RT
1498 }, 1502 },
1503 { }
1499}; 1504};
1500 1505
1501/* l4_per -> dss_hdmi */ 1506/* l4_per -> dss_hdmi */
@@ -1504,7 +1509,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1504 .slave = &omap44xx_dss_hdmi_hwmod, 1509 .slave = &omap44xx_dss_hdmi_hwmod,
1505 .clk = "l4_div_ck", 1510 .clk = "l4_div_ck",
1506 .addr = omap44xx_dss_hdmi_addrs, 1511 .addr = omap44xx_dss_hdmi_addrs,
1507 .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1508 .user = OCP_USER_MPU, 1512 .user = OCP_USER_MPU,
1509}; 1513};
1510 1514
@@ -1518,9 +1522,7 @@ static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1518 .name = "dss_hdmi", 1522 .name = "dss_hdmi",
1519 .class = &omap44xx_hdmi_hwmod_class, 1523 .class = &omap44xx_hdmi_hwmod_class,
1520 .mpu_irqs = omap44xx_dss_hdmi_irqs, 1524 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1521 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1522 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, 1525 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1523 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1524 .main_clk = "dss_fck", 1526 .main_clk = "dss_fck",
1525 .prcm = { 1527 .prcm = {
1526 .omap4 = { 1528 .omap4 = {
@@ -1556,6 +1558,7 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1556static struct omap_hwmod omap44xx_dss_rfbi_hwmod; 1558static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1557static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { 1559static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1558 { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, 1560 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1561 { .dma_req = -1 }
1559}; 1562};
1560 1563
1561static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { 1564static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
@@ -1564,6 +1567,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1564 .pa_end = 0x580020ff, 1567 .pa_end = 0x580020ff,
1565 .flags = ADDR_TYPE_RT 1568 .flags = ADDR_TYPE_RT
1566 }, 1569 },
1570 { }
1567}; 1571};
1568 1572
1569/* l3_main_2 -> dss_rfbi */ 1573/* l3_main_2 -> dss_rfbi */
@@ -1572,7 +1576,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1572 .slave = &omap44xx_dss_rfbi_hwmod, 1576 .slave = &omap44xx_dss_rfbi_hwmod,
1573 .clk = "l3_div_ck", 1577 .clk = "l3_div_ck",
1574 .addr = omap44xx_dss_rfbi_dma_addrs, 1578 .addr = omap44xx_dss_rfbi_dma_addrs,
1575 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1576 .user = OCP_USER_SDMA, 1579 .user = OCP_USER_SDMA,
1577}; 1580};
1578 1581
@@ -1582,6 +1585,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1582 .pa_end = 0x480420ff, 1585 .pa_end = 0x480420ff,
1583 .flags = ADDR_TYPE_RT 1586 .flags = ADDR_TYPE_RT
1584 }, 1587 },
1588 { }
1585}; 1589};
1586 1590
1587/* l4_per -> dss_rfbi */ 1591/* l4_per -> dss_rfbi */
@@ -1590,7 +1594,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1590 .slave = &omap44xx_dss_rfbi_hwmod, 1594 .slave = &omap44xx_dss_rfbi_hwmod,
1591 .clk = "l4_div_ck", 1595 .clk = "l4_div_ck",
1592 .addr = omap44xx_dss_rfbi_addrs, 1596 .addr = omap44xx_dss_rfbi_addrs,
1593 .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1594 .user = OCP_USER_MPU, 1597 .user = OCP_USER_MPU,
1595}; 1598};
1596 1599
@@ -1604,7 +1607,6 @@ static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1604 .name = "dss_rfbi", 1607 .name = "dss_rfbi",
1605 .class = &omap44xx_rfbi_hwmod_class, 1608 .class = &omap44xx_rfbi_hwmod_class,
1606 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, 1609 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1607 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1608 .main_clk = "dss_fck", 1610 .main_clk = "dss_fck",
1609 .prcm = { 1611 .prcm = {
1610 .omap4 = { 1612 .omap4 = {
@@ -1633,6 +1635,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1633 .pa_end = 0x580030ff, 1635 .pa_end = 0x580030ff,
1634 .flags = ADDR_TYPE_RT 1636 .flags = ADDR_TYPE_RT
1635 }, 1637 },
1638 { }
1636}; 1639};
1637 1640
1638/* l3_main_2 -> dss_venc */ 1641/* l3_main_2 -> dss_venc */
@@ -1641,7 +1644,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1641 .slave = &omap44xx_dss_venc_hwmod, 1644 .slave = &omap44xx_dss_venc_hwmod,
1642 .clk = "l3_div_ck", 1645 .clk = "l3_div_ck",
1643 .addr = omap44xx_dss_venc_dma_addrs, 1646 .addr = omap44xx_dss_venc_dma_addrs,
1644 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1645 .user = OCP_USER_SDMA, 1647 .user = OCP_USER_SDMA,
1646}; 1648};
1647 1649
@@ -1651,6 +1653,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1651 .pa_end = 0x480430ff, 1653 .pa_end = 0x480430ff,
1652 .flags = ADDR_TYPE_RT 1654 .flags = ADDR_TYPE_RT
1653 }, 1655 },
1656 { }
1654}; 1657};
1655 1658
1656/* l4_per -> dss_venc */ 1659/* l4_per -> dss_venc */
@@ -1659,7 +1662,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1659 .slave = &omap44xx_dss_venc_hwmod, 1662 .slave = &omap44xx_dss_venc_hwmod,
1660 .clk = "l4_div_ck", 1663 .clk = "l4_div_ck",
1661 .addr = omap44xx_dss_venc_addrs, 1664 .addr = omap44xx_dss_venc_addrs,
1662 .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1663 .user = OCP_USER_MPU, 1665 .user = OCP_USER_MPU,
1664}; 1666};
1665 1667
@@ -1716,6 +1718,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
1716static struct omap_hwmod omap44xx_gpio1_hwmod; 1718static struct omap_hwmod omap44xx_gpio1_hwmod;
1717static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { 1719static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1718 { .irq = 29 + OMAP44XX_IRQ_GIC_START }, 1720 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1721 { .irq = -1 }
1719}; 1722};
1720 1723
1721static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { 1724static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
@@ -1724,6 +1727,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1724 .pa_end = 0x4a3101ff, 1727 .pa_end = 0x4a3101ff,
1725 .flags = ADDR_TYPE_RT 1728 .flags = ADDR_TYPE_RT
1726 }, 1729 },
1730 { }
1727}; 1731};
1728 1732
1729/* l4_wkup -> gpio1 */ 1733/* l4_wkup -> gpio1 */
@@ -1732,7 +1736,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1732 .slave = &omap44xx_gpio1_hwmod, 1736 .slave = &omap44xx_gpio1_hwmod,
1733 .clk = "l4_wkup_clk_mux_ck", 1737 .clk = "l4_wkup_clk_mux_ck",
1734 .addr = omap44xx_gpio1_addrs, 1738 .addr = omap44xx_gpio1_addrs,
1735 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
1736 .user = OCP_USER_MPU | OCP_USER_SDMA, 1739 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737}; 1740};
1738 1741
@@ -1749,7 +1752,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1749 .name = "gpio1", 1752 .name = "gpio1",
1750 .class = &omap44xx_gpio_hwmod_class, 1753 .class = &omap44xx_gpio_hwmod_class,
1751 .mpu_irqs = omap44xx_gpio1_irqs, 1754 .mpu_irqs = omap44xx_gpio1_irqs,
1752 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1753 .main_clk = "gpio1_ick", 1755 .main_clk = "gpio1_ick",
1754 .prcm = { 1756 .prcm = {
1755 .omap4 = { 1757 .omap4 = {
@@ -1768,6 +1770,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
1768static struct omap_hwmod omap44xx_gpio2_hwmod; 1770static struct omap_hwmod omap44xx_gpio2_hwmod;
1769static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { 1771static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1770 { .irq = 30 + OMAP44XX_IRQ_GIC_START }, 1772 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1773 { .irq = -1 }
1771}; 1774};
1772 1775
1773static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { 1776static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
@@ -1776,6 +1779,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1776 .pa_end = 0x480551ff, 1779 .pa_end = 0x480551ff,
1777 .flags = ADDR_TYPE_RT 1780 .flags = ADDR_TYPE_RT
1778 }, 1781 },
1782 { }
1779}; 1783};
1780 1784
1781/* l4_per -> gpio2 */ 1785/* l4_per -> gpio2 */
@@ -1784,7 +1788,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1784 .slave = &omap44xx_gpio2_hwmod, 1788 .slave = &omap44xx_gpio2_hwmod,
1785 .clk = "l4_div_ck", 1789 .clk = "l4_div_ck",
1786 .addr = omap44xx_gpio2_addrs, 1790 .addr = omap44xx_gpio2_addrs,
1787 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
1788 .user = OCP_USER_MPU | OCP_USER_SDMA, 1791 .user = OCP_USER_MPU | OCP_USER_SDMA,
1789}; 1792};
1790 1793
@@ -1802,7 +1805,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1802 .class = &omap44xx_gpio_hwmod_class, 1805 .class = &omap44xx_gpio_hwmod_class,
1803 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1806 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1804 .mpu_irqs = omap44xx_gpio2_irqs, 1807 .mpu_irqs = omap44xx_gpio2_irqs,
1805 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1806 .main_clk = "gpio2_ick", 1808 .main_clk = "gpio2_ick",
1807 .prcm = { 1809 .prcm = {
1808 .omap4 = { 1810 .omap4 = {
@@ -1821,6 +1823,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
1821static struct omap_hwmod omap44xx_gpio3_hwmod; 1823static struct omap_hwmod omap44xx_gpio3_hwmod;
1822static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { 1824static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1823 { .irq = 31 + OMAP44XX_IRQ_GIC_START }, 1825 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1826 { .irq = -1 }
1824}; 1827};
1825 1828
1826static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { 1829static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
@@ -1829,6 +1832,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1829 .pa_end = 0x480571ff, 1832 .pa_end = 0x480571ff,
1830 .flags = ADDR_TYPE_RT 1833 .flags = ADDR_TYPE_RT
1831 }, 1834 },
1835 { }
1832}; 1836};
1833 1837
1834/* l4_per -> gpio3 */ 1838/* l4_per -> gpio3 */
@@ -1837,7 +1841,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1837 .slave = &omap44xx_gpio3_hwmod, 1841 .slave = &omap44xx_gpio3_hwmod,
1838 .clk = "l4_div_ck", 1842 .clk = "l4_div_ck",
1839 .addr = omap44xx_gpio3_addrs, 1843 .addr = omap44xx_gpio3_addrs,
1840 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
1841 .user = OCP_USER_MPU | OCP_USER_SDMA, 1844 .user = OCP_USER_MPU | OCP_USER_SDMA,
1842}; 1845};
1843 1846
@@ -1855,7 +1858,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1855 .class = &omap44xx_gpio_hwmod_class, 1858 .class = &omap44xx_gpio_hwmod_class,
1856 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1859 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1857 .mpu_irqs = omap44xx_gpio3_irqs, 1860 .mpu_irqs = omap44xx_gpio3_irqs,
1858 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
1859 .main_clk = "gpio3_ick", 1861 .main_clk = "gpio3_ick",
1860 .prcm = { 1862 .prcm = {
1861 .omap4 = { 1863 .omap4 = {
@@ -1874,6 +1876,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
1874static struct omap_hwmod omap44xx_gpio4_hwmod; 1876static struct omap_hwmod omap44xx_gpio4_hwmod;
1875static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { 1877static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1876 { .irq = 32 + OMAP44XX_IRQ_GIC_START }, 1878 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1879 { .irq = -1 }
1877}; 1880};
1878 1881
1879static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { 1882static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
@@ -1882,6 +1885,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1882 .pa_end = 0x480591ff, 1885 .pa_end = 0x480591ff,
1883 .flags = ADDR_TYPE_RT 1886 .flags = ADDR_TYPE_RT
1884 }, 1887 },
1888 { }
1885}; 1889};
1886 1890
1887/* l4_per -> gpio4 */ 1891/* l4_per -> gpio4 */
@@ -1890,7 +1894,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1890 .slave = &omap44xx_gpio4_hwmod, 1894 .slave = &omap44xx_gpio4_hwmod,
1891 .clk = "l4_div_ck", 1895 .clk = "l4_div_ck",
1892 .addr = omap44xx_gpio4_addrs, 1896 .addr = omap44xx_gpio4_addrs,
1893 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
1894 .user = OCP_USER_MPU | OCP_USER_SDMA, 1897 .user = OCP_USER_MPU | OCP_USER_SDMA,
1895}; 1898};
1896 1899
@@ -1908,7 +1911,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
1908 .class = &omap44xx_gpio_hwmod_class, 1911 .class = &omap44xx_gpio_hwmod_class,
1909 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1912 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1910 .mpu_irqs = omap44xx_gpio4_irqs, 1913 .mpu_irqs = omap44xx_gpio4_irqs,
1911 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1912 .main_clk = "gpio4_ick", 1914 .main_clk = "gpio4_ick",
1913 .prcm = { 1915 .prcm = {
1914 .omap4 = { 1916 .omap4 = {
@@ -1927,6 +1929,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
1927static struct omap_hwmod omap44xx_gpio5_hwmod; 1929static struct omap_hwmod omap44xx_gpio5_hwmod;
1928static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { 1930static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1929 { .irq = 33 + OMAP44XX_IRQ_GIC_START }, 1931 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1932 { .irq = -1 }
1930}; 1933};
1931 1934
1932static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { 1935static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
@@ -1935,6 +1938,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1935 .pa_end = 0x4805b1ff, 1938 .pa_end = 0x4805b1ff,
1936 .flags = ADDR_TYPE_RT 1939 .flags = ADDR_TYPE_RT
1937 }, 1940 },
1941 { }
1938}; 1942};
1939 1943
1940/* l4_per -> gpio5 */ 1944/* l4_per -> gpio5 */
@@ -1943,7 +1947,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1943 .slave = &omap44xx_gpio5_hwmod, 1947 .slave = &omap44xx_gpio5_hwmod,
1944 .clk = "l4_div_ck", 1948 .clk = "l4_div_ck",
1945 .addr = omap44xx_gpio5_addrs, 1949 .addr = omap44xx_gpio5_addrs,
1946 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1947 .user = OCP_USER_MPU | OCP_USER_SDMA, 1950 .user = OCP_USER_MPU | OCP_USER_SDMA,
1948}; 1951};
1949 1952
@@ -1961,7 +1964,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
1961 .class = &omap44xx_gpio_hwmod_class, 1964 .class = &omap44xx_gpio_hwmod_class,
1962 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 1965 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1963 .mpu_irqs = omap44xx_gpio5_irqs, 1966 .mpu_irqs = omap44xx_gpio5_irqs,
1964 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1965 .main_clk = "gpio5_ick", 1967 .main_clk = "gpio5_ick",
1966 .prcm = { 1968 .prcm = {
1967 .omap4 = { 1969 .omap4 = {
@@ -1980,6 +1982,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
1980static struct omap_hwmod omap44xx_gpio6_hwmod; 1982static struct omap_hwmod omap44xx_gpio6_hwmod;
1981static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { 1983static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1982 { .irq = 34 + OMAP44XX_IRQ_GIC_START }, 1984 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1985 { .irq = -1 }
1983}; 1986};
1984 1987
1985static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { 1988static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
@@ -1988,6 +1991,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1988 .pa_end = 0x4805d1ff, 1991 .pa_end = 0x4805d1ff,
1989 .flags = ADDR_TYPE_RT 1992 .flags = ADDR_TYPE_RT
1990 }, 1993 },
1994 { }
1991}; 1995};
1992 1996
1993/* l4_per -> gpio6 */ 1997/* l4_per -> gpio6 */
@@ -1996,7 +2000,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1996 .slave = &omap44xx_gpio6_hwmod, 2000 .slave = &omap44xx_gpio6_hwmod,
1997 .clk = "l4_div_ck", 2001 .clk = "l4_div_ck",
1998 .addr = omap44xx_gpio6_addrs, 2002 .addr = omap44xx_gpio6_addrs,
1999 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
2000 .user = OCP_USER_MPU | OCP_USER_SDMA, 2003 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001}; 2004};
2002 2005
@@ -2014,7 +2017,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
2014 .class = &omap44xx_gpio_hwmod_class, 2017 .class = &omap44xx_gpio_hwmod_class,
2015 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, 2018 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2016 .mpu_irqs = omap44xx_gpio6_irqs, 2019 .mpu_irqs = omap44xx_gpio6_irqs,
2017 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
2018 .main_clk = "gpio6_ick", 2020 .main_clk = "gpio6_ick",
2019 .prcm = { 2021 .prcm = {
2020 .omap4 = { 2022 .omap4 = {
@@ -2044,7 +2046,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2044 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), 2046 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2045 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2047 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2046 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 2048 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2047 MSTANDBY_SMART), 2049 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2048 .sysc_fields = &omap_hwmod_sysc_type1, 2050 .sysc_fields = &omap_hwmod_sysc_type1,
2049}; 2051};
2050 2052
@@ -2058,6 +2060,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2058 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, 2060 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2059 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, 2061 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2060 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, 2062 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2063 { .irq = -1 }
2061}; 2064};
2062 2065
2063/* hsi master ports */ 2066/* hsi master ports */
@@ -2071,6 +2074,7 @@ static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2071 .pa_end = 0x4a05bfff, 2074 .pa_end = 0x4a05bfff,
2072 .flags = ADDR_TYPE_RT 2075 .flags = ADDR_TYPE_RT
2073 }, 2076 },
2077 { }
2074}; 2078};
2075 2079
2076/* l4_cfg -> hsi */ 2080/* l4_cfg -> hsi */
@@ -2079,7 +2083,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2079 .slave = &omap44xx_hsi_hwmod, 2083 .slave = &omap44xx_hsi_hwmod,
2080 .clk = "l4_div_ck", 2084 .clk = "l4_div_ck",
2081 .addr = omap44xx_hsi_addrs, 2085 .addr = omap44xx_hsi_addrs,
2082 .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
2083 .user = OCP_USER_MPU | OCP_USER_SDMA, 2086 .user = OCP_USER_MPU | OCP_USER_SDMA,
2084}; 2087};
2085 2088
@@ -2092,9 +2095,8 @@ static struct omap_hwmod omap44xx_hsi_hwmod = {
2092 .name = "hsi", 2095 .name = "hsi",
2093 .class = &omap44xx_hsi_hwmod_class, 2096 .class = &omap44xx_hsi_hwmod_class,
2094 .mpu_irqs = omap44xx_hsi_irqs, 2097 .mpu_irqs = omap44xx_hsi_irqs,
2095 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
2096 .main_clk = "hsi_fck", 2098 .main_clk = "hsi_fck",
2097 .prcm = { 2099 .prcm = {
2098 .omap4 = { 2100 .omap4 = {
2099 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 2101 .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2100 }, 2102 },
@@ -2131,11 +2133,13 @@ static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2131static struct omap_hwmod omap44xx_i2c1_hwmod; 2133static struct omap_hwmod omap44xx_i2c1_hwmod;
2132static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { 2134static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2133 { .irq = 56 + OMAP44XX_IRQ_GIC_START }, 2135 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2136 { .irq = -1 }
2134}; 2137};
2135 2138
2136static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { 2139static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2137 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, 2140 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2138 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, 2141 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2142 { .dma_req = -1 }
2139}; 2143};
2140 2144
2141static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { 2145static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
@@ -2144,6 +2148,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2144 .pa_end = 0x480700ff, 2148 .pa_end = 0x480700ff,
2145 .flags = ADDR_TYPE_RT 2149 .flags = ADDR_TYPE_RT
2146 }, 2150 },
2151 { }
2147}; 2152};
2148 2153
2149/* l4_per -> i2c1 */ 2154/* l4_per -> i2c1 */
@@ -2152,7 +2157,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2152 .slave = &omap44xx_i2c1_hwmod, 2157 .slave = &omap44xx_i2c1_hwmod,
2153 .clk = "l4_div_ck", 2158 .clk = "l4_div_ck",
2154 .addr = omap44xx_i2c1_addrs, 2159 .addr = omap44xx_i2c1_addrs,
2155 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
2156 .user = OCP_USER_MPU | OCP_USER_SDMA, 2160 .user = OCP_USER_MPU | OCP_USER_SDMA,
2157}; 2161};
2158 2162
@@ -2166,9 +2170,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2166 .class = &omap44xx_i2c_hwmod_class, 2170 .class = &omap44xx_i2c_hwmod_class,
2167 .flags = HWMOD_INIT_NO_RESET, 2171 .flags = HWMOD_INIT_NO_RESET,
2168 .mpu_irqs = omap44xx_i2c1_irqs, 2172 .mpu_irqs = omap44xx_i2c1_irqs,
2169 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
2170 .sdma_reqs = omap44xx_i2c1_sdma_reqs, 2173 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2171 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2172 .main_clk = "i2c1_fck", 2174 .main_clk = "i2c1_fck",
2173 .prcm = { 2175 .prcm = {
2174 .omap4 = { 2176 .omap4 = {
@@ -2184,11 +2186,13 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
2184static struct omap_hwmod omap44xx_i2c2_hwmod; 2186static struct omap_hwmod omap44xx_i2c2_hwmod;
2185static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { 2187static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2186 { .irq = 57 + OMAP44XX_IRQ_GIC_START }, 2188 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2189 { .irq = -1 }
2187}; 2190};
2188 2191
2189static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { 2192static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2190 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, 2193 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2191 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, 2194 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2195 { .dma_req = -1 }
2192}; 2196};
2193 2197
2194static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { 2198static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
@@ -2197,6 +2201,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2197 .pa_end = 0x480720ff, 2201 .pa_end = 0x480720ff,
2198 .flags = ADDR_TYPE_RT 2202 .flags = ADDR_TYPE_RT
2199 }, 2203 },
2204 { }
2200}; 2205};
2201 2206
2202/* l4_per -> i2c2 */ 2207/* l4_per -> i2c2 */
@@ -2205,7 +2210,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2205 .slave = &omap44xx_i2c2_hwmod, 2210 .slave = &omap44xx_i2c2_hwmod,
2206 .clk = "l4_div_ck", 2211 .clk = "l4_div_ck",
2207 .addr = omap44xx_i2c2_addrs, 2212 .addr = omap44xx_i2c2_addrs,
2208 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
2209 .user = OCP_USER_MPU | OCP_USER_SDMA, 2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2210}; 2214};
2211 2215
@@ -2219,9 +2223,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
2219 .class = &omap44xx_i2c_hwmod_class, 2223 .class = &omap44xx_i2c_hwmod_class,
2220 .flags = HWMOD_INIT_NO_RESET, 2224 .flags = HWMOD_INIT_NO_RESET,
2221 .mpu_irqs = omap44xx_i2c2_irqs, 2225 .mpu_irqs = omap44xx_i2c2_irqs,
2222 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
2223 .sdma_reqs = omap44xx_i2c2_sdma_reqs, 2226 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2224 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2225 .main_clk = "i2c2_fck", 2227 .main_clk = "i2c2_fck",
2226 .prcm = { 2228 .prcm = {
2227 .omap4 = { 2229 .omap4 = {
@@ -2237,11 +2239,13 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
2237static struct omap_hwmod omap44xx_i2c3_hwmod; 2239static struct omap_hwmod omap44xx_i2c3_hwmod;
2238static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { 2240static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2239 { .irq = 61 + OMAP44XX_IRQ_GIC_START }, 2241 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2242 { .irq = -1 }
2240}; 2243};
2241 2244
2242static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { 2245static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2243 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, 2246 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2244 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, 2247 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2248 { .dma_req = -1 }
2245}; 2249};
2246 2250
2247static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { 2251static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
@@ -2250,6 +2254,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2250 .pa_end = 0x480600ff, 2254 .pa_end = 0x480600ff,
2251 .flags = ADDR_TYPE_RT 2255 .flags = ADDR_TYPE_RT
2252 }, 2256 },
2257 { }
2253}; 2258};
2254 2259
2255/* l4_per -> i2c3 */ 2260/* l4_per -> i2c3 */
@@ -2258,7 +2263,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2258 .slave = &omap44xx_i2c3_hwmod, 2263 .slave = &omap44xx_i2c3_hwmod,
2259 .clk = "l4_div_ck", 2264 .clk = "l4_div_ck",
2260 .addr = omap44xx_i2c3_addrs, 2265 .addr = omap44xx_i2c3_addrs,
2261 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
2262 .user = OCP_USER_MPU | OCP_USER_SDMA, 2266 .user = OCP_USER_MPU | OCP_USER_SDMA,
2263}; 2267};
2264 2268
@@ -2272,9 +2276,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
2272 .class = &omap44xx_i2c_hwmod_class, 2276 .class = &omap44xx_i2c_hwmod_class,
2273 .flags = HWMOD_INIT_NO_RESET, 2277 .flags = HWMOD_INIT_NO_RESET,
2274 .mpu_irqs = omap44xx_i2c3_irqs, 2278 .mpu_irqs = omap44xx_i2c3_irqs,
2275 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
2276 .sdma_reqs = omap44xx_i2c3_sdma_reqs, 2279 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2277 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2278 .main_clk = "i2c3_fck", 2280 .main_clk = "i2c3_fck",
2279 .prcm = { 2281 .prcm = {
2280 .omap4 = { 2282 .omap4 = {
@@ -2290,11 +2292,13 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
2290static struct omap_hwmod omap44xx_i2c4_hwmod; 2292static struct omap_hwmod omap44xx_i2c4_hwmod;
2291static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { 2293static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2292 { .irq = 62 + OMAP44XX_IRQ_GIC_START }, 2294 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2295 { .irq = -1 }
2293}; 2296};
2294 2297
2295static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { 2298static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2296 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, 2299 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2297 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, 2300 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2301 { .dma_req = -1 }
2298}; 2302};
2299 2303
2300static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { 2304static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
@@ -2303,6 +2307,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2303 .pa_end = 0x483500ff, 2307 .pa_end = 0x483500ff,
2304 .flags = ADDR_TYPE_RT 2308 .flags = ADDR_TYPE_RT
2305 }, 2309 },
2310 { }
2306}; 2311};
2307 2312
2308/* l4_per -> i2c4 */ 2313/* l4_per -> i2c4 */
@@ -2311,7 +2316,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2311 .slave = &omap44xx_i2c4_hwmod, 2316 .slave = &omap44xx_i2c4_hwmod,
2312 .clk = "l4_div_ck", 2317 .clk = "l4_div_ck",
2313 .addr = omap44xx_i2c4_addrs, 2318 .addr = omap44xx_i2c4_addrs,
2314 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
2315 .user = OCP_USER_MPU | OCP_USER_SDMA, 2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2316}; 2320};
2317 2321
@@ -2325,9 +2329,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
2325 .class = &omap44xx_i2c_hwmod_class, 2329 .class = &omap44xx_i2c_hwmod_class,
2326 .flags = HWMOD_INIT_NO_RESET, 2330 .flags = HWMOD_INIT_NO_RESET,
2327 .mpu_irqs = omap44xx_i2c4_irqs, 2331 .mpu_irqs = omap44xx_i2c4_irqs,
2328 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
2329 .sdma_reqs = omap44xx_i2c4_sdma_reqs, 2332 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2330 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2331 .main_clk = "i2c4_fck", 2333 .main_clk = "i2c4_fck",
2332 .prcm = { 2334 .prcm = {
2333 .omap4 = { 2335 .omap4 = {
@@ -2351,6 +2353,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2351/* ipu */ 2353/* ipu */
2352static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { 2354static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2353 { .irq = 100 + OMAP44XX_IRQ_GIC_START }, 2355 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2356 { .irq = -1 }
2354}; 2357};
2355 2358
2356static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = { 2359static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
@@ -2390,7 +2393,7 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2390 .flags = HWMOD_INIT_NO_RESET, 2393 .flags = HWMOD_INIT_NO_RESET,
2391 .rst_lines = omap44xx_ipu_c0_resets, 2394 .rst_lines = omap44xx_ipu_c0_resets,
2392 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets), 2395 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2393 .prcm = { 2396 .prcm = {
2394 .omap4 = { 2397 .omap4 = {
2395 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2398 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2396 }, 2399 },
@@ -2405,7 +2408,7 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2405 .flags = HWMOD_INIT_NO_RESET, 2408 .flags = HWMOD_INIT_NO_RESET,
2406 .rst_lines = omap44xx_ipu_c1_resets, 2409 .rst_lines = omap44xx_ipu_c1_resets,
2407 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets), 2410 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2408 .prcm = { 2411 .prcm = {
2409 .omap4 = { 2412 .omap4 = {
2410 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2413 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2411 }, 2414 },
@@ -2417,11 +2420,10 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
2417 .name = "ipu", 2420 .name = "ipu",
2418 .class = &omap44xx_ipu_hwmod_class, 2421 .class = &omap44xx_ipu_hwmod_class,
2419 .mpu_irqs = omap44xx_ipu_irqs, 2422 .mpu_irqs = omap44xx_ipu_irqs,
2420 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
2421 .rst_lines = omap44xx_ipu_resets, 2423 .rst_lines = omap44xx_ipu_resets,
2422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), 2424 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2423 .main_clk = "ipu_fck", 2425 .main_clk = "ipu_fck",
2424 .prcm = { 2426 .prcm = {
2425 .omap4 = { 2427 .omap4 = {
2426 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 2428 .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2427 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL, 2429 .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
@@ -2446,7 +2448,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2446 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), 2448 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2447 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 2449 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2448 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 2450 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2449 MSTANDBY_SMART), 2451 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2450 .sysc_fields = &omap_hwmod_sysc_type2, 2452 .sysc_fields = &omap_hwmod_sysc_type2,
2451}; 2453};
2452 2454
@@ -2458,6 +2460,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2458/* iss */ 2460/* iss */
2459static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { 2461static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2460 { .irq = 24 + OMAP44XX_IRQ_GIC_START }, 2462 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2463 { .irq = -1 }
2461}; 2464};
2462 2465
2463static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { 2466static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
@@ -2465,6 +2468,7 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2465 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, 2468 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2466 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, 2469 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2467 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, 2470 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2471 { .dma_req = -1 }
2468}; 2472};
2469 2473
2470/* iss master ports */ 2474/* iss master ports */
@@ -2478,6 +2482,7 @@ static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2478 .pa_end = 0x520000ff, 2482 .pa_end = 0x520000ff,
2479 .flags = ADDR_TYPE_RT 2483 .flags = ADDR_TYPE_RT
2480 }, 2484 },
2485 { }
2481}; 2486};
2482 2487
2483/* l3_main_2 -> iss */ 2488/* l3_main_2 -> iss */
@@ -2486,7 +2491,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2486 .slave = &omap44xx_iss_hwmod, 2491 .slave = &omap44xx_iss_hwmod,
2487 .clk = "l3_div_ck", 2492 .clk = "l3_div_ck",
2488 .addr = omap44xx_iss_addrs, 2493 .addr = omap44xx_iss_addrs,
2489 .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
2490 .user = OCP_USER_MPU | OCP_USER_SDMA, 2494 .user = OCP_USER_MPU | OCP_USER_SDMA,
2491}; 2495};
2492 2496
@@ -2503,11 +2507,9 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
2503 .name = "iss", 2507 .name = "iss",
2504 .class = &omap44xx_iss_hwmod_class, 2508 .class = &omap44xx_iss_hwmod_class,
2505 .mpu_irqs = omap44xx_iss_irqs, 2509 .mpu_irqs = omap44xx_iss_irqs,
2506 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
2507 .sdma_reqs = omap44xx_iss_sdma_reqs, 2510 .sdma_reqs = omap44xx_iss_sdma_reqs,
2508 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2509 .main_clk = "iss_fck", 2511 .main_clk = "iss_fck",
2510 .prcm = { 2512 .prcm = {
2511 .omap4 = { 2513 .omap4 = {
2512 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, 2514 .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2513 }, 2515 },
@@ -2535,6 +2537,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2535 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, 2537 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2536 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, 2538 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2537 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, 2539 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2540 { .irq = -1 }
2538}; 2541};
2539 2542
2540static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { 2543static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
@@ -2561,6 +2564,7 @@ static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2561 .pa_end = 0x5a07ffff, 2564 .pa_end = 0x5a07ffff,
2562 .flags = ADDR_TYPE_RT 2565 .flags = ADDR_TYPE_RT
2563 }, 2566 },
2567 { }
2564}; 2568};
2565 2569
2566/* l3_main_2 -> iva */ 2570/* l3_main_2 -> iva */
@@ -2569,7 +2573,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2569 .slave = &omap44xx_iva_hwmod, 2573 .slave = &omap44xx_iva_hwmod,
2570 .clk = "l3_div_ck", 2574 .clk = "l3_div_ck",
2571 .addr = omap44xx_iva_addrs, 2575 .addr = omap44xx_iva_addrs,
2572 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
2573 .user = OCP_USER_MPU, 2576 .user = OCP_USER_MPU,
2574}; 2577};
2575 2578
@@ -2613,7 +2616,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
2613 .name = "iva", 2616 .name = "iva",
2614 .class = &omap44xx_iva_hwmod_class, 2617 .class = &omap44xx_iva_hwmod_class,
2615 .mpu_irqs = omap44xx_iva_irqs, 2618 .mpu_irqs = omap44xx_iva_irqs,
2616 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
2617 .rst_lines = omap44xx_iva_resets, 2619 .rst_lines = omap44xx_iva_resets,
2618 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), 2620 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2619 .main_clk = "iva_fck", 2621 .main_clk = "iva_fck",
@@ -2656,6 +2658,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2656static struct omap_hwmod omap44xx_kbd_hwmod; 2658static struct omap_hwmod omap44xx_kbd_hwmod;
2657static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { 2659static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2658 { .irq = 120 + OMAP44XX_IRQ_GIC_START }, 2660 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2661 { .irq = -1 }
2659}; 2662};
2660 2663
2661static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { 2664static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
@@ -2664,6 +2667,7 @@ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2664 .pa_end = 0x4a31c07f, 2667 .pa_end = 0x4a31c07f,
2665 .flags = ADDR_TYPE_RT 2668 .flags = ADDR_TYPE_RT
2666 }, 2669 },
2670 { }
2667}; 2671};
2668 2672
2669/* l4_wkup -> kbd */ 2673/* l4_wkup -> kbd */
@@ -2672,7 +2676,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2672 .slave = &omap44xx_kbd_hwmod, 2676 .slave = &omap44xx_kbd_hwmod,
2673 .clk = "l4_wkup_clk_mux_ck", 2677 .clk = "l4_wkup_clk_mux_ck",
2674 .addr = omap44xx_kbd_addrs, 2678 .addr = omap44xx_kbd_addrs,
2675 .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
2676 .user = OCP_USER_MPU | OCP_USER_SDMA, 2679 .user = OCP_USER_MPU | OCP_USER_SDMA,
2677}; 2680};
2678 2681
@@ -2685,9 +2688,8 @@ static struct omap_hwmod omap44xx_kbd_hwmod = {
2685 .name = "kbd", 2688 .name = "kbd",
2686 .class = &omap44xx_kbd_hwmod_class, 2689 .class = &omap44xx_kbd_hwmod_class,
2687 .mpu_irqs = omap44xx_kbd_irqs, 2690 .mpu_irqs = omap44xx_kbd_irqs,
2688 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
2689 .main_clk = "kbd_fck", 2691 .main_clk = "kbd_fck",
2690 .prcm = { 2692 .prcm = {
2691 .omap4 = { 2693 .omap4 = {
2692 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 2694 .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2693 }, 2695 },
@@ -2721,6 +2723,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2721static struct omap_hwmod omap44xx_mailbox_hwmod; 2723static struct omap_hwmod omap44xx_mailbox_hwmod;
2722static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { 2724static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2723 { .irq = 26 + OMAP44XX_IRQ_GIC_START }, 2725 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2726 { .irq = -1 }
2724}; 2727};
2725 2728
2726static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { 2729static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
@@ -2729,6 +2732,7 @@ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2729 .pa_end = 0x4a0f41ff, 2732 .pa_end = 0x4a0f41ff,
2730 .flags = ADDR_TYPE_RT 2733 .flags = ADDR_TYPE_RT
2731 }, 2734 },
2735 { }
2732}; 2736};
2733 2737
2734/* l4_cfg -> mailbox */ 2738/* l4_cfg -> mailbox */
@@ -2737,7 +2741,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2737 .slave = &omap44xx_mailbox_hwmod, 2741 .slave = &omap44xx_mailbox_hwmod,
2738 .clk = "l4_div_ck", 2742 .clk = "l4_div_ck",
2739 .addr = omap44xx_mailbox_addrs, 2743 .addr = omap44xx_mailbox_addrs,
2740 .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
2741 .user = OCP_USER_MPU | OCP_USER_SDMA, 2744 .user = OCP_USER_MPU | OCP_USER_SDMA,
2742}; 2745};
2743 2746
@@ -2750,8 +2753,7 @@ static struct omap_hwmod omap44xx_mailbox_hwmod = {
2750 .name = "mailbox", 2753 .name = "mailbox",
2751 .class = &omap44xx_mailbox_hwmod_class, 2754 .class = &omap44xx_mailbox_hwmod_class,
2752 .mpu_irqs = omap44xx_mailbox_irqs, 2755 .mpu_irqs = omap44xx_mailbox_irqs,
2753 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs), 2756 .prcm = {
2754 .prcm = {
2755 .omap4 = { 2757 .omap4 = {
2756 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL, 2758 .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2757 }, 2759 },
@@ -2784,11 +2786,13 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2784static struct omap_hwmod omap44xx_mcbsp1_hwmod; 2786static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2785static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { 2787static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2786 { .irq = 17 + OMAP44XX_IRQ_GIC_START }, 2788 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2789 { .irq = -1 }
2787}; 2790};
2788 2791
2789static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { 2792static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2790 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, 2793 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2791 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, 2794 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2795 { .dma_req = -1 }
2792}; 2796};
2793 2797
2794static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { 2798static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
@@ -2798,6 +2802,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2798 .pa_end = 0x401220ff, 2802 .pa_end = 0x401220ff,
2799 .flags = ADDR_TYPE_RT 2803 .flags = ADDR_TYPE_RT
2800 }, 2804 },
2805 { }
2801}; 2806};
2802 2807
2803/* l4_abe -> mcbsp1 */ 2808/* l4_abe -> mcbsp1 */
@@ -2806,7 +2811,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2806 .slave = &omap44xx_mcbsp1_hwmod, 2811 .slave = &omap44xx_mcbsp1_hwmod,
2807 .clk = "ocp_abe_iclk", 2812 .clk = "ocp_abe_iclk",
2808 .addr = omap44xx_mcbsp1_addrs, 2813 .addr = omap44xx_mcbsp1_addrs,
2809 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2810 .user = OCP_USER_MPU, 2814 .user = OCP_USER_MPU,
2811}; 2815};
2812 2816
@@ -2817,6 +2821,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2817 .pa_end = 0x490220ff, 2821 .pa_end = 0x490220ff,
2818 .flags = ADDR_TYPE_RT 2822 .flags = ADDR_TYPE_RT
2819 }, 2823 },
2824 { }
2820}; 2825};
2821 2826
2822/* l4_abe -> mcbsp1 (dma) */ 2827/* l4_abe -> mcbsp1 (dma) */
@@ -2825,7 +2830,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2825 .slave = &omap44xx_mcbsp1_hwmod, 2830 .slave = &omap44xx_mcbsp1_hwmod,
2826 .clk = "ocp_abe_iclk", 2831 .clk = "ocp_abe_iclk",
2827 .addr = omap44xx_mcbsp1_dma_addrs, 2832 .addr = omap44xx_mcbsp1_dma_addrs,
2828 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2829 .user = OCP_USER_SDMA, 2833 .user = OCP_USER_SDMA,
2830}; 2834};
2831 2835
@@ -2839,9 +2843,7 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2839 .name = "mcbsp1", 2843 .name = "mcbsp1",
2840 .class = &omap44xx_mcbsp_hwmod_class, 2844 .class = &omap44xx_mcbsp_hwmod_class,
2841 .mpu_irqs = omap44xx_mcbsp1_irqs, 2845 .mpu_irqs = omap44xx_mcbsp1_irqs,
2842 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2843 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, 2846 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
2844 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2845 .main_clk = "mcbsp1_fck", 2847 .main_clk = "mcbsp1_fck",
2846 .prcm = { 2848 .prcm = {
2847 .omap4 = { 2849 .omap4 = {
@@ -2857,11 +2859,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2857static struct omap_hwmod omap44xx_mcbsp2_hwmod; 2859static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2858static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { 2860static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2859 { .irq = 22 + OMAP44XX_IRQ_GIC_START }, 2861 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2862 { .irq = -1 }
2860}; 2863};
2861 2864
2862static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { 2865static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2863 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, 2866 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2864 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, 2867 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2868 { .dma_req = -1 }
2865}; 2869};
2866 2870
2867static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { 2871static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
@@ -2871,6 +2875,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2871 .pa_end = 0x401240ff, 2875 .pa_end = 0x401240ff,
2872 .flags = ADDR_TYPE_RT 2876 .flags = ADDR_TYPE_RT
2873 }, 2877 },
2878 { }
2874}; 2879};
2875 2880
2876/* l4_abe -> mcbsp2 */ 2881/* l4_abe -> mcbsp2 */
@@ -2879,7 +2884,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2879 .slave = &omap44xx_mcbsp2_hwmod, 2884 .slave = &omap44xx_mcbsp2_hwmod,
2880 .clk = "ocp_abe_iclk", 2885 .clk = "ocp_abe_iclk",
2881 .addr = omap44xx_mcbsp2_addrs, 2886 .addr = omap44xx_mcbsp2_addrs,
2882 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2883 .user = OCP_USER_MPU, 2887 .user = OCP_USER_MPU,
2884}; 2888};
2885 2889
@@ -2890,6 +2894,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2890 .pa_end = 0x490240ff, 2894 .pa_end = 0x490240ff,
2891 .flags = ADDR_TYPE_RT 2895 .flags = ADDR_TYPE_RT
2892 }, 2896 },
2897 { }
2893}; 2898};
2894 2899
2895/* l4_abe -> mcbsp2 (dma) */ 2900/* l4_abe -> mcbsp2 (dma) */
@@ -2898,7 +2903,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2898 .slave = &omap44xx_mcbsp2_hwmod, 2903 .slave = &omap44xx_mcbsp2_hwmod,
2899 .clk = "ocp_abe_iclk", 2904 .clk = "ocp_abe_iclk",
2900 .addr = omap44xx_mcbsp2_dma_addrs, 2905 .addr = omap44xx_mcbsp2_dma_addrs,
2901 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2902 .user = OCP_USER_SDMA, 2906 .user = OCP_USER_SDMA,
2903}; 2907};
2904 2908
@@ -2912,9 +2916,7 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2912 .name = "mcbsp2", 2916 .name = "mcbsp2",
2913 .class = &omap44xx_mcbsp_hwmod_class, 2917 .class = &omap44xx_mcbsp_hwmod_class,
2914 .mpu_irqs = omap44xx_mcbsp2_irqs, 2918 .mpu_irqs = omap44xx_mcbsp2_irqs,
2915 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2916 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, 2919 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2917 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2918 .main_clk = "mcbsp2_fck", 2920 .main_clk = "mcbsp2_fck",
2919 .prcm = { 2921 .prcm = {
2920 .omap4 = { 2922 .omap4 = {
@@ -2930,11 +2932,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2930static struct omap_hwmod omap44xx_mcbsp3_hwmod; 2932static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2931static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { 2933static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2932 { .irq = 23 + OMAP44XX_IRQ_GIC_START }, 2934 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2935 { .irq = -1 }
2933}; 2936};
2934 2937
2935static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { 2938static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2936 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, 2939 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2937 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, 2940 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2941 { .dma_req = -1 }
2938}; 2942};
2939 2943
2940static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { 2944static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
@@ -2944,6 +2948,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2944 .pa_end = 0x401260ff, 2948 .pa_end = 0x401260ff,
2945 .flags = ADDR_TYPE_RT 2949 .flags = ADDR_TYPE_RT
2946 }, 2950 },
2951 { }
2947}; 2952};
2948 2953
2949/* l4_abe -> mcbsp3 */ 2954/* l4_abe -> mcbsp3 */
@@ -2952,7 +2957,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2952 .slave = &omap44xx_mcbsp3_hwmod, 2957 .slave = &omap44xx_mcbsp3_hwmod,
2953 .clk = "ocp_abe_iclk", 2958 .clk = "ocp_abe_iclk",
2954 .addr = omap44xx_mcbsp3_addrs, 2959 .addr = omap44xx_mcbsp3_addrs,
2955 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2956 .user = OCP_USER_MPU, 2960 .user = OCP_USER_MPU,
2957}; 2961};
2958 2962
@@ -2963,6 +2967,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2963 .pa_end = 0x490260ff, 2967 .pa_end = 0x490260ff,
2964 .flags = ADDR_TYPE_RT 2968 .flags = ADDR_TYPE_RT
2965 }, 2969 },
2970 { }
2966}; 2971};
2967 2972
2968/* l4_abe -> mcbsp3 (dma) */ 2973/* l4_abe -> mcbsp3 (dma) */
@@ -2971,7 +2976,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2971 .slave = &omap44xx_mcbsp3_hwmod, 2976 .slave = &omap44xx_mcbsp3_hwmod,
2972 .clk = "ocp_abe_iclk", 2977 .clk = "ocp_abe_iclk",
2973 .addr = omap44xx_mcbsp3_dma_addrs, 2978 .addr = omap44xx_mcbsp3_dma_addrs,
2974 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2975 .user = OCP_USER_SDMA, 2979 .user = OCP_USER_SDMA,
2976}; 2980};
2977 2981
@@ -2985,9 +2989,7 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2985 .name = "mcbsp3", 2989 .name = "mcbsp3",
2986 .class = &omap44xx_mcbsp_hwmod_class, 2990 .class = &omap44xx_mcbsp_hwmod_class,
2987 .mpu_irqs = omap44xx_mcbsp3_irqs, 2991 .mpu_irqs = omap44xx_mcbsp3_irqs,
2988 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2989 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, 2992 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2990 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2991 .main_clk = "mcbsp3_fck", 2993 .main_clk = "mcbsp3_fck",
2992 .prcm = { 2994 .prcm = {
2993 .omap4 = { 2995 .omap4 = {
@@ -3003,11 +3005,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3003static struct omap_hwmod omap44xx_mcbsp4_hwmod; 3005static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3004static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { 3006static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3005 { .irq = 16 + OMAP44XX_IRQ_GIC_START }, 3007 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3008 { .irq = -1 }
3006}; 3009};
3007 3010
3008static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { 3011static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3009 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, 3012 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3010 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, 3013 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3014 { .dma_req = -1 }
3011}; 3015};
3012 3016
3013static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { 3017static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
@@ -3016,6 +3020,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3016 .pa_end = 0x480960ff, 3020 .pa_end = 0x480960ff,
3017 .flags = ADDR_TYPE_RT 3021 .flags = ADDR_TYPE_RT
3018 }, 3022 },
3023 { }
3019}; 3024};
3020 3025
3021/* l4_per -> mcbsp4 */ 3026/* l4_per -> mcbsp4 */
@@ -3024,7 +3029,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3024 .slave = &omap44xx_mcbsp4_hwmod, 3029 .slave = &omap44xx_mcbsp4_hwmod,
3025 .clk = "l4_div_ck", 3030 .clk = "l4_div_ck",
3026 .addr = omap44xx_mcbsp4_addrs, 3031 .addr = omap44xx_mcbsp4_addrs,
3027 .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
3028 .user = OCP_USER_MPU | OCP_USER_SDMA, 3032 .user = OCP_USER_MPU | OCP_USER_SDMA,
3029}; 3033};
3030 3034
@@ -3037,9 +3041,7 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3037 .name = "mcbsp4", 3041 .name = "mcbsp4",
3038 .class = &omap44xx_mcbsp_hwmod_class, 3042 .class = &omap44xx_mcbsp_hwmod_class,
3039 .mpu_irqs = omap44xx_mcbsp4_irqs, 3043 .mpu_irqs = omap44xx_mcbsp4_irqs,
3040 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
3041 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, 3044 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3042 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
3043 .main_clk = "mcbsp4_fck", 3045 .main_clk = "mcbsp4_fck",
3044 .prcm = { 3046 .prcm = {
3045 .omap4 = { 3047 .omap4 = {
@@ -3076,11 +3078,13 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3076static struct omap_hwmod omap44xx_mcpdm_hwmod; 3078static struct omap_hwmod omap44xx_mcpdm_hwmod;
3077static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { 3079static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3078 { .irq = 112 + OMAP44XX_IRQ_GIC_START }, 3080 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3081 { .irq = -1 }
3079}; 3082};
3080 3083
3081static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { 3084static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3082 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, 3085 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3083 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, 3086 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3087 { .dma_req = -1 }
3084}; 3088};
3085 3089
3086static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { 3090static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
@@ -3089,6 +3093,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3089 .pa_end = 0x4013207f, 3093 .pa_end = 0x4013207f,
3090 .flags = ADDR_TYPE_RT 3094 .flags = ADDR_TYPE_RT
3091 }, 3095 },
3096 { }
3092}; 3097};
3093 3098
3094/* l4_abe -> mcpdm */ 3099/* l4_abe -> mcpdm */
@@ -3097,7 +3102,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3097 .slave = &omap44xx_mcpdm_hwmod, 3102 .slave = &omap44xx_mcpdm_hwmod,
3098 .clk = "ocp_abe_iclk", 3103 .clk = "ocp_abe_iclk",
3099 .addr = omap44xx_mcpdm_addrs, 3104 .addr = omap44xx_mcpdm_addrs,
3100 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3101 .user = OCP_USER_MPU, 3105 .user = OCP_USER_MPU,
3102}; 3106};
3103 3107
@@ -3107,6 +3111,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3107 .pa_end = 0x4903207f, 3111 .pa_end = 0x4903207f,
3108 .flags = ADDR_TYPE_RT 3112 .flags = ADDR_TYPE_RT
3109 }, 3113 },
3114 { }
3110}; 3115};
3111 3116
3112/* l4_abe -> mcpdm (dma) */ 3117/* l4_abe -> mcpdm (dma) */
@@ -3115,7 +3120,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3115 .slave = &omap44xx_mcpdm_hwmod, 3120 .slave = &omap44xx_mcpdm_hwmod,
3116 .clk = "ocp_abe_iclk", 3121 .clk = "ocp_abe_iclk",
3117 .addr = omap44xx_mcpdm_dma_addrs, 3122 .addr = omap44xx_mcpdm_dma_addrs,
3118 .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3119 .user = OCP_USER_SDMA, 3123 .user = OCP_USER_SDMA,
3120}; 3124};
3121 3125
@@ -3129,11 +3133,9 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3129 .name = "mcpdm", 3133 .name = "mcpdm",
3130 .class = &omap44xx_mcpdm_hwmod_class, 3134 .class = &omap44xx_mcpdm_hwmod_class,
3131 .mpu_irqs = omap44xx_mcpdm_irqs, 3135 .mpu_irqs = omap44xx_mcpdm_irqs,
3132 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3133 .sdma_reqs = omap44xx_mcpdm_sdma_reqs, 3136 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3134 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3135 .main_clk = "mcpdm_fck", 3137 .main_clk = "mcpdm_fck",
3136 .prcm = { 3138 .prcm = {
3137 .omap4 = { 3139 .omap4 = {
3138 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 3140 .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3139 }, 3141 },
@@ -3169,6 +3171,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3169static struct omap_hwmod omap44xx_mcspi1_hwmod; 3171static struct omap_hwmod omap44xx_mcspi1_hwmod;
3170static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { 3172static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3171 { .irq = 65 + OMAP44XX_IRQ_GIC_START }, 3173 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3174 { .irq = -1 }
3172}; 3175};
3173 3176
3174static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { 3177static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
@@ -3180,6 +3183,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3180 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, 3183 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3181 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, 3184 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3182 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, 3185 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3186 { .dma_req = -1 }
3183}; 3187};
3184 3188
3185static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { 3189static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
@@ -3188,6 +3192,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3188 .pa_end = 0x480981ff, 3192 .pa_end = 0x480981ff,
3189 .flags = ADDR_TYPE_RT 3193 .flags = ADDR_TYPE_RT
3190 }, 3194 },
3195 { }
3191}; 3196};
3192 3197
3193/* l4_per -> mcspi1 */ 3198/* l4_per -> mcspi1 */
@@ -3196,7 +3201,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3196 .slave = &omap44xx_mcspi1_hwmod, 3201 .slave = &omap44xx_mcspi1_hwmod,
3197 .clk = "l4_div_ck", 3202 .clk = "l4_div_ck",
3198 .addr = omap44xx_mcspi1_addrs, 3203 .addr = omap44xx_mcspi1_addrs,
3199 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3200 .user = OCP_USER_MPU | OCP_USER_SDMA, 3204 .user = OCP_USER_MPU | OCP_USER_SDMA,
3201}; 3205};
3202 3206
@@ -3214,9 +3218,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3214 .name = "mcspi1", 3218 .name = "mcspi1",
3215 .class = &omap44xx_mcspi_hwmod_class, 3219 .class = &omap44xx_mcspi_hwmod_class,
3216 .mpu_irqs = omap44xx_mcspi1_irqs, 3220 .mpu_irqs = omap44xx_mcspi1_irqs,
3217 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3218 .sdma_reqs = omap44xx_mcspi1_sdma_reqs, 3221 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3219 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3220 .main_clk = "mcspi1_fck", 3222 .main_clk = "mcspi1_fck",
3221 .prcm = { 3223 .prcm = {
3222 .omap4 = { 3224 .omap4 = {
@@ -3233,6 +3235,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3233static struct omap_hwmod omap44xx_mcspi2_hwmod; 3235static struct omap_hwmod omap44xx_mcspi2_hwmod;
3234static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { 3236static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3235 { .irq = 66 + OMAP44XX_IRQ_GIC_START }, 3237 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3238 { .irq = -1 }
3236}; 3239};
3237 3240
3238static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { 3241static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
@@ -3240,6 +3243,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3240 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, 3243 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3241 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, 3244 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3242 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, 3245 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3246 { .dma_req = -1 }
3243}; 3247};
3244 3248
3245static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { 3249static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
@@ -3248,6 +3252,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3248 .pa_end = 0x4809a1ff, 3252 .pa_end = 0x4809a1ff,
3249 .flags = ADDR_TYPE_RT 3253 .flags = ADDR_TYPE_RT
3250 }, 3254 },
3255 { }
3251}; 3256};
3252 3257
3253/* l4_per -> mcspi2 */ 3258/* l4_per -> mcspi2 */
@@ -3256,7 +3261,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3256 .slave = &omap44xx_mcspi2_hwmod, 3261 .slave = &omap44xx_mcspi2_hwmod,
3257 .clk = "l4_div_ck", 3262 .clk = "l4_div_ck",
3258 .addr = omap44xx_mcspi2_addrs, 3263 .addr = omap44xx_mcspi2_addrs,
3259 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3260 .user = OCP_USER_MPU | OCP_USER_SDMA, 3264 .user = OCP_USER_MPU | OCP_USER_SDMA,
3261}; 3265};
3262 3266
@@ -3274,9 +3278,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3274 .name = "mcspi2", 3278 .name = "mcspi2",
3275 .class = &omap44xx_mcspi_hwmod_class, 3279 .class = &omap44xx_mcspi_hwmod_class,
3276 .mpu_irqs = omap44xx_mcspi2_irqs, 3280 .mpu_irqs = omap44xx_mcspi2_irqs,
3277 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3278 .sdma_reqs = omap44xx_mcspi2_sdma_reqs, 3281 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3279 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3280 .main_clk = "mcspi2_fck", 3282 .main_clk = "mcspi2_fck",
3281 .prcm = { 3283 .prcm = {
3282 .omap4 = { 3284 .omap4 = {
@@ -3293,6 +3295,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3293static struct omap_hwmod omap44xx_mcspi3_hwmod; 3295static struct omap_hwmod omap44xx_mcspi3_hwmod;
3294static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { 3296static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3295 { .irq = 91 + OMAP44XX_IRQ_GIC_START }, 3297 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3298 { .irq = -1 }
3296}; 3299};
3297 3300
3298static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { 3301static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
@@ -3300,6 +3303,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3300 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, 3303 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3301 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, 3304 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3302 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, 3305 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3306 { .dma_req = -1 }
3303}; 3307};
3304 3308
3305static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { 3309static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
@@ -3308,6 +3312,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3308 .pa_end = 0x480b81ff, 3312 .pa_end = 0x480b81ff,
3309 .flags = ADDR_TYPE_RT 3313 .flags = ADDR_TYPE_RT
3310 }, 3314 },
3315 { }
3311}; 3316};
3312 3317
3313/* l4_per -> mcspi3 */ 3318/* l4_per -> mcspi3 */
@@ -3316,7 +3321,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3316 .slave = &omap44xx_mcspi3_hwmod, 3321 .slave = &omap44xx_mcspi3_hwmod,
3317 .clk = "l4_div_ck", 3322 .clk = "l4_div_ck",
3318 .addr = omap44xx_mcspi3_addrs, 3323 .addr = omap44xx_mcspi3_addrs,
3319 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3320 .user = OCP_USER_MPU | OCP_USER_SDMA, 3324 .user = OCP_USER_MPU | OCP_USER_SDMA,
3321}; 3325};
3322 3326
@@ -3334,9 +3338,7 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3334 .name = "mcspi3", 3338 .name = "mcspi3",
3335 .class = &omap44xx_mcspi_hwmod_class, 3339 .class = &omap44xx_mcspi_hwmod_class,
3336 .mpu_irqs = omap44xx_mcspi3_irqs, 3340 .mpu_irqs = omap44xx_mcspi3_irqs,
3337 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3338 .sdma_reqs = omap44xx_mcspi3_sdma_reqs, 3341 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3339 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3340 .main_clk = "mcspi3_fck", 3342 .main_clk = "mcspi3_fck",
3341 .prcm = { 3343 .prcm = {
3342 .omap4 = { 3344 .omap4 = {
@@ -3353,11 +3355,13 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3353static struct omap_hwmod omap44xx_mcspi4_hwmod; 3355static struct omap_hwmod omap44xx_mcspi4_hwmod;
3354static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { 3356static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3355 { .irq = 48 + OMAP44XX_IRQ_GIC_START }, 3357 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3358 { .irq = -1 }
3356}; 3359};
3357 3360
3358static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { 3361static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3359 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, 3362 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3360 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, 3363 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3364 { .dma_req = -1 }
3361}; 3365};
3362 3366
3363static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { 3367static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
@@ -3366,6 +3370,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3366 .pa_end = 0x480ba1ff, 3370 .pa_end = 0x480ba1ff,
3367 .flags = ADDR_TYPE_RT 3371 .flags = ADDR_TYPE_RT
3368 }, 3372 },
3373 { }
3369}; 3374};
3370 3375
3371/* l4_per -> mcspi4 */ 3376/* l4_per -> mcspi4 */
@@ -3374,7 +3379,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3374 .slave = &omap44xx_mcspi4_hwmod, 3379 .slave = &omap44xx_mcspi4_hwmod,
3375 .clk = "l4_div_ck", 3380 .clk = "l4_div_ck",
3376 .addr = omap44xx_mcspi4_addrs, 3381 .addr = omap44xx_mcspi4_addrs,
3377 .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3378 .user = OCP_USER_MPU | OCP_USER_SDMA, 3382 .user = OCP_USER_MPU | OCP_USER_SDMA,
3379}; 3383};
3380 3384
@@ -3392,9 +3396,7 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3392 .name = "mcspi4", 3396 .name = "mcspi4",
3393 .class = &omap44xx_mcspi_hwmod_class, 3397 .class = &omap44xx_mcspi_hwmod_class,
3394 .mpu_irqs = omap44xx_mcspi4_irqs, 3398 .mpu_irqs = omap44xx_mcspi4_irqs,
3395 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3396 .sdma_reqs = omap44xx_mcspi4_sdma_reqs, 3399 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3397 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3398 .main_clk = "mcspi4_fck", 3400 .main_clk = "mcspi4_fck",
3399 .prcm = { 3401 .prcm = {
3400 .omap4 = { 3402 .omap4 = {
@@ -3420,7 +3422,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3420 SYSC_HAS_SOFTRESET), 3422 SYSC_HAS_SOFTRESET),
3421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 3423 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3422 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | 3424 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3423 MSTANDBY_SMART), 3425 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3424 .sysc_fields = &omap_hwmod_sysc_type2, 3426 .sysc_fields = &omap_hwmod_sysc_type2,
3425}; 3427};
3426 3428
@@ -3430,14 +3432,15 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3430}; 3432};
3431 3433
3432/* mmc1 */ 3434/* mmc1 */
3433
3434static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { 3435static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3435 { .irq = 83 + OMAP44XX_IRQ_GIC_START }, 3436 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3437 { .irq = -1 }
3436}; 3438};
3437 3439
3438static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { 3440static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3439 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, 3441 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3440 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, 3442 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3443 { .dma_req = -1 }
3441}; 3444};
3442 3445
3443/* mmc1 master ports */ 3446/* mmc1 master ports */
@@ -3451,6 +3454,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3451 .pa_end = 0x4809c3ff, 3454 .pa_end = 0x4809c3ff,
3452 .flags = ADDR_TYPE_RT 3455 .flags = ADDR_TYPE_RT
3453 }, 3456 },
3457 { }
3454}; 3458};
3455 3459
3456/* l4_per -> mmc1 */ 3460/* l4_per -> mmc1 */
@@ -3459,7 +3463,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3459 .slave = &omap44xx_mmc1_hwmod, 3463 .slave = &omap44xx_mmc1_hwmod,
3460 .clk = "l4_div_ck", 3464 .clk = "l4_div_ck",
3461 .addr = omap44xx_mmc1_addrs, 3465 .addr = omap44xx_mmc1_addrs,
3462 .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
3463 .user = OCP_USER_MPU | OCP_USER_SDMA, 3466 .user = OCP_USER_MPU | OCP_USER_SDMA,
3464}; 3467};
3465 3468
@@ -3477,11 +3480,9 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3477 .name = "mmc1", 3480 .name = "mmc1",
3478 .class = &omap44xx_mmc_hwmod_class, 3481 .class = &omap44xx_mmc_hwmod_class,
3479 .mpu_irqs = omap44xx_mmc1_irqs, 3482 .mpu_irqs = omap44xx_mmc1_irqs,
3480 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
3481 .sdma_reqs = omap44xx_mmc1_sdma_reqs, 3483 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3482 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3483 .main_clk = "mmc1_fck", 3484 .main_clk = "mmc1_fck",
3484 .prcm = { 3485 .prcm = {
3485 .omap4 = { 3486 .omap4 = {
3486 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 3487 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3487 }, 3488 },
@@ -3497,11 +3498,13 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3497/* mmc2 */ 3498/* mmc2 */
3498static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { 3499static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3499 { .irq = 86 + OMAP44XX_IRQ_GIC_START }, 3500 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3501 { .irq = -1 }
3500}; 3502};
3501 3503
3502static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { 3504static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3503 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, 3505 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3504 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, 3506 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3507 { .dma_req = -1 }
3505}; 3508};
3506 3509
3507/* mmc2 master ports */ 3510/* mmc2 master ports */
@@ -3515,6 +3518,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3515 .pa_end = 0x480b43ff, 3518 .pa_end = 0x480b43ff,
3516 .flags = ADDR_TYPE_RT 3519 .flags = ADDR_TYPE_RT
3517 }, 3520 },
3521 { }
3518}; 3522};
3519 3523
3520/* l4_per -> mmc2 */ 3524/* l4_per -> mmc2 */
@@ -3523,7 +3527,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3523 .slave = &omap44xx_mmc2_hwmod, 3527 .slave = &omap44xx_mmc2_hwmod,
3524 .clk = "l4_div_ck", 3528 .clk = "l4_div_ck",
3525 .addr = omap44xx_mmc2_addrs, 3529 .addr = omap44xx_mmc2_addrs,
3526 .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
3527 .user = OCP_USER_MPU | OCP_USER_SDMA, 3530 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528}; 3531};
3529 3532
@@ -3536,11 +3539,9 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
3536 .name = "mmc2", 3539 .name = "mmc2",
3537 .class = &omap44xx_mmc_hwmod_class, 3540 .class = &omap44xx_mmc_hwmod_class,
3538 .mpu_irqs = omap44xx_mmc2_irqs, 3541 .mpu_irqs = omap44xx_mmc2_irqs,
3539 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
3540 .sdma_reqs = omap44xx_mmc2_sdma_reqs, 3542 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3541 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3542 .main_clk = "mmc2_fck", 3543 .main_clk = "mmc2_fck",
3543 .prcm = { 3544 .prcm = {
3544 .omap4 = { 3545 .omap4 = {
3545 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, 3546 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3546 }, 3547 },
@@ -3556,11 +3557,13 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
3556static struct omap_hwmod omap44xx_mmc3_hwmod; 3557static struct omap_hwmod omap44xx_mmc3_hwmod;
3557static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { 3558static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3558 { .irq = 94 + OMAP44XX_IRQ_GIC_START }, 3559 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3560 { .irq = -1 }
3559}; 3561};
3560 3562
3561static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { 3563static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3562 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, 3564 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3563 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, 3565 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3566 { .dma_req = -1 }
3564}; 3567};
3565 3568
3566static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { 3569static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
@@ -3569,6 +3572,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3569 .pa_end = 0x480ad3ff, 3572 .pa_end = 0x480ad3ff,
3570 .flags = ADDR_TYPE_RT 3573 .flags = ADDR_TYPE_RT
3571 }, 3574 },
3575 { }
3572}; 3576};
3573 3577
3574/* l4_per -> mmc3 */ 3578/* l4_per -> mmc3 */
@@ -3577,7 +3581,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3577 .slave = &omap44xx_mmc3_hwmod, 3581 .slave = &omap44xx_mmc3_hwmod,
3578 .clk = "l4_div_ck", 3582 .clk = "l4_div_ck",
3579 .addr = omap44xx_mmc3_addrs, 3583 .addr = omap44xx_mmc3_addrs,
3580 .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
3581 .user = OCP_USER_MPU | OCP_USER_SDMA, 3584 .user = OCP_USER_MPU | OCP_USER_SDMA,
3582}; 3585};
3583 3586
@@ -3590,11 +3593,9 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
3590 .name = "mmc3", 3593 .name = "mmc3",
3591 .class = &omap44xx_mmc_hwmod_class, 3594 .class = &omap44xx_mmc_hwmod_class,
3592 .mpu_irqs = omap44xx_mmc3_irqs, 3595 .mpu_irqs = omap44xx_mmc3_irqs,
3593 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
3594 .sdma_reqs = omap44xx_mmc3_sdma_reqs, 3596 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3595 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3596 .main_clk = "mmc3_fck", 3597 .main_clk = "mmc3_fck",
3597 .prcm = { 3598 .prcm = {
3598 .omap4 = { 3599 .omap4 = {
3599 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, 3600 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3600 }, 3601 },
@@ -3608,11 +3609,13 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
3608static struct omap_hwmod omap44xx_mmc4_hwmod; 3609static struct omap_hwmod omap44xx_mmc4_hwmod;
3609static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { 3610static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3610 { .irq = 96 + OMAP44XX_IRQ_GIC_START }, 3611 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3612 { .irq = -1 }
3611}; 3613};
3612 3614
3613static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { 3615static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3614 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, 3616 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3615 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, 3617 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3618 { .dma_req = -1 }
3616}; 3619};
3617 3620
3618static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { 3621static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
@@ -3621,6 +3624,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3621 .pa_end = 0x480d13ff, 3624 .pa_end = 0x480d13ff,
3622 .flags = ADDR_TYPE_RT 3625 .flags = ADDR_TYPE_RT
3623 }, 3626 },
3627 { }
3624}; 3628};
3625 3629
3626/* l4_per -> mmc4 */ 3630/* l4_per -> mmc4 */
@@ -3629,7 +3633,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3629 .slave = &omap44xx_mmc4_hwmod, 3633 .slave = &omap44xx_mmc4_hwmod,
3630 .clk = "l4_div_ck", 3634 .clk = "l4_div_ck",
3631 .addr = omap44xx_mmc4_addrs, 3635 .addr = omap44xx_mmc4_addrs,
3632 .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
3633 .user = OCP_USER_MPU | OCP_USER_SDMA, 3636 .user = OCP_USER_MPU | OCP_USER_SDMA,
3634}; 3637};
3635 3638
@@ -3642,11 +3645,10 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
3642 .name = "mmc4", 3645 .name = "mmc4",
3643 .class = &omap44xx_mmc_hwmod_class, 3646 .class = &omap44xx_mmc_hwmod_class,
3644 .mpu_irqs = omap44xx_mmc4_irqs, 3647 .mpu_irqs = omap44xx_mmc4_irqs,
3645 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs), 3648
3646 .sdma_reqs = omap44xx_mmc4_sdma_reqs, 3649 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3647 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3648 .main_clk = "mmc4_fck", 3650 .main_clk = "mmc4_fck",
3649 .prcm = { 3651 .prcm = {
3650 .omap4 = { 3652 .omap4 = {
3651 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, 3653 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3652 }, 3654 },
@@ -3660,11 +3662,13 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
3660static struct omap_hwmod omap44xx_mmc5_hwmod; 3662static struct omap_hwmod omap44xx_mmc5_hwmod;
3661static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { 3663static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3662 { .irq = 59 + OMAP44XX_IRQ_GIC_START }, 3664 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3665 { .irq = -1 }
3663}; 3666};
3664 3667
3665static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { 3668static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3666 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, 3669 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3667 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, 3670 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3671 { .dma_req = -1 }
3668}; 3672};
3669 3673
3670static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { 3674static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
@@ -3673,6 +3677,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3673 .pa_end = 0x480d53ff, 3677 .pa_end = 0x480d53ff,
3674 .flags = ADDR_TYPE_RT 3678 .flags = ADDR_TYPE_RT
3675 }, 3679 },
3680 { }
3676}; 3681};
3677 3682
3678/* l4_per -> mmc5 */ 3683/* l4_per -> mmc5 */
@@ -3681,7 +3686,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3681 .slave = &omap44xx_mmc5_hwmod, 3686 .slave = &omap44xx_mmc5_hwmod,
3682 .clk = "l4_div_ck", 3687 .clk = "l4_div_ck",
3683 .addr = omap44xx_mmc5_addrs, 3688 .addr = omap44xx_mmc5_addrs,
3684 .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
3685 .user = OCP_USER_MPU | OCP_USER_SDMA, 3689 .user = OCP_USER_MPU | OCP_USER_SDMA,
3686}; 3690};
3687 3691
@@ -3694,11 +3698,9 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
3694 .name = "mmc5", 3698 .name = "mmc5",
3695 .class = &omap44xx_mmc_hwmod_class, 3699 .class = &omap44xx_mmc_hwmod_class,
3696 .mpu_irqs = omap44xx_mmc5_irqs, 3700 .mpu_irqs = omap44xx_mmc5_irqs,
3697 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
3698 .sdma_reqs = omap44xx_mmc5_sdma_reqs, 3701 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3699 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3700 .main_clk = "mmc5_fck", 3702 .main_clk = "mmc5_fck",
3701 .prcm = { 3703 .prcm = {
3702 .omap4 = { 3704 .omap4 = {
3703 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, 3705 .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3704 }, 3706 },
@@ -3722,6 +3724,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3722 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, 3724 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3723 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, 3725 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3724 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, 3726 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3727 { .irq = -1 }
3725}; 3728};
3726 3729
3727/* mpu master ports */ 3730/* mpu master ports */
@@ -3734,9 +3737,8 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3734static struct omap_hwmod omap44xx_mpu_hwmod = { 3737static struct omap_hwmod omap44xx_mpu_hwmod = {
3735 .name = "mpu", 3738 .name = "mpu",
3736 .class = &omap44xx_mpu_hwmod_class, 3739 .class = &omap44xx_mpu_hwmod_class,
3737 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 3740 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3738 .mpu_irqs = omap44xx_mpu_irqs, 3741 .mpu_irqs = omap44xx_mpu_irqs,
3739 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
3740 .main_clk = "dpll_mpu_m2_ck", 3742 .main_clk = "dpll_mpu_m2_ck",
3741 .prcm = { 3743 .prcm = {
3742 .omap4 = { 3744 .omap4 = {
@@ -3778,6 +3780,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3778static struct omap_hwmod omap44xx_smartreflex_core_hwmod; 3780static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3779static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { 3781static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3780 { .irq = 19 + OMAP44XX_IRQ_GIC_START }, 3782 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3783 { .irq = -1 }
3781}; 3784};
3782 3785
3783static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { 3786static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
@@ -3786,6 +3789,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3786 .pa_end = 0x4a0dd03f, 3789 .pa_end = 0x4a0dd03f,
3787 .flags = ADDR_TYPE_RT 3790 .flags = ADDR_TYPE_RT
3788 }, 3791 },
3792 { }
3789}; 3793};
3790 3794
3791/* l4_cfg -> smartreflex_core */ 3795/* l4_cfg -> smartreflex_core */
@@ -3794,7 +3798,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3794 .slave = &omap44xx_smartreflex_core_hwmod, 3798 .slave = &omap44xx_smartreflex_core_hwmod,
3795 .clk = "l4_div_ck", 3799 .clk = "l4_div_ck",
3796 .addr = omap44xx_smartreflex_core_addrs, 3800 .addr = omap44xx_smartreflex_core_addrs,
3797 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3798 .user = OCP_USER_MPU | OCP_USER_SDMA, 3801 .user = OCP_USER_MPU | OCP_USER_SDMA,
3799}; 3802};
3800 3803
@@ -3807,7 +3810,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3807 .name = "smartreflex_core", 3810 .name = "smartreflex_core",
3808 .class = &omap44xx_smartreflex_hwmod_class, 3811 .class = &omap44xx_smartreflex_hwmod_class,
3809 .mpu_irqs = omap44xx_smartreflex_core_irqs, 3812 .mpu_irqs = omap44xx_smartreflex_core_irqs,
3810 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs), 3813
3811 .main_clk = "smartreflex_core_fck", 3814 .main_clk = "smartreflex_core_fck",
3812 .vdd_name = "core", 3815 .vdd_name = "core",
3813 .prcm = { 3816 .prcm = {
@@ -3824,6 +3827,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3824static struct omap_hwmod omap44xx_smartreflex_iva_hwmod; 3827static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3825static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { 3828static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3826 { .irq = 102 + OMAP44XX_IRQ_GIC_START }, 3829 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3830 { .irq = -1 }
3827}; 3831};
3828 3832
3829static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { 3833static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
@@ -3832,6 +3836,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3832 .pa_end = 0x4a0db03f, 3836 .pa_end = 0x4a0db03f,
3833 .flags = ADDR_TYPE_RT 3837 .flags = ADDR_TYPE_RT
3834 }, 3838 },
3839 { }
3835}; 3840};
3836 3841
3837/* l4_cfg -> smartreflex_iva */ 3842/* l4_cfg -> smartreflex_iva */
@@ -3840,7 +3845,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3840 .slave = &omap44xx_smartreflex_iva_hwmod, 3845 .slave = &omap44xx_smartreflex_iva_hwmod,
3841 .clk = "l4_div_ck", 3846 .clk = "l4_div_ck",
3842 .addr = omap44xx_smartreflex_iva_addrs, 3847 .addr = omap44xx_smartreflex_iva_addrs,
3843 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3844 .user = OCP_USER_MPU | OCP_USER_SDMA, 3848 .user = OCP_USER_MPU | OCP_USER_SDMA,
3845}; 3849};
3846 3850
@@ -3853,7 +3857,6 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3853 .name = "smartreflex_iva", 3857 .name = "smartreflex_iva",
3854 .class = &omap44xx_smartreflex_hwmod_class, 3858 .class = &omap44xx_smartreflex_hwmod_class,
3855 .mpu_irqs = omap44xx_smartreflex_iva_irqs, 3859 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
3856 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3857 .main_clk = "smartreflex_iva_fck", 3860 .main_clk = "smartreflex_iva_fck",
3858 .vdd_name = "iva", 3861 .vdd_name = "iva",
3859 .prcm = { 3862 .prcm = {
@@ -3870,6 +3873,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3870static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod; 3873static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3871static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { 3874static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3872 { .irq = 18 + OMAP44XX_IRQ_GIC_START }, 3875 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3876 { .irq = -1 }
3873}; 3877};
3874 3878
3875static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { 3879static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
@@ -3878,6 +3882,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3878 .pa_end = 0x4a0d903f, 3882 .pa_end = 0x4a0d903f,
3879 .flags = ADDR_TYPE_RT 3883 .flags = ADDR_TYPE_RT
3880 }, 3884 },
3885 { }
3881}; 3886};
3882 3887
3883/* l4_cfg -> smartreflex_mpu */ 3888/* l4_cfg -> smartreflex_mpu */
@@ -3886,7 +3891,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3886 .slave = &omap44xx_smartreflex_mpu_hwmod, 3891 .slave = &omap44xx_smartreflex_mpu_hwmod,
3887 .clk = "l4_div_ck", 3892 .clk = "l4_div_ck",
3888 .addr = omap44xx_smartreflex_mpu_addrs, 3893 .addr = omap44xx_smartreflex_mpu_addrs,
3889 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3890 .user = OCP_USER_MPU | OCP_USER_SDMA, 3894 .user = OCP_USER_MPU | OCP_USER_SDMA,
3891}; 3895};
3892 3896
@@ -3899,7 +3903,6 @@ static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3899 .name = "smartreflex_mpu", 3903 .name = "smartreflex_mpu",
3900 .class = &omap44xx_smartreflex_hwmod_class, 3904 .class = &omap44xx_smartreflex_hwmod_class,
3901 .mpu_irqs = omap44xx_smartreflex_mpu_irqs, 3905 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3902 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3903 .main_clk = "smartreflex_mpu_fck", 3906 .main_clk = "smartreflex_mpu_fck",
3904 .vdd_name = "mpu", 3907 .vdd_name = "mpu",
3905 .prcm = { 3908 .prcm = {
@@ -3943,6 +3946,7 @@ static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3943 .pa_end = 0x4a0f6fff, 3946 .pa_end = 0x4a0f6fff,
3944 .flags = ADDR_TYPE_RT 3947 .flags = ADDR_TYPE_RT
3945 }, 3948 },
3949 { }
3946}; 3950};
3947 3951
3948/* l4_cfg -> spinlock */ 3952/* l4_cfg -> spinlock */
@@ -3951,7 +3955,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3951 .slave = &omap44xx_spinlock_hwmod, 3955 .slave = &omap44xx_spinlock_hwmod,
3952 .clk = "l4_div_ck", 3956 .clk = "l4_div_ck",
3953 .addr = omap44xx_spinlock_addrs, 3957 .addr = omap44xx_spinlock_addrs,
3954 .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
3955 .user = OCP_USER_MPU | OCP_USER_SDMA, 3958 .user = OCP_USER_MPU | OCP_USER_SDMA,
3956}; 3959};
3957 3960
@@ -4015,6 +4018,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4015static struct omap_hwmod omap44xx_timer1_hwmod; 4018static struct omap_hwmod omap44xx_timer1_hwmod;
4016static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { 4019static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4017 { .irq = 37 + OMAP44XX_IRQ_GIC_START }, 4020 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4021 { .irq = -1 }
4018}; 4022};
4019 4023
4020static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { 4024static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
@@ -4023,6 +4027,7 @@ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4023 .pa_end = 0x4a31807f, 4027 .pa_end = 0x4a31807f,
4024 .flags = ADDR_TYPE_RT 4028 .flags = ADDR_TYPE_RT
4025 }, 4029 },
4030 { }
4026}; 4031};
4027 4032
4028/* l4_wkup -> timer1 */ 4033/* l4_wkup -> timer1 */
@@ -4031,7 +4036,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4031 .slave = &omap44xx_timer1_hwmod, 4036 .slave = &omap44xx_timer1_hwmod,
4032 .clk = "l4_wkup_clk_mux_ck", 4037 .clk = "l4_wkup_clk_mux_ck",
4033 .addr = omap44xx_timer1_addrs, 4038 .addr = omap44xx_timer1_addrs,
4034 .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
4035 .user = OCP_USER_MPU | OCP_USER_SDMA, 4039 .user = OCP_USER_MPU | OCP_USER_SDMA,
4036}; 4040};
4037 4041
@@ -4044,7 +4048,6 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
4044 .name = "timer1", 4048 .name = "timer1",
4045 .class = &omap44xx_timer_1ms_hwmod_class, 4049 .class = &omap44xx_timer_1ms_hwmod_class,
4046 .mpu_irqs = omap44xx_timer1_irqs, 4050 .mpu_irqs = omap44xx_timer1_irqs,
4047 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
4048 .main_clk = "timer1_fck", 4051 .main_clk = "timer1_fck",
4049 .prcm = { 4052 .prcm = {
4050 .omap4 = { 4053 .omap4 = {
@@ -4060,6 +4063,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
4060static struct omap_hwmod omap44xx_timer2_hwmod; 4063static struct omap_hwmod omap44xx_timer2_hwmod;
4061static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { 4064static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4062 { .irq = 38 + OMAP44XX_IRQ_GIC_START }, 4065 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4066 { .irq = -1 }
4063}; 4067};
4064 4068
4065static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { 4069static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
@@ -4068,6 +4072,7 @@ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4068 .pa_end = 0x4803207f, 4072 .pa_end = 0x4803207f,
4069 .flags = ADDR_TYPE_RT 4073 .flags = ADDR_TYPE_RT
4070 }, 4074 },
4075 { }
4071}; 4076};
4072 4077
4073/* l4_per -> timer2 */ 4078/* l4_per -> timer2 */
@@ -4076,7 +4081,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4076 .slave = &omap44xx_timer2_hwmod, 4081 .slave = &omap44xx_timer2_hwmod,
4077 .clk = "l4_div_ck", 4082 .clk = "l4_div_ck",
4078 .addr = omap44xx_timer2_addrs, 4083 .addr = omap44xx_timer2_addrs,
4079 .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
4080 .user = OCP_USER_MPU | OCP_USER_SDMA, 4084 .user = OCP_USER_MPU | OCP_USER_SDMA,
4081}; 4085};
4082 4086
@@ -4089,7 +4093,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
4089 .name = "timer2", 4093 .name = "timer2",
4090 .class = &omap44xx_timer_1ms_hwmod_class, 4094 .class = &omap44xx_timer_1ms_hwmod_class,
4091 .mpu_irqs = omap44xx_timer2_irqs, 4095 .mpu_irqs = omap44xx_timer2_irqs,
4092 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
4093 .main_clk = "timer2_fck", 4096 .main_clk = "timer2_fck",
4094 .prcm = { 4097 .prcm = {
4095 .omap4 = { 4098 .omap4 = {
@@ -4105,6 +4108,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
4105static struct omap_hwmod omap44xx_timer3_hwmod; 4108static struct omap_hwmod omap44xx_timer3_hwmod;
4106static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { 4109static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4107 { .irq = 39 + OMAP44XX_IRQ_GIC_START }, 4110 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4111 { .irq = -1 }
4108}; 4112};
4109 4113
4110static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { 4114static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
@@ -4113,6 +4117,7 @@ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4113 .pa_end = 0x4803407f, 4117 .pa_end = 0x4803407f,
4114 .flags = ADDR_TYPE_RT 4118 .flags = ADDR_TYPE_RT
4115 }, 4119 },
4120 { }
4116}; 4121};
4117 4122
4118/* l4_per -> timer3 */ 4123/* l4_per -> timer3 */
@@ -4121,7 +4126,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4121 .slave = &omap44xx_timer3_hwmod, 4126 .slave = &omap44xx_timer3_hwmod,
4122 .clk = "l4_div_ck", 4127 .clk = "l4_div_ck",
4123 .addr = omap44xx_timer3_addrs, 4128 .addr = omap44xx_timer3_addrs,
4124 .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
4125 .user = OCP_USER_MPU | OCP_USER_SDMA, 4129 .user = OCP_USER_MPU | OCP_USER_SDMA,
4126}; 4130};
4127 4131
@@ -4134,7 +4138,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
4134 .name = "timer3", 4138 .name = "timer3",
4135 .class = &omap44xx_timer_hwmod_class, 4139 .class = &omap44xx_timer_hwmod_class,
4136 .mpu_irqs = omap44xx_timer3_irqs, 4140 .mpu_irqs = omap44xx_timer3_irqs,
4137 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
4138 .main_clk = "timer3_fck", 4141 .main_clk = "timer3_fck",
4139 .prcm = { 4142 .prcm = {
4140 .omap4 = { 4143 .omap4 = {
@@ -4150,6 +4153,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
4150static struct omap_hwmod omap44xx_timer4_hwmod; 4153static struct omap_hwmod omap44xx_timer4_hwmod;
4151static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { 4154static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4152 { .irq = 40 + OMAP44XX_IRQ_GIC_START }, 4155 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4156 { .irq = -1 }
4153}; 4157};
4154 4158
4155static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { 4159static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
@@ -4158,6 +4162,7 @@ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4158 .pa_end = 0x4803607f, 4162 .pa_end = 0x4803607f,
4159 .flags = ADDR_TYPE_RT 4163 .flags = ADDR_TYPE_RT
4160 }, 4164 },
4165 { }
4161}; 4166};
4162 4167
4163/* l4_per -> timer4 */ 4168/* l4_per -> timer4 */
@@ -4166,7 +4171,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4166 .slave = &omap44xx_timer4_hwmod, 4171 .slave = &omap44xx_timer4_hwmod,
4167 .clk = "l4_div_ck", 4172 .clk = "l4_div_ck",
4168 .addr = omap44xx_timer4_addrs, 4173 .addr = omap44xx_timer4_addrs,
4169 .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
4170 .user = OCP_USER_MPU | OCP_USER_SDMA, 4174 .user = OCP_USER_MPU | OCP_USER_SDMA,
4171}; 4175};
4172 4176
@@ -4179,7 +4183,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
4179 .name = "timer4", 4183 .name = "timer4",
4180 .class = &omap44xx_timer_hwmod_class, 4184 .class = &omap44xx_timer_hwmod_class,
4181 .mpu_irqs = omap44xx_timer4_irqs, 4185 .mpu_irqs = omap44xx_timer4_irqs,
4182 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
4183 .main_clk = "timer4_fck", 4186 .main_clk = "timer4_fck",
4184 .prcm = { 4187 .prcm = {
4185 .omap4 = { 4188 .omap4 = {
@@ -4195,6 +4198,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
4195static struct omap_hwmod omap44xx_timer5_hwmod; 4198static struct omap_hwmod omap44xx_timer5_hwmod;
4196static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { 4199static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4197 { .irq = 41 + OMAP44XX_IRQ_GIC_START }, 4200 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4201 { .irq = -1 }
4198}; 4202};
4199 4203
4200static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { 4204static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
@@ -4203,6 +4207,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4203 .pa_end = 0x4013807f, 4207 .pa_end = 0x4013807f,
4204 .flags = ADDR_TYPE_RT 4208 .flags = ADDR_TYPE_RT
4205 }, 4209 },
4210 { }
4206}; 4211};
4207 4212
4208/* l4_abe -> timer5 */ 4213/* l4_abe -> timer5 */
@@ -4211,7 +4216,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4211 .slave = &omap44xx_timer5_hwmod, 4216 .slave = &omap44xx_timer5_hwmod,
4212 .clk = "ocp_abe_iclk", 4217 .clk = "ocp_abe_iclk",
4213 .addr = omap44xx_timer5_addrs, 4218 .addr = omap44xx_timer5_addrs,
4214 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
4215 .user = OCP_USER_MPU, 4219 .user = OCP_USER_MPU,
4216}; 4220};
4217 4221
@@ -4221,6 +4225,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4221 .pa_end = 0x4903807f, 4225 .pa_end = 0x4903807f,
4222 .flags = ADDR_TYPE_RT 4226 .flags = ADDR_TYPE_RT
4223 }, 4227 },
4228 { }
4224}; 4229};
4225 4230
4226/* l4_abe -> timer5 (dma) */ 4231/* l4_abe -> timer5 (dma) */
@@ -4229,7 +4234,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4229 .slave = &omap44xx_timer5_hwmod, 4234 .slave = &omap44xx_timer5_hwmod,
4230 .clk = "ocp_abe_iclk", 4235 .clk = "ocp_abe_iclk",
4231 .addr = omap44xx_timer5_dma_addrs, 4236 .addr = omap44xx_timer5_dma_addrs,
4232 .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4233 .user = OCP_USER_SDMA, 4237 .user = OCP_USER_SDMA,
4234}; 4238};
4235 4239
@@ -4243,7 +4247,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
4243 .name = "timer5", 4247 .name = "timer5",
4244 .class = &omap44xx_timer_hwmod_class, 4248 .class = &omap44xx_timer_hwmod_class,
4245 .mpu_irqs = omap44xx_timer5_irqs, 4249 .mpu_irqs = omap44xx_timer5_irqs,
4246 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
4247 .main_clk = "timer5_fck", 4250 .main_clk = "timer5_fck",
4248 .prcm = { 4251 .prcm = {
4249 .omap4 = { 4252 .omap4 = {
@@ -4259,6 +4262,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
4259static struct omap_hwmod omap44xx_timer6_hwmod; 4262static struct omap_hwmod omap44xx_timer6_hwmod;
4260static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { 4263static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4261 { .irq = 42 + OMAP44XX_IRQ_GIC_START }, 4264 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4265 { .irq = -1 }
4262}; 4266};
4263 4267
4264static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { 4268static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
@@ -4267,6 +4271,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4267 .pa_end = 0x4013a07f, 4271 .pa_end = 0x4013a07f,
4268 .flags = ADDR_TYPE_RT 4272 .flags = ADDR_TYPE_RT
4269 }, 4273 },
4274 { }
4270}; 4275};
4271 4276
4272/* l4_abe -> timer6 */ 4277/* l4_abe -> timer6 */
@@ -4275,7 +4280,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4275 .slave = &omap44xx_timer6_hwmod, 4280 .slave = &omap44xx_timer6_hwmod,
4276 .clk = "ocp_abe_iclk", 4281 .clk = "ocp_abe_iclk",
4277 .addr = omap44xx_timer6_addrs, 4282 .addr = omap44xx_timer6_addrs,
4278 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
4279 .user = OCP_USER_MPU, 4283 .user = OCP_USER_MPU,
4280}; 4284};
4281 4285
@@ -4285,6 +4289,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4285 .pa_end = 0x4903a07f, 4289 .pa_end = 0x4903a07f,
4286 .flags = ADDR_TYPE_RT 4290 .flags = ADDR_TYPE_RT
4287 }, 4291 },
4292 { }
4288}; 4293};
4289 4294
4290/* l4_abe -> timer6 (dma) */ 4295/* l4_abe -> timer6 (dma) */
@@ -4293,7 +4298,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4293 .slave = &omap44xx_timer6_hwmod, 4298 .slave = &omap44xx_timer6_hwmod,
4294 .clk = "ocp_abe_iclk", 4299 .clk = "ocp_abe_iclk",
4295 .addr = omap44xx_timer6_dma_addrs, 4300 .addr = omap44xx_timer6_dma_addrs,
4296 .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4297 .user = OCP_USER_SDMA, 4301 .user = OCP_USER_SDMA,
4298}; 4302};
4299 4303
@@ -4307,7 +4311,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
4307 .name = "timer6", 4311 .name = "timer6",
4308 .class = &omap44xx_timer_hwmod_class, 4312 .class = &omap44xx_timer_hwmod_class,
4309 .mpu_irqs = omap44xx_timer6_irqs, 4313 .mpu_irqs = omap44xx_timer6_irqs,
4310 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs), 4314
4311 .main_clk = "timer6_fck", 4315 .main_clk = "timer6_fck",
4312 .prcm = { 4316 .prcm = {
4313 .omap4 = { 4317 .omap4 = {
@@ -4323,6 +4327,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
4323static struct omap_hwmod omap44xx_timer7_hwmod; 4327static struct omap_hwmod omap44xx_timer7_hwmod;
4324static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { 4328static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4325 { .irq = 43 + OMAP44XX_IRQ_GIC_START }, 4329 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4330 { .irq = -1 }
4326}; 4331};
4327 4332
4328static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { 4333static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
@@ -4331,6 +4336,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4331 .pa_end = 0x4013c07f, 4336 .pa_end = 0x4013c07f,
4332 .flags = ADDR_TYPE_RT 4337 .flags = ADDR_TYPE_RT
4333 }, 4338 },
4339 { }
4334}; 4340};
4335 4341
4336/* l4_abe -> timer7 */ 4342/* l4_abe -> timer7 */
@@ -4339,7 +4345,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4339 .slave = &omap44xx_timer7_hwmod, 4345 .slave = &omap44xx_timer7_hwmod,
4340 .clk = "ocp_abe_iclk", 4346 .clk = "ocp_abe_iclk",
4341 .addr = omap44xx_timer7_addrs, 4347 .addr = omap44xx_timer7_addrs,
4342 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
4343 .user = OCP_USER_MPU, 4348 .user = OCP_USER_MPU,
4344}; 4349};
4345 4350
@@ -4349,6 +4354,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4349 .pa_end = 0x4903c07f, 4354 .pa_end = 0x4903c07f,
4350 .flags = ADDR_TYPE_RT 4355 .flags = ADDR_TYPE_RT
4351 }, 4356 },
4357 { }
4352}; 4358};
4353 4359
4354/* l4_abe -> timer7 (dma) */ 4360/* l4_abe -> timer7 (dma) */
@@ -4357,7 +4363,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4357 .slave = &omap44xx_timer7_hwmod, 4363 .slave = &omap44xx_timer7_hwmod,
4358 .clk = "ocp_abe_iclk", 4364 .clk = "ocp_abe_iclk",
4359 .addr = omap44xx_timer7_dma_addrs, 4365 .addr = omap44xx_timer7_dma_addrs,
4360 .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4361 .user = OCP_USER_SDMA, 4366 .user = OCP_USER_SDMA,
4362}; 4367};
4363 4368
@@ -4371,7 +4376,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
4371 .name = "timer7", 4376 .name = "timer7",
4372 .class = &omap44xx_timer_hwmod_class, 4377 .class = &omap44xx_timer_hwmod_class,
4373 .mpu_irqs = omap44xx_timer7_irqs, 4378 .mpu_irqs = omap44xx_timer7_irqs,
4374 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
4375 .main_clk = "timer7_fck", 4379 .main_clk = "timer7_fck",
4376 .prcm = { 4380 .prcm = {
4377 .omap4 = { 4381 .omap4 = {
@@ -4387,6 +4391,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
4387static struct omap_hwmod omap44xx_timer8_hwmod; 4391static struct omap_hwmod omap44xx_timer8_hwmod;
4388static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { 4392static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4389 { .irq = 44 + OMAP44XX_IRQ_GIC_START }, 4393 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4394 { .irq = -1 }
4390}; 4395};
4391 4396
4392static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { 4397static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
@@ -4395,6 +4400,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4395 .pa_end = 0x4013e07f, 4400 .pa_end = 0x4013e07f,
4396 .flags = ADDR_TYPE_RT 4401 .flags = ADDR_TYPE_RT
4397 }, 4402 },
4403 { }
4398}; 4404};
4399 4405
4400/* l4_abe -> timer8 */ 4406/* l4_abe -> timer8 */
@@ -4403,7 +4409,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4403 .slave = &omap44xx_timer8_hwmod, 4409 .slave = &omap44xx_timer8_hwmod,
4404 .clk = "ocp_abe_iclk", 4410 .clk = "ocp_abe_iclk",
4405 .addr = omap44xx_timer8_addrs, 4411 .addr = omap44xx_timer8_addrs,
4406 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
4407 .user = OCP_USER_MPU, 4412 .user = OCP_USER_MPU,
4408}; 4413};
4409 4414
@@ -4413,6 +4418,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4413 .pa_end = 0x4903e07f, 4418 .pa_end = 0x4903e07f,
4414 .flags = ADDR_TYPE_RT 4419 .flags = ADDR_TYPE_RT
4415 }, 4420 },
4421 { }
4416}; 4422};
4417 4423
4418/* l4_abe -> timer8 (dma) */ 4424/* l4_abe -> timer8 (dma) */
@@ -4421,7 +4427,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4421 .slave = &omap44xx_timer8_hwmod, 4427 .slave = &omap44xx_timer8_hwmod,
4422 .clk = "ocp_abe_iclk", 4428 .clk = "ocp_abe_iclk",
4423 .addr = omap44xx_timer8_dma_addrs, 4429 .addr = omap44xx_timer8_dma_addrs,
4424 .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4425 .user = OCP_USER_SDMA, 4430 .user = OCP_USER_SDMA,
4426}; 4431};
4427 4432
@@ -4435,7 +4440,6 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
4435 .name = "timer8", 4440 .name = "timer8",
4436 .class = &omap44xx_timer_hwmod_class, 4441 .class = &omap44xx_timer_hwmod_class,
4437 .mpu_irqs = omap44xx_timer8_irqs, 4442 .mpu_irqs = omap44xx_timer8_irqs,
4438 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
4439 .main_clk = "timer8_fck", 4443 .main_clk = "timer8_fck",
4440 .prcm = { 4444 .prcm = {
4441 .omap4 = { 4445 .omap4 = {
@@ -4451,6 +4455,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
4451static struct omap_hwmod omap44xx_timer9_hwmod; 4455static struct omap_hwmod omap44xx_timer9_hwmod;
4452static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { 4456static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4453 { .irq = 45 + OMAP44XX_IRQ_GIC_START }, 4457 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4458 { .irq = -1 }
4454}; 4459};
4455 4460
4456static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { 4461static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
@@ -4459,6 +4464,7 @@ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4459 .pa_end = 0x4803e07f, 4464 .pa_end = 0x4803e07f,
4460 .flags = ADDR_TYPE_RT 4465 .flags = ADDR_TYPE_RT
4461 }, 4466 },
4467 { }
4462}; 4468};
4463 4469
4464/* l4_per -> timer9 */ 4470/* l4_per -> timer9 */
@@ -4467,7 +4473,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4467 .slave = &omap44xx_timer9_hwmod, 4473 .slave = &omap44xx_timer9_hwmod,
4468 .clk = "l4_div_ck", 4474 .clk = "l4_div_ck",
4469 .addr = omap44xx_timer9_addrs, 4475 .addr = omap44xx_timer9_addrs,
4470 .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
4471 .user = OCP_USER_MPU | OCP_USER_SDMA, 4476 .user = OCP_USER_MPU | OCP_USER_SDMA,
4472}; 4477};
4473 4478
@@ -4480,7 +4485,6 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
4480 .name = "timer9", 4485 .name = "timer9",
4481 .class = &omap44xx_timer_hwmod_class, 4486 .class = &omap44xx_timer_hwmod_class,
4482 .mpu_irqs = omap44xx_timer9_irqs, 4487 .mpu_irqs = omap44xx_timer9_irqs,
4483 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
4484 .main_clk = "timer9_fck", 4488 .main_clk = "timer9_fck",
4485 .prcm = { 4489 .prcm = {
4486 .omap4 = { 4490 .omap4 = {
@@ -4496,6 +4500,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
4496static struct omap_hwmod omap44xx_timer10_hwmod; 4500static struct omap_hwmod omap44xx_timer10_hwmod;
4497static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { 4501static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4498 { .irq = 46 + OMAP44XX_IRQ_GIC_START }, 4502 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4503 { .irq = -1 }
4499}; 4504};
4500 4505
4501static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { 4506static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
@@ -4504,6 +4509,7 @@ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4504 .pa_end = 0x4808607f, 4509 .pa_end = 0x4808607f,
4505 .flags = ADDR_TYPE_RT 4510 .flags = ADDR_TYPE_RT
4506 }, 4511 },
4512 { }
4507}; 4513};
4508 4514
4509/* l4_per -> timer10 */ 4515/* l4_per -> timer10 */
@@ -4512,7 +4518,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4512 .slave = &omap44xx_timer10_hwmod, 4518 .slave = &omap44xx_timer10_hwmod,
4513 .clk = "l4_div_ck", 4519 .clk = "l4_div_ck",
4514 .addr = omap44xx_timer10_addrs, 4520 .addr = omap44xx_timer10_addrs,
4515 .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
4516 .user = OCP_USER_MPU | OCP_USER_SDMA, 4521 .user = OCP_USER_MPU | OCP_USER_SDMA,
4517}; 4522};
4518 4523
@@ -4525,7 +4530,6 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
4525 .name = "timer10", 4530 .name = "timer10",
4526 .class = &omap44xx_timer_1ms_hwmod_class, 4531 .class = &omap44xx_timer_1ms_hwmod_class,
4527 .mpu_irqs = omap44xx_timer10_irqs, 4532 .mpu_irqs = omap44xx_timer10_irqs,
4528 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
4529 .main_clk = "timer10_fck", 4533 .main_clk = "timer10_fck",
4530 .prcm = { 4534 .prcm = {
4531 .omap4 = { 4535 .omap4 = {
@@ -4541,6 +4545,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
4541static struct omap_hwmod omap44xx_timer11_hwmod; 4545static struct omap_hwmod omap44xx_timer11_hwmod;
4542static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { 4546static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4543 { .irq = 47 + OMAP44XX_IRQ_GIC_START }, 4547 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4548 { .irq = -1 }
4544}; 4549};
4545 4550
4546static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { 4551static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
@@ -4549,6 +4554,7 @@ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4549 .pa_end = 0x4808807f, 4554 .pa_end = 0x4808807f,
4550 .flags = ADDR_TYPE_RT 4555 .flags = ADDR_TYPE_RT
4551 }, 4556 },
4557 { }
4552}; 4558};
4553 4559
4554/* l4_per -> timer11 */ 4560/* l4_per -> timer11 */
@@ -4557,7 +4563,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4557 .slave = &omap44xx_timer11_hwmod, 4563 .slave = &omap44xx_timer11_hwmod,
4558 .clk = "l4_div_ck", 4564 .clk = "l4_div_ck",
4559 .addr = omap44xx_timer11_addrs, 4565 .addr = omap44xx_timer11_addrs,
4560 .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
4561 .user = OCP_USER_MPU | OCP_USER_SDMA, 4566 .user = OCP_USER_MPU | OCP_USER_SDMA,
4562}; 4567};
4563 4568
@@ -4570,7 +4575,6 @@ static struct omap_hwmod omap44xx_timer11_hwmod = {
4570 .name = "timer11", 4575 .name = "timer11",
4571 .class = &omap44xx_timer_hwmod_class, 4576 .class = &omap44xx_timer_hwmod_class,
4572 .mpu_irqs = omap44xx_timer11_irqs, 4577 .mpu_irqs = omap44xx_timer11_irqs,
4573 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
4574 .main_clk = "timer11_fck", 4578 .main_clk = "timer11_fck",
4575 .prcm = { 4579 .prcm = {
4576 .omap4 = { 4580 .omap4 = {
@@ -4608,11 +4612,13 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4608static struct omap_hwmod omap44xx_uart1_hwmod; 4612static struct omap_hwmod omap44xx_uart1_hwmod;
4609static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { 4613static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4610 { .irq = 72 + OMAP44XX_IRQ_GIC_START }, 4614 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4615 { .irq = -1 }
4611}; 4616};
4612 4617
4613static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { 4618static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4614 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, 4619 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4615 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, 4620 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4621 { .dma_req = -1 }
4616}; 4622};
4617 4623
4618static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { 4624static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
@@ -4621,6 +4627,7 @@ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4621 .pa_end = 0x4806a0ff, 4627 .pa_end = 0x4806a0ff,
4622 .flags = ADDR_TYPE_RT 4628 .flags = ADDR_TYPE_RT
4623 }, 4629 },
4630 { }
4624}; 4631};
4625 4632
4626/* l4_per -> uart1 */ 4633/* l4_per -> uart1 */
@@ -4629,7 +4636,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4629 .slave = &omap44xx_uart1_hwmod, 4636 .slave = &omap44xx_uart1_hwmod,
4630 .clk = "l4_div_ck", 4637 .clk = "l4_div_ck",
4631 .addr = omap44xx_uart1_addrs, 4638 .addr = omap44xx_uart1_addrs,
4632 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
4633 .user = OCP_USER_MPU | OCP_USER_SDMA, 4639 .user = OCP_USER_MPU | OCP_USER_SDMA,
4634}; 4640};
4635 4641
@@ -4642,9 +4648,7 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
4642 .name = "uart1", 4648 .name = "uart1",
4643 .class = &omap44xx_uart_hwmod_class, 4649 .class = &omap44xx_uart_hwmod_class,
4644 .mpu_irqs = omap44xx_uart1_irqs, 4650 .mpu_irqs = omap44xx_uart1_irqs,
4645 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
4646 .sdma_reqs = omap44xx_uart1_sdma_reqs, 4651 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4647 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4648 .main_clk = "uart1_fck", 4652 .main_clk = "uart1_fck",
4649 .prcm = { 4653 .prcm = {
4650 .omap4 = { 4654 .omap4 = {
@@ -4660,11 +4664,13 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
4660static struct omap_hwmod omap44xx_uart2_hwmod; 4664static struct omap_hwmod omap44xx_uart2_hwmod;
4661static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { 4665static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4662 { .irq = 73 + OMAP44XX_IRQ_GIC_START }, 4666 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4667 { .irq = -1 }
4663}; 4668};
4664 4669
4665static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { 4670static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4666 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, 4671 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4667 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, 4672 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4673 { .dma_req = -1 }
4668}; 4674};
4669 4675
4670static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { 4676static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
@@ -4673,6 +4679,7 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4673 .pa_end = 0x4806c0ff, 4679 .pa_end = 0x4806c0ff,
4674 .flags = ADDR_TYPE_RT 4680 .flags = ADDR_TYPE_RT
4675 }, 4681 },
4682 { }
4676}; 4683};
4677 4684
4678/* l4_per -> uart2 */ 4685/* l4_per -> uart2 */
@@ -4681,7 +4688,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4681 .slave = &omap44xx_uart2_hwmod, 4688 .slave = &omap44xx_uart2_hwmod,
4682 .clk = "l4_div_ck", 4689 .clk = "l4_div_ck",
4683 .addr = omap44xx_uart2_addrs, 4690 .addr = omap44xx_uart2_addrs,
4684 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
4685 .user = OCP_USER_MPU | OCP_USER_SDMA, 4691 .user = OCP_USER_MPU | OCP_USER_SDMA,
4686}; 4692};
4687 4693
@@ -4694,9 +4700,7 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
4694 .name = "uart2", 4700 .name = "uart2",
4695 .class = &omap44xx_uart_hwmod_class, 4701 .class = &omap44xx_uart_hwmod_class,
4696 .mpu_irqs = omap44xx_uart2_irqs, 4702 .mpu_irqs = omap44xx_uart2_irqs,
4697 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
4698 .sdma_reqs = omap44xx_uart2_sdma_reqs, 4703 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4699 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4700 .main_clk = "uart2_fck", 4704 .main_clk = "uart2_fck",
4701 .prcm = { 4705 .prcm = {
4702 .omap4 = { 4706 .omap4 = {
@@ -4712,11 +4716,13 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
4712static struct omap_hwmod omap44xx_uart3_hwmod; 4716static struct omap_hwmod omap44xx_uart3_hwmod;
4713static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { 4717static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4714 { .irq = 74 + OMAP44XX_IRQ_GIC_START }, 4718 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4719 { .irq = -1 }
4715}; 4720};
4716 4721
4717static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { 4722static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4718 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, 4723 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4719 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, 4724 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4725 { .dma_req = -1 }
4720}; 4726};
4721 4727
4722static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { 4728static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
@@ -4725,6 +4731,7 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4725 .pa_end = 0x480200ff, 4731 .pa_end = 0x480200ff,
4726 .flags = ADDR_TYPE_RT 4732 .flags = ADDR_TYPE_RT
4727 }, 4733 },
4734 { }
4728}; 4735};
4729 4736
4730/* l4_per -> uart3 */ 4737/* l4_per -> uart3 */
@@ -4733,7 +4740,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4733 .slave = &omap44xx_uart3_hwmod, 4740 .slave = &omap44xx_uart3_hwmod,
4734 .clk = "l4_div_ck", 4741 .clk = "l4_div_ck",
4735 .addr = omap44xx_uart3_addrs, 4742 .addr = omap44xx_uart3_addrs,
4736 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
4737 .user = OCP_USER_MPU | OCP_USER_SDMA, 4743 .user = OCP_USER_MPU | OCP_USER_SDMA,
4738}; 4744};
4739 4745
@@ -4745,11 +4751,9 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4745static struct omap_hwmod omap44xx_uart3_hwmod = { 4751static struct omap_hwmod omap44xx_uart3_hwmod = {
4746 .name = "uart3", 4752 .name = "uart3",
4747 .class = &omap44xx_uart_hwmod_class, 4753 .class = &omap44xx_uart_hwmod_class,
4748 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET), 4754 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4749 .mpu_irqs = omap44xx_uart3_irqs, 4755 .mpu_irqs = omap44xx_uart3_irqs,
4750 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
4751 .sdma_reqs = omap44xx_uart3_sdma_reqs, 4756 .sdma_reqs = omap44xx_uart3_sdma_reqs,
4752 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4753 .main_clk = "uart3_fck", 4757 .main_clk = "uart3_fck",
4754 .prcm = { 4758 .prcm = {
4755 .omap4 = { 4759 .omap4 = {
@@ -4765,11 +4769,13 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
4765static struct omap_hwmod omap44xx_uart4_hwmod; 4769static struct omap_hwmod omap44xx_uart4_hwmod;
4766static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { 4770static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4767 { .irq = 70 + OMAP44XX_IRQ_GIC_START }, 4771 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4772 { .irq = -1 }
4768}; 4773};
4769 4774
4770static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { 4775static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4771 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, 4776 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4772 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, 4777 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4778 { .dma_req = -1 }
4773}; 4779};
4774 4780
4775static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { 4781static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
@@ -4778,6 +4784,7 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4778 .pa_end = 0x4806e0ff, 4784 .pa_end = 0x4806e0ff,
4779 .flags = ADDR_TYPE_RT 4785 .flags = ADDR_TYPE_RT
4780 }, 4786 },
4787 { }
4781}; 4788};
4782 4789
4783/* l4_per -> uart4 */ 4790/* l4_per -> uart4 */
@@ -4786,7 +4793,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4786 .slave = &omap44xx_uart4_hwmod, 4793 .slave = &omap44xx_uart4_hwmod,
4787 .clk = "l4_div_ck", 4794 .clk = "l4_div_ck",
4788 .addr = omap44xx_uart4_addrs, 4795 .addr = omap44xx_uart4_addrs,
4789 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
4790 .user = OCP_USER_MPU | OCP_USER_SDMA, 4796 .user = OCP_USER_MPU | OCP_USER_SDMA,
4791}; 4797};
4792 4798
@@ -4799,9 +4805,7 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
4799 .name = "uart4", 4805 .name = "uart4",
4800 .class = &omap44xx_uart_hwmod_class, 4806 .class = &omap44xx_uart_hwmod_class,
4801 .mpu_irqs = omap44xx_uart4_irqs, 4807 .mpu_irqs = omap44xx_uart4_irqs,
4802 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
4803 .sdma_reqs = omap44xx_uart4_sdma_reqs, 4808 .sdma_reqs = omap44xx_uart4_sdma_reqs,
4804 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4805 .main_clk = "uart4_fck", 4809 .main_clk = "uart4_fck",
4806 .prcm = { 4810 .prcm = {
4807 .omap4 = { 4811 .omap4 = {
@@ -4832,14 +4836,15 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4832}; 4836};
4833 4837
4834static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { 4838static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4835 .name = "usb_otg_hs", 4839 .name = "usb_otg_hs",
4836 .sysc = &omap44xx_usb_otg_hs_sysc, 4840 .sysc = &omap44xx_usb_otg_hs_sysc,
4837}; 4841};
4838 4842
4839/* usb_otg_hs */ 4843/* usb_otg_hs */
4840static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { 4844static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4841 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, 4845 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4842 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, 4846 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4847 { .irq = -1 }
4843}; 4848};
4844 4849
4845/* usb_otg_hs master ports */ 4850/* usb_otg_hs master ports */
@@ -4853,6 +4858,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4853 .pa_end = 0x4a0ab003, 4858 .pa_end = 0x4a0ab003,
4854 .flags = ADDR_TYPE_RT 4859 .flags = ADDR_TYPE_RT
4855 }, 4860 },
4861 { }
4856}; 4862};
4857 4863
4858/* l4_cfg -> usb_otg_hs */ 4864/* l4_cfg -> usb_otg_hs */
@@ -4861,7 +4867,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4861 .slave = &omap44xx_usb_otg_hs_hwmod, 4867 .slave = &omap44xx_usb_otg_hs_hwmod,
4862 .clk = "l4_div_ck", 4868 .clk = "l4_div_ck",
4863 .addr = omap44xx_usb_otg_hs_addrs, 4869 .addr = omap44xx_usb_otg_hs_addrs,
4864 .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4865 .user = OCP_USER_MPU | OCP_USER_SDMA, 4870 .user = OCP_USER_MPU | OCP_USER_SDMA,
4866}; 4871};
4867 4872
@@ -4879,7 +4884,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4879 .class = &omap44xx_usb_otg_hs_hwmod_class, 4884 .class = &omap44xx_usb_otg_hs_hwmod_class,
4880 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, 4885 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4881 .mpu_irqs = omap44xx_usb_otg_hs_irqs, 4886 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
4882 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4883 .main_clk = "usb_otg_hs_ick", 4887 .main_clk = "usb_otg_hs_ick",
4884 .prcm = { 4888 .prcm = {
4885 .omap4 = { 4889 .omap4 = {
@@ -4887,7 +4891,7 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4887 }, 4891 },
4888 }, 4892 },
4889 .opt_clks = usb_otg_hs_opt_clks, 4893 .opt_clks = usb_otg_hs_opt_clks,
4890 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), 4894 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4891 .slaves = omap44xx_usb_otg_hs_slaves, 4895 .slaves = omap44xx_usb_otg_hs_slaves,
4892 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves), 4896 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4893 .masters = omap44xx_usb_otg_hs_masters, 4897 .masters = omap44xx_usb_otg_hs_masters,
@@ -4922,6 +4926,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4922static struct omap_hwmod omap44xx_wd_timer2_hwmod; 4926static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4923static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { 4927static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4924 { .irq = 80 + OMAP44XX_IRQ_GIC_START }, 4928 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4929 { .irq = -1 }
4925}; 4930};
4926 4931
4927static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { 4932static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
@@ -4930,6 +4935,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4930 .pa_end = 0x4a31407f, 4935 .pa_end = 0x4a31407f,
4931 .flags = ADDR_TYPE_RT 4936 .flags = ADDR_TYPE_RT
4932 }, 4937 },
4938 { }
4933}; 4939};
4934 4940
4935/* l4_wkup -> wd_timer2 */ 4941/* l4_wkup -> wd_timer2 */
@@ -4938,7 +4944,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4938 .slave = &omap44xx_wd_timer2_hwmod, 4944 .slave = &omap44xx_wd_timer2_hwmod,
4939 .clk = "l4_wkup_clk_mux_ck", 4945 .clk = "l4_wkup_clk_mux_ck",
4940 .addr = omap44xx_wd_timer2_addrs, 4946 .addr = omap44xx_wd_timer2_addrs,
4941 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4942 .user = OCP_USER_MPU | OCP_USER_SDMA, 4947 .user = OCP_USER_MPU | OCP_USER_SDMA,
4943}; 4948};
4944 4949
@@ -4951,7 +4956,6 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4951 .name = "wd_timer2", 4956 .name = "wd_timer2",
4952 .class = &omap44xx_wd_timer_hwmod_class, 4957 .class = &omap44xx_wd_timer_hwmod_class,
4953 .mpu_irqs = omap44xx_wd_timer2_irqs, 4958 .mpu_irqs = omap44xx_wd_timer2_irqs,
4954 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4955 .main_clk = "wd_timer2_fck", 4959 .main_clk = "wd_timer2_fck",
4956 .prcm = { 4960 .prcm = {
4957 .omap4 = { 4961 .omap4 = {
@@ -4967,6 +4971,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4967static struct omap_hwmod omap44xx_wd_timer3_hwmod; 4971static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4968static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { 4972static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4969 { .irq = 36 + OMAP44XX_IRQ_GIC_START }, 4973 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4974 { .irq = -1 }
4970}; 4975};
4971 4976
4972static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { 4977static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
@@ -4975,6 +4980,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4975 .pa_end = 0x4013007f, 4980 .pa_end = 0x4013007f,
4976 .flags = ADDR_TYPE_RT 4981 .flags = ADDR_TYPE_RT
4977 }, 4982 },
4983 { }
4978}; 4984};
4979 4985
4980/* l4_abe -> wd_timer3 */ 4986/* l4_abe -> wd_timer3 */
@@ -4983,7 +4989,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4983 .slave = &omap44xx_wd_timer3_hwmod, 4989 .slave = &omap44xx_wd_timer3_hwmod,
4984 .clk = "ocp_abe_iclk", 4990 .clk = "ocp_abe_iclk",
4985 .addr = omap44xx_wd_timer3_addrs, 4991 .addr = omap44xx_wd_timer3_addrs,
4986 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4987 .user = OCP_USER_MPU, 4992 .user = OCP_USER_MPU,
4988}; 4993};
4989 4994
@@ -4993,6 +4998,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4993 .pa_end = 0x4903007f, 4998 .pa_end = 0x4903007f,
4994 .flags = ADDR_TYPE_RT 4999 .flags = ADDR_TYPE_RT
4995 }, 5000 },
5001 { }
4996}; 5002};
4997 5003
4998/* l4_abe -> wd_timer3 (dma) */ 5004/* l4_abe -> wd_timer3 (dma) */
@@ -5001,7 +5007,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5001 .slave = &omap44xx_wd_timer3_hwmod, 5007 .slave = &omap44xx_wd_timer3_hwmod,
5002 .clk = "ocp_abe_iclk", 5008 .clk = "ocp_abe_iclk",
5003 .addr = omap44xx_wd_timer3_dma_addrs, 5009 .addr = omap44xx_wd_timer3_dma_addrs,
5004 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
5005 .user = OCP_USER_SDMA, 5010 .user = OCP_USER_SDMA,
5006}; 5011};
5007 5012
@@ -5015,7 +5020,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5015 .name = "wd_timer3", 5020 .name = "wd_timer3",
5016 .class = &omap44xx_wd_timer_hwmod_class, 5021 .class = &omap44xx_wd_timer_hwmod_class,
5017 .mpu_irqs = omap44xx_wd_timer3_irqs, 5022 .mpu_irqs = omap44xx_wd_timer3_irqs,
5018 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
5019 .main_clk = "wd_timer3_fck", 5023 .main_clk = "wd_timer3_fck",
5020 .prcm = { 5024 .prcm = {
5021 .omap4 = { 5025 .omap4 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 08a134243ecb..de832ebc93a9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT, 49 .srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
50}; 50};
51 51
52
53/*
54 * omap_hwmod class data
55 */
56
57struct omap_hwmod_class l3_hwmod_class = {
58 .name = "l3"
59};
60
61struct omap_hwmod_class l4_hwmod_class = {
62 .name = "l4"
63};
64
65struct omap_hwmod_class mpu_hwmod_class = {
66 .name = "mpu"
67};
68
69struct omap_hwmod_class iva_hwmod_class = {
70 .name = "iva"
71};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index c34e98bf1242..39a7c37f4587 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -1,10 +1,10 @@
1/* 1/*
2 * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations 2 * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
3 * 3 *
4 * Copyright (C) 2010 Nokia Corporation 4 * Copyright (C) 2010-2011 Nokia Corporation
5 * Paul Walmsley 5 * Paul Walmsley
6 * 6 *
7 * Copyright (C) 2010 Texas Instruments, Inc. 7 * Copyright (C) 2010-2011 Texas Instruments, Inc.
8 * Benoît Cousson 8 * Benoît Cousson
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
@@ -16,10 +16,99 @@
16 16
17#include <plat/omap_hwmod.h> 17#include <plat/omap_hwmod.h>
18 18
19/* Common address space across OMAP2xxx */
20extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
21extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
22extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
23extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
24extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
25extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
26extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
27extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
28extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
29extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
30extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
31extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
32extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
33
34/* Common address space across OMAP2xxx/3xxx */
35extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
36extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
37extern struct omap_hwmod_addr_space omap2_dss_addrs[];
38extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
39extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
40extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
41extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
42extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
43extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
44extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
45extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
46extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
47extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
48extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
49extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
50extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
51
52/* Common IP block data across OMAP2xxx */
53extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
54extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
55
56/* Common IP block data */
57extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
58extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
59extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
60extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
61extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
62extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
63extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
64extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
65extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
66
67/* Common IP block data on OMAP2430/OMAP3 */
68extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
69
70/* Common IP block data across OMAP2/3 */
71extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
72extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
73extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
74extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
75extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
76extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
77extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
78extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
79extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
80extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
81extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
82extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
83extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
84extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
85extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
86extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
87extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
88extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
89extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
90extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
91extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
92extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
93extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
94extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
95
19/* OMAP hwmod classes - forward declarations */ 96/* OMAP hwmod classes - forward declarations */
20extern struct omap_hwmod_class l3_hwmod_class; 97extern struct omap_hwmod_class l3_hwmod_class;
21extern struct omap_hwmod_class l4_hwmod_class; 98extern struct omap_hwmod_class l4_hwmod_class;
22extern struct omap_hwmod_class mpu_hwmod_class; 99extern struct omap_hwmod_class mpu_hwmod_class;
23extern struct omap_hwmod_class iva_hwmod_class; 100extern struct omap_hwmod_class iva_hwmod_class;
101extern struct omap_hwmod_class omap2_uart_class;
102extern struct omap_hwmod_class omap2_dss_hwmod_class;
103extern struct omap_hwmod_class omap2_dispc_hwmod_class;
104extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
105extern struct omap_hwmod_class omap2_venc_hwmod_class;
106
107extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
108extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
109extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
110extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
111extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
112extern struct omap_hwmod_class omap2xxx_mcspi_class;
24 113
25#endif 114#endif
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index c4222c7036a5..3a7e678fd5f1 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -53,7 +53,7 @@ static struct powerdomain core_44xx_pwrdm = {
53 [3] = PWRSTS_ON, /* ducati_l2ram */ 53 [3] = PWRSTS_ON, /* ducati_l2ram */
54 [4] = PWRSTS_ON, /* ducati_unicache */ 54 [4] = PWRSTS_ON, /* ducati_unicache */
55 }, 55 },
56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
57}; 57};
58 58
59/* gfx_44xx_pwrdm: 3D accelerator power domain */ 59/* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
70 .pwrsts_mem_on = { 70 .pwrsts_mem_on = {
71 [0] = PWRSTS_ON, /* gfx_mem */ 71 [0] = PWRSTS_ON, /* gfx_mem */
72 }, 72 },
73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
74}; 74};
75 75
76/* abe_44xx_pwrdm: Audio back end power domain */ 76/* abe_44xx_pwrdm: Audio back end power domain */
@@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
90 [0] = PWRSTS_ON, /* aessmem */ 90 [0] = PWRSTS_ON, /* aessmem */
91 [1] = PWRSTS_ON, /* periphmem */ 91 [1] = PWRSTS_ON, /* periphmem */
92 }, 92 },
93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
94}; 94};
95 95
96/* dss_44xx_pwrdm: Display subsystem power domain */ 96/* dss_44xx_pwrdm: Display subsystem power domain */
@@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
108 .pwrsts_mem_on = { 108 .pwrsts_mem_on = {
109 [0] = PWRSTS_ON, /* dss_mem */ 109 [0] = PWRSTS_ON, /* dss_mem */
110 }, 110 },
111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
112}; 112};
113 113
114/* tesla_44xx_pwrdm: Tesla processor power domain */ 114/* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
130 [1] = PWRSTS_ON, /* tesla_l1 */ 130 [1] = PWRSTS_ON, /* tesla_l1 */
131 [2] = PWRSTS_ON, /* tesla_l2 */ 131 [2] = PWRSTS_ON, /* tesla_l2 */
132 }, 132 },
133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
134}; 134};
135 135
136/* wkup_44xx_pwrdm: Wake-up power domain */ 136/* wkup_44xx_pwrdm: Wake-up power domain */
@@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
241 [2] = PWRSTS_ON, /* tcm1_mem */ 241 [2] = PWRSTS_ON, /* tcm1_mem */
242 [3] = PWRSTS_ON, /* tcm2_mem */ 242 [3] = PWRSTS_ON, /* tcm2_mem */
243 }, 243 },
244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
245}; 245};
246 246
247/* cam_44xx_pwrdm: Camera subsystem power domain */ 247/* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
258 .pwrsts_mem_on = { 258 .pwrsts_mem_on = {
259 [0] = PWRSTS_ON, /* cam_mem */ 259 [0] = PWRSTS_ON, /* cam_mem */
260 }, 260 },
261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
262}; 262};
263 263
264/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */ 264/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
@@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
276 .pwrsts_mem_on = { 276 .pwrsts_mem_on = {
277 [0] = PWRSTS_ON, /* l3init_bank1 */ 277 [0] = PWRSTS_ON, /* l3init_bank1 */
278 }, 278 },
279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
280}; 280};
281 281
282/* l4per_44xx_pwrdm: Target peripherals power domain */ 282/* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
296 [0] = PWRSTS_ON, /* nonretained_bank */ 296 [0] = PWRSTS_ON, /* nonretained_bank */
297 [1] = PWRSTS_ON, /* retained_bank */ 297 [1] = PWRSTS_ON, /* retained_bank */
298 }, 298 },
299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, 299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
300}; 300};
301 301
302/* 302/*
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index d22d1b43bccd..8a6e250f04b5 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -31,7 +31,6 @@
31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) 31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
32 32
33/* PRCM_MPU instances */ 33/* PRCM_MPU instances */
34
35#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 34#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
36#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 35#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
37#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 36#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
@@ -52,46 +51,46 @@
52 */ 51 */
53 52
54/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ 53/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
55#define OMAP4_REVISION_PRCM_OFFSET 0x0000 54#define OMAP4_REVISION_PRCM_OFFSET 0x0000
56#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) 55#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
57 56
58/* PRCM_MPU.DEVICE_PRM register offsets */ 57/* PRCM_MPU.DEVICE_PRM register offsets */
59#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 58#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
60#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) 59#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
61#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 60#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
62#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) 61#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
63 62
64/* PRCM_MPU.CPU0 register offsets */ 63/* PRCM_MPU.CPU0 register offsets */
65#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 64#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
66#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) 65#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
67#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 66#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
68#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) 67#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
69#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 68#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
70#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) 69#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
71#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c 70#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
72#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) 71#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
73#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 72#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
74#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) 73#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
75#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 74#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
76#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) 75#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
77#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 76#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
78#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) 77#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
79 78
80/* PRCM_MPU.CPU1 register offsets */ 79/* PRCM_MPU.CPU1 register offsets */
81#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 80#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
82#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) 81#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
83#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 82#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
84#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) 83#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
85#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 84#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
86#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) 85#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
87#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c 86#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
88#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) 87#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
89#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 88#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
90#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) 89#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
91#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 90#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
92#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) 91#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
93#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 92#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
94#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) 93#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
95 94
96/* Function prototypes */ 95/* Function prototypes */
97# ifndef __ASSEMBLER__ 96# ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 67a0d3feb3f6..6e53120fd6cb 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -31,7 +31,7 @@
31#define OMAP4430_PRM_BASE 0x4a306000 31#define OMAP4430_PRM_BASE 0x4a306000
32 32
33#define OMAP44XX_PRM_REGADDR(inst, reg) \ 33#define OMAP44XX_PRM_REGADDR(inst, reg) \
34 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) 34 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
35 35
36 36
37/* PRM instances */ 37/* PRM instances */
@@ -46,30 +46,18 @@
46#define OMAP4430_PRM_CAM_INST 0x1000 46#define OMAP4430_PRM_CAM_INST 0x1000
47#define OMAP4430_PRM_DSS_INST 0x1100 47#define OMAP4430_PRM_DSS_INST 0x1100
48#define OMAP4430_PRM_GFX_INST 0x1200 48#define OMAP4430_PRM_GFX_INST 0x1200
49#define OMAP4430_PRM_L3INIT_INST 0x1300 49#define OMAP4430_PRM_L3INIT_INST 0x1300
50#define OMAP4430_PRM_L4PER_INST 0x1400 50#define OMAP4430_PRM_L4PER_INST 0x1400
51#define OMAP4430_PRM_CEFUSE_INST 0x1600 51#define OMAP4430_PRM_CEFUSE_INST 0x1600
52#define OMAP4430_PRM_WKUP_INST 0x1700 52#define OMAP4430_PRM_WKUP_INST 0x1700
53#define OMAP4430_PRM_WKUP_CM_INST 0x1800 53#define OMAP4430_PRM_WKUP_CM_INST 0x1800
54#define OMAP4430_PRM_EMU_INST 0x1900 54#define OMAP4430_PRM_EMU_INST 0x1900
55#define OMAP4430_PRM_EMU_CM_INST 0x1a00 55#define OMAP4430_PRM_EMU_CM_INST 0x1a00
56#define OMAP4430_PRM_DEVICE_INST 0x1b00 56#define OMAP4430_PRM_DEVICE_INST 0x1b00
57#define OMAP4430_PRM_INSTR_INST 0x1f00 57#define OMAP4430_PRM_INSTR_INST 0x1f00
58 58
59/* PRM clockdomain register offsets (from instance start) */ 59/* PRM clockdomain register offsets (from instance start) */
60#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
61#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
62#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
63#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
64#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
65#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
66#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
67#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
68#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
69#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
70#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
71#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 60#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
72#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
73#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 61#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
74 62
75/* OMAP4 specific register offsets */ 63/* OMAP4 specific register offsets */
@@ -247,8 +235,8 @@
247#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) 235#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
248#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 236#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
249#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) 237#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
250#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c 238#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
251#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) 239#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
252#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 240#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
253#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) 241#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
254#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 242#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
@@ -713,8 +701,8 @@
713#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) 701#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
714#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 702#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
715#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) 703#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
716#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8 704#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
717#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) 705#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
718#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac 706#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
719#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) 707#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
720#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 708#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
@@ -751,8 +739,8 @@
751#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) 739#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
752#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 740#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
753#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) 741#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
754#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4 742#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
755#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) 743#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
756#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 744#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
757#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) 745#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
758 746
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 49a4c75243fc..6e6735f04ee3 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -211,9 +211,6 @@ choice
211 depends on ARCH_OMAP 211 depends on ARCH_OMAP
212 default OMAP_PM_NOOP 212 default OMAP_PM_NOOP
213 213
214config OMAP_PM_NONE
215 bool "No PM layer"
216
217config OMAP_PM_NOOP 214config OMAP_PM_NOOP
218 bool "No-op/debug PM layer" 215 bool "No-op/debug PM layer"
219 216
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 006e599c6613..f57e0649ab30 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -152,7 +152,7 @@ struct dpll_data {
152 u16 max_multiplier; 152 u16 max_multiplier;
153 u8 last_rounded_n; 153 u8 last_rounded_n;
154 u8 min_divider; 154 u8 min_divider;
155 u8 max_divider; 155 u16 max_divider;
156 u8 modes; 156 u8 modes;
157#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 157#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
158 void __iomem *autoidle_reg; 158 void __iomem *autoidle_reg;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index d0f3a2d22fd3..eb5d16c60cd9 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -34,6 +34,7 @@
34 34
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/delay.h> 36#include <linux/delay.h>
37#include <linux/io.h>
37 38
38#ifndef __ASM_ARCH_DMTIMER_H 39#ifndef __ASM_ARCH_DMTIMER_H
39#define __ASM_ARCH_DMTIMER_H 40#define __ASM_ARCH_DMTIMER_H
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index c0a752053039..0840df813f4f 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -40,11 +40,7 @@
40 * framework starts. The "_if_" is to avoid name collisions with the 40 * framework starts. The "_if_" is to avoid name collisions with the
41 * PM idle-loop code. 41 * PM idle-loop code.
42 */ 42 */
43#ifdef CONFIG_OMAP_PM_NONE
44#define omap_pm_if_early_init() 0
45#else
46int __init omap_pm_if_early_init(void); 43int __init omap_pm_if_early_init(void);
47#endif
48 44
49/** 45/**
50 * omap_pm_if_init - OMAP PM init code called after clock fw init 46 * omap_pm_if_init - OMAP PM init code called after clock fw init
@@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void);
52 * The main initialization code. OPP tables are passed in here. The 48 * The main initialization code. OPP tables are passed in here. The
53 * "_if_" is to avoid name collisions with the PM idle-loop code. 49 * "_if_" is to avoid name collisions with the PM idle-loop code.
54 */ 50 */
55#ifdef CONFIG_OMAP_PM_NONE
56#define omap_pm_if_init() 0
57#else
58int __init omap_pm_if_init(void); 51int __init omap_pm_if_init(void);
59#endif
60 52
61/** 53/**
62 * omap_pm_if_exit - OMAP PM exit code 54 * omap_pm_if_exit - OMAP PM exit code
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1adea9c62984..ce06ac6a9709 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -77,7 +77,6 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
77#define HWMOD_IDLEMODE_FORCE (1 << 0) 77#define HWMOD_IDLEMODE_FORCE (1 << 0)
78#define HWMOD_IDLEMODE_NO (1 << 1) 78#define HWMOD_IDLEMODE_NO (1 << 1)
79#define HWMOD_IDLEMODE_SMART (1 << 2) 79#define HWMOD_IDLEMODE_SMART (1 << 2)
80/* Slave idle mode flag only */
81#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3) 80#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
82 81
83/** 82/**
@@ -98,7 +97,7 @@ struct omap_hwmod_mux_info {
98/** 97/**
99 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod 98 * struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
100 * @name: name of the IRQ channel (module local name) 99 * @name: name of the IRQ channel (module local name)
101 * @irq_ch: IRQ channel ID 100 * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
102 * 101 *
103 * @name should be something short, e.g., "tx" or "rx". It is for use 102 * @name should be something short, e.g., "tx" or "rx". It is for use
104 * by platform_get_resource_byname(). It is defined locally to the 103 * by platform_get_resource_byname(). It is defined locally to the
@@ -106,13 +105,13 @@ struct omap_hwmod_mux_info {
106 */ 105 */
107struct omap_hwmod_irq_info { 106struct omap_hwmod_irq_info {
108 const char *name; 107 const char *name;
109 u16 irq; 108 s16 irq;
110}; 109};
111 110
112/** 111/**
113 * struct omap_hwmod_dma_info - DMA channels used by the hwmod 112 * struct omap_hwmod_dma_info - DMA channels used by the hwmod
114 * @name: name of the DMA channel (module local name) 113 * @name: name of the DMA channel (module local name)
115 * @dma_req: DMA request ID 114 * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
116 * 115 *
117 * @name should be something short, e.g., "tx" or "rx". It is for use 116 * @name should be something short, e.g., "tx" or "rx". It is for use
118 * by platform_get_resource_byname(). It is defined locally to the 117 * by platform_get_resource_byname(). It is defined locally to the
@@ -120,7 +119,7 @@ struct omap_hwmod_irq_info {
120 */ 119 */
121struct omap_hwmod_dma_info { 120struct omap_hwmod_dma_info {
122 const char *name; 121 const char *name;
123 u16 dma_req; 122 s16 dma_req;
124}; 123};
125 124
126/** 125/**
@@ -220,7 +219,6 @@ struct omap_hwmod_addr_space {
220 * @clk: interface clock: OMAP clock name 219 * @clk: interface clock: OMAP clock name
221 * @_clk: pointer to the interface struct clk (filled in at runtime) 220 * @_clk: pointer to the interface struct clk (filled in at runtime)
222 * @fw: interface firewall data 221 * @fw: interface firewall data
223 * @addr_cnt: ARRAY_SIZE(@addr)
224 * @width: OCP data width 222 * @width: OCP data width
225 * @user: initiators using this interface (see OCP_USER_* macros above) 223 * @user: initiators using this interface (see OCP_USER_* macros above)
226 * @flags: OCP interface flags (see OCPIF_* macros above) 224 * @flags: OCP interface flags (see OCPIF_* macros above)
@@ -239,7 +237,6 @@ struct omap_hwmod_ocp_if {
239 union { 237 union {
240 struct omap_hwmod_omap2_firewall omap2; 238 struct omap_hwmod_omap2_firewall omap2;
241 } fw; 239 } fw;
242 u8 addr_cnt;
243 u8 width; 240 u8 width;
244 u8 user; 241 u8 user;
245 u8 flags; 242 u8 flags;
@@ -258,6 +255,7 @@ struct omap_hwmod_ocp_if {
258#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT) 255#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
259#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT) 256#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
260#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT) 257#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
258#define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
261 259
262/* omap_hwmod_sysconfig.sysc_flags capability flags */ 260/* omap_hwmod_sysconfig.sysc_flags capability flags */
263#define SYSC_HAS_AUTOIDLE (1 << 0) 261#define SYSC_HAS_AUTOIDLE (1 << 0)
@@ -468,8 +466,8 @@ struct omap_hwmod_class {
468 * @name: name of the hwmod 466 * @name: name of the hwmod
469 * @class: struct omap_hwmod_class * to the class of this hwmod 467 * @class: struct omap_hwmod_class * to the class of this hwmod
470 * @od: struct omap_device currently associated with this hwmod (internal use) 468 * @od: struct omap_device currently associated with this hwmod (internal use)
471 * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt) 469 * @mpu_irqs: ptr to an array of MPU IRQs
472 * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt) 470 * @sdma_reqs: ptr to an array of System DMA request IDs
473 * @prcm: PRCM data pertaining to this hwmod 471 * @prcm: PRCM data pertaining to this hwmod
474 * @main_clk: main clock: OMAP clock name 472 * @main_clk: main clock: OMAP clock name
475 * @_clk: pointer to the main struct clk (filled in at runtime) 473 * @_clk: pointer to the main struct clk (filled in at runtime)
@@ -482,8 +480,6 @@ struct omap_hwmod_class {
482 * @_sysc_cache: internal-use hwmod flags 480 * @_sysc_cache: internal-use hwmod flags
483 * @_mpu_rt_va: cached register target start address (internal use) 481 * @_mpu_rt_va: cached register target start address (internal use)
484 * @_mpu_port_index: cached MPU register target slave ID (internal use) 482 * @_mpu_port_index: cached MPU register target slave ID (internal use)
485 * @mpu_irqs_cnt: number of @mpu_irqs
486 * @sdma_reqs_cnt: number of @sdma_reqs
487 * @opt_clks_cnt: number of @opt_clks 483 * @opt_clks_cnt: number of @opt_clks
488 * @master_cnt: number of @master entries 484 * @master_cnt: number of @master entries
489 * @slaves_cnt: number of @slave entries 485 * @slaves_cnt: number of @slave entries
@@ -531,8 +527,6 @@ struct omap_hwmod {
531 u16 flags; 527 u16 flags;
532 u8 _mpu_port_index; 528 u8 _mpu_port_index;
533 u8 response_lat; 529 u8 response_lat;
534 u8 mpu_irqs_cnt;
535 u8 sdma_reqs_cnt;
536 u8 rst_lines_cnt; 530 u8 rst_lines_cnt;
537 u8 opt_clks_cnt; 531 u8 opt_clks_cnt;
538 u8 masters_cnt; 532 u8 masters_cnt;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 49fc0df0c21f..c8b9cd1716ba 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -236,11 +236,6 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
236 return 0; 236 return 0;
237} 237}
238 238
239static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
240{
241 return container_of(pdev, struct omap_device, pdev);
242}
243
244/** 239/**
245 * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks 240 * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
246 * @od: struct omap_device *od 241 * @od: struct omap_device *od
@@ -316,7 +311,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
316 struct omap_device *od; 311 struct omap_device *od;
317 u32 ret = 0; 312 u32 ret = 0;
318 313
319 od = _find_by_pdev(pdev); 314 od = to_omap_device(pdev);
320 315
321 if (od->hwmods_cnt) 316 if (od->hwmods_cnt)
322 ret = omap_hwmod_get_context_loss_count(od->hwmods[0]); 317 ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
@@ -611,7 +606,7 @@ int omap_device_enable(struct platform_device *pdev)
611 int ret; 606 int ret;
612 struct omap_device *od; 607 struct omap_device *od;
613 608
614 od = _find_by_pdev(pdev); 609 od = to_omap_device(pdev);
615 610
616 if (od->_state == OMAP_DEVICE_STATE_ENABLED) { 611 if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
617 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 612 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -650,7 +645,7 @@ int omap_device_idle(struct platform_device *pdev)
650 int ret; 645 int ret;
651 struct omap_device *od; 646 struct omap_device *od;
652 647
653 od = _find_by_pdev(pdev); 648 od = to_omap_device(pdev);
654 649
655 if (od->_state != OMAP_DEVICE_STATE_ENABLED) { 650 if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
656 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n", 651 WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -681,7 +676,7 @@ int omap_device_shutdown(struct platform_device *pdev)
681 int ret, i; 676 int ret, i;
682 struct omap_device *od; 677 struct omap_device *od;
683 678
684 od = _find_by_pdev(pdev); 679 od = to_omap_device(pdev);
685 680
686 if (od->_state != OMAP_DEVICE_STATE_ENABLED && 681 if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
687 od->_state != OMAP_DEVICE_STATE_IDLE) { 682 od->_state != OMAP_DEVICE_STATE_IDLE) {
@@ -722,7 +717,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
722 int ret = -EINVAL; 717 int ret = -EINVAL;
723 struct omap_device *od; 718 struct omap_device *od;
724 719
725 od = _find_by_pdev(pdev); 720 od = to_omap_device(pdev);
726 721
727 if (new_wakeup_lat_limit == od->dev_wakeup_lat) 722 if (new_wakeup_lat_limit == od->dev_wakeup_lat)
728 return 0; 723 return 0;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 04:37:01 -0500