[PATCH] i386, apic: clean up the APIC code

The apic code is quite unstructured and missing a lot of comments.

- Restructure the code into helper functions, timer, setup/shutdown,
  interrupt and power management blocks.
- Fixup comments.
- Namespace fixups
- Inline helpers for version and is_integrated
- Combine the ack_bad_irq functions

No functional changes.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Cc: Zachary Amsden <zach@vmware.com>
Cc: "Eric W. Biederman" <ebiederm@xmission.com>
Cc: Rohit Seth <rohitseth@google.com>
Cc: Andi Kleen <ak@suse.de>
Cc: john stultz <johnstul@us.ibm.com>
Cc: Roman Zippel <zippel@linux-m68k.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

5 files changed, 816 insertions, 767 deletions

diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c
index f4159e0a7ae9..b56448f214a7 100644
--- a/arch/i386/kernel/apic.c
+++ b/arch/i386/kernel/apic.c
@@ -45,6 +45,13 @@
 #include "io_ports.h"
 
 /*
+ * Sanity check
+ */
+#if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
+# error SPURIOUS_APIC_VECTOR definition error
+#endif
+
+/*
  * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
  * IPIs in place of local APIC timers
  */
@@ -52,121 +59,472 @@ static cpumask_t timer_bcast_ipi;
 
 /*
  * Knob to control our willingness to enable the local APIC.
+ *
+ * -1=force-disable, +1=force-enable
  */
-static int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
+static int enable_local_apic __initdata = 0;
+
+/*
+ * Debug level, exported for io_apic.c
+ */
+int apic_verbosity;
+
+static void apic_pm_activate(void);
 
-static inline void lapic_disable(void)
+
+/* Using APIC to generate smp_local_timer_interrupt? */
+int using_apic_timer __read_mostly = 0;
+
+/* Local APIC was disabled by the BIOS and enabled by the kernel */
+static int enabled_via_apicbase;
+
+/*
+ * Get the LAPIC version
+ */
+static inline int lapic_get_version(void)
 {
-        enable_local_apic = -1;
-        clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
+        return GET_APIC_VERSION(apic_read(APIC_LVR));
 }
 
-static inline void lapic_enable(void)
+/*
+ * Check, if the APIC is integrated or a seperate chip
+ */
+static inline int lapic_is_integrated(void)
 {
-        enable_local_apic = 1;
+        return APIC_INTEGRATED(lapic_get_version());
 }
 
 /*
- * Debug level
+ * Check, whether this is a modern or a first generation APIC
  */
-int apic_verbosity;
-
-
-static void apic_pm_activate(void);
-
 static int modern_apic(void)
 {
-        unsigned int lvr, version;
         /* AMD systems use old APIC versions, so check the CPU */
         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-                boot_cpu_data.x86 >= 0xf)
+            boot_cpu_data.x86 >= 0xf)
                 return 1;
-        lvr = apic_read(APIC_LVR);
-        version = GET_APIC_VERSION(lvr);
-        return version >= 0x14;
+        return lapic_get_version() >= 0x14;
+}
+
+/**
+ * enable_NMI_through_LVT0 - enable NMI through local vector table 0
+ */
+void enable_NMI_through_LVT0 (void * dummy)
+{
+        unsigned int v = APIC_DM_NMI;
+
+        /* Level triggered for 82489DX */
+        if (!lapic_is_integrated())
+                v |= APIC_LVT_LEVEL_TRIGGER;
+        apic_write_around(APIC_LVT0, v);
+}
+
+/**
+ * get_physical_broadcast - Get number of physical broadcast IDs
+ */
+int get_physical_broadcast(void)
+{
+        return modern_apic() ? 0xff : 0xf;
+}
+
+/**
+ * lapic_get_maxlvt - get the maximum number of local vector table entries
+ */
+int lapic_get_maxlvt(void)
+{
+        unsigned int v = apic_read(APIC_LVR);
+
+        /* 82489DXs do not report # of LVT entries. */
+        return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
 }
 
 /*
- * 'what should we do if we get a hw irq event on an illegal vector'.
- * each architecture has to answer this themselves.
+ * Local APIC timer
+ */
+
+/*
+ * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
+ * per second. We assume that the caller has already set up the local
+ * APIC.
+ *
+ * The APIC timer is not exactly sync with the external timer chip, it
+ * closely follows bus clocks.
+ */
+
+/*
+ * The timer chip is already set up at HZ interrupts per second here,
+ * but we do not accept timer interrupts yet. We only allow the BP
+ * to calibrate.
  */
-void ack_bad_irq(unsigned int irq)
+static unsigned int __devinit get_8254_timer_count(void)
+{
+        unsigned long flags;
+
+        unsigned int count;
+
+        spin_lock_irqsave(&i8253_lock, flags);
+
+        outb_p(0x00, PIT_MODE);
+        count = inb_p(PIT_CH0);
+        count |= inb_p(PIT_CH0) << 8;
+
+        spin_unlock_irqrestore(&i8253_lock, flags);
+
+        return count;
+}
+
+/* next tick in 8254 can be caught by catching timer wraparound */
+static void __devinit wait_8254_wraparound(void)
 {
-        printk("unexpected IRQ trap at vector %02x\n", irq);
+        unsigned int curr_count, prev_count;
+
+        curr_count = get_8254_timer_count();
+        do {
+                prev_count = curr_count;
+                curr_count = get_8254_timer_count();
+
+                /* workaround for broken Mercury/Neptune */
+                if (prev_count >= curr_count + 0x100)
+                        curr_count = get_8254_timer_count();
+
+        } while (prev_count >= curr_count);
+}
+
+/*
+ * Default initialization for 8254 timers. If we use other timers like HPET,
+ * we override this later
+ */
+void (*wait_timer_tick)(void) __devinitdata = wait_8254_wraparound;
+
+/*
+ * This function sets up the local APIC timer, with a timeout of
+ * 'clocks' APIC bus clock. During calibration we actually call
+ * this function twice on the boot CPU, once with a bogus timeout
+ * value, second time for real. The other (noncalibrating) CPUs
+ * call this function only once, with the real, calibrated value.
+ *
+ * We do reads before writes even if unnecessary, to get around the