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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2014-12-02 11:00:56 -0500
committerSimon Horman <horms+renesas@verge.net.au>2014-12-21 03:03:50 -0500
commite042681894b62d60f3a8704999d7700ebcdb9117 (patch)
treec3fa2792d8844f79eeeb06282173fb00b7d1b6c7
parenta483dcbfa21f919c7666cb897e293eff785e3bee (diff)
ARM: shmobile: r8a7790: Remove legacy code
All r8a7790 boards are now used with multiplatform kernels only. We can remove all the unused r8a7790 legacy device and clock registration code. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat
-rw-r--r--arch/arm/mach-shmobile/Kconfig8
-rw-r--r--arch/arm/mach-shmobile/Makefile1
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c459
-rw-r--r--arch/arm/mach-shmobile/r8a7790.h28
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c284
5 files changed, 1 insertions, 779 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index d4211cba3513..bb3d07504d8b 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -128,14 +128,6 @@ config ARCH_R8A7779
128 select ARCH_WANT_OPTIONAL_GPIOLIB 128 select ARCH_WANT_OPTIONAL_GPIOLIB
129 select ARM_GIC 129 select ARM_GIC
130 130
131config ARCH_R8A7790
132 bool "R-Car H2 (R8A77900)"
133 select ARCH_RCAR_GEN2
134 select ARCH_WANT_OPTIONAL_GPIOLIB
135 select ARM_GIC
136 select MIGHT_HAVE_PCI
137 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
138
139comment "Renesas ARM SoCs Board Type" 131comment "Renesas ARM SoCs Board Type"
140 132
141config MACH_APE6EVM 133config MACH_APE6EVM
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 3eefe7dc74b6..d53996e6da97 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
27obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o 27obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 28obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o 29obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
30obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
31endif 30endif
32 31
33# CPU reset vector handling objects 32# CPU reset vector handling objects
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
deleted file mode 100644
index f9bbc5f0a9a1..000000000000
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ /dev/null
@@ -1,459 +0,0 @@
1/*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/sh_clk.h>
20#include <linux/clkdev.h>
21
22#include "clock.h"
23#include "common.h"
24#include "r8a7790.h"
25#include "rcar-gen2.h"
26
27/*
28 * MD EXTAL PLL0 PLL1 PLL3
29 * 14 13 19 (MHz) *1 *1
30 *---------------------------------------------------
31 * 0 0 0 15 x 1 x172/2 x208/2 x106
32 * 0 0 1 15 x 1 x172/2 x208/2 x88
33 * 0 1 0 20 x 1 x130/2 x156/2 x80
34 * 0 1 1 20 x 1 x130/2 x156/2 x66
35 * 1 0 0 26 / 2 x200/2 x240/2 x122
36 * 1 0 1 26 / 2 x200/2 x240/2 x102
37 * 1 1 0 30 / 2 x172/2 x208/2 x106
38 * 1 1 1 30 / 2 x172/2 x208/2 x88
39 *
40 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
41 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
42 */
43
44#define CPG_BASE 0xe6150000
45#define CPG_LEN 0x1000
46
47#define SMSTPCR1 0xe6150134
48#define SMSTPCR2 0xe6150138
49#define SMSTPCR3 0xe615013c
50#define SMSTPCR5 0xe6150144
51#define SMSTPCR7 0xe615014c
52#define SMSTPCR8 0xe6150990
53#define SMSTPCR9 0xe6150994
54#define SMSTPCR10 0xe6150998
55
56#define MSTPSR1 IOMEM(0xe6150038)
57#define MSTPSR2 IOMEM(0xe6150040)
58#define MSTPSR3 IOMEM(0xe6150048)
59#define MSTPSR5 IOMEM(0xe615003c)
60#define MSTPSR7 IOMEM(0xe61501c4)
61#define MSTPSR8 IOMEM(0xe61509a0)
62#define MSTPSR9 IOMEM(0xe61509a4)
63#define MSTPSR10 IOMEM(0xe61509a8)
64
65#define SDCKCR 0xE6150074
66#define SD2CKCR 0xE6150078
67#define SD3CKCR 0xE615026C
68#define MMC0CKCR 0xE6150240
69#define MMC1CKCR 0xE6150244
70#define SSPCKCR 0xE6150248
71#define SSPRSCKCR 0xE615024C
72
73static struct clk_mapping cpg_mapping = {
74 .phys = CPG_BASE,
75 .len = CPG_LEN,
76};
77
78static struct clk extal_clk = {
79 /* .rate will be updated on r8a7790_clock_init() */
80 .mapping = &cpg_mapping,
81};
82
83static struct sh_clk_ops followparent_clk_ops = {
84 .recalc = followparent_recalc,
85};
86
87static struct clk main_clk = {
88 /* .parent will be set r8a7790_clock_init */
89 .ops = &followparent_clk_ops,
90};
91
92static struct clk audio_clk_a = {
93};
94
95static struct clk audio_clk_b = {
96};
97
98static struct clk audio_clk_c = {
99};
100
101/*
102 * clock ratio of these clock will be updated
103 * on r8a7790_clock_init()
104 */
105SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
106SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
107SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
108SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
109
110/* fixed ratio clock */
111SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
112SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
113
114SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
115SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
116SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
117SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
118SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
119SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
120SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
121SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
122SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
123SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
124SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
125SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
126SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
127
128SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
129SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
130SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
131SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
132
133static struct clk *main_clks[] = {
134 &audio_clk_a,
135 &audio_clk_b,
136 &audio_clk_c,
137 &extal_clk,
138 &extal_div2_clk,
139 &main_clk,
140 &pll1_clk,
141 &pll1_div2_clk,
142 &pll3_clk,
143 &lb_clk,
144 &qspi_clk,
145 &zg_clk,
146 &zx_clk,
147 &zs_clk,
148 &hp_clk,
149 &i_clk,
150 &b_clk,
151 &p_clk,
152 &cl_clk,
153 &m2_clk,
154 &imp_clk,
155 &rclk_clk,
156 &oscclk_clk,
157 &zb3_clk,
158 &zb3d2_clk,
159 &ddr_clk,
160 &mp_clk,
161 &cp_clk,
162};
163
164/* SDHI (DIV4) clock */
165static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
166
167static struct clk_div_mult_table div4_div_mult_table = {
168 .divisors = divisors,
169 .nr_divisors = ARRAY_SIZE(divisors),
170};
171
172static struct clk_div4_table div4_table = {
173 .div_mult_table = &div4_div_mult_table,
174};
175
176enum {
177 DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
178};
179
180static struct clk div4_clks[DIV4_NR] = {
181 [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
182 [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
183 [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
184};
185
186/* DIV6 clocks */
187enum {
188 DIV6_SD2, DIV6_SD3,
189 DIV6_MMC0, DIV6_MMC1,
190 DIV6_SSP, DIV6_SSPRS,
191 DIV6_NR
192};
193
194static struct clk div6_clks[DIV6_NR] = {
195 [DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
196 [DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
197 [DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
198 [DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
199 [DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
200 [DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
201};
202
203/* MSTP */
204enum {
205 MSTP1017, /* parent of SCU */
206
207 MSTP1031, MSTP1030,
208 MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
209 MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
210 MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
211 MSTP931, MSTP930, MSTP929, MSTP928,
212 MSTP917,
213 MSTP815, MSTP814,
214 MSTP813,
215 MSTP811, MSTP810, MSTP809, MSTP808,
216 MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
217 MSTP717, MSTP716,
218 MSTP704, MSTP703,
219 MSTP522,
220 MSTP502, MSTP501,
221 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
222 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
223 MSTP124,
224 MSTP_NR
225};
226
227static struct clk mstp_clks[MSTP_NR] = {
228 [MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
229 [MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
230 [MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
231 [MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
232 [MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
233 [MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
234 [MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
235 [MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
236 [MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
237 [MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
238 [MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
239 [MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
240 [MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
241 [MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
242 [MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
243 [MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
244 [MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
245 [MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
246 [MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
247 [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
248 [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
249 [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
250 [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
251 [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
252 [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
253 [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
254 [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
255 [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
256 [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
257 [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
258 [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
259 [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
260 [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
261 [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
262 [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
263 [MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
264 [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
265 [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
266 [MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
267 [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
268 [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
269 [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
270 [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
271 [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
272 [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
273 [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
274 [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
275 [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
276 [MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
277 [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
278 [MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
279 [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
280 [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
281 [MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
282 [MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
283 [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
284 [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
285 [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
286 [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
287 [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
288 [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
289 [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
290};
291
292static struct clk_lookup lookups[] = {
293
294 /* main clocks */
295 CLKDEV_CON_ID("extal", &extal_clk),
296 CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
297 CLKDEV_CON_ID("main", &main_clk),
298 CLKDEV_CON_ID("pll1", &pll1_clk),
299 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
300 CLKDEV_CON_ID("pll3", &pll3_clk),
301 CLKDEV_CON_ID("zg", &zg_clk),
302 CLKDEV_CON_ID("zx", &zx_clk),
303 CLKDEV_CON_ID("zs", &zs_clk),
304 CLKDEV_CON_ID("hp", &hp_clk),
305 CLKDEV_CON_ID("i", &i_clk),
306 CLKDEV_CON_ID("b", &b_clk),
307 CLKDEV_CON_ID("lb", &lb_clk),
308 CLKDEV_CON_ID("p", &p_clk),
309 CLKDEV_CON_ID("cl", &cl_clk),
310 CLKDEV_CON_ID("m2", &m2_clk),
311 CLKDEV_CON_ID("imp", &imp_clk),
312 CLKDEV_CON_ID("rclk", &rclk_clk),
313 CLKDEV_CON_ID("oscclk", &oscclk_clk),
314 CLKDEV_CON_ID("zb3", &zb3_clk),
315 CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
316 CLKDEV_CON_ID("ddr", &ddr_clk),
317 CLKDEV_CON_ID("mp", &mp_clk),
318 CLKDEV_CON_ID("qspi", &qspi_clk),
319 CLKDEV_CON_ID("cp", &cp_clk),
320
321 /* DIV4 */
322 CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
323
324 /* DIV6 */
325 CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
326 CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
327
328 /* MSTP */
329 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
330 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
331 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
332 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
333 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
334 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
335 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
336 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
337 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
338 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
339 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
340 CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
341 CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
342 CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
343 CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
344 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
345 CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
346 CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
347 CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
348 CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
349 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
350 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
351 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
352 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
353 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
354 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
355 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
356 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
357 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
358 CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
359 CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
360 CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
361 CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
362 CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
363 CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
364 CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
365
366 /* ICK */
367 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
368 CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
369 CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
370 CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
371 CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
372 CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
373 CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
374 CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
375 CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
376 CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
377 CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
378 CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
379 CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
380 CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
381 CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
382 CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
383 CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
384 CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
385 CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
386 CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
387 CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
388 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
389 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
390 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
391 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
392 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
393 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
394 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
395 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
396 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
397 CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
398
399};
400
401#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
402 extal_clk.rate = e * 1000 * 1000; \
403 main_clk.parent = m; \
404 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
405 if (mode & MD(19)) \
406 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
407 else \
408 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
409
410
411void __init r8a7790_clock_init(void)
412{
413 u32 mode = rcar_gen2_read_mode_pins();
414 int k, ret = 0;
415
416 switch (mode & (MD(14) | MD(13))) {
417 case 0:
418 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
419 break;
420 case MD(13):
421 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
422 break;
423 case MD(14):
424 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
425 break;
426 case MD(13) | MD(14):
427 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
428 break;
429 }
430
431 if (mode & (MD(18)))
432 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
433 else
434 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
435
436 if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
437 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
438 else
439 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
440
441 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
442 ret = clk_register(main_clks[k]);
443
444 if (!ret)
445 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
446
447 if (!ret)
448 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
449
450 if (!ret)
451 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
452
453 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
454
455 if (!ret)
456 shmobile_clk_init();
457 else
458 panic("failed to setup r8a7790 clocks\n");
459}
diff --git a/arch/arm/mach-shmobile/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h
index 388f0514d931..bf73a850aaed 100644
--- a/arch/arm/mach-shmobile/r8a7790.h
+++ b/arch/arm/mach-shmobile/r8a7790.h
@@ -1,34 +1,6 @@
1#ifndef __ASM_R8A7790_H__ 1#ifndef __ASM_R8A7790_H__
2#define __ASM_R8A7790_H__ 2#define __ASM_R8A7790_H__
3 3
4/* DMA slave IDs */
5enum {
6 RCAR_DMA_SLAVE_INVALID,
7 AUDIO_DMAC_SLAVE_SSI0_TX,
8 AUDIO_DMAC_SLAVE_SSI0_RX,
9 AUDIO_DMAC_SLAVE_SSI1_TX,
10 AUDIO_DMAC_SLAVE_SSI1_RX,
11 AUDIO_DMAC_SLAVE_SSI2_TX,
12 AUDIO_DMAC_SLAVE_SSI2_RX,
13 AUDIO_DMAC_SLAVE_SSI3_TX,
14 AUDIO_DMAC_SLAVE_SSI3_RX,
15 AUDIO_DMAC_SLAVE_SSI4_TX,
16 AUDIO_DMAC_SLAVE_SSI4_RX,
17 AUDIO_DMAC_SLAVE_SSI5_TX,
18 AUDIO_DMAC_SLAVE_SSI5_RX,
19 AUDIO_DMAC_SLAVE_SSI6_TX,
20 AUDIO_DMAC_SLAVE_SSI6_RX,
21 AUDIO_DMAC_SLAVE_SSI7_TX,
22 AUDIO_DMAC_SLAVE_SSI7_RX,
23 AUDIO_DMAC_SLAVE_SSI8_TX,
24 AUDIO_DMAC_SLAVE_SSI8_RX,
25 AUDIO_DMAC_SLAVE_SSI9_TX,
26 AUDIO_DMAC_SLAVE_SSI9_RX,
27};
28
29void r8a7790_add_standard_devices(void);
30void r8a7790_clock_init(void);
31void r8a7790_pinmux_init(void);
32void r8a7790_pm_init(void); 4void r8a7790_pm_init(void);
33extern struct smp_operations r8a7790_smp_ops; 5extern struct smp_operations r8a7790_smp_ops;
34 6
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index ec7d97dca4de..3a18af4922b4 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -14,295 +14,14 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <linux/irq.h> 17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/of_platform.h>
20#include <linux/platform_data/gpio-rcar.h>
21#include <linux/platform_data/irq-renesas-irqc.h>
22#include <linux/serial_sci.h>
23#include <linux/sh_dma.h>
24#include <linux/sh_timer.h>
25 18
26#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
27 20
28#include "common.h" 21#include "common.h"
29#include "dma-register.h"
30#include "irqs.h"
31#include "r8a7790.h" 22#include "r8a7790.h"
32#include "rcar-gen2.h" 23#include "rcar-gen2.h"
33 24
34/* Audio-DMAC */
35#define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \
36{ \
37 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \
38 .addr = _addr + 0x8, \
39 .chcr = CHCR_TX(XMIT_SZ_32BIT), \
40 .mid_rid = t, \
41}, { \
42 .slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \
43 .addr = _addr + 0xc, \
44 .chcr = CHCR_RX(XMIT_SZ_32BIT), \
45 .mid_rid = r, \
46}
47
48static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
49 AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
50 AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
51 AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
52 AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
53 AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
54 AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
55 AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
56 AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
57 AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
58 AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
59};
60
61#define DMAE_CHANNEL(a, b) \
62{ \
63 .offset = (a) - 0x20, \
64 .dmars = (a) - 0x20 + 0x40, \
65 .chclr_bit = (b), \
66 .chclr_offset = 0x80 - 0x20, \
67}
68
69static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
70 DMAE_CHANNEL(0x8000, 0),
71 DMAE_CHANNEL(0x8080, 1),
72 DMAE_CHANNEL(0x8100, 2),
73 DMAE_CHANNEL(0x8180, 3),
74 DMAE_CHANNEL(0x8200, 4),
75 DMAE_CHANNEL(0x8280, 5),
76 DMAE_CHANNEL(0x8300, 6),
77 DMAE_CHANNEL(0x8380, 7),
78 DMAE_CHANNEL(0x8400, 8),
79 DMAE_CHANNEL(0x8480, 9),
80 DMAE_CHANNEL(0x8500, 10),
81 DMAE_CHANNEL(0x8580, 11),
82 DMAE_CHANNEL(0x8600, 12),
83};
84
85static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
86 .slave = r8a7790_audio_dmac_slaves,
87 .slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
88 .channel = r8a7790_audio_dmac_channels,
89 .channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels),
90 .ts_low_shift = TS_LOW_SHIFT,
91 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
92 .ts_high_shift = TS_HI_SHIFT,
93 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
94 .ts_shift = dma_ts_shift,
95 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
96 .dmaor_init = DMAOR_DME,
97 .chclr_present = 1,
98 .chclr_bitwise = 1,
99};
100
101static struct resource r8a7790_audio_dmac_resources[] = {
102 /* Channel registers and DMAOR for low */
103 DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
104 DEFINE_RES_IRQ(gic_spi(346)),
105 DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
106
107 /* Channel registers and DMAOR for hi */
108 DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
109 DEFINE_RES_IRQ(gic_spi(347)),
110 DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
111};
112
113#define r8a7790_register_audio_dmac(id) \
114 platform_device_register_resndata( \
115 NULL, "sh-dma-engine", id, \
116 &r8a7790_audio_dmac_resources[id * 3], 3, \
117 &r8a7790_audio_dmac_platform_data, \
118 sizeof(r8a7790_audio_dmac_platform_data))
119
120static const struct resource pfc_resources[] __initconst = {
121 DEFINE_RES_MEM(0xe6060000, 0x250),
122};
123
124#define r8a7790_register_pfc() \
125 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
126 ARRAY_SIZE(pfc_resources))
127
128#define R8A7790_GPIO(idx) \
129static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
130 DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \
131 DEFINE_RES_IRQ(gic_spi(4 + (idx))), \
132}; \
133 \
134static const struct gpio_rcar_config \
135r8a7790_gpio##idx##_platform_data __initconst = { \
136 .gpio_base = 32 * (idx), \
137 .irq_base = 0, \
138 .number_of_pins = 32, \
139 .pctl_name = "pfc-r8a7790", \
140 .has_both_edge_trigger = 1, \
141}; \
142
143R8A7790_GPIO(0);
144R8A7790_GPIO(1);
145R8A7790_GPIO(2);
146R8A7790_GPIO(3);
147R8A7790_GPIO(4);
148R8A7790_GPIO(5);
149
150#define r8a7790_register_gpio(idx) \
151 platform_device_register_resndata(NULL, "gpio_rcar", idx, \
152 r8a7790_gpio##idx##_resources, \
153 ARRAY_SIZE(r8a7790_gpio##idx##_resources), \
154 &r8a7790_gpio##idx##_platform_data, \
155 sizeof(r8a7790_gpio##idx##_platform_data))
156
157static struct resource i2c_resources[] __initdata = {
158 /* I2C0 */
159 DEFINE_RES_MEM(0xE6508000, 0x40),
160 DEFINE_RES_IRQ(gic_spi(287)),
161 /* I2C1 */
162 DEFINE_RES_MEM(0xE6518000, 0x40),
163 DEFINE_RES_IRQ(gic_spi(288)),
164 /* I2C2 */
165 DEFINE_RES_MEM(0xE6530000, 0x40),
166 DEFINE_RES_IRQ(gic_spi(286)),
167 /* I2C3 */
168 DEFINE_RES_MEM(0xE6540000, 0x40),
169 DEFINE_RES_IRQ(gic_spi(290)),
170
171};
172
173#define r8a7790_register_i2c(idx) \
174 platform_device_register_simple( \
175 "i2c-rcar_gen2", idx, \
176 i2c_resources + (2 * idx), 2); \
177
178void __init r8a7790_pinmux_init(void)
179{
180 r8a7790_register_pfc();
181 r8a7790_register_gpio(0);
182 r8a7790_register_gpio(1);
183 r8a7790_register_gpio(2);
184 r8a7790_register_gpio(3);
185 r8a7790_register_gpio(4);
186 r8a7790_register_gpio(5);
187}
188
189#define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \
190static struct plat_sci_port scif##index##_platform_data = { \
191 .type = scif_type, \
192 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
193 .scscr = _scscr, \
194}; \
195 \
196static struct resource scif##index##_resources[] = { \
197 DEFINE_RES_MEM(baseaddr, 0x100), \
198 DEFINE_RES_IRQ(irq), \
199}
200
201#define R8A7790_SCIF(index, baseaddr, irq) \
202 __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \
203 index, baseaddr, irq)
204
205#define R8A7790_SCIFA(index, baseaddr, irq) \
206 __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
207 index, baseaddr, irq)
208
209#define R8A7790_SCIFB(index, baseaddr, irq) \
210 __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
211 index, baseaddr, irq)
212
213#define R8A7790_HSCIF(index, baseaddr, irq) \
214 __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \
215 index, baseaddr, irq)
216
217R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
218R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
219R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
220R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
221R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
222R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
223R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */
224R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */
225R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
226R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
227
228#define r8a7790_register_scif(index) \
229 platform_device_register_resndata(NULL, "sh-sci", index, \
230 scif##index##_resources, \
231 ARRAY_SIZE(scif##index##_resources), \
232 &scif##index##_platform_data, \
233 sizeof(scif##index##_platform_data))
234
235static const struct renesas_irqc_config irqc0_data __initconst = {
236 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
237};
238
239static const struct resource irqc0_resources[] __initconst = {
240 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
241 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
242 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
243 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
244 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
245};
246
247#define r8a7790_register_irqc(idx) \
248 platform_device_register_resndata(NULL, "renesas_irqc", \
249 idx, irqc##idx##_resources, \
250 ARRAY_SIZE(irqc##idx##_resources), \
251 &irqc##idx##_data, \
252 sizeof(struct renesas_irqc_config))
253
254static const struct resource thermal_resources[] __initconst = {
255 DEFINE_RES_MEM(0xe61f0000, 0x14),
256 DEFINE_RES_MEM(0xe61f0100, 0x38),
257 DEFINE_RES_IRQ(gic_spi(69)),
258};
259
260#define r8a7790_register_thermal() \
261 platform_device_register_simple("rcar_thermal", -1, \
262 thermal_resources, \
263 ARRAY_SIZE(thermal_resources))
264
265static struct sh_timer_config cmt0_platform_data = {
266 .channels_mask = 0x60,
267};
268
269static struct resource cmt0_resources[] = {
270 DEFINE_RES_MEM(0xffca0000, 0x1004),
271 DEFINE_RES_IRQ(gic_spi(142)),
272};
273
274#define r8a7790_register_cmt(idx) \
275 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
276 idx, cmt##idx##_resources, \
277 ARRAY_SIZE(cmt##idx##_resources), \
278 &cmt##idx##_platform_data, \
279 sizeof(struct sh_timer_config))
280
281void __init r8a7790_add_standard_devices(void)
282{
283 r8a7790_register_scif(0);
284 r8a7790_register_scif(1);
285 r8a7790_register_scif(2);
286 r8a7790_register_scif(3);
287 r8a7790_register_scif(4);
288 r8a7790_register_scif(5);
289 r8a7790_register_scif(6);
290 r8a7790_register_scif(7);
291 r8a7790_register_scif(8);
292 r8a7790_register_scif(9);
293 r8a7790_register_cmt(0);
294 r8a7790_register_irqc(0);
295 r8a7790_register_thermal();
296 r8a7790_register_i2c(0);
297 r8a7790_register_i2c(1);
298 r8a7790_register_i2c(2);
299 r8a7790_register_i2c(3);
300 r8a7790_register_audio_dmac(0);
301 r8a7790_register_audio_dmac(1);
302}
303
304#ifdef CONFIG_USE_OF
305
306static const char * const r8a7790_boards_compat_dt[] __initconst = { 25static const char * const r8a7790_boards_compat_dt[] __initconst = {
307 "renesas,r8a7790", 26 "renesas,r8a7790",
308 NULL, 27 NULL,
@@ -316,4 +35,3 @@ DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
316 .reserve = rcar_gen2_reserve, 35 .reserve = rcar_gen2_reserve,
317 .dt_compat = r8a7790_boards_compat_dt, 36 .dt_compat = r8a7790_boards_compat_dt,
318MACHINE_END 37MACHINE_END
319#endif /* CONFIG_USE_OF */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 12:09:05 -0400