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authorJon Hunter <jon-hunter@ti.com>2012-11-01 10:09:51 -0400
committerBenoit Cousson <b-cousson@ti.com>2012-11-01 12:04:00 -0400
commitdf692a925185b08ab5e792d163ee997bd773cdb9 (patch)
tree4dcef710f1d30fde15606d38146e44f394315896
parentd03a93bbec5edfe33f09d629d27c1afd50f043aa (diff)
ARM: dts: OMAP5: Add timer nodes
Add the 11 timer nodes for OMAP5 devices. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Benoit Cousson <b-cousson@ti.com>
-rw-r--r--arch/arm/boot/dts/omap5.dtsi89
1 files changed, 89 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 930dbfe3bcff..c8954f1f96e4 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -379,5 +379,94 @@
379 ti,buffer-size = <128>; 379 ti,buffer-size = <128>;
380 ti,hwmods = "mcbsp3"; 380 ti,hwmods = "mcbsp3";
381 }; 381 };
382
383 timer1: timer@4ae18000 {
384 compatible = "ti,omap2-timer";
385 reg = <0x4ae18000 0x80>;
386 interrupts = <0 37 0x4>;
387 ti,hwmods = "timer1";
388 ti,timer-alwon;
389 };
390
391 timer2: timer@48032000 {
392 compatible = "ti,omap2-timer";
393 reg = <0x48032000 0x80>;
394 interrupts = <0 38 0x4>;
395 ti,hwmods = "timer2";
396 };
397
398 timer3: timer@48034000 {
399 compatible = "ti,omap2-timer";
400 reg = <0x48034000 0x80>;
401 interrupts = <0 39 0x4>;
402 ti,hwmods = "timer3";
403 };
404
405 timer4: timer@48036000 {
406 compatible = "ti,omap2-timer";
407 reg = <0x48036000 0x80>;
408 interrupts = <0 40 0x4>;
409 ti,hwmods = "timer4";
410 };
411
412 timer5: timer@40138000 {
413 compatible = "ti,omap2-timer";
414 reg = <0x40138000 0x80>,
415 <0x49038000 0x80>;
416 interrupts = <0 41 0x4>;
417 ti,hwmods = "timer5";
418 ti,timer-dsp;
419 };
420
421 timer6: timer@4013a000 {
422 compatible = "ti,omap2-timer";
423 reg = <0x4013a000 0x80>,
424 <0x4903a000 0x80>;
425 interrupts = <0 42 0x4>;
426 ti,hwmods = "timer6";
427 ti,timer-dsp;
428 ti,timer-pwm;
429 };
430
431 timer7: timer@4013c000 {
432 compatible = "ti,omap2-timer";
433 reg = <0x4013c000 0x80>,
434 <0x4903c000 0x80>;
435 interrupts = <0 43 0x4>;
436 ti,hwmods = "timer7";
437 ti,timer-dsp;
438 };
439
440 timer8: timer@4013e000 {
441 compatible = "ti,omap2-timer";
442 reg = <0x4013e000 0x80>,
443 <0x4903e000 0x80>;
444 interrupts = <0 44 0x4>;
445 ti,hwmods = "timer8";
446 ti,timer-dsp;
447 ti,timer-pwm;
448 };
449
450 timer9: timer@4803e000 {
451 compatible = "ti,omap2-timer";
452 reg = <0x4803e000 0x80>;
453 interrupts = <0 45 0x4>;
454 ti,hwmods = "timer9";
455 };
456
457 timer10: timer@48086000 {
458 compatible = "ti,omap2-timer";
459 reg = <0x48086000 0x80>;
460 interrupts = <0 46 0x4>;
461 ti,hwmods = "timer10";
462 };
463
464 timer11: timer@48088000 {
465 compatible = "ti,omap2-timer";
466 reg = <0x48088000 0x80>;
467 interrupts = <0 47 0x4>;
468 ti,hwmods = "timer11";
469 ti,timer-pwm;
470 };
382 }; 471 };
383}; 472};