diff options
| author | Kukjin Kim <kgene.kim@samsung.com> | 2011-02-01 02:26:33 -0500 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-02-16 22:52:52 -0500 |
| commit | df3ca747ebea6168059cd7ca7e1b3f65aae3bcc1 (patch) | |
| tree | e01b5de227360add5ebaf35532efbf2053b26003 | |
| parent | 85e2efbb1db9a18d218006706d6e4fbeb0216213 (diff) | |
ARM: S5PV310: Cleanup map.h file
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/mach-s5pv310/include/mach/map.h | 149 |
1 files changed, 73 insertions, 76 deletions
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h index 3060f78e12ab..901657fa7a12 100644 --- a/arch/arm/mach-s5pv310/include/mach/map.h +++ b/arch/arm/mach-s5pv310/include/mach/map.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv310/include/mach/map.h | 1 | /* linux/arch/arm/mach-s5pv310/include/mach/map.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | 3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com/ | 4 | * http://www.samsung.com/ |
| 5 | * | 5 | * |
| 6 | * S5PV310 - Memory map definitions | 6 | * S5PV310 - Memory map definitions |
| @@ -23,90 +23,43 @@ | |||
| 23 | 23 | ||
| 24 | #include <plat/map-s5p.h> | 24 | #include <plat/map-s5p.h> |
| 25 | 25 | ||
| 26 | #define S5PV310_PA_SYSRAM (0x02025000) | 26 | #define S5PV310_PA_SYSRAM 0x02025000 |
| 27 | 27 | ||
| 28 | #define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) | 28 | #define S5PV310_PA_I2S0 0x03830000 |
| 29 | 29 | #define S5PV310_PA_I2S1 0xE3100000 | |
| 30 | #define S5PC210_PA_ONENAND (0x0C000000) | 30 | #define S5PV310_PA_I2S2 0xE2A00000 |
| 31 | #define S5P_PA_ONENAND S5PC210_PA_ONENAND | ||
| 32 | |||
| 33 | #define S5PC210_PA_ONENAND_DMA (0x0C600000) | ||
| 34 | #define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA | ||
| 35 | |||
| 36 | #define S5PV310_PA_CHIPID (0x10000000) | ||
| 37 | #define S5P_PA_CHIPID S5PV310_PA_CHIPID | ||
| 38 | |||
| 39 | #define S5PV310_PA_SYSCON (0x10010000) | ||
| 40 | #define S5P_PA_SYSCON S5PV310_PA_SYSCON | ||
| 41 | 31 | ||
| 42 | #define S5PV310_PA_PMU (0x10020000) | 32 | #define S5PV310_PA_PCM0 0x03840000 |
| 33 | #define S5PV310_PA_PCM1 0x13980000 | ||
| 34 | #define S5PV310_PA_PCM2 0x13990000 | ||
| 43 | 35 | ||
| 44 | #define S5PV310_PA_CMU (0x10030000) | 36 | #define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) |
| 45 | |||
| 46 | #define S5PV310_PA_WATCHDOG (0x10060000) | ||
| 47 | #define S5PV310_PA_RTC (0x10070000) | ||
| 48 | |||
| 49 | #define S5PV310_PA_DMC0 (0x10400000) | ||
| 50 | |||
| 51 | #define S5PV310_PA_COMBINER (0x10448000) | ||
| 52 | |||
| 53 | #define S5PV310_PA_COREPERI (0x10500000) | ||
| 54 | #define S5PV310_PA_GIC_CPU (0x10500100) | ||
| 55 | #define S5PV310_PA_TWD (0x10500600) | ||
| 56 | #define S5PV310_PA_GIC_DIST (0x10501000) | ||
| 57 | #define S5PV310_PA_L2CC (0x10502000) | ||
| 58 | |||
| 59 | /* DMA */ | ||
| 60 | #define S5PV310_PA_MDMA 0x10810000 | ||
| 61 | #define S5PV310_PA_PDMA0 0x12680000 | ||
| 62 | #define S5PV310_PA_PDMA1 0x12690000 | ||
| 63 | |||
| 64 | #define S5PV310_PA_GPIO1 (0x11400000) | ||
| 65 | #define S5PV310_PA_GPIO2 (0x11000000) | ||
| 66 | #define S5PV310_PA_GPIO3 (0x03860000) | ||
| 67 | |||
| 68 | #define S5PV310_PA_MIPI_CSIS0 0x11880000 | ||
| 69 | #define S5PV310_PA_MIPI_CSIS1 0x11890000 | ||
| 70 | 37 | ||
| 71 | #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) | 38 | #define S5PC210_PA_ONENAND 0x0C000000 |
| 39 | #define S5PC210_PA_ONENAND_DMA 0x0C600000 | ||
| 72 | 40 | ||
| 73 | #define S5PV310_PA_SROMC (0x12570000) | 41 | #define S5PV310_PA_CHIPID 0x10000000 |
| 74 | #define S5P_PA_SROMC S5PV310_PA_SROMC | ||
| 75 | 42 | ||
| 76 | /* S/PDIF */ | 43 | #define S5PV310_PA_SYSCON 0x10010000 |
| 77 | #define S5PV310_PA_SPDIF 0xE1100000 | 44 | #define S5PV310_PA_PMU 0x10020000 |
| 45 | #define S5PV310_PA_CMU 0x10030000 | ||
| 78 | 46 | ||
| 79 | /* I2S */ | 47 | #define S5PV310_PA_WATCHDOG 0x10060000 |
| 80 | #define S5PV310_PA_I2S0 0x03830000 | 48 | #define S5PV310_PA_RTC 0x10070000 |
| 81 | #define S5PV310_PA_I2S1 0xE3100000 | ||
| 82 | #define S5PV310_PA_I2S2 0xE2A00000 | ||
| 83 | 49 | ||
| 84 | /* PCM */ | 50 | #define S5PV310_PA_DMC0 0x10400000 |
| 85 | #define S5PV310_PA_PCM0 0x03840000 | ||
| 86 | #define S5PV310_PA_PCM1 0x13980000 | ||
| 87 | #define S5PV310_PA_PCM2 0x13990000 | ||
| 88 | 51 | ||
| 89 | /* AC97 */ | 52 | #define S5PV310_PA_COMBINER 0x10448000 |
| 90 | #define S5PV310_PA_AC97 0x139A0000 | ||
| 91 | 53 | ||
| 92 | #define S5PV310_PA_UART (0x13800000) | 54 | #define S5PV310_PA_COREPERI 0x10500000 |
| 55 | #define S5PV310_PA_GIC_CPU 0x10500100 | ||
| 56 | #define S5PV310_PA_TWD 0x10500600 | ||
| 57 | #define S5PV310_PA_GIC_DIST 0x10501000 | ||
| 58 | #define S5PV310_PA_L2CC 0x10502000 | ||
| 93 | 59 | ||
| 94 | #define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) | 60 | #define S5PV310_PA_MDMA 0x10810000 |
| 95 | #define S5P_PA_UART0 S5P_PA_UART(0) | 61 | #define S5PV310_PA_PDMA0 0x12680000 |
| 96 | #define S5P_PA_UART1 S5P_PA_UART(1) | 62 | #define S5PV310_PA_PDMA1 0x12690000 |
| 97 | #define S5P_PA_UART2 S5P_PA_UART(2) | ||
| 98 | #define S5P_PA_UART3 S5P_PA_UART(3) | ||
| 99 | #define S5P_PA_UART4 S5P_PA_UART(4) | ||
| 100 | |||
| 101 | #define S5P_SZ_UART SZ_256 | ||
| 102 | |||
| 103 | #define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) | ||
| 104 | |||
| 105 | #define S5PV310_PA_TIMER (0x139D0000) | ||
| 106 | #define S5P_PA_TIMER S5PV310_PA_TIMER | ||
| 107 | |||
| 108 | #define S5PV310_PA_SDRAM (0x40000000) | ||
| 109 | #define S5P_PA_SDRAM S5PV310_PA_SDRAM | ||
| 110 | 63 | ||
| 111 | #define S5PV310_PA_SYSMMU_MDMA 0x10A40000 | 64 | #define S5PV310_PA_SYSMMU_MDMA 0x10A40000 |
| 112 | #define S5PV310_PA_SYSMMU_SSS 0x10A50000 | 65 | #define S5PV310_PA_SYSMMU_SSS 0x10A50000 |
| @@ -125,8 +78,31 @@ | |||
| 125 | #define S5PV310_PA_SYSMMU_MFC_L 0x13620000 | 78 | #define S5PV310_PA_SYSMMU_MFC_L 0x13620000 |
| 126 | #define S5PV310_PA_SYSMMU_MFC_R 0x13630000 | 79 | #define S5PV310_PA_SYSMMU_MFC_R 0x13630000 |
| 127 | 80 | ||
| 128 | /* compatibiltiy defines. */ | 81 | #define S5PV310_PA_GPIO1 0x11400000 |
| 129 | #define S3C_PA_UART S5PV310_PA_UART | 82 | #define S5PV310_PA_GPIO2 0x11000000 |
| 83 | #define S5PV310_PA_GPIO3 0x03860000 | ||
| 84 | |||
| 85 | #define S5PV310_PA_MIPI_CSIS0 0x11880000 | ||
| 86 | #define S5PV310_PA_MIPI_CSIS1 0x11890000 | ||
| 87 | |||
| 88 | #define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) | ||
| 89 | |||
| 90 | #define S5PV310_PA_SROMC 0x12570000 | ||
| 91 | |||
| 92 | #define S5PV310_PA_UART 0x13800000 | ||
| 93 | |||
| 94 | #define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) | ||
| 95 | |||
| 96 | #define S5PV310_PA_AC97 0x139A0000 | ||
| 97 | |||
| 98 | #define S5PV310_PA_TIMER 0x139D0000 | ||
| 99 | |||
| 100 | #define S5PV310_PA_SDRAM 0x40000000 | ||
| 101 | |||
| 102 | #define S5PV310_PA_SPDIF 0xE1100000 | ||
| 103 | |||
| 104 | /* Compatibiltiy Defines */ | ||
| 105 | |||
| 130 | #define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) | 106 | #define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) |
| 131 | #define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) | 107 | #define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) |
| 132 | #define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) | 108 | #define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) |
| @@ -141,7 +117,28 @@ | |||
| 141 | #define S3C_PA_IIC7 S5PV310_PA_IIC(7) | 117 | #define S3C_PA_IIC7 S5PV310_PA_IIC(7) |
| 142 | #define S3C_PA_RTC S5PV310_PA_RTC | 118 | #define S3C_PA_RTC S5PV310_PA_RTC |
| 143 | #define S3C_PA_WDT S5PV310_PA_WATCHDOG | 119 | #define S3C_PA_WDT S5PV310_PA_WATCHDOG |
| 120 | |||
| 121 | #define S5P_PA_CHIPID S5PV310_PA_CHIPID | ||
| 144 | #define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0 | 122 | #define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0 |
| 145 | #define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1 | 123 | #define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1 |
| 124 | #define S5P_PA_ONENAND S5PC210_PA_ONENAND | ||
| 125 | #define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA | ||
| 126 | #define S5P_PA_SDRAM S5PV310_PA_SDRAM | ||
| 127 | #define S5P_PA_SROMC S5PV310_PA_SROMC | ||
| 128 | #define S5P_PA_SYSCON S5PV310_PA_SYSCON | ||
| 129 | #define S5P_PA_TIMER S5PV310_PA_TIMER | ||
| 130 | |||
| 131 | /* UART */ | ||
| 132 | |||
| 133 | #define S3C_PA_UART S5PV310_PA_UART | ||
| 134 | |||
| 135 | #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) | ||
| 136 | #define S5P_PA_UART0 S5P_PA_UART(0) | ||
| 137 | #define S5P_PA_UART1 S5P_PA_UART(1) | ||
| 138 | #define S5P_PA_UART2 S5P_PA_UART(2) | ||
| 139 | #define S5P_PA_UART3 S5P_PA_UART(3) | ||
| 140 | #define S5P_PA_UART4 S5P_PA_UART(4) | ||
| 141 | |||
| 142 | #define S5P_SZ_UART SZ_256 | ||
| 146 | 143 | ||
| 147 | #endif /* __ASM_ARCH_MAP_H */ | 144 | #endif /* __ASM_ARCH_MAP_H */ |
