diff options
author | Roger Quadros <rogerq@ti.com> | 2014-07-05 19:44:58 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2014-07-22 16:35:05 -0400 |
commit | df0d0f11ff00db0b880e632549619a1b86b190d2 (patch) | |
tree | ea553caf9aee2a080867792368fd793a5d5209fe | |
parent | 509efaf3d1819cf2bed1be1396aa24e56c9db303 (diff) |
ARM: DRA7: hwmod: Add OCP2SCP3 module
This module is needed for the SATA and PCIe PHYs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 20b4398cec05..c9daee46d980 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c | |||
@@ -1215,6 +1215,21 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { | |||
1215 | }, | 1215 | }, |
1216 | }; | 1216 | }; |
1217 | 1217 | ||
1218 | /* ocp2scp3 */ | ||
1219 | static struct omap_hwmod dra7xx_ocp2scp3_hwmod = { | ||
1220 | .name = "ocp2scp3", | ||
1221 | .class = &dra7xx_ocp2scp_hwmod_class, | ||
1222 | .clkdm_name = "l3init_clkdm", | ||
1223 | .main_clk = "l4_root_clk_div", | ||
1224 | .prcm = { | ||
1225 | .omap4 = { | ||
1226 | .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET, | ||
1227 | .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET, | ||
1228 | .modulemode = MODULEMODE_HWCTRL, | ||
1229 | }, | ||
1230 | }, | ||
1231 | }; | ||
1232 | |||
1218 | /* | 1233 | /* |
1219 | * 'qspi' class | 1234 | * 'qspi' class |
1220 | * | 1235 | * |
@@ -2326,6 +2341,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { | |||
2326 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 2341 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
2327 | }; | 2342 | }; |
2328 | 2343 | ||
2344 | /* l4_cfg -> ocp2scp3 */ | ||
2345 | static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = { | ||
2346 | .master = &dra7xx_l4_cfg_hwmod, | ||
2347 | .slave = &dra7xx_ocp2scp3_hwmod, | ||
2348 | .clk = "l4_root_clk_div", | ||
2349 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
2350 | }; | ||
2351 | |||
2329 | static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { | 2352 | static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { |
2330 | { | 2353 | { |
2331 | .pa_start = 0x4b300000, | 2354 | .pa_start = 0x4b300000, |
@@ -2672,6 +2695,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { | |||
2672 | &dra7xx_l4_per1__mmc4, | 2695 | &dra7xx_l4_per1__mmc4, |
2673 | &dra7xx_l4_cfg__mpu, | 2696 | &dra7xx_l4_cfg__mpu, |
2674 | &dra7xx_l4_cfg__ocp2scp1, | 2697 | &dra7xx_l4_cfg__ocp2scp1, |
2698 | &dra7xx_l4_cfg__ocp2scp3, | ||
2675 | &dra7xx_l3_main_1__qspi, | 2699 | &dra7xx_l3_main_1__qspi, |
2676 | &dra7xx_l4_cfg__sata, | 2700 | &dra7xx_l4_cfg__sata, |
2677 | &dra7xx_l4_cfg__smartreflex_core, | 2701 | &dra7xx_l4_cfg__smartreflex_core, |