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authorOlof Johansson <olof@lixom.net>2014-05-22 01:45:52 -0400
committerOlof Johansson <olof@lixom.net>2014-05-22 01:45:52 -0400
commitdee1c20c2a16bb73f1efaed5a535fcc64fdeb72d (patch)
tree74d0ea42599d7a08a7045b9d39c3ffb7a4e01d0f
parent89f6dfacebccf1666253ad1487585e6b234b9531 (diff)
parentb5839bd87f197e133a0025c36df286eab6e1d858 (diff)
Merge tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Samsung DT updates for v3.16 - exynos4 : add missing pinctrls - exynos4412-trats2 : update camera nodes and add rear camera nodes : rename alias for i2c_ak8975 label Update camera nodes for exynos4 and exynos4412-trats2 - exynos5250 : update DWC3 usb controller and enable to use generic USB DRD phy - exynos5250-snow : enable dp-controller, fimd, hdmi and pwm backlight : add sound node and Vbus regulator for USB 3.0 : add tps65090 power regulator : add pinctrl for EC irq and i2c-arbitrator - exynos5420 : change to correct compatible string for hdmi : add PD entry to MFC codec and enable DWC3 and USB 3.0 PHY : add MFC memory banks for smdk5420 and arndale-octa boards - exynos5420-peach-pit : add support exynos5420 based peach-pit board : add sound node and Vbus regulatro for USB 3.0 : enable dp-controller, fimd - exynos5420-smdk5420 : add Vbus regulatro for USB 3.0 - use generic DT bindings for map SYSRAM [olof: Fixed up conflict with a fix for 4212 secondary CPU startup, carrying over the fix to the reworked code] * tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (32 commits) ARM: dts: Add MFC memory banks to exynos5420 boards ARM: dts: enable dp-controller for exynos5420-peach-pit board ARM: dts: enable fimd for exynos5420 based peach-pit board ARM: dts: enable dp-controller for exynos5250-snow board ARM: dts: enable fimd for exynos5250-snow board ARM: dts: enable pwm backlight for exynos5250-snow ARM: dts: Add pwmX_out pinctrl nodes to exynos5250 ARM: dts: Add Vbus regulator for USB 3.0 on exynos5420-smdk5420 ARM: dts: Add Vbus regulator for USB 3.0 on exynos5420-peach-pit ARM: dts: Add Vbus regulator for USB 3.0 on exynos5250-snow ARM: dts: Add PD entry to MFC codec on exynos5420 ARM: dts: Add sound node for exynos5420-peach-pit board ARM: dts: Add sound node for exynos5250-snow board ARM: dts: Update DWC3 usb controller to use new phy driver for exynos5250 ARM: dts: Enable support for generic USB DRD phy for exynos5250 ARM: dts: Enable support for DWC3 controller for exynos5420 ARM: dts: Enable support for USB 3.0 PHY controller for exynos5420 ARM: dts: enable hdmi for exynos5420-peach-pit board ARM: dts: change to correct compatible string for exynos5420 hdmi ARM: dts: enable hdmi for exynos5250 based snow board ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/exynos/smp-sysram.txt38
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi18
-rw-r--r--arch/arm/boot/dts/exynos4210-universal_c210.dts15
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi18
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts79
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi18
-rw-r--r--arch/arm/boot/dts/exynos5250-cros-common.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos5250-pinctrl.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts224
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi38
-rw-r--r--arch/arm/boot/dts/exynos5420-arndale-octa.dts5
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts287
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts51
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi106
-rw-r--r--arch/arm/mach-exynos/common.h1
-rw-r--r--arch/arm/mach-exynos/exynos.c64
-rw-r--r--arch/arm/mach-exynos/firmware.c8
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h7
-rw-r--r--arch/arm/mach-exynos/platsmp.c56
22 files changed, 984 insertions, 113 deletions
diff --git a/Documentation/devicetree/bindings/arm/exynos/smp-sysram.txt b/Documentation/devicetree/bindings/arm/exynos/smp-sysram.txt
new file mode 100644
index 000000000000..4a0a4f70a0ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/exynos/smp-sysram.txt
@@ -0,0 +1,38 @@
1Samsung Exynos SYSRAM for SMP bringup:
2------------------------------------
3
4Samsung SMP-capable Exynos SoCs use part of the SYSRAM for the bringup
5of the secondary cores. Once the core gets powered up it executes the
6code that is residing at some specific location of the SYSRAM.
7
8Therefore reserved section sub-nodes have to be added to the mmio-sram
9declaration. These nodes are of two types depending upon secure or
10non-secure execution environment.
11
12Required sub-node properties:
13- compatible : depending upon boot mode, should be
14 "samsung,exynos4210-sysram" : for Secure SYSRAM
15 "samsung,exynos4210-sysram-ns" : for Non-secure SYSRAM
16
17The rest of the properties should follow the generic mmio-sram discription
18found in ../../misc/sysram.txt
19
20Example:
21
22 sysram@02020000 {
23 compatible = "mmio-sram";
24 reg = <0x02020000 0x54000>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges = <0 0x02020000 0x54000>;
28
29 smp-sysram@0 {
30 compatible = "samsung,exynos4210-sysram";
31 reg = <0x0 0x1000>;
32 };
33
34 smp-sysram@53000 {
35 compatible = "samsung,exynos4210-sysram-ns";
36 reg = <0x53000 0x1000>;
37 };
38 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index db3c5414223e..8f417c20013f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -844,6 +844,7 @@ config ARCH_EXYNOS
844 select HAVE_S3C_RTC if RTC_CLASS 844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_MEMORY_H 845 select NEED_MACH_MEMORY_H
846 select SPARSE_IRQ 846 select SPARSE_IRQ
847 select SRAM
847 select USE_OF 848 select USE_OF
848 help 849 help
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5) 850 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ff58faa97ff0..d6a9e728e592 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
73 exynos5250-smdk5250.dtb \ 73 exynos5250-smdk5250.dtb \
74 exynos5250-snow.dtb \ 74 exynos5250-snow.dtb \
75 exynos5420-arndale-octa.dtb \ 75 exynos5420-arndale-octa.dtb \
76 exynos5420-peach-pit.dtb \
76 exynos5420-smdk5420.dtb \ 77 exynos5420-smdk5420.dtb \
77 exynos5440-sd5v1.dtb \ 78 exynos5440-sd5v1.dtb \
78 exynos5440-ssdk5440.dtb 79 exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 2f8bcd068d17..58ff8e28c74f 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -129,12 +129,10 @@
129 status = "disabled"; 129 status = "disabled";
130 #address-cells = <1>; 130 #address-cells = <1>;
131 #size-cells = <1>; 131 #size-cells = <1>;
132 #clock-cells = <1>;
133 clock-output-names = "cam_a_clkout", "cam_b_clkout";
132 ranges; 134 ranges;
133 135
134 clock_cam: clock-controller {
135 #clock-cells = <1>;
136 };
137
138 fimc_0: fimc@11800000 { 136 fimc_0: fimc@11800000 {
139 compatible = "samsung,exynos4210-fimc"; 137 compatible = "samsung,exynos4210-fimc";
140 reg = <0x11800000 0x1000>; 138 reg = <0x11800000 0x1000>;
@@ -371,6 +369,8 @@
371 interrupts = <0 60 0>; 369 interrupts = <0 60 0>;
372 clocks = <&clock CLK_I2C2>; 370 clocks = <&clock CLK_I2C2>;
373 clock-names = "i2c"; 371 clock-names = "i2c";
372 pinctrl-names = "default";
373 pinctrl-0 = <&i2c2_bus>;
374 status = "disabled"; 374 status = "disabled";
375 }; 375 };
376 376
@@ -382,6 +382,8 @@
382 interrupts = <0 61 0>; 382 interrupts = <0 61 0>;
383 clocks = <&clock CLK_I2C3>; 383 clocks = <&clock CLK_I2C3>;
384 clock-names = "i2c"; 384 clock-names = "i2c";
385 pinctrl-names = "default";
386 pinctrl-0 = <&i2c3_bus>;
385 status = "disabled"; 387 status = "disabled";
386 }; 388 };
387 389
@@ -393,6 +395,8 @@
393 interrupts = <0 62 0>; 395 interrupts = <0 62 0>;
394 clocks = <&clock CLK_I2C4>; 396 clocks = <&clock CLK_I2C4>;
395 clock-names = "i2c"; 397 clock-names = "i2c";
398 pinctrl-names = "default";
399 pinctrl-0 = <&i2c4_bus>;
396 status = "disabled"; 400 status = "disabled";
397 }; 401 };
398 402
@@ -404,6 +408,8 @@
404 interrupts = <0 63 0>; 408 interrupts = <0 63 0>;
405 clocks = <&clock CLK_I2C5>; 409 clocks = <&clock CLK_I2C5>;
406 clock-names = "i2c"; 410 clock-names = "i2c";
411 pinctrl-names = "default";
412 pinctrl-0 = <&i2c5_bus>;
407 status = "disabled"; 413 status = "disabled";
408 }; 414 };
409 415
@@ -415,6 +421,8 @@
415 interrupts = <0 64 0>; 421 interrupts = <0 64 0>;
416 clocks = <&clock CLK_I2C6>; 422 clocks = <&clock CLK_I2C6>;
417 clock-names = "i2c"; 423 clock-names = "i2c";
424 pinctrl-names = "default";
425 pinctrl-0 = <&i2c6_bus>;
418 status = "disabled"; 426 status = "disabled";
419 }; 427 };
420 428
@@ -426,6 +434,8 @@
426 interrupts = <0 65 0>; 434 interrupts = <0 65 0>;
427 clocks = <&clock CLK_I2C7>; 435 clocks = <&clock CLK_I2C7>;
428 clock-names = "i2c"; 436 clock-names = "i2c";
437 pinctrl-names = "default";
438 pinctrl-0 = <&i2c7_bus>;
429 status = "disabled"; 439 status = "disabled";
430 }; 440 };
431 441
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 63e34b24b04f..9296dee10e26 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,21 @@
28 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; 28 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
29 }; 29 };
30 30
31 sysram@02020000 {
32 smp-sysram@0 {
33 status = "disabled";
34 };
35
36 smp-sysram@5000 {
37 compatible = "samsung,exynos4210-sysram";
38 reg = <0x5000 0x1000>;
39 };
40
41 smp-sysram@1f000 {
42 status = "disabled";
43 };
44 };
45
31 mct@10050000 { 46 mct@10050000 {
32 compatible = "none"; 47 compatible = "none";
33 }; 48 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index cacf6140dd2f..ee3001f38821 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,24 @@
31 pinctrl2 = &pinctrl_2; 31 pinctrl2 = &pinctrl_2;
32 }; 32 };
33 33
34 sysram@02020000 {
35 compatible = "mmio-sram";
36 reg = <0x02020000 0x20000>;
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges = <0 0x02020000 0x20000>;
40
41 smp-sysram@0 {
42 compatible = "samsung,exynos4210-sysram";
43 reg = <0x0 0x1000>;
44 };
45
46 smp-sysram@1f000 {
47 compatible = "samsung,exynos4210-sysram-ns";
48 reg = <0x1f000 0x1000>;
49 };
50 };
51
34 pd_lcd1: lcd1-power-domain@10023CA0 { 52 pd_lcd1: lcd1-power-domain@10023CA0 {
35 compatible = "samsung,exynos4210-pd"; 53 compatible = "samsung,exynos4210-pd";
36 reg = <0x10023CA0 0x20>; 54 reg = <0x10023CA0 0x20>;
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 9583563dd0ef..f621fd976815 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -20,7 +20,7 @@
20 compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4"; 20 compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
21 21
22 aliases { 22 aliases {
23 i2c8 = &i2c_ak8975; 23 i2c9 = &i2c_ak8975;
24 }; 24 };
25 25
26 memory { 26 memory {
@@ -80,7 +80,24 @@
80 enable-active-high; 80 enable-active-high;
81 }; 81 };
82 82
83 /* More to come */ 83 cam_af_reg: voltage-regulator-3 {
84 compatible = "regulator-fixed";
85 regulator-name = "CAM_AF";
86 regulator-min-microvolt = <2800000>;
87 regulator-max-microvolt = <2800000>;
88 gpio = <&gpm0 4 0>;
89 enable-active-high;
90 };
91
92 cam_isp_core_reg: voltage-regulator-4 {
93 compatible = "regulator-fixed";
94 regulator-name = "CAM_ISP_CORE_1.2V_EN";
95 regulator-min-microvolt = <1200000>;
96 regulator-max-microvolt = <1200000>;
97 gpio = <&gpm0 3 0>;
98 enable-active-high;
99 regulator-always-on;
100 };
84 }; 101 };
85 102
86 gpio-keys { 103 gpio-keys {
@@ -140,6 +157,38 @@
140 }; 157 };
141 }; 158 };
142 159
160 i2c_0: i2c@13860000 {
161 samsung,i2c-sda-delay = <100>;
162 samsung,i2c-slave-addr = <0x10>;
163 samsung,i2c-max-bus-freq = <400000>;
164 pinctrl-0 = <&i2c0_bus>;
165 pinctrl-names = "default";
166 status = "okay";
167
168 s5c73m3@3c {
169 compatible = "samsung,s5c73m3";
170 reg = <0x3c>;
171 standby-gpios = <&gpm0 1 1>; /* ISP_STANDBY */
172 xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */
173 vdd-int-supply = <&buck9_reg>;
174 vddio-cis-supply = <&ldo9_reg>;
175 vdda-supply = <&ldo17_reg>;
176 vddio-host-supply = <&ldo18_reg>;
177 vdd-af-supply = <&cam_af_reg>;
178 vdd-reg-supply = <&cam_io_reg>;
179 clock-frequency = <24000000>;
180 /* CAM_A_CLKOUT */
181 clocks = <&camera 0>;
182 clock-names = "cis_extclk";
183 port {
184 s5c73m3_ep: endpoint {
185 remote-endpoint = <&csis0_ep>;
186 data-lanes = <1 2 3 4>;
187 };
188 };
189 };
190 };
191
143 i2c@138D0000 { 192 i2c@138D0000 {
144 samsung,i2c-sda-delay = <100>; 193 samsung,i2c-sda-delay = <100>;
145 samsung,i2c-slave-addr = <0x10>; 194 samsung,i2c-slave-addr = <0x10>;
@@ -586,8 +635,8 @@
586 status = "okay"; 635 status = "okay";
587 }; 636 };
588 637
589 camera { 638 camera: camera {
590 pinctrl-0 = <&cam_port_b_clk_active>; 639 pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
591 pinctrl-names = "default"; 640 pinctrl-names = "default";
592 status = "okay"; 641 status = "okay";
593 642
@@ -607,6 +656,23 @@
607 status = "okay"; 656 status = "okay";
608 }; 657 };
609 658
659 csis_0: csis@11880000 {
660 status = "okay";
661 vddcore-supply = <&ldo8_reg>;
662 vddio-supply = <&ldo10_reg>;
663 clock-frequency = <176000000>;
664
665 /* Camera C (3) MIPI CSI-2 (CSIS0) */
666 port@3 {
667 reg = <3>;
668 csis0_ep: endpoint {
669 remote-endpoint = <&s5c73m3_ep>;
670 data-lanes = <1 2 3 4>;
671 samsung,csis-hs-settle = <12>;
672 };
673 };
674 };
675
610 csis_1: csis@11890000 { 676 csis_1: csis@11890000 {
611 vddcore-supply = <&ldo8_reg>; 677 vddcore-supply = <&ldo8_reg>;
612 vddio-supply = <&ldo10_reg>; 678 vddio-supply = <&ldo10_reg>;
@@ -647,10 +713,11 @@
647 reg = <0x10>; 713 reg = <0x10>;
648 svdda-supply = <&cam_io_reg>; 714 svdda-supply = <&cam_io_reg>;
649 svddio-supply = <&ldo19_reg>; 715 svddio-supply = <&ldo19_reg>;
716 afvdd-supply = <&ldo19_reg>;
650 clock-frequency = <24000000>; 717 clock-frequency = <24000000>;
651 /* CAM_B_CLKOUT */ 718 /* CAM_B_CLKOUT */
652 clocks = <&clock_cam 1>; 719 clocks = <&camera 1>;
653 clock-names = "mclk"; 720 clock-names = "extclk";
654 samsung,camclk-out = <1>; 721 samsung,camclk-out = <1>;
655 gpios = <&gpm1 6 0>; 722 gpios = <&gpm1 6 0>;
656 723
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c4a9306f8529..70e3765b51ee 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -37,6 +37,24 @@
37 interrupts = <2 2>, <3 2>, <18 2>, <19 2>; 37 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
38 }; 38 };
39 39
40 sysram@02020000 {
41 compatible = "mmio-sram";
42 reg = <0x02020000 0x40000>;
43 #address-cells = <1>;
44 #size-cells = <1>;
45 ranges = <0 0x02020000 0x40000>;
46
47 smp-sysram@0 {
48 compatible = "samsung,exynos4210-sysram";
49 reg = <0x0 0x1000>;
50 };
51
52 smp-sysram@2f000 {
53 compatible = "samsung,exynos4210-sysram-ns";
54 reg = <0x2f000 0x1000>;
55 };
56 };
57
40 pd_isp: isp-power-domain@10023CA0 { 58 pd_isp: isp-power-domain@10023CA0 {
41 compatible = "samsung,exynos4210-pd"; 59 compatible = "samsung,exynos4210-pd";
42 reg = <0x10023CA0 0x20>; 60 reg = <0x10023CA0 0x20>;
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 2c1560d52f1a..89ac90f59e2e 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -240,7 +240,7 @@
240 samsung,i2c-sda-delay = <100>; 240 samsung,i2c-sda-delay = <100>;
241 samsung,i2c-max-bus-freq = <378000>; 241 samsung,i2c-max-bus-freq = <378000>;
242 242
243 hdmiphy@38 { 243 hdmiphy: hdmiphy@38 {
244 compatible = "samsung,exynos4212-hdmiphy"; 244 compatible = "samsung,exynos4212-hdmiphy";
245 reg = <0x38>; 245 reg = <0x38>;
246 }; 246 };
@@ -304,6 +304,10 @@
304 304
305 hdmi { 305 hdmi {
306 hpd-gpio = <&gpx3 7 0>; 306 hpd-gpio = <&gpx3 7 0>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&hdmi_hpd_irq>;
309 phy = <&hdmiphy>;
310 ddc = <&i2c_2>;
307 }; 311 };
308 312
309 gpio-keys { 313 gpio-keys {
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 9a49e6804ae1..886cfca044ac 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -351,6 +351,34 @@
351 samsung,pin-drv = <0>; 351 samsung,pin-drv = <0>;
352 }; 352 };
353 353
354 pwm0_out: pwm0-out {
355 samsung,pins = "gpb2-0";
356 samsung,pin-function = <2>;
357 samsung,pin-pud = <0>;
358 samsung,pin-drv = <0>;
359 };
360
361 pwm1_out: pwm1-out {
362 samsung,pins = "gpb2-1";
363 samsung,pin-function = <2>;
364 samsung,pin-pud = <0>;
365 samsung,pin-drv = <0>;
366 };
367
368 pwm2_out: pwm2-out {
369 samsung,pins = "gpb2-2";
370 samsung,pin-function = <2>;
371 samsung,pin-pud = <0>;
372 samsung,pin-drv = <0>;
373 };
374
375 pwm3_out: pwm3-out {
376 samsung,pins = "gpb2-3";
377 samsung,pin-function = <2>;
378 samsung,pin-pud = <0>;
379 samsung,pin-drv = <0>;
380 };
381
354 i2c7_bus: i2c7-bus { 382 i2c7_bus: i2c7-bus {
355 samsung,pins = "gpb2-2", "gpb2-3"; 383 samsung,pins = "gpb2-2", "gpb2-3";
356 samsung,pin-function = <3>; 384 samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 1ce1088a00fb..079fdf9e3f18 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -25,6 +25,13 @@
25 }; 25 };
26 26
27 pinctrl@11400000 { 27 pinctrl@11400000 {
28 ec_irq: ec-irq {
29 samsung,pins = "gpx1-6";
30 samsung,pin-function = <0>;
31 samsung,pin-pud = <0>;
32 samsung,pin-drv = <0>;
33 };
34
28 sd3_clk: sd3-clk { 35 sd3_clk: sd3-clk {
29 samsung,pin-drv = <0>; 36 samsung,pin-drv = <0>;
30 }; 37 };
@@ -37,6 +44,50 @@
37 sd3_bus4: sd3-bus-width4 { 44 sd3_bus4: sd3-bus-width4 {
38 samsung,pin-drv = <0>; 45 samsung,pin-drv = <0>;
39 }; 46 };
47
48 max98095_en: max98095-en {
49 samsung,pins = "gpx1-7";
50 samsung,pin-function = <0>;
51 samsung,pin-pud = <3>;
52 samsung,pin-drv = <0>;
53 };
54
55 tps65090_irq: tps65090-irq {
56 samsung,pins = "gpx2-6";
57 samsung,pin-function = <0>;
58 samsung,pin-pud = <0>;
59 samsung,pin-drv = <0>;
60 };
61
62 usb3_vbus_en: usb3-vbus-en {
63 samsung,pins = "gpx2-7";
64 samsung,pin-function = <1>;
65 samsung,pin-pud = <0>;
66 samsung,pin-drv = <0>;
67 };
68
69 hdmi_hpd_irq: hdmi-hpd-irq {
70 samsung,pins = "gpx3-7";
71 samsung,pin-function = <0>;
72 samsung,pin-pud = <1>;
73 samsung,pin-drv = <0>;
74 };
75 };
76
77 pinctrl@13400000 {
78 arb_their_claim: arb-their-claim {
79 samsung,pins = "gpe0-4";
80 samsung,pin-function = <0>;
81 samsung,pin-pud = <3>;
82 samsung,pin-drv = <0>;
83 };
84
85 arb_our_claim: arb-our-claim {
86 samsung,pins = "gpf0-3";
87 samsung,pin-function = <1>;
88 samsung,pin-pud = <0>;
89 samsung,pin-drv = <0>;
90 };
40 }; 91 };
41 92
42 gpio-keys { 93 gpio-keys {
@@ -52,6 +103,12 @@
52 }; 103 };
53 }; 104 };
54 105
106 vbat: vbat-fixed-regulator {
107 compatible = "regulator-fixed";
108 regulator-name = "vbat-supply";
109 regulator-boot-on;
110 };
111
55 i2c-arbitrator { 112 i2c-arbitrator {
56 compatible = "i2c-arb-gpio-challenge"; 113 compatible = "i2c-arb-gpio-challenge";
57 #address-cells = <1>; 114 #address-cells = <1>;
@@ -65,6 +122,9 @@
65 wait-retry-us = <3000>; 122 wait-retry-us = <3000>;
66 wait-free-us = <50000>; 123 wait-free-us = <50000>;
67 124
125 pinctrl-names = "default";
126 pinctrl-0 = <&arb_our_claim &arb_their_claim>;
127
68 /* Use ID 104 as a hint that we're on physical bus 4 */ 128 /* Use ID 104 as a hint that we're on physical bus 4 */
69 i2c_104: i2c@0 { 129 i2c_104: i2c@0 {
70 reg = <0>; 130 reg = <0>;
@@ -82,6 +142,8 @@
82 reg = <0x1e>; 142 reg = <0x1e>;
83 interrupts = <6 0>; 143 interrupts = <6 0>;
84 interrupt-parent = <&gpx1>; 144 interrupt-parent = <&gpx1>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&ec_irq>;
85 wakeup-source; 147 wakeup-source;
86 148
87 keyboard-controller { 149 keyboard-controller {
@@ -173,6 +235,83 @@
173 0x070c0069>; /* LEFT */ 235 0x070c0069>; /* LEFT */
174 }; 236 };
175 }; 237 };
238
239 power-regulator {
240 compatible = "ti,tps65090";
241 reg = <0x48>;
242
243 /*
244 * Config irq to disable internal pulls
245 * even though we run in polling mode.
246 */
247 pinctrl-names = "default";
248 pinctrl-0 = <&tps65090_irq>;
249
250 vsys1-supply = <&vbat>;
251 vsys2-supply = <&vbat>;
252 vsys3-supply = <&vbat>;
253 infet1-supply = <&vbat>;
254 infet2-supply = <&vbat>;
255 infet3-supply = <&vbat>;
256 infet4-supply = <&vbat>;
257 infet5-supply = <&vbat>;
258 infet6-supply = <&vbat>;
259 infet7-supply = <&vbat>;
260 vsys-l1-supply = <&vbat>;
261 vsys-l2-supply = <&vbat>;
262
263 regulators {
264 dcdc1 {
265 ti,enable-ext-control;
266 };
267 dcdc2 {
268 ti,enable-ext-control;
269 };
270 dcdc3 {
271 ti,enable-ext-control;
272 };
273 fet1 {
274 regulator-name = "vcd_led";
275 ti,overcurrent-wait = <3>;
276 };
277 tps65090_fet2: fet2 {
278 regulator-name = "video_mid";
279 regulator-always-on;
280 ti,overcurrent-wait = <3>;
281 };
282 fet3 {
283 regulator-name = "wwan_r";
284 regulator-always-on;
285 ti,overcurrent-wait = <3>;
286 };
287 fet4 {
288 regulator-name = "sdcard";
289 ti,overcurrent-wait = <3>;
290 };
291 fet5 {
292 regulator-name = "camout";
293 regulator-always-on;
294 ti,overcurrent-wait = <3>;
295 };
296 fet6 {
297 regulator-name = "lcd_vdd";
298 ti,overcurrent-wait = <3>;
299 };
300 tps65090_fet7: fet7 {
301 regulator-name = "video_mid_1a";
302 regulator-always-on;
303 ti,overcurrent-wait = <3>;
304 };
305 ldo1 {
306 };
307 ldo2 {
308 };
309 };
310
311 charger {
312 compatible = "ti,tps65090-charger";
313 };
314 };
176 }; 315 };
177 }; 316 };
178 317
@@ -196,6 +335,41 @@
196 }; 335 };
197 }; 336 };
198 337
338 i2c@12CD0000 {
339 max98095: codec@11 {
340 compatible = "maxim,max98095";
341 reg = <0x11>;
342 pinctrl-0 = <&max98095_en>;
343 pinctrl-names = "default";
344 };
345 };
346
347 i2s0: i2s@03830000 {
348 status = "okay";
349 };
350
351 sound {
352 compatible = "google,snow-audio-max98095";
353
354 samsung,i2s-controller = <&i2s0>;
355 samsung,audio-codec = <&max98095>;
356 };
357
358 usb3_vbus_reg: regulator-usb3 {
359 compatible = "regulator-fixed";
360 regulator-name = "P5.0V_USB3CON";
361 regulator-min-microvolt = <5000000>;
362 regulator-max-microvolt = <5000000>;
363 gpio = <&gpx2 7 0>;
364 pinctrl-names = "default";
365 pinctrl-0 = <&usb3_vbus_en>;
366 enable-active-high;
367 };
368
369 phy@12100000 {
370 vbus-supply = <&usb3_vbus_reg>;
371 };
372
199 usb@12110000 { 373 usb@12110000 {
200 samsung,vbus-gpio = <&gpx1 1 0>; 374 samsung,vbus-gpio = <&gpx1 1 0>;
201 }; 375 };
@@ -206,4 +380,54 @@
206 clock-frequency = <24000000>; 380 clock-frequency = <24000000>;
207 }; 381 };
208 }; 382 };
383
384 hdmi {
385 hdmi-en-supply = <&tps65090_fet7>;
386 vdd-supply = <&ldo8_reg>;
387 vdd_osc-supply = <&ldo10_reg>;
388 vdd_pll-supply = <&ldo8_reg>;
389 };
390
391 backlight {
392 compatible = "pwm-backlight";
393 pwms = <&pwm 0 1000000 0>;
394 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
395 default-brightness-level = <7>;
396 pinctrl-0 = <&pwm0_out>;
397 pinctrl-names = "default";
398 };
399
400 fimd@14400000 {
401 status = "okay";
402 samsung,invert-vclk;
403 };
404
405 dp-controller@145B0000 {
406 status = "okay";
407 pinctrl-names = "default";
408 pinctrl-0 = <&dp_hpd>;
409 samsung,color-space = <0>;
410 samsung,dynamic-range = <0>;
411 samsung,ycbcr-coeff = <0>;
412 samsung,color-depth = <1>;
413 samsung,link-rate = <0x0a>;
414 samsung,lane-count = <2>;
415 samsung,hpd-gpio = <&gpx0 7 0>;
416
417 display-timings {
418 native-mode = <&timing1>;
419
420 timing1: timing@1 {
421 clock-frequency = <70589280>;
422 hactive = <1366>;
423 vactive = <768>;
424 hfront-porch = <40>;
425 hback-porch = <40>;
426 hsync-len = <32>;
427 vback-porch = <10>;
428 vfront-porch = <12>;
429 vsync-len = <6>;
430 };
431 };
432 };
209}; 433};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 37423314a028..68a3e6f254d9 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,24 @@
72 }; 72 };
73 }; 73 };
74 74
75 sysram@02020000 {
76 compatible = "mmio-sram";
77 reg = <0x02020000 0x30000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x02020000 0x30000>;
81
82 smp-sysram@0 {
83 compatible = "samsung,exynos4210-sysram";
84 reg = <0x0 0x1000>;
85 };
86
87 smp-sysram@2f000 {
88 compatible = "samsung,exynos4210-sysram-ns";
89 reg = <0x2f000 0x1000>;
90 };
91 };
92
75 pd_gsc: gsc-power-domain@10044000 { 93 pd_gsc: gsc-power-domain@10044000 {
76 compatible = "samsung,exynos4210-pd"; 94 compatible = "samsung,exynos4210-pd";
77 reg = <0x10044000 0x20>; 95 reg = <0x10044000 0x20>;
@@ -533,22 +551,18 @@
533 compatible = "synopsys,dwc3"; 551 compatible = "synopsys,dwc3";
534 reg = <0x12000000 0x10000>; 552 reg = <0x12000000 0x10000>;
535 interrupts = <0 72 0>; 553 interrupts = <0 72 0>;
536 usb-phy = <&usb2_phy &usb3_phy>; 554 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
555 phy-names = "usb2-phy", "usb3-phy";
537 }; 556 };
538 }; 557 };
539 558
540 usb3_phy: usbphy@12100000 { 559 usbdrd_phy: phy@12100000 {
541 compatible = "samsung,exynos5250-usb3phy"; 560 compatible = "samsung,exynos5250-usbdrd-phy";
542 reg = <0x12100000 0x100>; 561 reg = <0x12100000 0x100>;
543 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>; 562 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
544 clock-names = "ext_xtal", "usbdrd30"; 563 clock-names = "phy", "ref";
545 #address-cells = <1>; 564 samsung,pmu-syscon = <&pmu_system_controller>;
546 #size-cells = <1>; 565 #phy-cells = <1>;
547 ranges;
548
549 usbphy-sys {
550 reg = <0x10040704 0x8>;
551 };
552 }; 566 };
553 567
554 usb@12110000 { 568 usb@12110000 {
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 896a2a6619e0..6ee8149fd5c4 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -37,6 +37,11 @@
37 status = "okay"; 37 status = "okay";
38 }; 38 };
39 39
40 codec@11000000 {
41 samsung,mfc-r = <0x43000000 0x800000>;
42 samsung,mfc-l = <0x51000000 0x800000>;
43 };
44
40 mmc@12200000 { 45 mmc@12200000 {
41 status = "okay"; 46 status = "okay";
42 broken-cd; 47 broken-cd;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
new file mode 100644
index 000000000000..d4127b0ba83f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -0,0 +1,287 @@
1/*
2 * Google Peach Pit Rev 6+ board device tree source
3 *
4 * Copyright (c) 2014 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12#include <dt-bindings/input/input.h>
13#include <dt-bindings/gpio/gpio.h>
14#include "exynos5420.dtsi"
15
16/ {
17 model = "Google Peach Pit Rev 6+";
18
19 compatible = "google,pit-rev16",
20 "google,pit-rev15", "google,pit-rev14",
21 "google,pit-rev13", "google,pit-rev12",
22 "google,pit-rev11", "google,pit-rev10",
23 "google,pit-rev9", "google,pit-rev8",
24 "google,pit-rev7", "google,pit-rev6",
25 "google,pit", "google,peach","samsung,exynos5420",
26 "samsung,exynos5";
27
28 memory {
29 reg = <0x20000000 0x80000000>;
30 };
31
32 fixed-rate-clocks {
33 oscclk {
34 compatible = "samsung,exynos5420-oscclk";
35 clock-frequency = <24000000>;
36 };
37 };
38
39 gpio-keys {
40 compatible = "gpio-keys";
41
42 pinctrl-names = "default";
43 pinctrl-0 = <&power_key_irq>;
44
45 power {
46 label = "Power";
47 gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_POWER>;
49 gpio-key,wakeup;
50 };
51 };
52
53 backlight {
54 compatible = "pwm-backlight";
55 pwms = <&pwm 0 1000000 0>;
56 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
57 default-brightness-level = <7>;
58 pinctrl-0 = <&pwm0_out>;
59 pinctrl-names = "default";
60 };
61
62 sound {
63 compatible = "google,snow-audio-max98090";
64
65 samsung,i2s-controller = <&i2s0>;
66 samsung,audio-codec = <&max98090>;
67 };
68
69 usb300_vbus_reg: regulator-usb300 {
70 compatible = "regulator-fixed";
71 regulator-name = "P5.0V_USB3CON0";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 gpio = <&gph0 0 0>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&usb300_vbus_en>;
77 enable-active-high;
78 };
79
80 usb301_vbus_reg: regulator-usb301 {
81 compatible = "regulator-fixed";
82 regulator-name = "P5.0V_USB3CON1";
83 regulator-min-microvolt = <5000000>;
84 regulator-max-microvolt = <5000000>;
85 gpio = <&gph0 1 0>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&usb301_vbus_en>;
88 enable-active-high;
89 };
90};
91
92&pinctrl_0 {
93 max98090_irq: max98090-irq {
94 samsung,pins = "gpx0-2";
95 samsung,pin-function = <0>;
96 samsung,pin-pud = <0>;
97 samsung,pin-drv = <0>;
98 };
99
100 tpm_irq: tpm-irq {
101 samsung,pins = "gpx1-0";
102 samsung,pin-function = <0>;
103 samsung,pin-pud = <0>;
104 samsung,pin-drv = <0>;
105 };
106
107 power_key_irq: power-key-irq {
108 samsung,pins = "gpx1-2";
109 samsung,pin-function = <0>;
110 samsung,pin-pud = <0>;
111 samsung,pin-drv = <0>;
112 };
113
114 hdmi_hpd_irq: hdmi-hpd-irq {
115 samsung,pins = "gpx3-7";
116 samsung,pin-function = <0>;
117 samsung,pin-pud = <1>;
118 samsung,pin-drv = <0>;
119 };
120};
121
122&pinctrl_3 {
123 usb300_vbus_en: usb300-vbus-en {
124 samsung,pins = "gph0-0";
125 samsung,pin-function = <1>;
126 samsung,pin-pud = <0>;
127 samsung,pin-drv = <0>;
128 };
129
130 usb301_vbus_en: usb301-vbus-en {
131 samsung,pins = "gph0-1";
132 samsung,pin-function = <1>;
133 samsung,pin-pud = <0>;
134 samsung,pin-drv = <0>;
135 };
136
137 dp_hpd_gpio: dp_hpd_gpio {
138 samsung,pins = "gpx2-6";
139 samsung,pin-function = <0>;
140 samsung,pin-pud = <3>;
141 samsung,pin-drv = <0>;
142 };
143};
144
145&rtc {
146 status = "okay";
147};
148
149&uart_3 {
150 status = "okay";
151};
152
153&mmc_0 {
154 status = "okay";
155 num-slots = <1>;
156 broken-cd;
157 caps2-mmc-hs200-1_8v;
158 supports-highspeed;
159 non-removable;
160 card-detect-delay = <200>;
161 clock-frequency = <400000000>;
162 samsung,dw-mshc-ciu-div = <3>;
163 samsung,dw-mshc-sdr-timing = <0 4>;
164 samsung,dw-mshc-ddr-timing = <0 2>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
167
168 slot@0 {
169 reg = <0>;
170 bus-width = <8>;
171 };
172};
173
174&mmc_2 {
175 status = "okay";
176 num-slots = <1>;
177 supports-highspeed;
178 card-detect-delay = <200>;
179 clock-frequency = <400000000>;
180 samsung,dw-mshc-ciu-div = <3>;
181 samsung,dw-mshc-sdr-timing = <2 3>;
182 samsung,dw-mshc-ddr-timing = <1 2>;
183 pinctrl-names = "default";
184 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
185
186 slot@0 {
187 reg = <0>;
188 bus-width = <4>;
189 };
190};
191
192&hsi2c_7 {
193 status = "okay";
194
195 max98090: codec@10 {
196 compatible = "maxim,max98090";
197 reg = <0x10>;
198 interrupts = <2 0>;
199 interrupt-parent = <&gpx0>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&max98090_irq>;
202 };
203};
204
205&hsi2c_9 {
206 status = "okay";
207 clock-frequency = <400000>;
208
209 tpm@20 {
210 compatible = "infineon,slb9645tt";
211 reg = <0x20>;
212
213 /* Unused irq; but still need to configure the pins */
214 pinctrl-names = "default";
215 pinctrl-0 = <&tpm_irq>;
216 };
217};
218
219&i2c_2 {
220 status = "okay";
221 samsung,i2c-sda-delay = <100>;
222 samsung,i2c-max-bus-freq = <66000>;
223 samsung,i2c-slave-addr = <0x50>;
224};
225
226&hdmi {
227 status = "okay";
228 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&hdmi_hpd_irq>;
231 ddc = <&i2c_2>;
232};
233
234&usbdrd3_0 {
235 vbus-supply = <&usb300_vbus_reg>;
236};
237
238&usbdrd3_1 {
239 vbus-supply = <&usb301_vbus_reg>;
240};
241
242/*
243 * Use longest HW watchdog in SoC (32 seconds) since the hardware
244 * watchdog provides no debugging information (compared to soft/hard
245 * lockup detectors) and so should be last resort.
246 */
247&watchdog {
248 timeout-sec = <32>;
249};
250
251&i2s0 {
252 status = "okay";
253};
254
255&fimd {
256 status = "okay";
257 samsung,invert-vclk;
258};
259
260&dp {
261 status = "okay";
262 pinctrl-names = "default";
263 pinctrl-0 = <&dp_hpd_gpio>;
264 samsung,color-space = <0>;
265 samsung,dynamic-range = <0>;
266 samsung,ycbcr-coeff = <0>;
267 samsung,color-depth = <1>;
268 samsung,link-rate = <0x06>;
269 samsung,lane-count = <2>;
270 samsung,hpd-gpio = <&gpx2 6 0>;
271
272 display-timings {
273 native-mode = <&timing1>;
274
275 timing1: timing@1 {
276 clock-frequency = <70589280>;
277 hactive = <1366>;
278 vactive = <768>;
279 hfront-porch = <40>;
280 hback-porch = <40>;
281 hsync-len = <32>;
282 vback-porch = <10>;
283 vfront-porch = <12>;
284 vsync-len = <6>;
285 };
286 };
287};
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index e62c8eb57438..ba686e40eac7 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -624,6 +624,34 @@
624 samsung,pin-drv = <0>; 624 samsung,pin-drv = <0>;
625 }; 625 };
626 626
627 pwm0_out: pwm0-out {
628 samsung,pins = "gpb2-0";
629 samsung,pin-function = <2>;
630 samsung,pin-pud = <0>;
631 samsung,pin-drv = <0>;
632 };
633
634 pwm1_out: pwm1-out {
635 samsung,pins = "gpb2-1";
636 samsung,pin-function = <2>;
637 samsung,pin-pud = <0>;
638 samsung,pin-drv = <0>;
639 };
640
641 pwm2_out: pwm2-out {
642 samsung,pins = "gpb2-2";
643 samsung,pin-function = <2>;
644 samsung,pin-pud = <0>;
645 samsung,pin-drv = <0>;
646 };
647
648 pwm3_out: pwm3-out {
649 samsung,pins = "gpb2-3";
650 samsung,pin-function = <2>;
651 samsung,pin-pud = <0>;
652 samsung,pin-drv = <0>;
653 };
654
627 i2c7_hs_bus: i2c7-hs-bus { 655 i2c7_hs_bus: i2c7-hs-bus {
628 samsung,pins = "gpb2-2", "gpb2-3"; 656 samsung,pins = "gpb2-2", "gpb2-3";
629 samsung,pin-function = <3>; 657 samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 69104850eb5e..6052aa9c5659 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -68,6 +68,11 @@
68 status = "okay"; 68 status = "okay";
69 }; 69 };
70 70
71 codec@11000000 {
72 samsung,mfc-r = <0x43000000 0x800000>;
73 samsung,mfc-l = <0x51000000 0x800000>;
74 };
75
71 mmc@12200000 { 76 mmc@12200000 {
72 status = "okay"; 77 status = "okay";
73 broken-cd; 78 broken-cd;
@@ -140,6 +145,22 @@
140 }; 145 };
141 }; 146 };
142 147
148 pinctrl@14000000 {
149 usb300_vbus_en: usb300-vbus-en {
150 samsung,pins = "gpg0-5";
151 samsung,pin-function = <1>;
152 samsung,pin-pud = <0>;
153 samsung,pin-drv = <0>;
154 };
155
156 usb301_vbus_en: usb301-vbus-en {
157 samsung,pins = "gpg1-4";
158 samsung,pin-function = <1>;
159 samsung,pin-pud = <0>;
160 samsung,pin-drv = <0>;
161 };
162 };
163
143 hdmi@14530000 { 164 hdmi@14530000 {
144 status = "okay"; 165 status = "okay";
145 hpd-gpio = <&gpx3 7 0>; 166 hpd-gpio = <&gpx3 7 0>;
@@ -147,6 +168,36 @@
147 pinctrl-0 = <&hdmi_hpd_irq>; 168 pinctrl-0 = <&hdmi_hpd_irq>;
148 }; 169 };
149 170
171 usb300_vbus_reg: regulator-usb300 {
172 compatible = "regulator-fixed";
173 regulator-name = "VBUS0";
174 regulator-min-microvolt = <5000000>;
175 regulator-max-microvolt = <5000000>;
176 gpio = <&gpg0 5 0>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&usb300_vbus_en>;
179 enable-active-high;
180 };
181
182 usb301_vbus_reg: regulator-usb301 {
183 compatible = "regulator-fixed";
184 regulator-name = "VBUS1";
185 regulator-min-microvolt = <5000000>;
186 regulator-max-microvolt = <5000000>;
187 gpio = <&gpg1 4 0>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&usb301_vbus_en>;
190 enable-active-high;
191 };
192
193 phy@12100000 {
194 vbus-supply = <&usb300_vbus_reg>;
195 };
196
197 phy@12500000 {
198 vbus-supply = <&usb301_vbus_reg>;
199 };
200
150 i2c_2: i2c@12C80000 { 201 i2c_2: i2c@12C80000 {
151 samsung,i2c-sda-delay = <100>; 202 samsung,i2c-sda-delay = <100>;
152 samsung,i2c-max-bus-freq = <66000>; 203 samsung,i2c-max-bus-freq = <66000>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 418f2506aaf0..9b6414a9e8a1 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -47,6 +47,8 @@
47 spi0 = &spi_0; 47 spi0 = &spi_0;
48 spi1 = &spi_1; 48 spi1 = &spi_1;
49 spi2 = &spi_2; 49 spi2 = &spi_2;
50 usbdrdphy0 = &usbdrd_phy0;
51 usbdrdphy1 = &usbdrd_phy1;
50 }; 52 };
51 53
52 cpus { 54 cpus {
@@ -110,6 +112,24 @@
110 }; 112 };
111 }; 113 };
112 114
115 sysram@02020000 {
116 compatible = "mmio-sram";
117 reg = <0x02020000 0x54000>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 ranges = <0 0x02020000 0x54000>;
121
122 smp-sysram@0 {
123 compatible = "samsung,exynos4210-sysram";
124 reg = <0x0 0x1000>;
125 };
126
127 smp-sysram@53000 {
128 compatible = "samsung,exynos4210-sysram-ns";
129 reg = <0x53000 0x1000>;
130 };
131 };
132
113 clock: clock-controller@10010000 { 133 clock: clock-controller@10010000 {
114 compatible = "samsung,exynos5420-clock"; 134 compatible = "samsung,exynos5420-clock";
115 reg = <0x10010000 0x30000>; 135 reg = <0x10010000 0x30000>;
@@ -125,12 +145,13 @@
125 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; 145 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
126 }; 146 };
127 147
128 codec@11000000 { 148 mfc: codec@11000000 {
129 compatible = "samsung,mfc-v7"; 149 compatible = "samsung,mfc-v7";
130 reg = <0x11000000 0x10000>; 150 reg = <0x11000000 0x10000>;
131 interrupts = <0 96 0>; 151 interrupts = <0 96 0>;
132 clocks = <&clock CLK_MFC>; 152 clocks = <&clock CLK_MFC>;
133 clock-names = "mfc"; 153 clock-names = "mfc";
154 samsung,power-domain = <&mfc_pd>;
134 }; 155 };
135 156
136 mmc_0: mmc@12200000 { 157 mmc_0: mmc@12200000 {
@@ -169,7 +190,7 @@
169 status = "disabled"; 190 status = "disabled";
170 }; 191 };
171 192
172 mct@101C0000 { 193 mct: mct@101C0000 {
173 compatible = "samsung,exynos4210-mct"; 194 compatible = "samsung,exynos4210-mct";
174 reg = <0x101C0000 0x800>; 195 reg = <0x101C0000 0x800>;
175 interrupt-controller; 196 interrupt-controller;
@@ -260,7 +281,7 @@
260 interrupts = <0 47 0>; 281 interrupts = <0 47 0>;
261 }; 282 };
262 283
263 rtc@101E0000 { 284 rtc: rtc@101E0000 {
264 clocks = <&clock CLK_RTC>; 285 clocks = <&clock CLK_RTC>;
265 clock-names = "rtc"; 286 clock-names = "rtc";
266 status = "disabled"; 287 status = "disabled";
@@ -427,22 +448,22 @@
427 status = "disabled"; 448 status = "disabled";
428 }; 449 };
429 450
430 serial@12C00000 { 451 uart_0: serial@12C00000 {
431 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 452 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
432 clock-names = "uart", "clk_uart_baud0"; 453 clock-names = "uart", "clk_uart_baud0";
433 }; 454 };
434 455
435 serial@12C10000 { 456 uart_1: serial@12C10000 {
436 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 457 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
437 clock-names = "uart", "clk_uart_baud0"; 458 clock-names = "uart", "clk_uart_baud0";
438 }; 459 };
439 460
440 serial@12C20000 { 461 uart_2: serial@12C20000 {
441 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 462 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
442 clock-names = "uart", "clk_uart_baud0"; 463 clock-names = "uart", "clk_uart_baud0";
443 }; 464 };
444 465
445 serial@12C30000 { 466 uart_3: serial@12C30000 {
446 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 467 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
447 clock-names = "uart", "clk_uart_baud0"; 468 clock-names = "uart", "clk_uart_baud0";
448 }; 469 };
@@ -462,14 +483,14 @@
462 #phy-cells = <0>; 483 #phy-cells = <0>;
463 }; 484 };
464 485
465 dp-controller@145B0000 { 486 dp: dp-controller@145B0000 {
466 clocks = <&clock CLK_DP1>; 487 clocks = <&clock CLK_DP1>;
467 clock-names = "dp"; 488 clock-names = "dp";
468 phys = <&dp_phy>; 489 phys = <&dp_phy>;
469 phy-names = "dp"; 490 phy-names = "dp";
470 }; 491 };
471 492
472 fimd@14400000 { 493 fimd: fimd@14400000 {
473 samsung,power-domain = <&disp_pd>; 494 samsung,power-domain = <&disp_pd>;
474 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 495 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
475 clock-names = "sclk_fimd", "fimd"; 496 clock-names = "sclk_fimd", "fimd";
@@ -629,8 +650,8 @@
629 status = "disabled"; 650 status = "disabled";
630 }; 651 };
631 652
632 hdmi@14530000 { 653 hdmi: hdmi@14530000 {
633 compatible = "samsung,exynos4212-hdmi"; 654 compatible = "samsung,exynos5420-hdmi";
634 reg = <0x14530000 0x70000>; 655 reg = <0x14530000 0x70000>;
635 interrupts = <0 95 0>; 656 interrupts = <0 95 0>;
636 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 657 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@@ -638,10 +659,15 @@
638 <&clock CLK_MOUT_HDMI>; 659 <&clock CLK_MOUT_HDMI>;
639 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", 660 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
640 "sclk_hdmiphy", "mout_hdmi"; 661 "sclk_hdmiphy", "mout_hdmi";
662 phy = <&hdmiphy>;
641 status = "disabled"; 663 status = "disabled";
642 }; 664 };
643 665
644 mixer@14450000 { 666 hdmiphy: hdmiphy@145D0000 {
667 reg = <0x145D0000 0x20>;
668 };
669
670 mixer: mixer@14450000 {
645 compatible = "samsung,exynos5420-mixer"; 671 compatible = "samsung,exynos5420-mixer";
646 reg = <0x14450000 0x10000>; 672 reg = <0x14450000 0x10000>;
647 interrupts = <0 94 0>; 673 interrupts = <0 94 0>;
@@ -712,7 +738,7 @@
712 clock-names = "tmu_apbif", "tmu_triminfo_apbif"; 738 clock-names = "tmu_apbif", "tmu_triminfo_apbif";
713 }; 739 };
714 740
715 watchdog@101D0000 { 741 watchdog: watchdog@101D0000 {
716 compatible = "samsung,exynos5420-wdt"; 742 compatible = "samsung,exynos5420-wdt";
717 reg = <0x101D0000 0x100>; 743 reg = <0x101D0000 0x100>;
718 interrupts = <0 42 0>; 744 interrupts = <0 42 0>;
@@ -721,11 +747,63 @@
721 samsung,syscon-phandle = <&pmu_system_controller>; 747 samsung,syscon-phandle = <&pmu_system_controller>;
722 }; 748 };
723 749
724 sss@10830000 { 750 sss: sss@10830000 {
725 compatible = "samsung,exynos4210-secss"; 751 compatible = "samsung,exynos4210-secss";
726 reg = <0x10830000 0x10000>; 752 reg = <0x10830000 0x10000>;
727 interrupts = <0 112 0>; 753 interrupts = <0 112 0>;
728 clocks = <&clock 471>; 754 clocks = <&clock 471>;
729 clock-names = "secss"; 755 clock-names = "secss";
730 }; 756 };
757
758 usbdrd3_0: usb@12000000 {
759 compatible = "samsung,exynos5250-dwusb3";
760 clocks = <&clock CLK_USBD300>;
761 clock-names = "usbdrd30";
762 #address-cells = <1>;
763 #size-cells = <1>;
764 ranges;
765
766 dwc3 {
767 compatible = "snps,dwc3";
768 reg = <0x12000000 0x10000>;
769 interrupts = <0 72 0>;
770 phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
771 phy-names = "usb2-phy", "usb3-phy";
772 };
773 };
774
775 usbdrd_phy0: phy@12100000 {
776 compatible = "samsung,exynos5420-usbdrd-phy";
777 reg = <0x12100000 0x100>;
778 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
779 clock-names = "phy", "ref";
780 samsung,pmu-syscon = <&pmu_system_controller>;
781 #phy-cells = <1>;
782 };
783
784 usbdrd3_1: usb@12400000 {
785 compatible = "samsung,exynos5250-dwusb3";
786 clocks = <&clock CLK_USBD301>;
787 clock-names = "usbdrd30";
788 #address-cells = <1>;
789 #size-cells = <1>;
790 ranges;
791
792 dwc3 {
793 compatible = "snps,dwc3";
794 reg = <0x12400000 0x10000>;
795 interrupts = <0 73 0>;
796 phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
797 phy-names = "usb2-phy", "usb3-phy";
798 };
799 };
800
801 usbdrd_phy1: phy@12500000 {
802 compatible = "samsung,exynos5420-usbdrd-phy";
803 reg = <0x12500000 0x100>;
804 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
805 clock-names = "phy", "ref";
806 samsung,pmu-syscon = <&pmu_system_controller>;
807 #phy-cells = <1>;
808 };
731}; 809};
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83efaff..963c51fb606c 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -18,6 +18,7 @@
18void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); 18void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
19 19
20struct map_desc; 20struct map_desc;
21extern void __iomem *sysram_ns_base_addr;
21void exynos_init_io(void); 22void exynos_init_io(void);
22void exynos_restart(enum reboot_mode mode, const char *cmd); 23void exynos_restart(enum reboot_mode mode, const char *cmd);
23void exynos_cpuidle_init(void); 24void exynos_cpuidle_init(void);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907d021d..e973ff5de7b3 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -114,51 +114,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
114 }, 114 },
115}; 115};
116 116
117static struct map_desc exynos4_iodesc0[] __initdata = {
118 {
119 .virtual = (unsigned long)S5P_VA_SYSRAM,
120 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
121 .length = SZ_4K,
122 .type = MT_DEVICE,
123 },
124};
125
126static struct map_desc exynos4_iodesc1[] __initdata = {
127 {
128 .virtual = (unsigned long)S5P_VA_SYSRAM,
129 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133};
134
135static struct map_desc exynos4210_iodesc[] __initdata = {
136 {
137 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
138 .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
139 .length = SZ_4K,
140 .type = MT_DEVICE,
141 },
142};
143
144static struct map_desc exynos4x12_iodesc[] __initdata = {
145 {
146 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
147 .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
148 .length = SZ_4K,
149 .type = MT_DEVICE,
150 },
151};
152
153static struct map_desc exynos5250_iodesc[] __initdata = {
154 {
155 .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
156 .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
157 .length = SZ_4K,
158 .type = MT_DEVICE,
159 },
160};
161
162static struct map_desc exynos5_iodesc[] __initdata = { 117static struct map_desc exynos5_iodesc[] __initdata = {
163 { 118 {
164 .virtual = (unsigned long)S3C_VA_SYS, 119 .virtual = (unsigned long)S3C_VA_SYS,
@@ -181,11 +136,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
181 .length = SZ_4K, 136 .length = SZ_4K,
182 .type = MT_DEVICE, 137 .type = MT_DEVICE,
183 }, { 138 }, {
184 .virtual = (unsigned long)S5P_VA_SYSRAM,
185 .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
186 .length = SZ_4K,
187 .type = MT_DEVICE,
188 }, {
189 .virtual = (unsigned long)S5P_VA_CMU, 139 .virtual = (unsigned long)S5P_VA_CMU,
190 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), 140 .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
191 .length = 144 * SZ_1K, 141 .length = 144 * SZ_1K,
@@ -280,20 +230,6 @@ static void __init exynos_map_io(void)
280 230
281 if (soc_is_exynos5()) 231 if (soc_is_exynos5())
282 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); 232 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
283
284 if (soc_is_exynos4210()) {
285 if (samsung_rev() == EXYNOS4210_REV_0)
286 iotable_init(exynos4_iodesc0,
287 ARRAY_SIZE(exynos4_iodesc0));
288 else
289 iotable_init(exynos4_iodesc1,
290 ARRAY_SIZE(exynos4_iodesc1));
291 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
292 }
293 if (soc_is_exynos4212() || soc_is_exynos4412())
294 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
295 if (soc_is_exynos5250())
296 iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
297} 233}
298 234
299void __init exynos_init_io(void) 235void __init exynos_init_io(void)
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index aa01c4222b40..4135edbc0270 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -20,6 +20,7 @@
20 20
21#include <plat/cpu.h> 21#include <plat/cpu.h>
22 22
23#include "common.h"
23#include "smc.h" 24#include "smc.h"
24 25
25static int exynos_do_idle(void) 26static int exynos_do_idle(void)
@@ -44,7 +45,12 @@ static int exynos_cpu_boot(int cpu)
44 45
45static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr) 46static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
46{ 47{
47 void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c; 48 void __iomem *boot_reg;
49
50 if (!sysram_ns_base_addr)
51 return -ENODEV;
52
53 boot_reg = sysram_ns_base_addr + 0x1c;
48 54
49 if (!soc_is_exynos4212()) 55 if (!soc_is_exynos4212())
50 boot_reg += 4*cpu; 56 boot_reg += 4*cpu;
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b59d9ec..548269a60634 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -23,13 +23,6 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define EXYNOS4_PA_SYSRAM0 0x02025000
27#define EXYNOS4_PA_SYSRAM1 0x02020000
28#define EXYNOS5_PA_SYSRAM 0x02020000
29#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
30#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
31#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
32
33#define EXYNOS_PA_CHIPID 0x10000000 26#define EXYNOS_PA_CHIPID 0x10000000
34 27
35#define EXYNOS4_PA_SYSCON 0x10010000 28#define EXYNOS4_PA_SYSCON 0x10010000
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f94705..c11c5418e0fc 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,6 +20,7 @@
20#include <linux/jiffies.h> 20#include <linux/jiffies.h>
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/of_address.h>
23 24
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
25#include <asm/smp_plat.h> 26#include <asm/smp_plat.h>
@@ -33,11 +34,33 @@
33 34
34extern void exynos4_secondary_startup(void); 35extern void exynos4_secondary_startup(void);
35 36
37static void __iomem *sysram_base_addr;
38void __iomem *sysram_ns_base_addr;
39
40static void __init exynos_smp_prepare_sysram(void)
41{
42 struct device_node *node;
43
44 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
45 if (!of_device_is_available(node))
46 continue;
47 sysram_base_addr = of_iomap(node, 0);
48 break;
49 }
50
51 for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
52 if (!of_device_is_available(node))
53 continue;
54 sysram_ns_base_addr = of_iomap(node, 0);
55 break;
56 }
57}
58
36static inline void __iomem *cpu_boot_reg_base(void) 59static inline void __iomem *cpu_boot_reg_base(void)
37{ 60{
38 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) 61 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
39 return S5P_INFORM5; 62 return S5P_INFORM5;
40 return S5P_VA_SYSRAM; 63 return sysram_base_addr;
41} 64}
42 65
43static inline void __iomem *cpu_boot_reg(int cpu) 66static inline void __iomem *cpu_boot_reg(int cpu)
@@ -45,6 +68,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
45 void __iomem *boot_reg; 68 void __iomem *boot_reg;
46 69
47 boot_reg = cpu_boot_reg_base(); 70 boot_reg = cpu_boot_reg_base();
71 if (!boot_reg)
72 return ERR_PTR(-ENODEV);
48 if (soc_is_exynos4412()) 73 if (soc_is_exynos4412())
49 boot_reg += 4*cpu; 74 boot_reg += 4*cpu;
50 else if (soc_is_exynos5420()) 75 else if (soc_is_exynos5420())
@@ -90,6 +115,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
90{ 115{
91 unsigned long timeout; 116 unsigned long timeout;
92 unsigned long phys_cpu = cpu_logical_map(cpu); 117 unsigned long phys_cpu = cpu_logical_map(cpu);
118 int ret = -ENOSYS;
93 119
94 /* 120 /*
95 * Set synchronisation state between this boot processor 121 * Set synchronisation state between this boot processor
@@ -146,8 +172,18 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
146 * Try to set boot address using firmware first 172 * Try to set boot address using firmware first
147 * and fall back to boot register if it fails. 173 * and fall back to boot register if it fails.
148 */ 174 */
149 if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr)) 175 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
176 if (ret && ret != -ENOSYS)
177 goto fail;
178 if (ret == -ENOSYS) {
179 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
180
181 if (IS_ERR(boot_reg)) {
182 ret = PTR_ERR(boot_reg);
183 goto fail;
184 }
150 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu)); 185 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
186 }
151 187
152 call_firmware_op(cpu_boot, phys_cpu); 188 call_firmware_op(cpu_boot, phys_cpu);
153 189
@@ -163,9 +199,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
163 * now the secondary core is starting up let it run its 199 * now the secondary core is starting up let it run its
164 * calibrations, then wait for it to finish 200 * calibrations, then wait for it to finish
165 */ 201 */
202fail:
166 spin_unlock(&boot_lock); 203 spin_unlock(&boot_lock);
167 204
168 return pen_release != -1 ? -ENOSYS : 0; 205 return pen_release != -1 ? ret : 0;
169} 206}
170 207
171/* 208/*
@@ -205,6 +242,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
205 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9) 242 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
206 scu_enable(scu_base_addr()); 243 scu_enable(scu_base_addr());
207 244
245 exynos_smp_prepare_sysram();
246
208 /* 247 /*
209 * Write the address of secondary startup into the 248 * Write the address of secondary startup into the
210 * system-wide flags register. The boot monitor waits 249 * system-wide flags register. The boot monitor waits
@@ -217,12 +256,21 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
217 for (i = 1; i < max_cpus; ++i) { 256 for (i = 1; i < max_cpus; ++i) {
218 unsigned long phys_cpu; 257 unsigned long phys_cpu;
219 unsigned long boot_addr; 258 unsigned long boot_addr;
259 int ret;
220 260
221 phys_cpu = cpu_logical_map(i); 261 phys_cpu = cpu_logical_map(i);
222 boot_addr = virt_to_phys(exynos4_secondary_startup); 262 boot_addr = virt_to_phys(exynos4_secondary_startup);
223 263
224 if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr)) 264 ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
265 if (ret && ret != -ENOSYS)
266 break;
267 if (ret == -ENOSYS) {
268 void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
269
270 if (IS_ERR(boot_reg))
271 break;
225 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu)); 272 __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
273 }
226 } 274 }
227} 275}
228 276
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-31 01:48:13 -0400