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authorMarc Zyngier <marc.zyngier@arm.com>2015-03-11 11:42:59 -0400
committerJason Cooper <jason@lakedaemon.net>2015-03-14 20:40:29 -0400
commitde3ce0804916a9b4f3b58e4e78727d5483c4df04 (patch)
tree0e866286aa47ae6f13a4a2832dcc3cf8b08dd6df
parentb3aa14c39944c6ea2ce20278afe87241413b0477 (diff)
irqchip: tegra: Add DT-based support for legacy interrupt controller
Tegra's LIC (Legacy Interrupt Controller) has been so far only supported as a weird extension of the GIC, which is not exactly pretty. The stacked IRQ domain framework fits this pretty well, and allows the LIC code to be turned into a standalone irqchip. In the process, make the driver DT aware, something that was sorely missing from the mach-tegra implementation. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1426088583-15097-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r--drivers/irqchip/Makefile1
-rw-r--r--drivers/irqchip/irq-tegra.c371
2 files changed, 372 insertions, 0 deletions
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 42965d2476bb..c6d607f1ec50 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
6obj-$(CONFIG_ARCH_MMP) += irq-mmp.o 6obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
7obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o 7obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
8obj-$(CONFIG_ARCH_MXS) += irq-mxs.o 8obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
9obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
9obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o 10obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
10obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o 11obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
11obj-$(CONFIG_METAG) += irq-metag-ext.o 12obj-$(CONFIG_METAG) += irq-metag-ext.o
diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
new file mode 100644
index 000000000000..d919ecf29cf4
--- /dev/null
+++ b/drivers/irqchip/irq-tegra.c
@@ -0,0 +1,371 @@
1/*
2 * Driver code for Tegra's Legacy Interrupt Controller
3 *
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Heavily based on the original arch/arm/mach-tegra/irq.c code:
7 * Copyright (C) 2011 Google, Inc.
8 *
9 * Author:
10 * Colin Cross <ccross@android.com>
11 *
12 * Copyright (C) 2010,2013, NVIDIA Corporation
13 *
14 * This software is licensed under the terms of the GNU General Public
15 * License version 2, as published by the Free Software Foundation, and
16 * may be copied, distributed, and modified under those terms.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 */
24
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/irqdomain.h>
28#include <linux/of_address.h>
29#include <linux/slab.h>
30#include <linux/syscore_ops.h>
31
32#include <dt-bindings/interrupt-controller/arm-gic.h>
33
34#include "irqchip.h"
35
36#define ICTLR_CPU_IEP_VFIQ 0x08
37#define ICTLR_CPU_IEP_FIR 0x14
38#define ICTLR_CPU_IEP_FIR_SET 0x18
39#define ICTLR_CPU_IEP_FIR_CLR 0x1c
40
41#define ICTLR_CPU_IER 0x20
42#define ICTLR_CPU_IER_SET 0x24
43#define ICTLR_CPU_IER_CLR 0x28
44#define ICTLR_CPU_IEP_CLASS 0x2C
45
46#define ICTLR_COP_IER 0x30
47#define ICTLR_COP_IER_SET 0x34
48#define ICTLR_COP_IER_CLR 0x38
49#define ICTLR_COP_IEP_CLASS 0x3c
50
51#define TEGRA_MAX_NUM_ICTLRS 5
52
53static unsigned int num_ictlrs;
54
55struct tegra_ictlr_soc {
56 unsigned int num_ictlrs;
57};
58
59static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
60 .num_ictlrs = 4,
61};
62
63static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
64 .num_ictlrs = 5,
65};
66
67static const struct of_device_id ictlr_matches[] = {
68 { .compatible = "nvidia,tegra30-ictlr", .data = &tegra30_ictlr_soc },
69 { .compatible = "nvidia,tegra20-ictlr", .data = &tegra20_ictlr_soc },
70 { }
71};
72
73struct tegra_ictlr_info {
74 void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
75#ifdef CONFIG_PM_SLEEP
76 u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
77 u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
78 u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
79 u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
80
81 u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
82#endif
83};
84
85static struct tegra_ictlr_info *lic;
86
87static inline void tegra_ictlr_write_mask(struct irq_data *d, unsigned long reg)
88{
89 void __iomem *base = d->chip_data;
90 u32 mask;
91
92 mask = BIT(d->hwirq % 32);
93 writel_relaxed(mask, base + reg);
94}
95
96static void tegra_mask(struct irq_data *d)
97{
98 tegra_ictlr_write_mask(d, ICTLR_CPU_IER_CLR);
99 irq_chip_mask_parent(d);
100}
101
102static void tegra_unmask(struct irq_data *d)
103{
104 tegra_ictlr_write_mask(d, ICTLR_CPU_IER_SET);
105 irq_chip_unmask_parent(d);
106}
107
108static void tegra_eoi(struct irq_data *d)
109{
110 tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_CLR);
111 irq_chip_eoi_parent(d);
112}
113
114static int tegra_retrigger(struct irq_data *d)
115{
116 tegra_ictlr_write_mask(d, ICTLR_CPU_IEP_FIR_SET);
117 return irq_chip_retrigger_hierarchy(d);
118}
119
120#ifdef CONFIG_PM_SLEEP
121static int tegra_set_wake(struct irq_data *d, unsigned int enable)
122{
123 u32 irq = d->hwirq;
124 u32 index, mask;
125
126 index = (irq / 32);
127 mask = BIT(irq % 32);
128 if (enable)
129 lic->ictlr_wake_mask[index] |= mask;
130 else
131 lic->ictlr_wake_mask[index] &= ~mask;
132
133 /*
134 * Do *not* call into the parent, as the GIC doesn't have any
135 * wake-up facility...
136 */
137 return 0;
138}
139
140static int tegra_ictlr_suspend(void)
141{
142 unsigned long flags;
143 unsigned int i;
144
145 local_irq_save(flags);
146 for (i = 0; i < num_ictlrs; i++) {
147 void __iomem *ictlr = lic->base[i];
148
149 /* Save interrupt state */
150 lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER);
151 lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS);
152 lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
153 lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
154
155 /* Disable COP interrupts */
156 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
157
158 /* Disable CPU interrupts */
159 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
160
161 /* Enable the wakeup sources of ictlr */
162 writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
163 }
164 local_irq_restore(flags);
165
166 return 0;
167}
168
169static void tegra_ictlr_resume(void)
170{
171 unsigned long flags;
172 unsigned int i;
173
174 local_irq_save(flags);
175 for (i = 0; i < num_ictlrs; i++) {
176 void __iomem *ictlr = lic->base[i];
177
178 writel_relaxed(lic->cpu_iep[i],
179 ictlr + ICTLR_CPU_IEP_CLASS);
180 writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
181 writel_relaxed(lic->cpu_ier[i],
182 ictlr + ICTLR_CPU_IER_SET);
183 writel_relaxed(lic->cop_iep[i],
184 ictlr + ICTLR_COP_IEP_CLASS);
185 writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
186 writel_relaxed(lic->cop_ier[i],
187 ictlr + ICTLR_COP_IER_SET);
188 }
189 local_irq_restore(flags);
190}
191
192static struct syscore_ops tegra_ictlr_syscore_ops = {
193 .suspend = tegra_ictlr_suspend,
194 .resume = tegra_ictlr_resume,
195};
196
197static void tegra_ictlr_syscore_init(void)
198{
199 register_syscore_ops(&tegra_ictlr_syscore_ops);
200}
201#else
202#define tegra_set_wake NULL
203static inline void tegra_ictlr_syscore_init(void) {}
204#endif
205
206static struct irq_chip tegra_ictlr_chip = {
207 .name = "LIC",
208 .irq_eoi = tegra_eoi,
209 .irq_mask = tegra_mask,
210 .irq_unmask = tegra_unmask,
211 .irq_retrigger = tegra_retrigger,
212 .irq_set_wake = tegra_set_wake,
213 .flags = IRQCHIP_MASK_ON_SUSPEND,
214#ifdef CONFIG_SMP
215 .irq_set_affinity = irq_chip_set_affinity_parent,
216#endif
217};
218
219static int tegra_ictlr_domain_xlate(struct irq_domain *domain,
220 struct device_node *controller,
221 const u32 *intspec,
222 unsigned int intsize,
223 unsigned long *out_hwirq,
224 unsigned int *out_type)
225{
226 if (domain->of_node != controller)
227 return -EINVAL; /* Shouldn't happen, really... */
228 if (intsize != 3)
229 return -EINVAL; /* Not GIC compliant */
230 if (intspec[0] != GIC_SPI)
231 return -EINVAL; /* No PPI should point to this domain */
232
233 *out_hwirq = intspec[1];
234 *out_type = intspec[2];
235 return 0;
236}
237
238static int tegra_ictlr_domain_alloc(struct irq_domain *domain,
239 unsigned int virq,
240 unsigned int nr_irqs, void *data)
241{
242 struct of_phandle_args *args = data;
243 struct of_phandle_args parent_args;
244 struct tegra_ictlr_info *info = domain->host_data;
245 irq_hw_number_t hwirq;
246 unsigned int i;
247
248 if (args->args_count != 3)
249 return -EINVAL; /* Not GIC compliant */
250 if (args->args[0] != GIC_SPI)
251 return -EINVAL; /* No PPI should point to this domain */
252
253 hwirq = args->args[1];
254 if (hwirq >= (num_ictlrs * 32))
255 return -EINVAL;
256
257 for (i = 0; i < nr_irqs; i++) {
258 int ictlr = (hwirq + i) / 32;
259
260 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
261 &tegra_ictlr_chip,
262 &info->base[ictlr]);
263 }
264
265 parent_args = *args;
266 parent_args.np = domain->parent->of_node;
267 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_args);
268}
269
270static void tegra_ictlr_domain_free(struct irq_domain *domain,
271 unsigned int virq,
272 unsigned int nr_irqs)
273{
274 unsigned int i;
275
276 for (i = 0; i < nr_irqs; i++) {
277 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
278 irq_domain_reset_irq_data(d);
279 }
280}
281
282static const struct irq_domain_ops tegra_ictlr_domain_ops = {
283 .xlate = tegra_ictlr_domain_xlate,
284 .alloc = tegra_ictlr_domain_alloc,
285 .free = tegra_ictlr_domain_free,
286};
287
288static int __init tegra_ictlr_init(struct device_node *node,
289 struct device_node *parent)
290{
291 struct irq_domain *parent_domain, *domain;
292 const struct of_device_id *match;
293 const struct tegra_ictlr_soc *soc;
294 unsigned int i;
295 int err;
296
297 if (!parent) {
298 pr_err("%s: no parent, giving up\n", node->full_name);
299 return -ENODEV;
300 }
301
302 parent_domain = irq_find_host(parent);
303 if (!parent_domain) {
304 pr_err("%s: unable to obtain parent domain\n", node->full_name);
305 return -ENXIO;
306 }
307
308 match = of_match_node(ictlr_matches, node);
309 if (!match) /* Should never happen... */
310 return -ENODEV;
311
312 soc = match->data;
313
314 lic = kzalloc(sizeof(*lic), GFP_KERNEL);
315 if (!lic)
316 return -ENOMEM;
317
318 for (i = 0; i < TEGRA_MAX_NUM_ICTLRS; i++) {
319 void __iomem *base;
320
321 base = of_iomap(node, i);
322 if (!base)
323 break;
324
325 lic->base[i] = base;
326
327 /* Disable all interrupts */
328 writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
329 /* All interrupts target IRQ */
330 writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);
331
332 num_ictlrs++;
333 }
334
335 if (!num_ictlrs) {
336 pr_err("%s: no valid regions, giving up\n", node->full_name);
337 err = -ENOMEM;
338 goto out_free;
339 }
340
341 WARN(num_ictlrs != soc->num_ictlrs,
342 "%s: Found %u interrupt controllers in DT; expected %u.\n",
343 node->full_name, num_ictlrs, soc->num_ictlrs);
344
345
346 domain = irq_domain_add_hierarchy(parent_domain, 0, num_ictlrs * 32,
347 node, &tegra_ictlr_domain_ops,
348 lic);
349 if (!domain) {
350 pr_err("%s: failed to allocated domain\n", node->full_name);
351 err = -ENOMEM;
352 goto out_unmap;
353 }
354
355 tegra_ictlr_syscore_init();
356
357 pr_info("%s: %d interrupts forwarded to %s\n",
358 node->full_name, num_ictlrs * 32, parent->full_name);
359
360 return 0;
361
362out_unmap:
363 for (i = 0; i < num_ictlrs; i++)
364 iounmap(lic->base[i]);
365out_free:
366 kfree(lic);
367 return err;
368}
369
370IRQCHIP_DECLARE(tegra20_ictlr, "nvidia,tegra20-ictlr", tegra_ictlr_init);
371IRQCHIP_DECLARE(tegra30_ictlr, "nvidia,tegra30-ictlr", tegra_ictlr_init);