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authorDamien Lespiau <damien.lespiau@intel.com>2014-03-12 21:40:28 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-03-12 22:52:31 -0400
commitdc616b89dbc4bb6a99884d214bd1ed1e0eef59a0 (patch)
tree18a0547a3e6b620cb308b58ca7137f436baca1b8
parent065f2ec2afc850960dcebc3b00766bc31c4ffd3b (diff)
drm/i915/bdw: The TLB invalidation mechanism has been removed from INSTPM
While wandering in the spec, I noticed that BDW removes those 2 bits from INSTPM. I couldn't find any direct way to invalidate the TLB (ie without the ring working already). Maybe someone will be more lucky. At least, we now know we may be a problem. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c50388a86bca..4eb3e062b4e3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -981,8 +981,14 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
981 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); 981 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
982 POSTING_READ(mmio); 982 POSTING_READ(mmio);
983 983
984 /* Flush the TLB for this page */ 984 /*
985 if (INTEL_INFO(dev)->gen >= 6) { 985 * Flush the TLB for this page
986 *
987 * FIXME: These two bits have disappeared on gen8, so a question
988 * arises: do we still need this and if so how should we go about
989 * invalidating the TLB?
990 */
991 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
986 u32 reg = RING_INSTPM(ring->mmio_base); 992 u32 reg = RING_INSTPM(ring->mmio_base);
987 993
988 /* ring should be idle before issuing a sync flush*/ 994 /* ring should be idle before issuing a sync flush*/