Merge branch 'for-joerg/arm-smmu/updates' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into arm/smmu

2 files changed, 77 insertions, 34 deletions

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index e34c6cdd8ba8..f284b99402bc 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -48,6 +48,12 @@ conditions.
                   from the mmu-masters towards memory) node for this
                   SMMU.
 
+- calxeda,smmu-secure-config-access : Enable proper handling of buggy
+                  implementations that always use secure access to
+                  SMMU configuration registers. In this case non-secure
+                  aliases of secure registers have to be used during
+                  SMMU configuration.
+
 Example:
 
         smmu {
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 1d9ab39af29f..8b89e33a89fe 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -48,7 +48,7 @@
 #include <asm/pgalloc.h>
 
 /* Maximum number of stream IDs assigned to a single device */
-#define MAX_MASTER_STREAMIDS            8
+#define MAX_MASTER_STREAMIDS            MAX_PHANDLE_ARGS
 
 /* Maximum number of context banks per SMMU */
 #define ARM_SMMU_MAX_CBS                128
@@ -60,6 +60,16 @@
 #define ARM_SMMU_GR0(smmu)              ((smmu)->base)
 #define ARM_SMMU_GR1(smmu)              ((smmu)->base + (smmu)->pagesize)
 
+/*
+ * SMMU global address space with conditional offset to access secure
+ * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
+ * nsGFSYNR0: 0x450)
+ */
+#define ARM_SMMU_GR0_NS(smmu)                                           \
+        ((smmu)->base +                                                 \
+                ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)       \
+                        ? 0x400 : 0))
+
 /* Page table bits */
 #define ARM_SMMU_PTE_XN                 (((pteval_t)3) << 53)
 #define ARM_SMMU_PTE_CONT               (((pteval_t)1) << 52)
@@ -351,6 +361,9 @@ struct arm_smmu_device {
 #define ARM_SMMU_FEAT_TRANS_S2          (1 << 3)
 #define ARM_SMMU_FEAT_TRANS_NESTED      (1 << 4)
         u32                             features;
+
+#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
+        u32                             options;
         int                             version;
 
         u32                             num_context_banks;
@@ -401,6 +414,29 @@ struct arm_smmu_domain {
 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
 static LIST_HEAD(arm_smmu_devices);
 
+struct arm_smmu_option_prop {
+        u32 opt;
+        const char *prop;
+};
+
+static struct arm_smmu_option_prop arm_smmu_options [] = {
+        { ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
+        { 0, NULL},
+};
+
+static void parse_driver_options(struct arm_smmu_device *smmu)
+{
+        int i = 0;
+        do {
+                if (of_property_read_bool(smmu->dev->of_node,
+                                                arm_smmu_options[i].prop)) {
+                        smmu->options |= arm_smmu_options[i].opt;
+                        dev_notice(smmu->dev, "option %s\n",
+                                arm_smmu_options[i].prop);
+                }
+        } while (arm_smmu_options[++i].opt);
+}
+
 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
                                                 struct device_node *dev_node)
 {
@@ -614,16 +650,16 @@ static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
 {
         u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
         struct arm_smmu_device *smmu = dev;
-        void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
+        void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
 
         gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
-        if (!gfsr)
-                return IRQ_NONE;
-
         gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
         gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
         gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
 
+        if (!gfsr)
+                return IRQ_NONE;
+
         dev_err_ratelimited(smmu->dev,
                 "Unexpected global fault, this could be serious\n");
         dev_err_ratelimited(smmu->dev,
@@ -642,7 +678,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
 
         /* Ensure new page tables are visible to the hardware walker */
         if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
-                dsb();
+                dsb(ishst);
         } else {
                 /*
                  * If the SMMU can't walk tables in the CPU caches, treat them
@@ -990,9 +1026,8 @@ static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
 
         /*
          * Recursively free the page tables for this domain. We don't
-         * care about speculative TLB filling, because the TLB will be
-         * nuked next time this context bank is re-allocated and no devices
-         * currently map to these tables.
+         * care about speculative TLB filling because the tables should
+         * not be active in any context bank at this point (SCTLR.M is 0).
          */
         pgd = pgd_base;
         for (i = 0; i < PTRS_PER_PGD; ++i) {
@@ -1218,7 +1253,7 @@ static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
 
 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
                                    unsigned long addr, unsigned long end,
-                                   unsigned long pfn, int flags, int stage)
+                                   unsigned long pfn, int prot, int stage)
 {
         pte_t *pte, *start;
         pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
@@ -1240,28 +1275,28 @@ static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
 
         if (stage == 1) {
                 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
-                if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
+                if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
                         pteval |= ARM_SMMU_PTE_AP_RDONLY;
 
-                if (flags & IOMMU_CACHE)
+                if (prot & IOMMU_CACHE)
                         pteval |= (MAIR_ATTR_IDX_CACHE <<
                                    ARM_SMMU_PTE_ATTRINDX_SHIFT);
         } else {
                 pteval |= ARM_SMMU_PTE_HAP_FAULT;
-                if (flags & IOMMU_READ)
+                if (prot & IOMMU_READ)
                         pteval |= ARM_SMMU_PTE_HAP_READ;
-                if (flags & IOMMU_WRITE)
+                if (prot & IOMMU_WRITE)
                         pteval |= ARM_SMMU_PTE_HAP_WRITE;
-                if (flags & IOMMU_CACHE)
+                if (prot & IOMMU_CACHE)
                         pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;