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authorBernd Schmidt <bernds_cb1@t-online.de>2008-04-22 19:11:55 -0400
committerBryan Wu <cooloney@kernel.org>2008-04-22 19:11:55 -0400
commitdbfe44f02b6855efb5a596e942ec2fd96d592f60 (patch)
tree9e66be31b671bd6ac0df65f8e2d82119580ffc72
parentb594272c5e2837b6856b93520303c5981c852327 (diff)
[Blackfin] arch: fix up - CONFIG_BLKFIN_WT was renamed CONFIG_BFIN_WT while the MPU code was out-of-tree.
Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Bryan Wu <cooloney@kernel.org>
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbinit.c2
-rw-r--r--arch/blackfin/kernel/cplb-mpu/cplbmgr.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index dc6e8a7a8bda..7310e5fc6399 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -49,7 +49,7 @@ void __init generate_cpl_tables(void)
49 49
50#ifdef CONFIG_BFIN_DCACHE 50#ifdef CONFIG_BFIN_DCACHE
51 d_cache = CPLB_L1_CHBL; 51 d_cache = CPLB_L1_CHBL;
52#ifdef CONFIG_BLKFIN_WT 52#ifdef CONFIG_BFIN_WT
53 d_cache |= CPLB_L1_AOW | CPLB_WT; 53 d_cache |= CPLB_L1_AOW | CPLB_WT;
54#endif 54#endif
55#endif 55#endif
diff --git a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
index c426a22f9907..0a30d6256073 100644
--- a/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbmgr.c
@@ -149,7 +149,7 @@ static noinline int dcplb_miss(void)
149 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; 149 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
150#ifdef CONFIG_BFIN_DCACHE 150#ifdef CONFIG_BFIN_DCACHE
151 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND; 151 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
152#ifdef CONFIG_BLKFIN_WT 152#ifdef CONFIG_BFIN_WT
153 d_data |= CPLB_L1_AOW | CPLB_WT; 153 d_data |= CPLB_L1_AOW | CPLB_WT;
154#endif 154#endif
155#endif 155#endif
@@ -319,7 +319,7 @@ void set_mask_dcplbs(unsigned long *masks)
319 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB; 319 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
320#ifdef CONFIG_BFIN_DCACHE 320#ifdef CONFIG_BFIN_DCACHE
321 d_data |= CPLB_L1_CHBL; 321 d_data |= CPLB_L1_CHBL;
322#ifdef CONFIG_BLKFIN_WT 322#ifdef CONFIG_BFIN_WT
323 d_data |= CPLB_L1_AOW | CPLB_WT; 323 d_data |= CPLB_L1_AOW | CPLB_WT;
324#endif 324#endif
325#endif 325#endif