aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorBen Skeggs <bskeggs@redhat.com>2013-05-13 19:23:52 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-06-30 23:50:40 -0400
commitdba50728fdf22d9c7e7d2cac7fc5d2e8715aadcd (patch)
treed9cff7e5f3b8c59ad3f46526c9b5aae1343d1f9a
parent58ef23056ae0bc060086f71ad04254e188a30ff0 (diff)
drm/nvc4/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c31
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc8
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c22
6 files changed, 62 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index f98d0878dd12..52712fbc856b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1327,6 +1327,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
1327 switch (nv_device(priv)->chipset) { 1327 switch (nv_device(priv)->chipset) {
1328 case 0xc0: 1328 case 0xc0:
1329 case 0xc3: 1329 case 0xc3:
1330 case 0xc4:
1330 case 0xc1: 1331 case 0xc1:
1331 case 0xd9: 1332 case 0xd9:
1332 case 0xd7: 1333 case 0xd7:
@@ -1476,6 +1477,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1476 break; 1477 break;
1477 case 0xc0: 1478 case 0xc0:
1478 case 0xc3: 1479 case 0xc3:
1480 case 0xc4:
1479 case 0xc1: 1481 case 0xc1:
1480 default: 1482 default:
1481 break; 1483 break;
@@ -1498,6 +1500,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1498 switch (nv_device(priv)->chipset) { 1500 switch (nv_device(priv)->chipset) {
1499 case 0xc0: 1501 case 0xc0:
1500 case 0xc3: 1502 case 0xc3:
1503 case 0xc4:
1501 case 0xc1: 1504 case 0xc1:
1502 case 0xd9: 1505 case 0xd9:
1503 case 0xd7: 1506 case 0xd7:
@@ -1527,6 +1530,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
1527 break; 1530 break;
1528 case 0xc0: 1531 case 0xc0:
1529 case 0xc3: 1532 case 0xc3:
1533 case 0xc4:
1530 case 0xc1: 1534 case 0xc1:
1531 default: 1535 default:
1532 nv_wr32(priv, 0x404174, 0x00000000); 1536 nv_wr32(priv, 0x404174, 0x00000000);
@@ -1671,6 +1675,7 @@ nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
1671 break; 1675 break;
1672 case 0xc0: 1676 case 0xc0:
1673 case 0xc3: 1677 case 0xc3:
1678 case 0xc4:
1674 default: 1679 default:
1675 nv_wr32(priv, 0x405800, 0x078000bf); 1680 nv_wr32(priv, 0x405800, 0x078000bf);
1676 nv_wr32(priv, 0x405830, 0x02180000); 1681 nv_wr32(priv, 0x405830, 0x02180000);
@@ -1713,6 +1718,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
1713 break; 1718 break;
1714 case 0xc0: 1719 case 0xc0:
1715 case 0xc3: 1720 case 0xc3:
1721 case 0xc4:
1716 case 0xc1: 1722 case 0xc1:
1717 default: 1723 default:
1718 break; 1724 break;
@@ -1726,6 +1732,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
1726 break; 1732 break;
1727 case 0xc0: 1733 case 0xc0:
1728 case 0xc3: 1734 case 0xc3:
1735 case 0xc4:
1729 default: 1736 default:
1730 break; 1737 break;
1731 } 1738 }
@@ -1766,6 +1773,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
1766 switch (nv_device(priv)->chipset) { 1773 switch (nv_device(priv)->chipset) {
1767 case 0xc0: 1774 case 0xc0:
1768 case 0xc3: 1775 case 0xc3:
1776 case 0xc4:
1769 nv_wr32(priv, 0x408808, 0x0003e00d); 1777 nv_wr32(priv, 0x408808, 0x0003e00d);
1770 nv_wr32(priv, 0x408900, 0x3080b801); 1778 nv_wr32(priv, 0x408900, 0x3080b801);
1771 nv_wr32(priv, 0x408904, 0x02000001); 1779 nv_wr32(priv, 0x408904, 0x02000001);
@@ -1810,6 +1818,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1810 break; 1818 break;
1811 case 0xc0: 1819 case 0xc0:
1812 case 0xc3: 1820 case 0xc3:
1821 case 0xc4:
1813 case 0xc1: 1822 case 0xc1:
1814 default: 1823 default:
1815 nv_wr32(priv, 0x418408, 0x00000000); 1824 nv_wr32(priv, 0x418408, 0x00000000);
@@ -1824,6 +1833,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1824 break; 1833 break;
1825 case 0xc0: 1834 case 0xc0:
1826 case 0xc3: 1835 case 0xc3:
1836 case 0xc4:
1827 case 0xc1: 1837 case 0xc1:
1828 default: 1838 default:
1829 nv_wr32(priv, 0x418414, 0x00200fff); 1839 nv_wr32(priv, 0x418414, 0x00200fff);
@@ -1850,6 +1860,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1850 break; 1860 break;
1851 case 0xc0: 1861 case 0xc0:
1852 case 0xc3: 1862 case 0xc3:
1863 case 0xc4:
1853 case 0xc1: 1864 case 0xc1:
1854 default: 1865 default:
1855 nv_wr32(priv, 0x41870c, 0x07c80000); 1866 nv_wr32(priv, 0x41870c, 0x07c80000);
@@ -1863,6 +1874,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1863 break; 1874 break;
1864 case 0xc0: 1875 case 0xc0:
1865 case 0xc3: 1876 case 0xc3:
1877 case 0xc4:
1866 case 0xc1: 1878 case 0xc1:
1867 default: 1879 default:
1868 nv_wr32(priv, 0x418800, 0x0006860a); 1880 nv_wr32(priv, 0x418800, 0x0006860a);
@@ -1880,6 +1892,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1880 break; 1892 break;
1881 case 0xc0: 1893 case 0xc0:
1882 case 0xc3: 1894 case 0xc3:
1895 case 0xc4:
1883 default: 1896 default:
1884 nv_wr32(priv, 0x418830, 0x00000001); 1897 nv_wr32(priv, 0x418830, 0x00000001);
1885 break; 1898 break;
@@ -1901,6 +1914,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1901 break; 1914 break;
1902 case 0xc0: 1915 case 0xc0:
1903 case 0xc3: 1916 case 0xc3:
1917 case 0xc4:
1904 default: 1918 default:
1905 nv_wr32(priv, 0x4188fc, 0x00100000); 1919 nv_wr32(priv, 0x4188fc, 0x00100000);
1906 break; 1920 break;
@@ -1925,6 +1939,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1925 break; 1939 break;
1926 case 0xc0: 1940 case 0xc0:
1927 case 0xc3: 1941 case 0xc3:
1942 case 0xc4:
1928 case 0xc1: 1943 case 0xc1:
1929 default: 1944 default:
1930 nv_wr32(priv, 0x418b00, 0x00000000); 1945 nv_wr32(priv, 0x418b00, 0x00000000);
@@ -1954,6 +1969,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
1954 break; 1969 break;
1955 case 0xc0: 1970 case 0xc0:
1956 case 0xc3: 1971 case 0xc3:
1972 case 0xc4:
1957 default: 1973 default:
1958 break; 1974 break;
1959 } 1975 }
@@ -1980,6 +1996,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
1980 break; 1996 break;
1981 case 0xc0: 1997 case 0xc0:
1982 case 0xc3: 1998 case 0xc3:
1999 case 0xc4:
1983 default: 2000 default:
1984 nv_wr32(priv, 0x419864, 0x0000012a); 2001 nv_wr32(priv, 0x419864, 0x0000012a);
1985 break; 2002 break;
@@ -1995,6 +2012,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
1995 case 0xc0: 2012 case 0xc0:
1996 break; 2013 break;
1997 case 0xc3: 2014 case 0xc3:
2015 case 0xc4:
1998 case 0xc1: 2016 case 0xc1:
1999 default: 2017 default:
2000 nv_wr32(priv, 0x419a1c, 0x00000000); 2018 nv_wr32(priv, 0x419a1c, 0x00000000);
@@ -2010,6 +2028,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2010 nv_wr32(priv, 0x00419ac4, 0x0017f440); 2028 nv_wr32(priv, 0x00419ac4, 0x0017f440);
2011 break; 2029 break;
2012 case 0xc3: 2030 case 0xc3:
2031 case 0xc4:
2013 case 0xc1: 2032 case 0xc1:
2014 default: 2033 default:
2015 nv_wr32(priv, 0x00419ac4, 0x0007f440); 2034 nv_wr32(priv, 0x00419ac4, 0x0007f440);
@@ -2030,6 +2049,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2030 break; 2049 break;
2031 case 0xc0: 2050 case 0xc0:
2032 case 0xc3: 2051 case 0xc3:
2052 case 0xc4:
2033 default: 2053 default:
2034 nv_wr32(priv, 0x419be0, 0x00000001); 2054 nv_wr32(priv, 0x419be0, 0x00000001);
2035 break; 2055 break;
@@ -2042,6 +2062,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2042 break; 2062 break;
2043 case 0xc0: 2063 case 0xc0:
2044 case 0xc3: 2064 case 0xc3:
2065 case 0xc4:
2045 case 0xc1: 2066 case 0xc1:
2046 default: 2067 default:
2047 nv_wr32(priv, 0x419c00, 0x00000002); 2068 nv_wr32(priv, 0x419c00, 0x00000002);
@@ -2052,6 +2073,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2052 nv_wr32(priv, 0x419c20, 0x00000000); 2073 nv_wr32(priv, 0x419c20, 0x00000000);
2053 switch (nv_device(priv)->chipset) { 2074 switch (nv_device(priv)->chipset) {
2054 case 0xc3: 2075 case 0xc3:
2076 case 0xc4:
2055 case 0xc1: 2077 case 0xc1:
2056 case 0xce: 2078 case 0xce:
2057 case 0xcf: 2079 case 0xcf:
@@ -2078,6 +2100,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2078 break; 2100 break;
2079 case 0xc0: 2101 case 0xc0:
2080 case 0xc3: 2102 case 0xc3:
2103 case 0xc4:
2081 default: 2104 default:
2082 nv_wr32(priv, 0x419d20, 0x02180000); 2105 nv_wr32(priv, 0x419d20, 0x02180000);
2083 break; 2106 break;
@@ -2091,6 +2114,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2091 break; 2114 break;
2092 case 0xc0: 2115 case 0xc0:
2093 case 0xc3: 2116 case 0xc3:
2117 case 0xc4:
2094 default: 2118 default:
2095 break; 2119 break;
2096 } 2120 }
@@ -2128,6 +2152,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2128 nv_wr32(priv, 0x419ee0, 0x00010110); 2152 nv_wr32(priv, 0x419ee0, 0x00010110);
2129 break; 2153 break;
2130 case 0xc3: 2154 case 0xc3:
2155 case 0xc4:
2131 case 0xc1: 2156 case 0xc1:
2132 default: 2157 default:
2133 nv_wr32(priv, 0x419ee0, 0x00011110); 2158 nv_wr32(priv, 0x419ee0, 0x00011110);
@@ -2140,6 +2165,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
2140 nv_wr32(priv, 0x419f54, 0x00000000); 2165 nv_wr32(priv, 0x419f54, 0x00000000);
2141 break; 2166 break;
2142 case 0xc3: 2167 case 0xc3:
2168 case 0xc4:
2143 case 0xc1: 2169 case 0xc1:
2144 case 0xd9: 2170 case 0xd9:
2145 case 0xd7: 2171 case 0xd7:
@@ -2478,6 +2504,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2478 break; 2504 break;
2479 case 0xc0: 2505 case 0xc0:
2480 case 0xc3: 2506 case 0xc3:
2507 case 0xc4:
2481 case 0xc1: 2508 case 0xc1:
2482 default: 2509 default:
2483 break; 2510 break;
@@ -2498,6 +2525,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
2498 break; 2525 break;
2499 case 0xc0: 2526 case 0xc0:
2500 case 0xc3: 2527 case 0xc3:
2528 case 0xc4:
2501 case 0xc1: 2529 case 0xc1:
2502 break; 2530 break;
2503 default: 2531 default:
@@ -3073,6 +3101,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3073 break; 3101 break;
3074 case 0xc0: 3102 case 0xc0:
3075 case 0xc3: 3103 case 0xc3:
3104 case 0xc4:
3076 default: 3105 default:
3077 break; 3106 break;
3078 } 3107 }
@@ -3183,6 +3212,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3183 break; 3212 break;
3184 case 0xc0: 3213 case 0xc0:
3185 case 0xc3: 3214 case 0xc3:
3215 case 0xc4:
3186 case 0xc1: 3216 case 0xc1:
3187 default: 3217 default:
3188 break; 3218 break;
@@ -3332,6 +3362,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
3332 switch (nv_device(priv)->chipset) { 3362 switch (nv_device(priv)->chipset) {
3333 case 0xc0: 3363 case 0xc0:
3334 case 0xc3: 3364 case 0xc3:
3365 case 0xc4:
3335 case 0xc1: 3366 case 0xc1:
3336 nv_mthd(priv, 0x902d, 0x3410, 0x00000000); 3367 nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
3337 break; 3368 break;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index 79a3a501180a..c5dd2f68d41c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -63,10 +63,10 @@ chipsets:
63.b16 #nnvc3_tpc_mmio_head 63.b16 #nnvc3_tpc_mmio_head
64.b16 #nnvc3_tpc_mmio_tail 64.b16 #nnvc3_tpc_mmio_tail
65.b8 0xc4 0 0 0 65.b8 0xc4 0 0 0
66.b16 #nvc0_gpc_mmio_head 66.b16 #nnvc0_gpc_mmio_head
67.b16 #nvc0_gpc_mmio_tail 67.b16 #nnvc0_gpc_mmio_tail
68.b16 #nvc0_tpc_mmio_head 68.b16 #nnvc3_tpc_mmio_head
69.b16 #nvc3_tpc_mmio_tail 69.b16 #nnvc3_tpc_mmio_tail
70.b8 0xc8 0 0 0 70.b8 0xc8 0 0 0
71.b16 #nvc0_gpc_mmio_head 71.b16 #nvc0_gpc_mmio_head
72.b16 #nvc0_gpc_mmio_tail 72.b16 #nvc0_gpc_mmio_tail
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
index 1a16cbf561c3..f3a560ce438e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -43,8 +43,8 @@ uint32_t nvc0_grgpc_data[] = {
43 0x01940134, 43 0x01940134,
44 0x030402ac, 44 0x030402ac,
45 0x000000c4, 45 0x000000c4,
46 0x013400d4, 46 0x01940134,
47 0x02600200, 47 0x030402ac,
48 0x000000c8, 48 0x000000c8,
49 0x013400d4, 49 0x013400d4,
50 0x02500200, 50 0x02500200,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index 5305b0928e82..92df038abc48 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -57,8 +57,8 @@ chipsets:
57.b16 #nnvc0_hub_mmio_head 57.b16 #nnvc0_hub_mmio_head
58.b16 #nnvc0_hub_mmio_tail 58.b16 #nnvc0_hub_mmio_tail
59.b8 0xc4 0 0 0 59.b8 0xc4 0 0 0
60.b16 #nvc0_hub_mmio_head 60.b16 #nnvc0_hub_mmio_head
61.b16 #nvc0_hub_mmio_tail 61.b16 #nnvc0_hub_mmio_tail
62.b8 0xc8 0 0 0 62.b8 0xc8 0 0 0
63.b16 #nvc0_hub_mmio_head 63.b16 #nvc0_hub_mmio_head
64.b16 #nvc0_hub_mmio_tail 64.b16 #nvc0_hub_mmio_tail
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index 1cdf9e991a3f..bf4f4b32e25b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -209,7 +209,7 @@ uint32_t nvc0_grhub_data[] = {
209 0x000000c3, 209 0x000000c3,
210 0x048403e8, 210 0x048403e8,
211 0x000000c4, 211 0x000000c4,
212 0x03e8034c, 212 0x048403e8,
213 0x000000c8, 213 0x000000c8,
214 0x03e8034c, 214 0x03e8034c,
215 0x000000ce, 215 0x000000ce,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 18bcc34e9f81..664747d62906 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -754,6 +754,7 @@ nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
754 break; 754 break;
755 case 0xc0: 755 case 0xc0:
756 case 0xc3: 756 case 0xc3:
757 case 0xc4:
757 case 0xc1: 758 case 0xc1:
758 default: 759 default:
759 break; 760 break;
@@ -767,6 +768,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
767 nv_wr32(priv, 0x405850, 0x00000000); 768 nv_wr32(priv, 0x405850, 0x00000000);
768 switch (nv_device(priv)->chipset) { 769 switch (nv_device(priv)->chipset) {
769 case 0xc3: 770 case 0xc3:
771 case 0xc4:
770 case 0xc1: 772 case 0xc1:
771 case 0xd9: 773 case 0xd9:
772 case 0xd7: 774 case 0xd7:
@@ -785,6 +787,7 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
785 break; 787 break;
786 case 0xc0: 788 case 0xc0:
787 case 0xc3: 789 case 0xc3:
790 case 0xc4:
788 case 0xc1: 791 case 0xc1:
789 default: 792 default:
790 break; 793 break;
@@ -807,6 +810,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
807 break; 810 break;
808 case 0xc0: 811 case 0xc0:
809 case 0xc3: 812 case 0xc3:
813 case 0xc4:
810 case 0xc1: 814 case 0xc1:
811 default: 815 default:
812 break; 816 break;
@@ -820,6 +824,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
820 break; 824 break;
821 case 0xc0: 825 case 0xc0:
822 case 0xc3: 826 case 0xc3:
827 case 0xc4:
823 case 0xc1: 828 case 0xc1:
824 default: 829 default:
825 break; 830 break;
@@ -834,6 +839,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
834 break; 839 break;
835 case 0xc0: 840 case 0xc0:
836 case 0xc3: 841 case 0xc3:
842 case 0xc4:
837 default: 843 default:
838 nv_wr32(priv, 0x418714, 0x80000000); 844 nv_wr32(priv, 0x418714, 0x80000000);
839 break; 845 break;
@@ -851,6 +857,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
851 break; 857 break;
852 case 0xc0: 858 case 0xc0:
853 case 0xc3: 859 case 0xc3:
860 case 0xc4:
854 default: 861 default:
855 nv_wr32(priv, 0x4188c8, 0x80000000); 862 nv_wr32(priv, 0x4188c8, 0x80000000);
856 break; 863 break;
@@ -874,6 +881,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
874 break; 881 break;
875 case 0xc0: 882 case 0xc0:
876 case 0xc3: 883 case 0xc3:
884 case 0xc4:
877 case 0xc1: 885 case 0xc1:
878 default: 886 default:
879 break; 887 break;
@@ -887,6 +895,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
887 break; 895 break;
888 case 0xc0: 896 case 0xc0:
889 case 0xc3: 897 case 0xc3:
898 case 0xc4:
890 case 0xc1: 899 case 0xc1:
891 default: 900 default:
892 break; 901 break;
@@ -901,6 +910,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
901 break; 910 break;
902 case 0xc0: 911 case 0xc0:
903 case 0xc3: 912 case 0xc3:
913 case 0xc4:
904 case 0xc1: 914 case 0xc1:
905 default: 915 default:
906 break; 916 break;
@@ -917,6 +927,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
917 break; 927 break;
918 case 0xc0: 928 case 0xc0:
919 case 0xc3: 929 case 0xc3:
930 case 0xc4:
920 default: 931 default:
921 nv_wr32(priv, 0x418e00, 0x00000050); 932 nv_wr32(priv, 0x418e00, 0x00000050);
922 break; 933 break;
@@ -930,6 +941,7 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
930 break; 941 break;
931 case 0xc0: 942 case 0xc0:
932 case 0xc3: 943 case 0xc3:
944 case 0xc4:
933 case 0xc1: 945 case 0xc1:
934 default: 946 default:
935 break; 947 break;
@@ -947,6 +959,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
947 nv_wr32(priv, 0x419ab0, 0x00000000); 959 nv_wr32(priv, 0x419ab0, 0x00000000);
948 switch (nv_device(priv)->chipset) { 960 switch (nv_device(priv)->chipset) {
949 case 0xc3: 961 case 0xc3:
962 case 0xc4:
950 case 0xc1: 963 case 0xc1:
951 case 0xd9: 964 case 0xd9:
952 case 0xd7: 965 case 0xd7:
@@ -967,6 +980,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
967 break; 980 break;
968 case 0xc0: 981 case 0xc0:
969 case 0xc3: 982 case 0xc3:
983 case 0xc4:
970 case 0xc1: 984 case 0xc1:
971 default: 985 default:
972 nv_wr32(priv, 0x41980c, 0x00000000); 986 nv_wr32(priv, 0x41980c, 0x00000000);
@@ -981,6 +995,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
981 break; 995 break;
982 case 0xc0: 996 case 0xc0:
983 case 0xc3: 997 case 0xc3:
998 case 0xc4:
984 default: 999 default:
985 nv_wr32(priv, 0x419814, 0x00000000); 1000 nv_wr32(priv, 0x419814, 0x00000000);
986 break; 1001 break;
@@ -993,6 +1008,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
993 break; 1008 break;
994 case 0xc0: 1009 case 0xc0:
995 case 0xc3: 1010 case 0xc3:
1011 case 0xc4:
996 case 0xc1: 1012 case 0xc1:
997 default: 1013 default:
998 nv_wr32(priv, 0x41984c, 0x00005bc5); 1014 nv_wr32(priv, 0x41984c, 0x00005bc5);
@@ -1004,6 +1020,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1004 nv_wr32(priv, 0x41985c, 0x00000000); 1020 nv_wr32(priv, 0x41985c, 0x00000000);
1005 switch (nv_device(priv)->chipset) { 1021 switch (nv_device(priv)->chipset) {
1006 case 0xc3: 1022 case 0xc3:
1023 case 0xc4:
1007 case 0xc1: 1024 case 0xc1:
1008 case 0xd9: 1025 case 0xd9:
1009 case 0xd7: 1026 case 0xd7:
@@ -1030,6 +1047,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1030 break; 1047 break;
1031 case 0xc0: 1048 case 0xc0:
1032 case 0xc3: 1049 case 0xc3:
1050 case 0xc4:
1033 case 0xc1: 1051 case 0xc1:
1034 default: 1052 default:
1035 break; 1053 break;
@@ -1043,6 +1061,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1043 break; 1061 break;
1044 case 0xc0: 1062 case 0xc0:
1045 case 0xc3: 1063 case 0xc3:
1064 case 0xc4:
1046 case 0xc1: 1065 case 0xc1:
1047 default: 1066 default:
1048 break; 1067 break;
@@ -1058,6 +1077,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1058 break; 1077 break;
1059 case 0xc0: 1078 case 0xc0:
1060 case 0xc3: 1079 case 0xc3:
1080 case 0xc4:
1061 case 0xc1: 1081 case 0xc1:
1062 default: 1082 default:
1063 nv_wr32(priv, 0x419ea8, 0x00001100); 1083 nv_wr32(priv, 0x419ea8, 0x00001100);
@@ -1071,6 +1091,7 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
1071 nv_wr32(priv, 0x419ec0, 0x00000000); 1091 nv_wr32(priv, 0x419ec0, 0x00000000);
1072 switch (nv_device(priv)->chipset) { 1092 switch (nv_device(priv)->chipset) {
1073 case 0xc3: 1093 case 0xc3:
1094 case 0xc4:
1074 case 0xc1: 1095 case 0xc1:
1075 case 0xd9: 1096 case 0xd9:
1076 case 0xd7: 1097 case 0xd7:
@@ -1355,6 +1376,7 @@ nvc0_graph_init(struct nouveau_object *object)
1355 switch (nv_device(priv)->chipset) { 1376 switch (nv_device(priv)->chipset) {
1356 case 0xc0: 1377 case 0xc0:
1357 case 0xc3: 1378 case 0xc3:
1379 case 0xc4:
1358 case 0xc1: 1380 case 0xc1:
1359 case 0xd9: 1381 case 0xd9:
1360 case 0xd7: 1382 case 0xd7: