diff options
| author | Ben Dooks <ben-linux@fluff.org> | 2008-01-28 07:01:26 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-01-28 08:20:51 -0500 |
| commit | db9b85c527a397e4cb75956ae69acea92904f6dc (patch) | |
| tree | 9945727855a7b7c49cb7360d89aa14edbbf534fd | |
| parent | e5812bf66881a7d9c67d807b09d69a023d6e4b86 (diff) | |
[ARM] 4786/1: S3C2412: Add SPI FIFO controll constants
Add control constants for the S3C2412 SPI unit FIFO.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | include/asm-arm/plat-s3c24xx/regs-spi.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-arm/plat-s3c24xx/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h index 960907f17914..ea565b007d04 100644 --- a/include/asm-arm/plat-s3c24xx/regs-spi.h +++ b/include/asm-arm/plat-s3c24xx/regs-spi.h | |||
| @@ -17,7 +17,21 @@ | |||
| 17 | 17 | ||
| 18 | #define S3C2410_SPCON (0x00) | 18 | #define S3C2410_SPCON (0x00) |
| 19 | 19 | ||
| 20 | #define S3C2412_SPCON_RXFIFO_RB2 (0<<14) | ||
| 21 | #define S3C2412_SPCON_RXFIFO_RB4 (1<<14) | ||
| 22 | #define S3C2412_SPCON_RXFIFO_RB12 (2<<14) | ||
| 23 | #define S3C2412_SPCON_RXFIFO_RB14 (3<<14) | ||
| 24 | #define S3C2412_SPCON_TXFIFO_RB2 (0<<12) | ||
| 25 | #define S3C2412_SPCON_TXFIFO_RB4 (1<<12) | ||
| 26 | #define S3C2412_SPCON_TXFIFO_RB12 (2<<12) | ||
| 27 | #define S3C2412_SPCON_TXFIFO_RB14 (3<<12) | ||
| 28 | #define S3C2412_SPCON_RXFIFO_RESET (1<<11) /* RxFIFO reset */ | ||
| 29 | #define S3C2412_SPCON_TXFIFO_RESET (1<<10) /* TxFIFO reset */ | ||
| 30 | #define S3C2412_SPCON_RXFIFO_EN (1<<9) /* RxFIFO Enable */ | ||
| 31 | #define S3C2412_SPCON_TXFIFO_EN (1<<8) /* TxFIFO Enable */ | ||
| 32 | |||
| 20 | #define S3C2412_SPCON_DIRC_RX (1<<7) | 33 | #define S3C2412_SPCON_DIRC_RX (1<<7) |
| 34 | |||
| 21 | #define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ | 35 | #define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */ |
| 22 | #define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ | 36 | #define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */ |
| 23 | #define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ | 37 | #define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */ |
| @@ -35,6 +49,15 @@ | |||
| 35 | 49 | ||
| 36 | #define S3C2410_SPSTA (0x04) | 50 | #define S3C2410_SPSTA (0x04) |
| 37 | 51 | ||
| 52 | #define S3C2412_SPSTA_RXFIFO_AE (1<<11) | ||
| 53 | #define S3C2412_SPSTA_TXFIFO_AE (1<<10) | ||
| 54 | #define S3C2412_SPSTA_RXFIFO_ERROR (1<<9) | ||
| 55 | #define S3C2412_SPSTA_TXFIFO_ERROR (1<<8) | ||
| 56 | #define S3C2412_SPSTA_RXFIFO_FIFO (1<<7) | ||
| 57 | #define S3C2412_SPSTA_RXFIFO_EMPTY (1<<6) | ||
| 58 | #define S3C2412_SPSTA_TXFIFO_NFULL (1<<5) | ||
| 59 | #define S3C2412_SPSTA_TXFIFO_EMPTY (1<<4) | ||
| 60 | |||
| 38 | #define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ | 61 | #define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */ |
| 39 | #define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ | 62 | #define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */ |
| 40 | #define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ | 63 | #define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */ |