diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-06-09 06:09:00 -0400 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-07-04 04:17:58 -0400 |
| commit | db85ca7ca51ca886e8cd127368e09a7955bb041c (patch) | |
| tree | 8f896c094cc7ce449e9506eaae0214a7e0771dc3 | |
| parent | 89a2d6183bbd87431fccf9f57a7fec7ae38843e1 (diff) | |
OMAPDSS: HDMI4: use common AVI infoframe support
Instead of using OMAP specific AVI infoframe structs, use the common one
from include/linux/hdmi.h.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| -rw-r--r-- | drivers/video/fbdev/omap2/dss/hdmi.h | 2 | ||||
| -rw-r--r-- | drivers/video/fbdev/omap2/dss/hdmi4_core.c | 136 | ||||
| -rw-r--r-- | drivers/video/fbdev/omap2/dss/hdmi4_core.h | 1 |
3 files changed, 28 insertions, 111 deletions
diff --git a/drivers/video/fbdev/omap2/dss/hdmi.h b/drivers/video/fbdev/omap2/dss/hdmi.h index 1a62dc3fe54e..6cd4a755b0ac 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi.h +++ b/drivers/video/fbdev/omap2/dss/hdmi.h | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/hdmi.h> | ||
| 25 | #include <video/omapdss.h> | 26 | #include <video/omapdss.h> |
| 26 | 27 | ||
| 27 | #include "dss.h" | 28 | #include "dss.h" |
| @@ -360,6 +361,7 @@ struct hdmi_core_data { | |||
| 360 | void __iomem *base; | 361 | void __iomem *base; |
| 361 | 362 | ||
| 362 | struct hdmi_core_infoframe_avi avi_cfg; | 363 | struct hdmi_core_infoframe_avi avi_cfg; |
| 364 | struct hdmi_avi_infoframe avi_infoframe; | ||
| 363 | }; | 365 | }; |
| 364 | 366 | ||
| 365 | static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, | 367 | static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, |
diff --git a/drivers/video/fbdev/omap2/dss/hdmi4_core.c b/drivers/video/fbdev/omap2/dss/hdmi4_core.c index 8bde7b7e95ff..dbdbc5836d51 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi4_core.c +++ b/drivers/video/fbdev/omap2/dss/hdmi4_core.c | |||
| @@ -198,7 +198,6 @@ int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len) | |||
| 198 | } | 198 | } |
| 199 | 199 | ||
| 200 | static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | 200 | static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, |
| 201 | struct hdmi_core_infoframe_avi *avi_cfg, | ||
| 202 | struct hdmi_core_packet_enable_repeat *repeat_cfg) | 201 | struct hdmi_core_packet_enable_repeat *repeat_cfg) |
| 203 | { | 202 | { |
| 204 | DSSDBG("Enter hdmi_core_init\n"); | 203 | DSSDBG("Enter hdmi_core_init\n"); |
| @@ -211,25 +210,6 @@ static void hdmi_core_init(struct hdmi_core_video_config *video_cfg, | |||
| 211 | video_cfg->hdmi_dvi = HDMI_DVI; | 210 | video_cfg->hdmi_dvi = HDMI_DVI; |
| 212 | video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; | 211 | video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK; |
| 213 | 212 | ||
| 214 | /* info frame */ | ||
| 215 | avi_cfg->db1_format = 0; | ||
| 216 | avi_cfg->db1_active_info = 0; | ||
| 217 | avi_cfg->db1_bar_info_dv = 0; | ||
| 218 | avi_cfg->db1_scan_info = 0; | ||
| 219 | avi_cfg->db2_colorimetry = 0; | ||
| 220 | avi_cfg->db2_aspect_ratio = 0; | ||
| 221 | avi_cfg->db2_active_fmt_ar = 0; | ||
| 222 | avi_cfg->db3_itc = 0; | ||
| 223 | avi_cfg->db3_ec = 0; | ||
| 224 | avi_cfg->db3_q_range = 0; | ||
| 225 | avi_cfg->db3_nup_scaling = 0; | ||
| 226 | avi_cfg->db4_videocode = 0; | ||
| 227 | avi_cfg->db5_pixel_repeat = 0; | ||
| 228 | avi_cfg->db6_7_line_eoftop = 0; | ||
| 229 | avi_cfg->db8_9_line_sofbottom = 0; | ||
| 230 | avi_cfg->db10_11_pixel_eofleft = 0; | ||
| 231 | avi_cfg->db12_13_pixel_sofright = 0; | ||
| 232 | |||
| 233 | /* packet enable and repeat */ | 213 | /* packet enable and repeat */ |
| 234 | repeat_cfg->audio_pkt = 0; | 214 | repeat_cfg->audio_pkt = 0; |
| 235 | repeat_cfg->audio_pkt_repeat = 0; | 215 | repeat_cfg->audio_pkt_repeat = 0; |
| @@ -305,78 +285,17 @@ static void hdmi_core_video_config(struct hdmi_core_data *core, | |||
| 305 | 285 | ||
| 306 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) | 286 | static void hdmi_core_aux_infoframe_avi_config(struct hdmi_core_data *core) |
| 307 | { | 287 | { |
| 308 | u32 val; | ||
| 309 | char sum = 0, checksum = 0; | ||
| 310 | void __iomem *av_base = hdmi_av_base(core); | 288 | void __iomem *av_base = hdmi_av_base(core); |
| 311 | struct hdmi_core_infoframe_avi info_avi = core->avi_cfg; | 289 | struct hdmi_avi_infoframe *frame = &core->avi_infoframe; |
| 312 | 290 | u8 data[HDMI_INFOFRAME_SIZE(AVI)]; | |
| 313 | sum += 0x82 + 0x002 + 0x00D; | 291 | int i; |
| 314 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082); | ||
| 315 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002); | ||
| 316 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D); | ||
| 317 | |||
| 318 | val = (info_avi.db1_format << 5) | | ||
| 319 | (info_avi.db1_active_info << 4) | | ||
| 320 | (info_avi.db1_bar_info_dv << 2) | | ||
| 321 | (info_avi.db1_scan_info); | ||
| 322 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val); | ||
| 323 | sum += val; | ||
| 324 | |||
| 325 | val = (info_avi.db2_colorimetry << 6) | | ||
| 326 | (info_avi.db2_aspect_ratio << 4) | | ||
| 327 | (info_avi.db2_active_fmt_ar); | ||
| 328 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val); | ||
| 329 | sum += val; | ||
| 330 | |||
| 331 | val = (info_avi.db3_itc << 7) | | ||
| 332 | (info_avi.db3_ec << 4) | | ||
| 333 | (info_avi.db3_q_range << 2) | | ||
| 334 | (info_avi.db3_nup_scaling); | ||
| 335 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val); | ||
| 336 | sum += val; | ||
| 337 | |||
| 338 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3), | ||
| 339 | info_avi.db4_videocode); | ||
| 340 | sum += info_avi.db4_videocode; | ||
| 341 | |||
| 342 | val = info_avi.db5_pixel_repeat; | ||
| 343 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val); | ||
| 344 | sum += val; | ||
| 345 | |||
| 346 | val = info_avi.db6_7_line_eoftop & 0x00FF; | ||
| 347 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val); | ||
| 348 | sum += val; | ||
| 349 | |||
| 350 | val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF); | ||
| 351 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val); | ||
| 352 | sum += val; | ||
| 353 | |||
| 354 | val = info_avi.db8_9_line_sofbottom & 0x00FF; | ||
| 355 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val); | ||
| 356 | sum += val; | ||
| 357 | |||
| 358 | val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF); | ||
| 359 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val); | ||
| 360 | sum += val; | ||
| 361 | |||
| 362 | val = info_avi.db10_11_pixel_eofleft & 0x00FF; | ||
| 363 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val); | ||
| 364 | sum += val; | ||
| 365 | |||
| 366 | val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF); | ||
| 367 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val); | ||
| 368 | sum += val; | ||
| 369 | |||
| 370 | val = info_avi.db12_13_pixel_sofright & 0x00FF; | ||
| 371 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val); | ||
| 372 | sum += val; | ||
| 373 | |||
| 374 | val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF); | ||
| 375 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val); | ||
| 376 | sum += val; | ||
| 377 | 292 | ||
| 378 | checksum = 0x100 - sum; | 293 | hdmi_avi_infoframe_pack(frame, data, sizeof(data)); |
| 379 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum); | 294 | |
| 295 | for (i = 0; i < sizeof(data); ++i) { | ||
| 296 | hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_BASE + i * 4, | ||
| 297 | data[i]); | ||
| 298 | } | ||
| 380 | } | 299 | } |
| 381 | 300 | ||
| 382 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, | 301 | static void hdmi_core_av_packet_config(struct hdmi_core_data *core, |
| @@ -404,11 +323,11 @@ void hdmi4_configure(struct hdmi_core_data *core, | |||
| 404 | struct omap_video_timings video_timing; | 323 | struct omap_video_timings video_timing; |
| 405 | struct hdmi_video_format video_format; | 324 | struct hdmi_video_format video_format; |
| 406 | /* HDMI core */ | 325 | /* HDMI core */ |
| 407 | struct hdmi_core_infoframe_avi *avi_cfg = &core->avi_cfg; | ||
| 408 | struct hdmi_core_video_config v_core_cfg; | 326 | struct hdmi_core_video_config v_core_cfg; |
| 409 | struct hdmi_core_packet_enable_repeat repeat_cfg; | 327 | struct hdmi_core_packet_enable_repeat repeat_cfg; |
| 328 | struct hdmi_avi_infoframe *avi_infoframe = &core->avi_infoframe; | ||
| 410 | 329 | ||
| 411 | hdmi_core_init(&v_core_cfg, avi_cfg, &repeat_cfg); | 330 | hdmi_core_init(&v_core_cfg, &repeat_cfg); |
| 412 | 331 | ||
| 413 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); | 332 | hdmi_wp_init_vid_fmt_timings(&video_format, &video_timing, cfg); |
| 414 | 333 | ||
| @@ -442,25 +361,20 @@ void hdmi4_configure(struct hdmi_core_data *core, | |||
| 442 | * configure packet | 361 | * configure packet |
| 443 | * info frame video see doc CEA861-D page 65 | 362 | * info frame video see doc CEA861-D page 65 |
| 444 | */ | 363 | */ |
| 445 | avi_cfg->db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB; | 364 | hdmi_avi_infoframe_init(avi_infoframe); |
