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authorBen Skeggs <bskeggs@redhat.com>2013-11-30 00:15:28 -0500
committerBen Skeggs <bskeggs@redhat.com>2014-01-22 22:38:56 -0500
commitdb6735cab2b0f12a824f04b1d8fb4da2ea978c8d (patch)
tree96d61d67daeb67a6890b9ac1c860acc1330ab64f
parentf4aa2c6677be2f0046a7431f23d4c76baba5ecc8 (diff)
drm/nve0/fb/gddr5: somewhat better attempt at 100770/10f604/610/614
Signed-off-by: Ben Skeggs <bskeggs@redhat.com> fb/gddr5/nve0: 100770 is like 10f604 Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c61
1 files changed, 47 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
index 659183b858e2..a4c84d6f50e5 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
@@ -41,6 +41,14 @@
41 41
42#include "ramfuc.h" 42#include "ramfuc.h"
43 43
44/* binary driver only executes this path if the condition (a) is true
45 * for any configuration (combination of rammap+ramcfg+timing) that
46 * can be reached on a given card. for now, we will execute the branch
47 * unconditionally in the hope that a "false everywhere" in the bios
48 * tables doesn't actually mean "don't touch this".
49 */
50#define NOTE00(a) 1
51
44struct nve0_ramfuc { 52struct nve0_ramfuc {
45 struct ramfuc base; 53 struct ramfuc base;
46 54
@@ -466,23 +474,41 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
466 ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20)); 474 ram_mask(fuc, 0x10f2cc, 0xffffffff, nv_ro32(bios, timing + 0x20));
467 ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24)); 475 ram_mask(fuc, 0x10f2e8, 0xffffffff, nv_ro32(bios, timing + 0x24));
468 476
469 /*XXX: what's the condition here? */ 477 data = mask = 0x00000000;
470 if (1) { 478 if (NOTE00(ramcfg_02_03 != 0)) {
471 data = (nv_ro08(bios, ramcfg + 0x02) & 0x03) << 8; 479 data |= (nv_ro08(bios, ramcfg + 0x02) & 0x03) << 8;
480 mask |= 0x00000300;
481 }
482 if (NOTE00(ramcfg_01_10)) {
472 if (nv_ro08(bios, ramcfg + 0x01) & 0x10) 483 if (nv_ro08(bios, ramcfg + 0x01) & 0x10)
473 data |= 0x70000000; 484 data |= 0x70000000;
474 ram_mask(fuc, 0x10f604, 0x70000300, data); 485 mask |= 0x70000000;
486 }
487 ram_mask(fuc, 0x10f604, mask, data);
475 488
476 data = (nv_ro08(bios, timing + 0x30) & 0x07) << 28; 489 data = mask = 0x00000000;
490 if (NOTE00(timing_30_07 != 0)) {
491 data |= (nv_ro08(bios, timing + 0x30) & 0x07) << 28;
492 mask |= 0x70000000;
493 }
494 if (NOTE00(ramcfg_01_01)) {
477 if (nv_ro08(bios, ramcfg + 0x01) & 0x01) 495 if (nv_ro08(bios, ramcfg + 0x01) & 0x01)
478 data |= 0x00000100; 496 data |= 0x00000100;
479 ram_mask(fuc, 0x10f614, 0x70000000, data); 497 mask |= 0x00000100;
498 }
499 ram_mask(fuc, 0x10f614, mask, data);
480 500
481 data = (nv_ro08(bios, timing + 0x30) & 0x07) << 28; 501 data = mask = 0x00000000;
502 if (NOTE00(timing_30_07 != 0)) {
503 data |= (nv_ro08(bios, timing + 0x30) & 0x07) << 28;
504 mask |= 0x70000000;
505 }
506 if (NOTE00(ramcfg_01_02)) {
482 if (nv_ro08(bios, ramcfg + 0x01) & 0x02) 507 if (nv_ro08(bios, ramcfg + 0x01) & 0x02)
483 data |= 0x00000100; 508 data |= 0x00000100;
484 ram_mask(fuc, 0x10f610, 0x70000000, data); 509 mask |= 0x00000100;
485 } 510 }
511 ram_mask(fuc, 0x10f610, mask, data);
486 512
487 mask = 0x33f00000; 513 mask = 0x33f00000;
488 data = 0x00000000; 514 data = 0x00000000;
@@ -511,15 +537,22 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
511 data = nv_ro08(bios, ramcfg + 0x03) & 0x0f; 537 data = nv_ro08(bios, ramcfg + 0x03) & 0x0f;
512 ram_wr32(fuc, 0x10f870, 0x11111111 * data); 538 ram_wr32(fuc, 0x10f870, 0x11111111 * data);
513 539
514 data = nv_ro08(bios, ramcfg + 0x02) & 0x03; 540 data = mask = 0x00000000;
515 if (nv_ro08(bios, ramcfg + 0x01) & 0x10) 541 if (NOTE00(ramcfg_02_03 != 0)) {
516 data |= 0x00000004; 542 data |= nv_ro08(bios, ramcfg + 0x02) & 0x03;
517 if ((ram_rd32(fuc, 0x100770) & 0x00000004) != (data & 0x00000004)) { 543 mask |= 0x00000003;
518 ram_wr32(fuc, 0x100750, 0x04000009); 544 }
545 if (NOTE00(ramcfg_01_10)) {
546 if (nv_ro08(bios, ramcfg + 0x01) & 0x10)
547 data |= 0x00000004;
548 mask |= 0x00000004;
549 }
550
551 if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
552 ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
519 ram_wr32(fuc, 0x100710, 0x00000000); 553 ram_wr32(fuc, 0x100710, 0x00000000);
520 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); 554 ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
521 } 555 }
522 ram_mask(fuc, 0x100770, 0x00000007, data);
523 556
524 data = (nv_ro08(bios, timing + 0x30) & 0x07) << 8; 557 data = (nv_ro08(bios, timing + 0x30) & 0x07) << 8;
525 if (nv_ro08(bios, ramcfg + 0x01) & 0x01) 558 if (nv_ro08(bios, ramcfg + 0x01) & 0x01)