Merge tag 'qcom-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next

qcom clock changes for 3.18

Some fixes for the IPQ driver and some code consolidation
and refactoring.

9 files changed, 219 insertions, 88 deletions

diff --git a/drivers/clk/qcom/clk-pll.c b/drivers/clk/qcom/clk-pll.c
index 9db03d3b1657..b823bc3b6250 100644
--- a/drivers/clk/qcom/clk-pll.c
+++ b/drivers/clk/qcom/clk-pll.c
@@ -97,7 +97,7 @@ static unsigned long
 clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
         struct clk_pll *pll = to_clk_pll(hw);
-        u32 l, m, n;
+        u32 l, m, n, config;
         unsigned long rate;
         u64 tmp;
 
@@ -116,13 +116,79 @@ clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
                 do_div(tmp, n);
                 rate += tmp;
         }
+        if (pll->post_div_width) {
+                regmap_read(pll->clkr.regmap, pll->config_reg, &config);
+                config >>= pll->post_div_shift;
+                config &= BIT(pll->post_div_width) - 1;
+                rate /= config + 1;
+        }
+
         return rate;
 }
 
+static const
+struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
+{
+        if (!f)
+                return NULL;
+
+        for (; f->freq; f++)
+                if (rate <= f->freq)
+                        return f;
+
+        return NULL;
+}
+
+static long
+clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
+                       unsigned long *p_rate, struct clk **p)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        const struct pll_freq_tbl *f;
+
+        f = find_freq(pll->freq_tbl, rate);
+        if (!f)
+                return clk_pll_recalc_rate(hw, *p_rate);
+
+        return f->freq;
+}
+
+static int
+clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        const struct pll_freq_tbl *f;
+        bool enabled;
+        u32 mode;
+        u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
+
+        f = find_freq(pll->freq_tbl, rate);
+        if (!f)
+                return -EINVAL;
+
+        regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
+        enabled = (mode & enable_mask) == enable_mask;
+
+        if (enabled)
+                clk_pll_disable(hw);
+
+        regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
+        regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
+        regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
+        regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
+
+        if (enabled)
+                clk_pll_enable(hw);
+
+        return 0;
+}
+
 const struct clk_ops clk_pll_ops = {
         .enable = clk_pll_enable,
         .disable = clk_pll_disable,
         .recalc_rate = clk_pll_recalc_rate,
+        .determine_rate = clk_pll_determine_rate,
+        .set_rate = clk_pll_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_pll_ops);
 
diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index 3003e9962472..c9c0cda306d0 100644
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -18,6 +18,21 @@
 #include "clk-regmap.h"
 
 /**
+ * struct pll_freq_tbl - PLL frequency table
+ * @l: L value
+ * @m: M value
+ * @n: N value
+ * @ibits: internal values
+ */
+struct pll_freq_tbl {
+        unsigned long freq;
+        u16 l;
+        u16 m;
+        u16 n;
+        u32 ibits;
+};
+
+/**
  * struct clk_pll - phase locked loop (PLL)
  * @l_reg: L register
  * @m_reg: M register
@@ -26,6 +41,7 @@
  * @mode_reg: mode register
  * @status_reg: status register
  * @status_bit: ANDed with @status_reg to determine if PLL is enabled
+ * @freq_tbl: PLL frequency table
  * @hw: handle between common and hardware-specific interfaces
  */
 struct clk_pll {
@@ -36,6 +52,10 @@ struct clk_pll {
         u32     mode_reg;
         u32     status_reg;
         u8      status_bit;
+        u8      post_div_width;
+        u8      post_div_shift;
+
+        const struct pll_freq_tbl *freq_tbl;
 
         struct clk_regmap clkr;
 };
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index b638c5846dbf..b6e6959e89aa 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -21,6 +21,7 @@
 #include <asm/div64.h>
 
 #include "clk-rcg.h"
+#include "common.h"
 
 static u32 ns_to_src(struct src_sel *s, u32 ns)
 {
@@ -67,16 +68,16 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
 {
         struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
         int num_parents = __clk_get_num_parents(hw->clk);
-        u32 ns, ctl;
+        u32 ns, reg;
         int bank;
         int i;
         struct src_sel *s;
 
-        regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
-        bank = reg_to_bank(rcg, ctl);
+        regmap_read(rcg->clkr.regmap, rcg->bank_reg, &reg);
+        bank = reg_to_bank(rcg, reg);
         s = &rcg->s[bank];
 
-        regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
+        regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
         ns = ns_to_src(s, ns);
 
         for (i = 0; i < num_parents; i++)
@@ -192,90 +193,93 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)