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authorMikhail Ulyanov <mikhail.ulyanov@cogentembedded.com>2014-08-19 08:50:49 -0400
committerSimon Horman <horms+renesas@verge.net.au>2014-08-21 21:49:39 -0400
commitda076a888ab19f13816372796ed231e7d6ff5fed (patch)
tree675b3b499665a183ddcc317a08d3dde39e9889c7
parentd594c9775409a4276133db5e34dbd791329c5eae (diff)
ARM: shmobile: r8a7790: Add JPU clock dt and CPG define.
Signed-off-by: Mikhail Ulyanov <mikhail.ulyanov@cogentembedded.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi6
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h1
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 2278bd0968d1..c11541d6dc25 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -836,17 +836,17 @@
836 mstp1_clks: mstp1_clks@e6150134 { 836 mstp1_clks: mstp1_clks@e6150134 {
837 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 837 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
838 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 838 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
839 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, 839 clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
840 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, 840 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
841 <&zs_clk>; 841 <&zs_clk>;
842 #clock-cells = <1>; 842 #clock-cells = <1>;
843 renesas,clock-indices = < 843 renesas,clock-indices = <
844 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 844 R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
845 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 845 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
846 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S 846 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
847 >; 847 >;
848 clock-output-names = 848 clock-output-names =
849 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", 849 "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
850 "vsp1-du0", "vsp1-rt", "vsp1-sy"; 850 "vsp1-du0", "vsp1-rt", "vsp1-sy";
851 }; 851 };
852 mstp2_clks: mstp2_clks@e6150138 { 852 mstp2_clks: mstp2_clks@e6150138 {
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index f929a79e6998..8ea7ab0346ad 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -26,6 +26,7 @@
26#define R8A7790_CLK_MSIOF0 0 26#define R8A7790_CLK_MSIOF0 0
27 27
28/* MSTP1 */ 28/* MSTP1 */
29#define R8A7790_CLK_JPU 6
29#define R8A7790_CLK_TMU1 11 30#define R8A7790_CLK_TMU1 11
30#define R8A7790_CLK_TMU3 21 31#define R8A7790_CLK_TMU3 21
31#define R8A7790_CLK_TMU2 22 32#define R8A7790_CLK_TMU2 22