diff options
author | Wolfram Sang <wsa@sang-engineering.com> | 2013-12-18 16:31:58 -0500 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2013-12-24 07:09:19 -0500 |
commit | d85bcfa916ffdf078f188aeab60f738b290f4309 (patch) | |
tree | 3a9cfce48e29a5745a62752742051404d8255e92 | |
parent | f72ed4beb198eb25c8532e76addc0034ae2aa8c7 (diff) |
arm: shmobile: r7s72100: add i2c clocks
Tested with RIIC2 on a genmai board. Others untested but hopefully
trivial enough to be added.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r-- | arch/arm/mach-shmobile/clock-r7s72100.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c index 4aba20ca127e..850a8a371b43 100644 --- a/arch/arm/mach-shmobile/clock-r7s72100.c +++ b/arch/arm/mach-shmobile/clock-r7s72100.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #define FRQCR2 0xfcfe0014 | 27 | #define FRQCR2 0xfcfe0014 |
28 | #define STBCR3 0xfcfe0420 | 28 | #define STBCR3 0xfcfe0420 |
29 | #define STBCR4 0xfcfe0424 | 29 | #define STBCR4 0xfcfe0424 |
30 | #define STBCR9 0xfcfe0438 | ||
30 | 31 | ||
31 | #define PLL_RATE 30 | 32 | #define PLL_RATE 30 |
32 | 33 | ||
@@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = { | |||
144 | | CLK_ENABLE_ON_INIT), | 145 | | CLK_ENABLE_ON_INIT), |
145 | }; | 146 | }; |
146 | 147 | ||
147 | enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | 148 | enum { MSTP97, MSTP96, MSTP95, MSTP94, |
149 | MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | ||
148 | MSTP33, MSTP_NR }; | 150 | MSTP33, MSTP_NR }; |
149 | 151 | ||
150 | static struct clk mstp_clks[MSTP_NR] = { | 152 | static struct clk mstp_clks[MSTP_NR] = { |
153 | [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */ | ||
154 | [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */ | ||
155 | [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */ | ||
156 | [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */ | ||
151 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ | 157 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ |
152 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ | 158 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ |
153 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ | 159 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ |