diff options
author | Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2012-10-11 21:08:04 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-11-28 07:37:57 -0500 |
commit | d83501a0416160cc45e84b6719f7a2784013cf16 (patch) | |
tree | 2382d6bf3a15c12ffd641bdb609c526ace48d490 | |
parent | 07d19e3cce15ed4a481236fe5e24668a720d0cbd (diff) |
[media] omap3isp: Remove unneeded module memory address definitions
The OMAP3ISP_*_REG_OFFSET, OMAP3ISP_*_REG_BASE and OMAP3ISP_*_REG macros
are not needed. Remove them.
The only exception is the OMAP3ISP_HIST_REG_BASE address. Replace it
with the memory address received through platform resources.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
-rw-r--r-- | drivers/media/platform/omap3isp/isphist.c | 8 | ||||
-rw-r--r-- | drivers/media/platform/omap3isp/ispreg.h | 77 |
2 files changed, 6 insertions, 79 deletions
diff --git a/drivers/media/platform/omap3isp/isphist.c b/drivers/media/platform/omap3isp/isphist.c index d1a8dee5e1ca..74326ff342a5 100644 --- a/drivers/media/platform/omap3isp/isphist.c +++ b/drivers/media/platform/omap3isp/isphist.c | |||
@@ -72,11 +72,14 @@ static void hist_reset_mem(struct ispstat *hist) | |||
72 | 72 | ||
73 | static void hist_dma_config(struct ispstat *hist) | 73 | static void hist_dma_config(struct ispstat *hist) |
74 | { | 74 | { |
75 | struct isp_device *isp = hist->isp; | ||
76 | |||
75 | hist->dma_config.data_type = OMAP_DMA_DATA_TYPE_S32; | 77 | hist->dma_config.data_type = OMAP_DMA_DATA_TYPE_S32; |
76 | hist->dma_config.sync_mode = OMAP_DMA_SYNC_ELEMENT; | 78 | hist->dma_config.sync_mode = OMAP_DMA_SYNC_ELEMENT; |
77 | hist->dma_config.frame_count = 1; | 79 | hist->dma_config.frame_count = 1; |
78 | hist->dma_config.src_amode = OMAP_DMA_AMODE_CONSTANT; | 80 | hist->dma_config.src_amode = OMAP_DMA_AMODE_CONSTANT; |
79 | hist->dma_config.src_start = OMAP3ISP_HIST_REG_BASE + ISPHIST_DATA; | 81 | hist->dma_config.src_start = isp->mmio_base_phys[OMAP3_ISP_IOMEM_HIST] |
82 | + ISPHIST_DATA; | ||
80 | hist->dma_config.dst_amode = OMAP_DMA_AMODE_POST_INC; | 83 | hist->dma_config.dst_amode = OMAP_DMA_AMODE_POST_INC; |
81 | hist->dma_config.src_or_dst_synch = OMAP_DMA_SRC_SYNC; | 84 | hist->dma_config.src_or_dst_synch = OMAP_DMA_SRC_SYNC; |
82 | } | 85 | } |
@@ -477,6 +480,8 @@ int omap3isp_hist_init(struct isp_device *isp) | |||
477 | return -ENOMEM; | 480 | return -ENOMEM; |
478 | 481 | ||
479 | memset(hist, 0, sizeof(*hist)); | 482 | memset(hist, 0, sizeof(*hist)); |
483 | hist->isp = isp; | ||
484 | |||
480 | if (HIST_CONFIG_DMA) | 485 | if (HIST_CONFIG_DMA) |
481 | ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, "DMA_ISP_HIST", | 486 | ret = omap_request_dma(OMAP24XX_DMA_NO_DEVICE, "DMA_ISP_HIST", |
482 | hist_dma_cb, hist, &hist->dma_ch); | 487 | hist_dma_cb, hist, &hist->dma_ch); |
@@ -494,7 +499,6 @@ int omap3isp_hist_init(struct isp_device *isp) | |||
494 | hist->ops = &hist_ops; | 499 | hist->ops = &hist_ops; |
495 | hist->priv = hist_cfg; | 500 | hist->priv = hist_cfg; |
496 | hist->event_type = V4L2_EVENT_OMAP3ISP_HIST; | 501 | hist->event_type = V4L2_EVENT_OMAP3ISP_HIST; |
497 | hist->isp = isp; | ||
498 | 502 | ||
499 | ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops); | 503 | ret = omap3isp_stat_init(hist, "histogram", &hist_subdev_ops); |
500 | if (ret) { | 504 | if (ret) { |
diff --git a/drivers/media/platform/omap3isp/ispreg.h b/drivers/media/platform/omap3isp/ispreg.h index e2c57f334c5d..fd13d8bb63e2 100644 --- a/drivers/media/platform/omap3isp/ispreg.h +++ b/drivers/media/platform/omap3isp/ispreg.h | |||
@@ -29,83 +29,6 @@ | |||
29 | 29 | ||
30 | #define CM_CAM_MCLK_HZ 172800000 /* Hz */ | 30 | #define CM_CAM_MCLK_HZ 172800000 /* Hz */ |
31 | 31 | ||
32 | /* ISP Submodules offset */ | ||
33 | |||
34 | #define L4_34XX_BASE 0x48000000 | ||
35 | #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) | ||
36 | |||
37 | #define OMAP3ISP_REG_BASE OMAP3430_ISP_BASE | ||
38 | #define OMAP3ISP_REG(offset) (OMAP3ISP_REG_BASE + (offset)) | ||
39 | |||
40 | #define OMAP3ISP_CCP2_REG_OFFSET 0x0400 | ||
41 | #define OMAP3ISP_CCP2_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
42 | OMAP3ISP_CCP2_REG_OFFSET) | ||
43 | #define OMAP3ISP_CCP2_REG(offset) (OMAP3ISP_CCP2_REG_BASE + (offset)) | ||
44 | |||
45 | #define OMAP3ISP_CCDC_REG_OFFSET 0x0600 | ||
46 | #define OMAP3ISP_CCDC_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
47 | OMAP3ISP_CCDC_REG_OFFSET) | ||
48 | #define OMAP3ISP_CCDC_REG(offset) (OMAP3ISP_CCDC_REG_BASE + (offset)) | ||
49 | |||
50 | #define OMAP3ISP_HIST_REG_OFFSET 0x0A00 | ||
51 | #define OMAP3ISP_HIST_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
52 | OMAP3ISP_HIST_REG_OFFSET) | ||
53 | #define OMAP3ISP_HIST_REG(offset) (OMAP3ISP_HIST_REG_BASE + (offset)) | ||
54 | |||
55 | #define OMAP3ISP_H3A_REG_OFFSET 0x0C00 | ||
56 | #define OMAP3ISP_H3A_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
57 | OMAP3ISP_H3A_REG_OFFSET) | ||
58 | #define OMAP3ISP_H3A_REG(offset) (OMAP3ISP_H3A_REG_BASE + (offset)) | ||
59 | |||
60 | #define OMAP3ISP_PREV_REG_OFFSET 0x0E00 | ||
61 | #define OMAP3ISP_PREV_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
62 | OMAP3ISP_PREV_REG_OFFSET) | ||
63 | #define OMAP3ISP_PREV_REG(offset) (OMAP3ISP_PREV_REG_BASE + (offset)) | ||
64 | |||
65 | #define OMAP3ISP_RESZ_REG_OFFSET 0x1000 | ||
66 | #define OMAP3ISP_RESZ_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
67 | OMAP3ISP_RESZ_REG_OFFSET) | ||
68 | #define OMAP3ISP_RESZ_REG(offset) (OMAP3ISP_RESZ_REG_BASE + (offset)) | ||
69 | |||
70 | #define OMAP3ISP_SBL_REG_OFFSET 0x1200 | ||
71 | #define OMAP3ISP_SBL_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
72 | OMAP3ISP_SBL_REG_OFFSET) | ||
73 | #define OMAP3ISP_SBL_REG(offset) (OMAP3ISP_SBL_REG_BASE + (offset)) | ||
74 | |||
75 | #define OMAP3ISP_CSI2A_REGS1_REG_OFFSET 0x1800 | ||
76 | #define OMAP3ISP_CSI2A_REGS1_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
77 | OMAP3ISP_CSI2A_REGS1_REG_OFFSET) | ||
78 | #define OMAP3ISP_CSI2A_REGS1_REG(offset) \ | ||
79 | (OMAP3ISP_CSI2A_REGS1_REG_BASE + (offset)) | ||
80 | |||
81 | #define OMAP3ISP_CSIPHY2_REG_OFFSET 0x1970 | ||
82 | #define OMAP3ISP_CSIPHY2_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
83 | OMAP3ISP_CSIPHY2_REG_OFFSET) | ||
84 | #define OMAP3ISP_CSIPHY2_REG(offset) (OMAP3ISP_CSIPHY2_REG_BASE + (offset)) | ||
85 | |||
86 | #define OMAP3ISP_CSI2A_REGS2_REG_OFFSET 0x19C0 | ||
87 | #define OMAP3ISP_CSI2A_REGS2_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
88 | OMAP3ISP_CSI2A_REGS2_REG_OFFSET) | ||
89 | #define OMAP3ISP_CSI2A_REGS2_REG(offset) \ | ||
90 | (OMAP3ISP_CSI2A_REGS2_REG_BASE + (offset)) | ||
91 | |||
92 | #define OMAP3ISP_CSI2C_REGS1_REG_OFFSET 0x1C00 | ||
93 | #define OMAP3ISP_CSI2C_REGS1_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
94 | OMAP3ISP_CSI2C_REGS1_REG_OFFSET) | ||
95 | #define OMAP3ISP_CSI2C_REGS1_REG(offset) \ | ||
96 | (OMAP3ISP_CSI2C_REGS1_REG_BASE + (offset)) | ||
97 | |||
98 | #define OMAP3ISP_CSIPHY1_REG_OFFSET 0x1D70 | ||
99 | #define OMAP3ISP_CSIPHY1_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
100 | OMAP3ISP_CSIPHY1_REG_OFFSET) | ||
101 | #define OMAP3ISP_CSIPHY1_REG(offset) (OMAP3ISP_CSIPHY1_REG_BASE + (offset)) | ||
102 | |||
103 | #define OMAP3ISP_CSI2C_REGS2_REG_OFFSET 0x1DC0 | ||
104 | #define OMAP3ISP_CSI2C_REGS2_REG_BASE (OMAP3ISP_REG_BASE + \ | ||
105 | OMAP3ISP_CSI2C_REGS2_REG_OFFSET) | ||
106 | #define OMAP3ISP_CSI2C_REGS2_REG(offset) \ | ||
107 | (OMAP3ISP_CSI2C_REGS2_REG_BASE + (offset)) | ||
108 | |||
109 | /* ISP module register offset */ | 32 | /* ISP module register offset */ |
110 | 33 | ||
111 | #define ISP_REVISION (0x000) | 34 | #define ISP_REVISION (0x000) |