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authorDmitry Lavnikevich <d.lavnikevich@sam-solutions.com>2014-11-04 08:05:47 -0500
committerShawn Guo <shawn.guo@linaro.org>2014-11-23 02:08:11 -0500
commitd76fab80ef32a7421feb7b71b6e2fdddf3a036fd (patch)
tree6cbb2bd8b47eb2feaff365cc01b1e10c94826560
parente1bf86ace4d2ac915e130699aefe6e9d9bc7164d (diff)
ARM: dts: pbab01: move i2c pins and frequency configuration into pfla02
Since pins and frequency are specific to module (pfla02), not base board (pbab02), it is better to be initialized in corresponding dts file. This patch fixes i2c2, i2c3 pin configuration which caused messages: imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c2grp imx6q-pinctrl 20e0000.iomuxc: no groups defined in /soc/aips-bus@02000000/iomuxc@020e0000/i2c3grp imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c2grp imx6q-pinctrl 20e0000.iomuxc: unable to find group for node i2c3grp Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi22
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi26
2 files changed, 26 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index 584721264121..f1bdcae5b97d 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -28,9 +28,6 @@
28}; 28};
29 29
30&i2c2 { 30&i2c2 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_i2c2>;
33 clock-frequency = <100000>;
34 status = "okay"; 31 status = "okay";
35 32
36 tlv320@18 { 33 tlv320@18 {
@@ -55,9 +52,6 @@
55}; 52};
56 53
57&i2c3 { 54&i2c3 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_i2c3>;
60 clock-frequency = <100000>;
61 status = "okay"; 55 status = "okay";
62}; 56};
63 57
@@ -84,19 +78,3 @@
84&usdhc3 { 78&usdhc3 {
85 status = "okay"; 79 status = "okay";
86}; 80};
87
88&iomuxc {
89 pinctrl_i2c2: i2c2grp {
90 fsl,pins = <
91 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
92 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
93 >;
94 };
95
96 pinctrl_i2c3: i2c3grp {
97 fsl,pins = <
98 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
99 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
100 >;
101 };
102};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index 0e50bb0a6b94..aa2275671d2c 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -162,6 +162,18 @@
162 }; 162 };
163}; 163};
164 164
165&i2c2 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c2>;
168 clock-frequency = <100000>;
169};
170
171&i2c3 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_i2c3>;
174 clock-frequency = <100000>;
175};
176
165&iomuxc { 177&iomuxc {
166 pinctrl-names = "default"; 178 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_hog>; 179 pinctrl-0 = <&pinctrl_hog>;
@@ -235,6 +247,20 @@
235 >; 247 >;
236 }; 248 };
237 249
250 pinctrl_i2c2: i2c2grp {
251 fsl,pins = <
252 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
253 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
254 >;
255 };
256
257 pinctrl_i2c3: i2c3grp {
258 fsl,pins = <
259 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
260 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
261 >;
262 };
263
238 pinctrl_uart3: uart3grp { 264 pinctrl_uart3: uart3grp {
239 fsl,pins = < 265 fsl,pins = <
240 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 266 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1